TI1 CSD22206WT 8-v p-channel nexfet power mosfet Datasheet

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CSD22206W
SLPS689 – MAY 2017
CSD22206W –8-V P-Channel NexFET™ Power MOSFET
1 Features
•
•
•
•
•
•
•
1
Product Summary
Ultra-Low Resistance
Small Footprint 1.5 mm × 1.5 mm
Lead Free
Gate ESD Protection
RoHS Compliant
Halogen Free
Gate-Source Voltage Clamp
TA = 25°C
TYPICAL VALUE
VDS
Drain-to-Source Voltage
Qg
Gate Charge Total (–4.5 V)
Qgd
Gate Charge Gate-to-Drain
RDS(on)
Drain-to-Source On Resistance
VGS(th)
Threshold Voltage
Load Switch Applications
Battery Management
Battery Protection
S
S
QTY
CSD22206W
3000
nC
6.8
VGS = –4.5 V
4.7
mΩ
–0.7
V
MEDIA
PACKAGE
SHIP
7-Inch Reel
1.50-mm × 1.50-mm
Wafer BGA
Package
Tape
and
Reel
250
VALUE
UNIT
VDS
Drain-to-Source Voltage
–8
V
VGS
Gate-to-Source Voltage
–6
V
Continuous Drain Current(1)
–5
A
ID
Pulsed Drain Current(2)
PD
Power Dissipation
TJ,
Tstg
Operating Junction,
Storage Temperature
–108
A
1.7
W
–55 to 150
°C
(1) Device operating at a temperature of 105°C.
(2) Typ RθJA = 75°C/W ,mounted on FR4 material with maximum
Cu mounting area, pulse width ≤ 100 μs, duty cycle ≤ 1%.
Source
S
1.8
Absolute Maximum Ratings
Top View and Circuit Configuration
S
nC
VGS = –2.5 V
TA = 25°C
This –8-V, 4.7-mΩ, 1.5-mm × 1.5-mm device is
designed to deliver the lowest on resistance and gate
charge in the smallest outline possible with excellent
thermal characteristics in an ultra-low profile. Low on
resistance coupled with the small footprint and low
profile make the device ideal for battery operated
space constrained applications.
S
DEVICE
CSD22206WT
3 Description
G
V
11.2
Device Information
2 Applications
•
•
•
UNIT
–8
Gate
D
D
D
Drain
RDS(on) vs VGS
Gate Charge
4.5
TC = 25°C, I D = -2 A
TC = 125°C, I D = -2 A
25
-VGS - Gate-to-Source Voltage (V)
RDS(on) - On-State Resistance (m:)
30
20
15
10
5
0
ID = -2 A
4 VDS = -4 V
3.5
3
2.5
2
1.5
1
0.5
0
0
1
2
3
4
-VGS - Gate-to-Source Voltage (V)
5
6
D007
0
2
4
6
8
Qg - Gate Charge (nC)
10
12
D004
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
CSD22206W
SLPS689 – MAY 2017
www.ti.com
Table of Contents
1
2
3
4
5
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
1
1
1
2
3
7
5.1 Electrical Characteristics........................................... 3
5.2 Thermal Information .................................................. 3
5.3 Typical MOSFET Characteristics.............................. 4
6
Receiving Notification of Documentation Updates....
Community Resources..............................................
Trademarks ...............................................................
Electrostatic Discharge Caution ................................
Glossary ....................................................................
7
7
7
7
7
Mechanical, Packaging, and Orderable
Information ............................................................. 8
7.1 CSD22206W Package Dimensions .......................... 8
7.2 Recommended Land Pattern .................................... 9
Device and Documentation Support.................... 7
4 Revision History
2
DATE
REVISION
NOTES
May 2017
*
Initial release.
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5 Specifications
5.1 Electrical Characteristics
TA = 25°C (unless otherwise stated)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
STATIC CHARACTERISTICS
BVDSS
Drain-to-source voltage
VGS = 0 V, IDS = –250 μA
–8
BVGSS
Gate-to-source voltage
VDS = 0 V, IG = –250 μA
–6
IDSS
Drain-to-source leakage current
VGS = 0 V, VDS = –6.4 V
IGSS
Gate-to-source leakage current
VDS = 0 V, VGS = –6 V
VGS(th)
Gate-to-source threshold voltage
VDS = VGS, IDS = –250 μA
RDS(on)
Drain-to-source on resistance
gfs
Transconductance
V
V
–1
μA
–100
nA
–0.7
–1.05
V
VGS = –2.5 V, IDS = –2 A
6.8
9.1
VGS = –4.5 V, IDS = –2 A
4.7
5.7
VDS = –0.8 V, IDS = –2 A
20
–0.4
mΩ
S
DYNAMIC CHARACTERISTICS
CISS
Input capacitance
VGS = 0 V, VDS = –4 V,
ƒ = 1 MHz
1750
2275
pF
960
1250
pF
340
440
pF
COSS
Output capacitance
CRSS
Reverse transfer capacitance
RG
Series gate resistance
Qg
Gate charge total (–4.5 V)
11.2
Qgd
Gate charge gate-to-drain
1.8
nC
Qgs
Gate charge gate-to-source
2.1
nC
Qg(th)
Gate charge at Vth
1.3
nC
QOSS
Output charge
7.2
nC
td(on)
Turnon delay time
37
ns
tr
Rise time
17
ns
td(off)
Turnoff delay time
118
ns
tf
Fall time
45
ns
30
VDS = –4 V,
ID = –2 A
VDS = –4 V, VGS = 0 V
VDS = –4 V, VGS = –4.5 V,
IDS = –2 A, RG = 0 Ω
Ω
14.6
nC
DIODE CHARACTERISTICS
VSD
Diode forward voltage
Qrr
Reverse recovery charge
trr
Reverse recovery time
IDS = –2 A, VGS = 0 V
–0.69
VDS= –4 V, IF = –1 A,
di/dt = 200 A/μs
24
–1.0
nC
59
ns
5.2 Thermal Information
TA = 25°C (unless otherwise stated)
THERMAL METRIC
RθJA
(1)
(2)
TYPICAL VALUES
Junction-to-ambient thermal resistance (1)
75
Junction-to-ambient thermal resistance (2)
230
UNIT
°C/W
Device mounted on FR4 material with 1-in2 (6.45-cm2), 2-oz (0.071-mm) thick Cu.
Device mounted on FR4 material with minimum Cu mounting area.
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Typ RθJA = 230°C/W
when mounted on
minimum pad area of
2-oz Cu.
Typ RθJA = 75°C/W
when mounted on 1 in2
of 2-oz Cu.
M0149-01
M0150-01
5.3 Typical MOSFET Characteristics
TA = 25°C (unless otherwise stated)
Figure 1. Transient Thermal Impedance
4
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Typical MOSFET Characteristics (continued)
45
50
40
45
-IDS - Drain-to-Source Current (A)
-IDS - Drain-to-Source Current (A)
TA = 25°C (unless otherwise stated)
35
30
25
20
15
10
VGS = -2.5 V
VGS = -4.5 V
5
0
0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
-VDS - Drain-to-Source Voltage (V)
D002
TC = 125°C
TC = 25°C
TC = -55°C
40
35
30
25
20
15
10
5
0
0
0.5
1
1.5
2
2.5
-VGS - Gate-to-Source Voltage (V)
3
D003
VDS = –4 V
Figure 2. Saturation Characteristics
Figure 3. Transfer Characteristics
10000
Ciss = Cgd + Cgs
Coss = Cds + Cgd
Crss = Cgd
4
3.5
C - Capacitance (pF)
-VGS - Gate-to-Source Voltage (V)
4.5
3
2.5
2
1.5
1000
1
0.5
100
0
0
2
4
6
8
Qg - Gate Charge (nC)
ID = –2 A
10
0
12
1
D004
8
D005
Figure 5. Capacitance
30
RDS(on) - On-State Resistance (m:)
1
-VGS(th) - Threshold Voltage (V)
7
VDS = –4 V
Figure 4. Gate Charge
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
-75
2
3
4
5
6
-VDS -Drain-to-Source Voltage (V)
TC = 25°C, I D = -2 A
TC = 125°C, I D = -2 A
25
20
15
10
5
0
-50
-25
0
25
50
75 100
TC - Case Temperature (°C)
125
150
175
0
D006
1
2
3
4
-VGS - Gate-to-Source Voltage (V)
5
6
D007
ID = –250 µA
Figure 6. Threshold Voltage vs Temperature
Figure 7. On-State Resistance vs Gate-to-Source Voltage
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Typical MOSFET Characteristics (continued)
TA = 25°C (unless otherwise stated)
10
1.4
TC = -55qC
TC = -40qC
TC = 25qC
TC = 125qC
TC = 150qC
-ISD - Source-to-Drain Current (A)
Normalized On-State Resistance
VGS = -4.5 V
1.3
1.2
1.1
1
0.9
0.8
0.7
-75
1
0.1
0.01
0.001
0.0001
-50
-25
0
25
50
75 100 125
TA - Ambient Temperature (qC)
150
0
175
0.2
0.4
0.6
0.8
-VSD - Source-to-Drain Voltage (V)
D008
1
D009
ID = –2 A
Figure 8. Normalized On-State Resistance vs Temperature
Figure 9. Typical Diode Forward Voltage
6
100
-IDS - Drain-to-Source Current (A)
-IDS - Drain-to-Source Current (A)
200
10
1
100 ms
10 ms
0.1
0.1
1 ms
1
-VDS - Drain-to-Source Voltage (V)
10
20
5
4
3
2
1
0
-50
-25
D010
0
25
50
75
100 125
TA - Ambient Temperature (° C)
150
175
D011
Single pulse, max RθJA = 75°C/W
Figure 10. Maximum Safe Operating Area
6
Figure 11. Maximum Drain Current vs Temperature
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SLPS689 – MAY 2017
6 Device and Documentation Support
6.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
6.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
6.3 Trademarks
NexFET, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
6.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
6.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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SLPS689 – MAY 2017
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7 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
7.1 CSD22206W Package Dimensions
Solder Ball
Ø 0.31 ±0.075
Pin 1
Mark
1
2
3
2
3
1
A
B
1.50
B
1.00
+0.00
–0.08
0.50
A
C
C
1.50
+0.00
–0.08
0.62 Max
Top View
0.50
Bottom View
0.04
0.62 Max
0.35 ±0.10
Side View
Seating Plate
Front View
M0171-01
NOTE: All dimensions are in mm (unless otherwise specified).
Table 1. Pinout
POSITION
8
DESIGNATION
A1
Gate
A2, A3, B1, B2, B3
Source
C1, C2, C3
Drain
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SLPS689 – MAY 2017
7.2 Recommended Land Pattern
Ø 0.25
1
2
3
1.00
0.50
A
B
C
0.50
M0172-01
NOTE: All dimensions are in mm (unless otherwise specified).
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9
PACKAGE OPTION ADDENDUM
www.ti.com
22-May-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
CSD22206W
PREVIEW
DSBGA
YZF
9
3000
TBD
Call TI
Call TI
-55 to 150
22206
CSD22206WT
PREVIEW
DSBGA
YZF
9
250
TBD
Call TI
Call TI
-55 to 150
22206
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
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provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
D: Max = 1.49 mm, Min = 1.43 mm
E: Max = 1.49 mm, Min = 1.43 mm
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