Am29BDS128H/Am29BDS640H Data Sheet RETIRED PRODUCT (AM29BDS40H ONLY) ( The Am29BDS640H has been retired and is not recommended for designs. For new designs, S29WS064K supersedes Am29BDS640H. Please refer to the S29WS-K family data sheet for specifications and ordering information. The Am29BDS128H is available and is not affected by this revision. The following document contains information on Spansion memory products. Continuity of Specifications There is no change to this data sheet as a result of offering the device as a Spansion product. Any changes that have been made are the result of normal data sheet improvement and are noted in the document revision summary. Future routine revisions will occur when appropriate, and changes will be noted in a revision summary. Continuity of Ordering Part Numbers Spansion continues to support the Am29BDS640H part numbers. To order these products, please use only the Ordering Part Numbers listed in this document. For More Information Please contact your local sales office for additional information about Spansion memory solutions. Publication Number 27024 Revision B Amendment 3 Issue Date May 10, 2006 THIS PAGE LEFT INTENTIONALLY BLANK. DATA SHEET Am29BDS128H/Am29BDS640H 128 or 64 Megabit (8 M or 4 M x 16-Bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory The Am29BDS640H has been retired and is not recommended for designs. For new designs, S29WS064K supersedes Am29BDS640H. Please refer to the S29WS-K family data sheet for specifications and ordering information. The Am29BDS128H is available and is not affected by this revision. DISTINCTIVE CHARACTERISTICS ARCHITECTURAL ADVANTAGES HARDWARE FEATURES ■ Single 1.8 volt read, program and erase (1.65 to 1.95 volt) ■ ■ Manufactured on 0.13 µm process technology ■ VersatileIO™ (VIO) Feature — Device generates data output voltages and tolerates data input voltages as determined by the voltage on the VIO pin — 1.8V compatible I/O signals ■ Simultaneous Read/Write operation — Data can be continuously read from one bank while executing erase/program functions in other bank — Zero latency between read and write operations — Four bank architecture: 128 Mb has 16/48/48/16 Mbit banks 64 Mb has 8/24/24/8 Mbit banks ■ ■ ■ — Reduced Wait-state handshaking option further reduces initial access cycles required for burst accesses beginning on even addresses ■ Hardware reset input (RESET#) — Hardware method to reset the device for reading array data ■ WP# input — Write protect (WP#) function allows protection of the four highest and four lowest 4 kWord boot sectors, regardless of sector protect status Persistent Sector Protection — A command sector protection method to lock combinations of individual sectors and sector groups to prevent program or erase operations within that sector ■ Programable Burst Interface — 2 Modes of Burst Read Operation — Linear Burst: 8, 16, and 32 words with wrap-around — Continuous Sequential Burst SecSiTM (Secured Silicon) Sector region — Up to 128 words accessible through a command sequence — Up to 64 factory-locked words — Up to 64 customer-lockable words Sector Architecture — Banks A and D each contain both 4 Kword sectors and 32 Kword sectors; Banks B and C contain ninety-six 32 Kword sectors — Sixteen 4 Kword boot sectors Half of the boot sectors are at the top of the address range; half are at the bottom of address range ■ ■ Minimum 1 million erase cycle guarantee per sector 20-year data retention at 125°C — Reliable operation for the life of the system ■ 80-ball FBGA package (128 Mb) or 64-ball FBGA (64 Mb) package — Sectors can be locked and unlocked in-system at VCC level ■ Password Sector Protection — A sophisticated sector protection method to lock combinations of individual sectors and sector groups to prevent program or erase operations within that sector using a user-defined 64-bit password ■ ACC input: Acceleration function reduces programming time; all sectors locked when ACC = VIL ■ CMOS compatible inputs, CMOS compatible outputs ■ Low VCC write inhibit SOFTWARE FEATURES ■ Supports Common Flash Memory Interface (CFI) ■ Software command set compatible with JEDEC 42.4 standards — Backwards compatible with Am29F and Am29LV families ■ Data# Polling and toggle bits — Provides a software method of detecting program and erase operation completion Erase Suspend/Resume — Suspends an erase operation to read data from, or program data to, a sector that is not being erased, then resumes the erase operation PERFORMANCE CHARCTERISTICS ■ ■ Handshaking feature — Provides host system with minimum possible latency by monitoring RDY Read access times at 75/66/54 MHz (CL=30 pF) — Burst access times of 9.3/11/13.5 ns at industrial temperature range — Synchronous latency of 49/56/69 ns ■ — Asynchronous random access times of 45/50/55 ns Power dissipation (typical values, CL = 30 pF) — Burst Mode Read: 10 mA — Simultaneous Operation: 25 mA — Program/Erase: 15 mA — Standby mode: 0.2 µA ■ Unlock Bypass Program command — Reduces overall programming time when issuing multiple program command sequences ■ Burst Suspend/Resume — Suspends a burst operation to allow system use of the address and data bus, than resumes the burst at the previous state Publication# 27024 Rev: B Amendment: 3 Issue Date: May 10, 2006 D A T A S H E E T GENERAL DESCRIPTION The Am29BDS128H/Am29BDS640H is a 128 or 64 Mbit, 1.8 Volt-only, simultaneous Read/Write, Burst Mode Flash memory device, organized as 8,388,608 or 4,194,304 words of 16 bits each. This device uses a single VCC of 1.65 to 1.95 V to read, program, and erase the memory array. A 12.0-volt VHH on ACC may be used for faster program performance if desired. The device can also be programmed in standard EPROM programmers. At 75 MHz, the device provides a burst access of 9.3 ns at 30 pF with a latency of 49 ns at 30 pF. At 66 MHz, the device provides a burst access of 11 ns at 30 pF with a latency of 56 ns at 30 pF. At 54 MHz, the device provides a burst access of 13.5 ns at 30 pF with a latency of 69ns at 30 pF. The device operates within the industrial temperature range of -40°C to +85°C. The device is offered in FBGA packages. The Simultaneous Read/Write architecture provides simultaneous operation by dividing the memory space into four banks. The device can improve overall system performance by allowing a host system to program or erase in one bank, then immediately and simultaneously read from another bank, with zero latency. This releases the system from waiting for the completion of program or erase operations. The device is divided as shown in the following table: Quantity Bank 128 Mb 64 Mb Size 8 8 4 Kwords 31 15 32 Kwords B 96 48 32 Kwords C 96 48 32 Kwords 31 15 32 Kwords 8 8 4 Kwords A D The VersatileIO™ (VIO) control allows the host system to set the voltage levels that the device generates at its data outputs and the voltages tolerated at its data inputs to the same voltage level that is asserted on the VIO pin. The device uses Chip Enable (CE#), Write Enable (WE#), Address Valid (AVD#) and Output Enable (OE#) to control asynchronous read and write operations. For burst operations, the device additionally requires Ready (RDY), and Clock (CLK). This implementation allows easy interface with minimal glue logic to a wide range of microprocessors/microcontrollers for high performance read operations. The burst read mode feature gives system designers flexibility in the interface to the device. The user can preset the burst length and wrap through the same memory space, or read the flash array in continuous mode. 2 The clock polarity feature provides system designers a choice of active clock edges, either rising or falling. The active clock edge initiates burst accesses and determines when data will be output. The device is entirely command set compatible with the JEDEC 42.4 single-power-supply Flash standard. Commands are written to the command register using standard microprocessor write timing. Register contents serve as inputs to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices. The Erase Suspend/Erase Resume feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved. If a read is needed from the SecSi Sector area (One Time Program area) after an erase suspend, then the user must use the proper command sequence to enter and exit this region. The hardware RESET# pin terminates any operation in progress and resets the internal state machine to reading array data. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system microprocessor to read boot-up firmware from the Flash memory device. The host system can detect whether a program or erase operation is complete by using the device status bit DQ7 (Data# Polling) and DQ6/DQ2 (toggle bits). After a program or erase cycle has been completed, the device automatically returns to reading array data. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low VCC detector that automatically inhibits write operations during power transitions. The device also offers two types of data protection at the sector level. When at VIL, WP# locks the four highest and four lowest boot sectors. The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly reduced in both modes. AMD Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunnelling. The data is programmed using hot electron injection. Am29BDS128H/Am29BDS640H 27024B3 May 10, 2006 D A T A S H E E T TABLE OF CONTENTS Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 5 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Block Diagram of Simultaneous Operation Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . 7 Special Handling Instructions for FBGA Package .................... 8 Input/Output Descriptions . . . . . . . . . . . . . . . . . . . 9 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Ordering Information . . . . . . . . . . . . . . . . . . . . . . 10 Device Bus Operations . . . . . . . . . . . . . . . . . . . . . 11 Table 1. Device Bus Operations ....................................................11 Requirements for Asynchronous Read Operation (Non-Burst) ............................................................ 11 Requirements for Synchronous (Burst) Read Operation ........ 11 8-, 16-, and 32-Word Linear Burst with Wrap Around ............ 12 Table 2. Burst Address Groups .......................................................12 Burst Suspend/Resume .......................................................... 12 Configuration Register ............................................................ 13 Reduced Wait-state Handshaking Option .............................. 13 Simultaneous Read/Write Operations with Zero Latency ....... 13 Writing Commands/Command Sequences ............................ 13 Accelerated Program Operation ............................................. 14 Autoselect Mode ..................................................................... 14 Table 3. Autoselect Codes (High Voltage Method) ........................15 Table 4. Am29BDS128H Boot Sector/Sector Block Addresses for Protection/Unprotection ........................................................................16 Table 5. Am29BDS640H Boot Sector/Sector Block Addresses for Protection/Unprotection ........................................................................17 Sector/Sector Block Protection and Unprotection .................. 17 Sector Protection .................................................................... 17 Selecting a Sector Protection Mode ....................................... 17 Persistent Sector Protection ................................................... 18 Persistent Protection Bit (PPB) ............................................... 18 Persistent Protection Bit Lock (PPB Lock) ............................. 18 Dynamic Protection Bit (DYB) ................................................ 18 Table 6. Sector Protection Schemes ...............................................19 Persistent Sector Protection Mode Locking Bit ...................... 19 Password Protection Mode ..................................................... 19 Password and Password Mode Locking Bit ........................... 20 64-bit Password ...................................................................... 20 Persistent Protection Bit Lock ................................................. 20 High Voltage Sector Protection .............................................. 20 Standby Mode ........................................................................ 20 Automatic Sleep Mode ........................................................... 21 RESET#: Hardware Reset Input ............................................. 21 Output Disable Mode .............................................................. 21 Figure 1. Temporary Sector Unprotect Operation........................... 21 Figure 2. In-System Sector Protection/ Sector Unprotection Algorithms ...................................................... 22 SecSi™ (Secured Silicon) Sector Flash Memory Region ............................................................ 23 Factory-Locked Area (64 words) ............................................ 23 Table 7. SecSiTM Sector Addresses ...............................................23 Customer-Lockable Area (64 words) ...................................... 23 SecSi Sector Protection Bits ................................................... 23 Hardware Data Protection ...................................................... 23 Write Protect (WP#) ................................................................ 24 May 10, 2006 27024B3 Low VCC Write Inhibit .............................................................. 24 Write Pulse “Glitch” Protection ................................................ 24 Logical Inhibit .......................................................................... 24 Power-Up Write Inhibit ............................................................ 24 Table 8. CFI Query Identification String ......................................... 24 Table 9. System Interface String .................................................... 25 Table 10. Device Geometry Definition ........................................... 25 Table 11. Primary Vendor-Specific Extended Query ..................... 26 Table 12. Am29BDS128H Sector Address Table .......................... 27 Table 13. Am29BDS640H Sector Address Table .......................... 31 Command Definitions . . . . . . . . . . . . . . . . . . . . . 33 Reading Array Data ................................................................ 33 Set Configuration Register Command Sequence ................... 33 Figure 3. Synchronous/Asynchronous State Diagram ................... 33 Read Mode Setting ................................................................. 33 Programmable Wait State Configuration ................................ 33 Table 14. Programmable Wait State Settings ................................ 34 Reduced Wait-state Handshaking Option ............................... 34 Table 15. Wait States for Reduced Wait-state Handshaking ........ 34 Standard Handshaking Option ................................................ 35 Table 16. Wait States for Standard Handshaking .......................... 35 Read Mode Configuration ....................................................... 35 Table 17. Read Mode Settings ....................................................... 35 Burst Active Clock Edge Configuration ................................... 35 RDY Configuration .................................................................. 35 Table 18. Configuration Register ................................................... 36 Reset Command ..................................................................... 36 Autoselect Command Sequence ............................................ 36 Table 19. Autoselect Data .............................................................. 37 Enter SecSi™ Sector/Exit SecSi Sector Command Sequence .............................................................. 37 Program Command Sequence ............................................... 37 Unlock Bypass Command Sequence ..................................... 37 Figure 4. Program Operation ......................................................... 38 Chip Erase Command Sequence ........................................... 38 Sector Erase Command Sequence ........................................ 38 Erase Suspend/Erase Resume Commands ........................... 39 Figure 5. Erase Operation.............................................................. 40 Password Program Command ................................................ 40 Password Verify Command .................................................... 40 Password Protection Mode Locking Bit Program Command .. 40 Persistent Sector Protection Mode Locking Bit Program Command ....................................................................................... 40 SecSi Sector Protection Bit Program Command .................... 41 PPB Lock Bit Set Command ................................................... 41 DYB Write Command ............................................................. 41 Password Unlock Command .................................................. 41 Figure 6. PPB Program Algorithm.................................................. 42 PPB Program Command ........................................................ 43 All PPB Erase Command ........................................................ 43 Figure 7. PPB Erase Algorithm ...................................................... 44 DYB Write Command ............................................................. 45 PPB Status Command ............................................................ 45 PPB Lock Bit Status Command .............................................. 45 DYB Status Command ............................................................ 45 Command Definitions ............................................................. 46 Table 20. Memory Array Command Definitions ............................ 46 Table 21. Sector Protection Command Definitions ....................... 47 Am29BDS128H/Am29BDS640H 3 D A T A Write Operation Status . . . . . . . . . . . . . . . . . . . . . 48 DQ7: Data# Polling ................................................................. 48 Figure 8. Data# Polling Algorithm ................................................... 48 DQ6: Toggle Bit I .................................................................... 49 Figure 9. Toggle Bit Algorithm......................................................... 50 DQ2: Toggle Bit II ................................................................... 50 Table 22. DQ6 and DQ2 Indications ...............................................51 Reading Toggle Bits DQ6/DQ2 .............................................. 51 DQ5: Exceeded Timing Limits ................................................ 51 DQ3: Sector Erase Timer ....................................................... 51 Table 23. Write Operation Status ....................................................52 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . 53 Figure 10. Maximum Negative Overshoot Waveform ..................... 53 Figure 11. Maximum Positive Overshoot Waveform....................... 53 Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . 53 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 54 CMOS Compatible . . . . . . . . . . . . . . . . . . . . . . . . . 54 Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Figure 12. Test Setup...................................................................... 55 Table 24. Test Specifications ..........................................................55 Key to Switching Waveforms . . . . . . . . . . . . . . . 55 Switching Waveforms . . . . . . . . . . . . . . . . . . . . . 55 Figure 13. Input Waveforms and Measurement Levels .................. 55 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 56 VCC Power-up ......................................................................... 56 Figure 14. VCC Power-up Diagram ................................................. 56 CLK Characterization ............................................................. 56 Figure 15. CLK Characterization..................................................... 56 Synchronous/Burst Read ....................................................... 57 Figure 16. CLK Synchronous Burst Mode Read (rising active CLK) ... .........................................................................................................58 Figure 17. CLK Synchronous Burst Mode Read (Falling Active Clock) .........................................................................................................58 Figure 18. Synchronous Burst Mode Read..................................... 59 Figure 19. 8-word Linear Burst with Wrap Around .......................... 59 Figure 20. Linear Burst with RDY Set One Cycle Before Data ....... 60 Figure 21. Reduced Wait-state Handshake Burst Suspend/Resume at an Even Address............................................................................. 61 Figure 22. Reduced Wait-state Handshake Burst Suspend/Resume at an Odd Address .............................................................................. 61 Figure 23. Reduced Wait-state Handshake Burst Suspend/Resume at Address 3Eh (or Offset from 3Eh)................................................... 62 Figure 24. Reduced Wait-state Handshake Burst Suspend/Resume at Address 3Fh (or Offset from 3Fh by a Multiple of 64) ..................... 62 Figure 25. Standard Handshake Burst Suspend Prior to Initial Access .........................................................................................................63 Figure 26. Standard Handshake Burst Suspend at or after Initial Ac- 4 S H E E T cess................................................................................................ 63 Figure 27. Standard Handshake Burst Suspend at Address 3Fh (Starting Address 3Dh or Earlier)............................................................ 64 Figure 28. Standard Handshake Burst Suspend at Address 3Eh/3Fh (Without a Valid Initial Access)....................................................... 64 Figure 29. Standard Handshake Burst Suspend at Address 3Eh/3Fh (with 1 Access CLK)....................................................................... 65 Figure 30. Read Cycle for Continuous Suspend............................ 65 Asynchronous Mode Read .................................................... 66 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 67 Figure 31. Asynchronous Mode Read with Latched Addresses .... 67 Figure 32. Asynchronous Mode Read............................................ 67 Figure 33. Reset Timings ............................................................... 68 Erase/Program Operations ..................................................... 69 Figure 34. Asynchronous Program Operation Timings: AVD# Latched Addresses ...................................................................................... 70 Figure 35. Asynchronous Program Operation Timings: WE# Latched Addresses ...................................................................................... 71 Figure 36. Synchronous Program Operation Timings: WE# Latched Addresses ...................................................................................... 72 Figure 37. Synchronous Program Operation Timings: CLK Latched Addresses ...................................................................................... 73 Figure 38. Chip/Sector Erase Command Sequence ...................... 74 Figure 39. Accelerated Programming Timing................................. 75 Figure 40. Data# Polling Timings (During Embedded Algorithm) .. 76 Figure 41. Toggle Bit Timings (During Embedded Algorithm)........ 76 Figure 42. Synchronous Data Polling Timings/Toggle Bit Timings 77 Figure 43. DQ2 vs. DQ6................................................................. 77 Temporary Sector Unprotect .................................................. 78 Figure 44. Temporary Sector Unprotect Timing Diagram .............. Figure 45. Sector/Sector Block Protect and Unprotect Timing Diagram ............................................................. Figure 46. Latency with Boundary Crossing .................................. Figure 47. Latency with Boundary Crossing into Program/Erase Bank ............................................................... Figure 48. Example of Wait States Insertion.................................. Figure 49. Back-to-Back Read/Write Cycle Timings ...................... 78 79 80 81 82 83 Erase and Programming Performance . . . . . . . 84 BGA Ball Capacitance . . . . . . . . . . . . . . . . . . . . . 84 Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 85 VBB080—80-ball Fine-Pitch Ball Grid Array (BGA) 11.5 x 9 mm Package ........................................................................ 85 VBD064—64-ball Fine-Pitch Ball Grid Array (BGA) 9 x 8 mm Package ........................................................................ 86 Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 87 Am29BDS128H/Am29BDS640H 27024B3 May 10, 2006 D A T A S H E E T PRODUCT SELECTOR GUIDE Part Number Am29BDS128H/Am29BDS640H Burst Frequency VCC, VIO = 1.65 – 1.95 V Speed Option Max Initial Synchronous Access Time, ns (TIACC) Reduced Wait-state Handshaking; Even Address Max Initial Synchronous Access Time, ns (TIACC) Reduced Wait-state Handshaking; Odd Address; or Standard Handshaking Max Burst Access Time, ns (TBACC) Max Asynchronous Access Time, ns (TACC) 66 MHz 54 MHz E8, E9 D8, D9 56 69 71 87.5 11 13.5 50 55 11 13.5 Max CE# Access Time, ns (TCE) Max OE# Access Time, ns (TOE) Note: Speed Options ending in “8” indicate the “reduced wait-state handshaking” option, which speeds initial synchronous accesses for even addresses. Speed Options ending in “9” indicate the “standard handshaking” option. See the AC Characteristics section of this data sheet for full specifications. BLOCK DIAGRAM VCC DQ15–DQ0 VSS RDY Buffer VIO RDY Erase Voltage Generator Input/Output Buffers WE# WP# ACC State Control Command Register PGM Voltage Generator Chip Enable Output Enable Logic CE# OE# VCC Detector AVD# CLK Burst State Control Timer Burst Address Counter Address Latch RESET# Data Latch Y-Decoder Y-Gating X-Decoder Cell Matrix Amax–A0 Note: Amax = A22 (128 Mb) or A21 (64 Mb) May 10, 2006 27024B3 Am29BDS128H/Am29BDS640H 5 D A T A S H E E T BLOCK DIAGRAM OF SIMULTANEOUS OPERATION CIRCUIT VCC Bank A Latches and Control Logic Bank A Address Y-Decoder VSS VIO DQ15–DQ0 Amax–A0 X-Decoder OE# WP# ACC RESET# WE# CE# AVD# RDY DQ15–DQ0 Bank B Latches and Control Logic Y-Decoder Bank B Address DQ15–DQ0 X-Decoder Amax–A0 STATE CONTROL & COMMAND REGISTER DQ15–DQ0 Status Control Amax–A0 Amax –A0 Bank C Latches and Control Logic Bank C Address Y-Decoder X-Decoder DQ15–DQ0 Amax –A0 6 Bank D Am29BDS128H/Am29BDS640H Latches and Control Logic Bank D Address Y-Decoder X-Decoder DQ15–DQ0 27024B3 May 10, 2006 D A T A S H E E T CONNECTION DIAGRAM 80-ball Fine-Pitch Ball Grid Array Top View, Balls Facing Down (Am29BDS128H only) A8 B8 C8 D8 E8 F8 G8 H8 J8 K8 L8 M8 NC NC NC A22 NC VIO VSS NC NC NC NC NC A7 B7 C7 D7 E7 F7 G7 H7 J7 K7 L7 M7 NC NC A13 A12 A14 A15 A16 NC DQ15 VSS NC NC C6 D6 E6 F6 G6 H6 J6 K6 A9 A8 A10 A11 DQ7 DQ14 DQ13 DQ6 C5 D5 E5 F5 G5 H5 J5 K5 DQ4 WE# RESET# A21 A19 DQ5 DQ12 VCC C4 D4 E4 F4 G4 H4 J4 K4 RDY ACC A18 A20 DQ2 DQ10 DQ11 DQ3 C3 D3 E3 F3 G3 H3 J3 K3 A7 A17 A6 A5 DQ0 DQ8 DQ9 DQ1 A2 B2 C2 D2 E2 F2 G2 H2 J2 K2 L2 M2 NC NC A3 A4 A2 A1 A0 CE# OE# VSS NC NC A1 B1 C1 D1 E1 F1 G1 H1 J1 K1 L1 M1 NC NC NC VCC CLK WP# AVD# VIO VSS NC NC NC May 10, 2006 27024B3 Am29BDS128H/Am29BDS640H 7 D A T A S H E E T 64-ball Fine-Pitch Ball Grid Array Top View, Balls Facing Down (Am29BDS640H only) A8 B8 C8 D8 E8 F8 G8 H8 NC NC NC VIO VSS NC NC NC A7 B7 C7 D7 E7 F7 G7 H7 A13 A12 A14 A15 A16 NC DQ15 VSS A6 B6 C6 D6 E6 F6 G6 H6 A9 A8 A10 A11 DQ7 DQ14 DQ13 DQ6 A5 B5 C5 D5 E5 F5 G5 H5 WE# RESET# A21 A19 DQ5 DQ12 VCC DQ4 A4 B4 C4 D4 E4 F4 G4 H4 RDY ACC A18 A20 DQ2 DQ10 DQ11 DQ3 A3 B3 C3 D3 E3 F3 G3 H3 A7 A17 A6 A5 DQ0 DQ8 DQ9 DQ1 A2 B2 C2 D2 E2 F2 G2 H2 A3 A4 A2 A1 A0 CE# OE# VSS A1 B1 C1 D1 E1 F1 G1 H1 NC VCC CLK WP# AVD# VIO VSS NC Special Handling Instructions for FBGA Package Special handling is required for Flash Memory products in FBGA packages. 8 Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning methods. The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150°C for prolonged periods of time. Am29BDS128H/Am29BDS640H 27024B3 May 10, 2006 D A T A S H E E T INPUT/OUTPUT DESCRIPTIONS Amax–A0 = Address inputs Amax = A22 (128 Mb) or A21 (64 Mb) AVD# = Address Valid input. Indicates to device that the valid address is present on the address inputs (Amax–A0). DQ15–DQ0 = Data input/output CE# = Chip Enable input. Asynchronous relative to CLK for the Burst mode. OE# = Output Enable input. Asynchronous relative to CLK for the Burst mode. Low = for asynchronous mode, indicates valid address; for burst mode, causes starting address to be latched. WE# = Write Enable input. High = device ignores address inputs VCC = Device Power Supply (1.65 – 1.95 V). VIO = Input & Output Buffer Power Supply (1.65 – 1.95 V). VSS = Ground NC = No Connect; not connected internally RDY = Ready output; In Synchronous Mode, indicates the status of the Burst read. RESET# = Hardware reset input. Low = device resets and returns to reading array data WP# = Hardware write protect input. At VIL, disables program and erase functions in the four highest and four lowest sectors. At VIH, does not protect any sectors. ACC = At VHH, accelerates programming; automatically places device in unlock bypass mode. At VIL, locks all sectors. Should be at VIH for all other conditions. Low = data invalid. High = data valid. In Asynchronous Mode, indicates the status of the internal program and erase function. LOGIC SYMBOL Low = program/erase in progress. High Impedance = program/erase completed. CLK = 23 or 22 CLK is not required in asynchronous mode. In burst mode, after the initial word is output, subsequent active edges of CLK increment the internal address counter. Amax–A0 CLK 16 DQ15–DQ0 WP# ACC CE# OE# WE# RESET# RDY AVD# May 10, 2006 27024B3 Am29BDS128H/Am29BDS640H 9 D A T A S H E E T ORDERING INFORMATION The order number (Valid Combination) is formed by the following: Am29BDS 128 H E 8 VK I TEMPERATURE RANGE I = Industrial (–40°C to +85°C) PACKAGE TYPE VK = VF = VM = 80-Ball Fine-Pitch Ball Grid Array (BGA) 0.80 mm pitch, 11.5 x 9 mm package (VBB080) 80-Ball Fine-Pitch Ball Grid Array (BGA) 0.80 mm pitch, 11.5 x 9mm, Pb-free Package (VBB080) 64-Ball Fine-Pitch Ball Grid Array (BGA) 0.80 mm pitch, 8 X 9 mm package (VBD064) VIO AND HANDSHAKING OPTIONS 8 9 = = VIO = 1.8 V, reduced wait-state handshaking enabled VIO = 1.8 V, standard handshaking SPEED E D = = 66 MHz 54 MHz PROCESS TECHNOLOGY H = 0.13 µm DENSITY 128 = 64 = 128 Mbit (8 M x 16-bit) 64 Mbit (4 M x 16-bit) DEVICE FAMILY Am29BDS CMOS Flash Memory, Simultaneous Read/Write, Burst Mode Flash Memory, 1.8 Volt-only Read, Program, and Erase Valid Combinations Order Number Package Marking Am29BDS128HE8 BS128HE8V Am29BDS128HE9 BS128HE9V Burst Frequency (MHz) Density 66 VKI Am29BDS128HD8 BS128HD8V Am29BDS128HD9 BS128HD9V Am29BDS128HE8 BS128HE8VF 54 128 Mbit 66 Am29BDS128HE9 BS128HE9VF VFI Am29BDS128HD8 BS128HD8VF Am29BDS128HD9 BS128HD9VF Am29BDS640HE8 BS640HE8V Am29BDS640HE9 BS640HE9V 54 66 VMI Am29BDS640HD8 64 Mbit BS640HD8V 54 Am29BDS640HD9 BS640HD9V Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. 10 Am29BDS128H/Am29BDS640H 27024B3 May 10, 2006 D A T A S H E E T DEVICE BUS OPERATIONS This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory location. The register is composed of latches that store the commands, along with the address and data information needed to execute the command. The contents of Table 1. the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. Table 1 lists the device bus operations, the inputs and control levels they require, and the resulting output. The following subsections describe each of these operations in further detail. Device Bus Operations CE# OE# WE# Amax–0 DQ15–0 RESET# CLK (See Note) Asynchronous Read - Addresses Latched L L H Addr In I/O H X Asynchronous Read - Addresses Steady State L L H Addr In I/O H X L Asynchronous Write L H L Addr In I/O H X L Synchronous Write L H L Addr In I/O H Standby (CE#) H X X HIGH Z HIGH Z H X X Hardware Reset X X X HIGH Z HIGH Z L X X Load Starting Burst Address L X H Addr In X H Advance Burst to next address with appropriate Data presented on the Data Bus L L H HIGH Z Burst Data Out H H Terminate current Burst read cycle H X H HIGH Z HIGH Z H X Terminate current Burst read cycle via RESET# X X H HIGH Z HIGH Z L Terminate current Burst read cycle and start new Burst read cycle L X H HIGH Z I/O H Operation AVD# Burst Read Operations X X Legend: L = Logic 0, H = Logic 1, X = Don’t Care, S = Stable Logic 0 or 1 but no transitions. Note: Default active edge of CLK is the rising edge. Requirements for Asynchronous Read Operation (Non-Burst) To read data from the memory array, the system must first assert a valid address on Amax–A0, while driving AVD# and CE# to VIL. WE# should remain at VIH. The rising edge of AVD# latches the address. The data will appear on DQ15–DQ0. Since the memory array is divided into four banks, each bank remains enabled for read access until the command register contents are altered. Address access time (tACC) is equal to the delay from stable addresses to valid output data. The chip enable access time (t C E ) is the delay from the stable addresses and stable CE# to valid data at the outputs. The output enable access time (tOE) is the delay from the falling edge of OE# to valid data at the output. May 10, 2006 27024B3 The internal state machine is set for reading array data in asynchronous mode upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. Requirements for Synchronous (Burst) Read Operation The device is capable of continuous sequential burst operation and linear burst operation of a preset length. When the device first powers up, it is enabled for asynchronous read operation. Prior to entering burst mode, the system should determine how many wait states are desired for the initial word (tIACC) of each burst access, what mode of burst operation is desired, which edge of the clock will be the Am29BDS128H/Am29BDS640H 11 D A T A active clock edge, and how the RDY signal will transition with valid data. The system would then write the configuration register command sequence. See “Set Configuration Register Command Sequence” section on page 33 and “Command Definitions” section on page 33 for further details. Once the system has written the “Set Configuration Register” command sequence, the device is enabled for synchronous reads only. The initial word is output tIACC after the active edge of the first CLK cycle. Subsequent words are output tBACC after the active edge of each successive clock cycle, which automatically increments the internal address counter. Note that the device has a fixed internal address boundary that occurs every 64 words, starting at address 00003Fh. During the time the device is outputting data at this fixed internal address boundary (address 00003Fh, 00007Fh, 0000BFh, etc.), a two cycle latency occurs before data appears for the next address (address 000040h, 000080h, 0000C0h, etc.). The RDY output indicates this condition to the system by pulsing low. For standard handshaking devices, there is no two cycle latency between 3Fh and 40h (or offset from these values by a multiple of 64) if the latched address was 3Eh or 3Fh or offset from these values by a multiple of 64). See Figure 46, “Latency with Boundary Crossing,” on page 80. For reduced wait-state handshaking devices, if the address latched is 3Eh or 3Fh (or offset from these values by a multiple of 64) two additional cycle latency occurs prior to the initial access and the two cycle latency between 3Fh and 40h (or offset from these values by a multiple of 64) will not occur. The device will continue to output sequential burst data, wrapping around to address 000000h after it reaches the highest addressable memory location, until the system drives CE# high, RESET# low, or AVD# low in conjunction with a new address. See Table 1, “Device Bus Operations,” on page 11. If the host system crosses the bank boundary while reading in burst mode, and the device is not programming or erasing, a two-cycle latency will occur as described above in the subsequent bank. If the host system crosses the bank boundary while the device is programming or erasing, the device will provide read status information. The clock will be ignored. After the host has completed status reads, or the device has completed the program or erase operation, the host can restart a burst operation using a new address and AVD# pulse. If the clock frequency is less than 6 MHz during a burst mode operation, additional latencies will occur. RDY indicates the length of the latency by pulsing low. 12 S H E E T 8-, 16-, and 32-Word Linear Burst with Wrap Around The remaining three modes are of the linear wrap around design, in which a fixed number of words are read from consecutive addresses. In each of these modes, the burst addresses read are determined by the group within which the starting address falls. The groups are sized according to the number of words read in a single burst sequence for a given mode (see Table 2.) Table 2. Mode Burst Address Groups Group Size Group Address Ranges 8-word 8 words 0-7h, 8-Fh, 10-17h,... 16-word 16 words 0-Fh, 10-1Fh, 20-2Fh,... 32-word 32 words 00-1Fh, 20-3Fh, 40-5Fh,... As an example: if the starting address in the 8-word mode is 39h, the address range to be read would be 38-3Fh, and the burst sequence would be 39-3A-3B-3C-3D-3E-3F-38h-etc. The burst sequence begins with the starting address written to the device, but wraps back to the first address in the selected group. In a similar fashion, the 16-word and 32-word Linear Wrap modes begin their burst sequence on the starting address written to the device, and then wrap back to the first address in the selected address group. Note that in these three burst read modes the address pointer does not cross the boundary that occurs every 64 words; thus, no wait states are inserted (except during the initial access). The RDY pin indicates when data is valid on the bus. The devices can wrap through a maximum of 128 words of data (8 words up to 16 times, 16 words up to 8 times, or 32 words up to 4 times) before requiring a new synchronous access (latching of a new address). Burst Suspend/Resume The Burst Suspend/Resume feature allows the system to temporarily suspend a synchronous burst operation during the initial access (before data is available) or after the device is outputting data. When the burst operation is suspended, any previously latched internal data and the current state are retained. Burst Suspend requires CE# to be asserted, WE# de-asserted, and the initial address latched by AVD# or the CLK edge. Burst Suspend occurs when OE# is de-asserted. See Figure 21, “Reduced Wait-state Handshake Burst Suspend/Resume at an Even Address,” on page 61, Figure 22, “Reduced Wait-state Handshake Burst Suspend/Resume at an Odd Address,” on page 61, Figure 23, “Reduced Wait-state Handshake Burst Suspend/Resume at Address 3Eh (or Offset from 3Eh),” on page 62, Figure 24, “Reduced Wait-state Handshake Burst Suspend/Resume at Am29BDS128H/Am29BDS640H 27024B3 May 10, 2006 D A T A Address 3Fh (or Offset from 3Fh by a Multiple of 64),” on page 62, Figure 25, “Standard Handshake Burst Suspend Prior to Initial Access,” on page 63, Figure 26, “Standard Handshake Burst Suspend at or after Initial Access,” on page 63, Figure 27, “Standard Handshake Burst Suspend at Address 3Fh (Starting Address 3Dh or Earlier),” on page 64, Figure 28, “Standard Handshake Burst Suspend at Address 3Eh/3Fh (Without a Valid Initial Access),” on page 64, and Figure 29, “Standard Handshake Burst Suspend at Address 3Eh/3Fh (with 1 Access CLK),” on page 65. Burst plus Burst Suspend should not last longer than tRCC without re-latching an address or crossing an address boundary. To resume the burst access, OE# must be re-asserted. The next active CLK edge will resume the burst sequence where it had been suspended. See Figure 30, “Read Cycle for Continuous Suspend,” on page 65. The RDY pin is only controlled by CE#. RDY will remain active and is not placed into a high-impedance state when OE# is de-asserted. Configuration Register The device uses a configuration register to set the various burst parameters: number of wait states, burst read mode, active clock edge, RDY configuration, and synchronous mode active. Reduced Wait-state Handshaking Option The device can be equipped with a reduced wait-state handshaking feature that allows the host system to simply monitor the RDY signal from the device to determine when the initial word of burst data is ready to be read. The host system should use the programmable wait state configuration to set the number of wait states for optimal burst mode operation. The initial word of burst data is indicated by the rising edge of RDY after OE# goes low. The presence of the reduced wait-state handshaking feature may be verified by writing the autoselect command sequence to the device. See “Autoselect Command Sequence” for details. For optimal burst mode performance on devices without the reduced wait-state handshaking option, the host system must set the appropriate number of wait states in the flash device depending on clock frequency and the presence of a boundary crossing. See “Set Configuration Register Command Sequence” section on page 33 section for more information. The device will automatically delay RDY and data by one additional clock cycle when the starting address is odd. The autoselect function allows the host system to determine whether the flash device is enabled for reduced wait-state handshaking. See the “Autoselect Command Sequence” section for more information. May 10, 2006 27024B3 S H E E T Simultaneous Read/Write Operations with Zero Latency This device is capable of reading data from one bank of memory while programming or erasing in another bank of memory. An erase operation may also be suspended to read from or program to another location within the same bank (except the sector being erased). Figure 49, “Back-to-Back Read/Write Cycle Timings,” on page 83 shows how read and write cycles may be initiated for simultaneous operation with zero latency. R e fe r t o t h e D C C h a r a c t e r i s t i c s t a b l e fo r read-while-program and read-while-erase current specifications. Writing Commands/Command Sequences The device has the capability of performing an asynchronous or synchronous write operation. While the device is configured in Asynchronous read it is able to perform Asynchronous write operations only. CLK is ignored in the Asynchronous programming mode. When in the Synchronous read mode configuration, the device is able to perform both Asynchronous and Synchronous write operations. CLK and WE# address latch is supported in the Synchronous programming mode. During a synchronous write operation, to write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive AVD# and CE# to VIL, and OE# to V IH when providing an address to the device, and drive WE# and CE# to VIL, and OE# to VIH when writing commands or data. During an asynchronous write operation, the system must drive CE# and WE# to VIL and OE# to VIH when providing an address, command, and data. Addresses are latched on the last falling edge of WE# or CE#, while data is latched on the 1st rising edge of WE# or CE#. The asynchronous and synchronous programing operation is independent of the Set Device Read Mode bit in the Configuration Register (see Table 18, “Configuration Register,” on page 36). The device features an Unlock Bypass mode to facilitate faster programming. Once the device enters the Unlock Bypass mode, only two write cycles are required to program a word, instead of four. An erase operation can erase one sector, multiple sectors, or the entire device. Table 12, “Am29BDS128H Sector Address Table,” on page 27 indicates the address space that each sector occupies. The device address space is divided into four banks: Banks B and C contain only 32 Kword sectors, while Banks A and D contain both 4 Kword boot sectors in addition to 32 Kword sectors. A “bank address” is the address bits required to uniquely select a bank. Similarly, a “sector address” is the address bits required to uniquely select a sector. Am29BDS128H/Am29BDS640H 13 D A T A ICC2 in the “DC Characteristics” section on page 54 represents the active current specification for the write mode. The AC Characteristics section contains timing specification tables and timing diagrams for write operations. Accelerated Program Operation The device offers accelerated program operations through the ACC function. ACC is primarily intended to allow faster manufacturing throughput at the factory. If the system asserts VHH on this input, the device automatically enters the aforementioned Unlock Bypass mode and uses the higher voltage on the input to reduce the time required for program operations. The system would use a two-cycle program command sequence as required by the Unlock Bypass mode. Removing VHH from the ACC input returns the device to normal operation. Note that sectors must be unlocked prior to raising ACC to VHH. Note that the ACC pin must not be at VHH for operations other than accelerated programming, or device damage may result. In addition, the ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result. When at VIL, ACC locks all sectors. ACC should be at VIH for all other conditions. Autoselect Mode The autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier codes output from the internal register (which is separate from the memory array) on DQ15–DQ0. This mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding program- 14 S H E E T ming algorithm. However, the autoselect codes can also be accessed in-system through the command register. When using programming equipment, the autoselect mode requires VID on address pin A9. Address pins must be as shown in Table 3, “Autoselect Codes (High Voltage Method),” on page 15. In addition, when verifying sector protection, the sector address must appear on the appropriate highest order address bits (see Table 4, “Am29BDS128H Boot Sector/Sector Block Addresses for Protection/Unprotection,” on page 16). Table 3 shows the remaining address bits that are don’t care. When all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on DQ15–DQ0. However, the autoselect codes can also be accessed in-system through the command register, for instances when the device is erased or programmed in a system without access to high voltage on the A9 pin. The command sequence is illustrated in Table 20, “Memory Array Command Definitions,” on page 46. Note that if a Bank Address (BA) is asserted during the third write cycle of the autoselect command, the host system can read autoselect data that bank and then immediately read array data from the other bank, without exiting the autoselect mode. To access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in Table 20, “Memory Array Command Definitions,” on page 46. This method does not require VID. Autoselect mode may only be entered and used when in the asynchronous read mode. Refer to the “Autoselect Command Sequence” section on page 36 for more information. Am29BDS128H/Am29BDS640H 27024B3 May 10, 2006 D A T A S H E E T Table 3. Autoselect Codes (High Voltage Method) Description Manufacturer ID: AMD Amax A11 to to CE# OE# WE# RESET# A12 A10 L L H H X X A9 VID A8 A7 X X A6 L A5 to A4 A3 A2 A1 A0 X Device ID Read Cycle 1 Read Cycle 2 L L H H X X VID X L L L Read Cycle 3 Sector Protection Verification L L H H SA X VID X L L L DQ15 to DQ0 L L L L 0001h L L L H 227Eh H H H L 2218h (128 Mb) 221Eh (64 Mb) H H H H 2200h (128 Mb) 2201h (64 Mb) L L H L 0001h (protected), 0000h (unprotected) Indicator Bits L L H H X X VID X X L X L L H H DQ15 - DQ8 = 0 DQ7 - Factory Lock Bit 1 = Locked, 0 = Not Locked DQ6 -Customer Lock Bit 1 = Locked, 0 = Not Locked DQ5 = Handshake Bit 1 = Reduced wait-state Handshake, 0 = Standard Handshake DQ4 - DQ0 = 0 Hardware Sector Group Protection L L H H SA X VID X X X L L L H L 0001h (protected), 0000h (unprotected) Legend: L = Logic Low = VIL, H = Logic High = VIH, BA = Bank Address, SA = Sector Address, X = Don’t care. Notes: 1. The autoselect codes may also be accessed in-system via command sequences. 2. PPB Protection Status is shown on the data bus May 10, 2006 27024B3 Am29BDS128H/Am29BDS640H 15 D A T A Table 4. Am29BDS128H Boot Sector/Sector Block Addresses for Protection/Unprotection S H E E T Sector A22–A12 Sector/ Sector Block Size SA131-SA134 011111XXXXX 128 (4x32) Kwords SA135-SA138 100000XXXXX 128 (4x32) Kwords SA139-SA142 100001XXXXX 128 (4x32) Kwords SA143-SA146 100010XXXXX 128 (4x32) Kwords Sector A22–A12 Sector/ Sector Block Size SA0 00000000000 4 Kwords SA1 00000000001 4 Kwords SA147-SA150 100011XXXXX 128 (4x32) Kwords SA2 00000000010 4 Kwords SA151–SA154 100100XXXXX 128 (4x32) Kwords SA3 00000000011 4 Kwords SA155–SA158 100101XXXXX 128 (4x32) Kwords SA4 00000000100 4 Kwords SA159–SA162 100110XXXXX 128 (4x32) Kwords SA5 00000000101 4 Kwords SA163–SA166 100111XXXXX 128 (4x32) Kwords SA6 00000000110 4 Kwords SA167–SA170 101000XXXXX 128 (4x32) Kwords SA7 00000000111 4 Kwords SA171–SA174 101001XXXXX 128 (4x32) Kwords SA8 00000001XXX 32 Kwords SA175–SA178 101010XXXXX 128 (4x32) Kwords SA9 00000010XXX 32 Kwords SA179–SA182 101011XXXXX 128 (4x32) Kwords SA10 00000011XXX 32 Kwords SA183–SA186 101100XXXXX 128 (4x32) Kwords SA11–SA14 000001XXXXX 128 (4x32) Kwords SA187–SA190 101101XXXXX 128 (4x32) Kwords SA15–SA18 000010XXXXX 128 (4x32) Kwords SA191–SA194 101110XXXXX 128 (4x32) Kwords SA19–SA22 000011XXXXX 128 (4x32) Kwords SA195–SA198 101111XXXXX 128 (4x32) Kwords SA23-SA26 000100XXXXX 128 (4x32) Kwords SA199–SA202 110000XXXXX 128 (4x32) Kwords SA27-SA30 000101XXXXX 128 (4x32) Kwords SA203–SA206 110001XXXXX 128 (4x32) Kwords SA31-SA34 000110XXXXX 128 (4x32) Kwords SA207–SA210 110010XXXXX 128 (4x32) Kwords SA35-SA38 000111XXXXX 128 (4x32) Kwords SA211–SA214 110011XXXXX 128 (4x32) Kwords SA39-SA42 001000XXXXX 128 (4x32) Kwords SA215–SA218 110100XXXXX 128 (4x32) Kwords SA43-SA46 001001XXXXX 128 (4x32) Kwords SA219–SA222 110101XXXXX 128 (4x32) Kwords SA47-SA50 001010XXXXX 128 (4x32) Kwords SA223–SA226 110110XXXXX 128 (4x32) Kwords SA51–SA54 001011XXXXX 128 (4x32) Kwords SA227–SA230 110111XXXXX 128 (4x32) Kwords SA55–SA58 001100XXXXX 128 (4x32) Kwords SA231–SA234 111000XXXXX 128 (4x32) Kwords SA59–SA62 001101XXXXX 128 (4x32) Kwords SA235–SA238 111001XXXXX 128 (4x32) Kwords SA63–SA66 001110XXXXX 128 (4x32) Kwords SA239–SA242 111010XXXXX 128 (4x32) Kwords SA67–SA70 001111XXXXX 128 (4x32) Kwords SA243–SA246 111011XXXXX 128 (4x32) Kwords SA71–SA74 010000XXXXX 128 (4x32) Kwords SA247–SA250 111100XXXXX 128 (4x32) Kwords SA75–SA78 010001XXXXX 128 (4x32) Kwords SA251–SA254 111101XXXXX 128 (4x32) Kwords SA79–SA82 010010XXXXX 128 (4x32) Kwords SA255–SA258 111110XXXXX 128 (4x32) Kwords SA83–SA86 010011XXXXX 128 (4x32) Kwords SA259 11111100XXX 32 Kwords SA87–SA90 010100XXXXX 128 (4x32) Kwords SA260 11111101XXX 32 Kwords SA91–SA94 010101XXXXX 128 (4x32) Kwords SA261 11111110XXX 32 Kwords SA95–SA98 010110XXXXX 128 (4x32) Kwords SA262 11111111000 4 Kwords SA99–SA102 010111XXXXX 128 (4x32) Kwords SA263 11111111001 4 Kwords SA103–SA106 011000XXXXX 128 (4x32) Kwords SA264 11111111010 4 Kwords SA107–SA110 011001XXXXX 128 (4x32) Kwords SA265 11111111011 4 Kwords SA111–SA114 011010XXXXX 128 (4x32) Kwords SA266 11111111100 4 Kwords SA115–SA118 011011XXXXX 128 (4x32) Kwords SA267 11111111101 4 Kwords SA119–SA122 011100XXXXX 128 (4x32) Kwords SA268 11111111110 4 Kwords SA123–SA126 011101XXXXX 128 (4x32) Kwords SA269 11111111111 4 Kwords SA127–SA130 011110XXXXX 128 (4x32) Kwords 16 Am29BDS128H/Am29BDS640H 27024B3 May 10, 2006 D A T A Table 5. Am29BDS640H Boot Sector/Sector Block Addresses for Protection/Unprotection S H E E T Sector A21–A12 Sector/ Sector Block Size SA135 1111111001 4 Kwords SA136 1111111010 4 Kwords Sector A21–A12 Sector/ Sector Block Size SA137 1111111011 4 Kwords SA0 0000000000 4 Kwords SA138 1111111100 4 Kwords SA1 0000000001 4 Kwords SA139 1111111101 4 Kwords SA2 0000000010 4 Kwords SA140 1111111110 4 Kwords SA3 0000000011 4 Kwords SA141 1111111111 4 Kwords SA4 0000000100 4 Kwords SA5 0000000101 4 Kwords SA6 0000000110 4 Kwords SA7 0000000111 4 Kwords SA8 0000001XXX 32 Kwords SA9 0000010XXX 32 Kwords SA10 0000011XXX 32 Kwords SA11–SA14 00001XXXXX 128 (4x32) Kwords SA15–SA18 00010XXXXX 128 (4x32) Kwords SA19–SA22 00011XXXXX 128 (4x32) Kwords SA23-SA26 00100XXXXX 128 (4x32) Kwords SA27-SA30 00101XXXXX 128 (4x32) Kwords SA31-SA34 00110XXXXX 128 (4x32) Kwords SA35-SA38 00111XXXXX 128 (4x32) Kwords SA39-SA42 01000XXXXX 128 (4x32) Kwords SA43-SA46 01001XXXXX 128 (4x32) Kwords SA47-SA50 01010XXXXX 128 (4x32) Kwords SA51–SA54 01011XXXXX 128 (4x32) Kwords SA55–SA58 01100XXXXX 128 (4x32) Kwords SA59–SA62 01101XXXXX 128 (4x32) Kwords SA63–SA66 01110XXXXX 128 (4x32) Kwords SA67–SA70 01111XXXXX 128 (4x32) Kwords SA71–SA74 10000XXXXX 128 (4x32) Kwords SA75–SA78 10001XXXXX 128 (4x32) Kwords SA79–SA82 10010XXXXX 128 (4x32) Kwords SA83–SA86 10011XXXXX 128 (4x32) Kwords SA87–SA90 10100XXXXX 128 (4x32) Kwords SA91–SA94 10101XXXXX 128 (4x32) Kwords SA95–SA98 10110XXXXX 128 (4x32) Kwords Sector/Sector Block Protection and Unprotection The hardware sector protection feature disables both programming and erase operations in any sector. The hardware sector unprotection feature re-enables both program and erase operations in previously protected sectors. Sector protection/unprotection can be implemented via two methods. (Note: For the following discussion, the term “sector” applies to both sectors and sector blocks. A sector block consists of two or more adjacent sectors that are protected or unprotected at the same time (see Table 4, “Am29BDS128H Boot Sector/Sector Block Addresses for Protection/Unprotection,” on page 16 Sector Protection The Am29BDSxxxH family features several levels of sector protection, which can disable both the program and erase operations in certain sectors or sector groups: Persistent Sector Protection A command sector protection method that replaces the old 12 V controlled protection method. Password Sector Protection A highly sophisticated protection method that requires a password before changes to certain sectors or sector groups are permitted WP# Hardware Protection A write protect pin that can prevent program or erase operations in the outermost sectors. SA99–SA102 10111XXXXX 128 (4x32) Kwords SA103–SA106 11000XXXXX 128 (4x32) Kwords SA107–SA110 11001XXXXX 128 (4x32) Kwords SA111–SA114 11010XXXXX 128 (4x32) Kwords The WP# Hardware Protection feature is always available, independent of the software managed protection method chosen. SA115–SA118 11011XXXXX 128 (4x32) Kwords Selecting a Sector Protection Mode SA119–SA122 11100XXXXX 128 (4x32) Kwords SA123–SA126 11101XXXXX 128 (4x32) Kwords SA127–SA130 11110XXXXX 128 (4x32) Kwords SA131 1111100XXX 32 Kwords SA132 1111101XXX 32 Kwords SA133 1111110XXX 32 Kwords SA134 1111111000 4 Kwords All parts default to operate in the Persistent Sector Protection mode. The customer must then choose if the Persistent or Password Protection method is most desirable. There are two one-time programmable non-volatile bits that define which sector protection method will be used. If the customer decides to continue using the Persistent Sector Protection method, they must set the Persistent Sector Protection Mode May 10, 2006 27024B3 Am29BDS128H/Am29BDS640H 17 D A T A S H E E T Locking Bit. This will permanently set the part to operate only using Persistent Sector Protection. If the customer decides to use the password method, they must set the Password Mode Locking Bit. This will permanently set the part to operate only using password sector protection. dividual PPBs are programmable. It is the responsibility of the user to perfor m the preprogramming operation. Otherwise, an already erased sector PPBs has the potential of being over-erased. There is no h ar d wa r e m e c h a ni s m t o p r even t s ec to r P P B s over-erasure. It is important to remember that setting either the Persistent Sector Protection Mode Locking Bit or the Password Mode Locking Bit permanently selects the protection mode. It is not possible to switch between the two methods once a locking bit has been set. It is important that one mode is explicitly selected when the device is first programmed, rather than relying on the default mode alone. This is so that it is not possible for a system program or virus to later set the Password Mode Locking Bit, which would cause an unexpected shift from the default Persistent Sector Protection Mode into the Password Protection Mode. Persistent Protection Bit Lock (PPB Lock) The device is shipped with all sectors unprotected. AMD offers the option of programming and protecting sectors at the factory prior to shipping the device through AMD’s ExpressFlash™ Service. Contact an AMD representative for details. It is possible to determine whether a sector is protected or unprotected. See “Autoselect Command Sequence” section on page 36 for details. Persistent Sector Protection The Persistent Sector Protection method replaces the old 12 V controlled protection method while at the same time enhancing flexibility by providing three different sector protection states: ■ Persistently Locked—A sector is protected and cannot be changed. ■ Dynamically Locked—The sector is protected and can be changed by a simple command ■ Unlocked—The sector is unprotected and can be changed by a simple command In order to achieve these states, three types of “bits” are going to be used: Persistent Protection Bit (PPB) A single Persistent (non-volatile) Protection Bit is assigned to a maximum four sectors (“Am29BDS128H Boot Sector/Sector Block Addresses for Protection/Unprotection” section on page 16). All 4 Kbyte boot-block sectors have individual sector Persistent Protection Bits (PPBs) for greater flexibility. Each PPB is individually modifiable through the PPB Program Command. Note: If a PPB requires erasure, all of the sector PPBs must first be preprogrammed prior to PPB erasing. All PPBs erase in parallel, unlike programming where in- 18 A global volatile bit. When set to “1”, the PPBs cannot be changed. When cleared (“0”), the PPBs are changeable. There is only one PPB Lock bit per device. The PPB Lock is cleared after power-up or hardware reset. There is no command sequence to unlock the PPB Lock. Dynamic Protection Bit (DYB) A volatile protection bit is assigned for each sector. After power-up or hardware reset, the contents of all DYBs is “0”. Each DYB is individually modifiable through the DYB Write Command. When the par ts are first shipped, the PPBs are cleared. The DYBs and PPB Lock are defaulted to power up in the cleared state – meaning the PPBs are changeable. When the device is first powered on the DYBs power up cleared (sectors not protected). The Protection State for each sector is determined by the logical OR of the PPB and the DYB related to that sector. For the sectors that have the PPBs cleared, the DYBs control whether or not the sector is protected or unprotected. By issuing the DYB Write command sequences, the DYBs will be set or cleared, thus placing each sector in the protected or unprotected state. These are the so-called Dynamic Locked or Unlocked states. They are called dynamic states because it is very easy to switch back and forth between the protected and unprotected conditions. This allows software to easily protect sectors against inadvertent changes yet does not prevent the easy removal of protection when changes are needed. The DYBs maybe set or cleared as often as needed. The PPBs allow for a more static, and difficult to change, level of protection. The PPBs retain their state across power cycles because they are Non-Volatile. Individual PPBs are set with a command but must all be cleared as a group through a complex sequence of program and erasing commands. The PPBs are also limited to 100 erase cycles. The PBB Lock bit adds an additional level of protection. Once all PPBs are programmed to the desired settings, the PPB Lock may be set to “1”. Setting the PPB Lock disables all program and erase commands to the Non-Volatile PPBs. In effect, the PPB Lock Bit locks the PPBs into their current state. The only way to clear the PPB Lock is to go through a power cycle. Am29BDS128H/Am29BDS640H 27024B3 May 10, 2006 D A T A System boot code can determine if any changes to the PPB are needed e.g. to allow new system code to be downloaded. If no changes are needed then the boot code can set the PPB Lock to disable any further changes to the PPBs during system operation. The WP# write protect pin adds a final level of hardware protection to the four highest and four lowest 4 Kbyte sectors. When this pin is low it is not possible to change the contents of these four sectors. These sectors generally hold system boot code. So, the WP# pin can prevent any changes to the boot code that could override the choices made while setting up sector protection during system initialization. It is possible to have sectors that have been persistently locked, and sectors that are left in the dynamic state. The sectors in the dynamic state are all unprotected. If there is a need to protect some of them, a simple DYB Write command sequence is all that is necessary. The DYB write command for the dynamic sectors switch the DYBs to signify protected and unprotected, respectively. If there is a need to change the status of the persistently locked sectors, a few more steps are required. First, the PPB Lock bit must be disabled by either putting the device through a power-cycle, or hardware reset. The PPBs can then be changed to reflect the desired settings. Setting the PPB lock bit once again will lock the PPBs, and the device operates normally again. Note: to achieve the best protection, it’s recommended to execute the PPB lock bit set command early in the boot code, and protect the boot code by holding WP# = VIL. Table 6. Sector Protection Schemes S H E E T In summary, if the PPB is set, and the PPB lock is set, the sector is protected and the protection can not be removed until the next power cycle clears the PPB lock. If the PPB is cleared, the sector can be dynamically locked or unlocked. The DYB then controls whether or not the sector is protected or unprotected. If the user attempts to program or erase a protected sector, the device ignores the command and returns to read mode. A program command to a protected sector enables status polling for approximately tPSP before the device returns to read mode without having modified the contents of the protected sector. An erase command to a protected sector enables status polling for approximately tSEA after which the device returns to read mode without having erased the protected sector. The programming of the DYB, PPB, and PPB lock for a given sector can be ver ified by wr iting a DYB/PPB/PPB lock verify command to the device. Persistent Sector Protection Mode Locking Bit Like the password mode locking bit, a Persistent Sector Protection mode locking bit exists to guarantee that the device remain in software sector protection. Once set, the Persistent Sector Protection locking bit prevents programming of the password protection mode locking bit. This guarantees that a hacker could not place the device in password protection mode. Password Protection Mode The Password Sector Protection Mode method allows an even higher level of security than the Persistent Sector Protection Mode. There are two main differences between the Persistent Sector Protection and the Password Sector Protection Mode: DYB PPB PPB Lock 0 0 0 Unprotected—PPB and DYB are changeable ■ When the device is first powered on, or comes out of a reset cycle, the PPB Lock bit is set to the locked state, rather than cleared to the unlocked state. 0 0 1 Unprotected—PPB not changeable, DYB is changeable ■ The only means to clear the PPB Lock bit is by writing a unique 64-bit Password to the device. 0 1 0 1 0 0 1 1 0 0 1 1 1 0 1 1 1 1 Sector State Protected—PPB and DYB are changeable Protected—PPB not changeable, DYB is changeable Table 6 contains all possible combinations of the DYB, PPB, and PPB lock relating to the status of the sector. May 10, 2006 27024B3 The Password Sector Protection method is otherwise identical to the Persistent Sector Protection method. A 64-bit password is the only additional tool utilized in this method. The password is stored in a one-time programmable (OTP) region of the flash memory. Once the Password Mode Locking Bit is set, the password is permanently set with no means to read, program, or erase it. The password is used to clear the PPB Lock bit. The Password Unlock command must be written to the flash, along with a password. The flash device internally compares the given password with the pre-pro- Am29BDS128H/Am29BDS640H 19 D A T A grammed password. If they match, the PPB Lock bit is cleared, and the PPBs can be altered. If they do not match, the flash device does nothing. There is a built-in 2 µs delay for each “password check.” This delay is intended to thwart any efforts to run a program that tries all possible combinations in order to crack the password. Password and Password Mode Locking Bit In order to select the Password sector protection scheme, the customer must first program the password. It is recommended that the password be somehow correlated to the unique Electronic Serial Number (ESN) of the particular flash device. Each ESN is different for every flash device; therefore each password should be different for every flash device. While programming in the password region, the customer may perform Password Verify operations. Once the desired password is programmed in, the customer must then set the Password Mode Locking Bit. This operation achieves two objectives: 1. It permanently sets the device to operate using the Password Protection Mode. It is not possible to reverse this function. 2. It also disables all further commands to the password region. All program, and read operations are ignored. Both of these objectives are important, and if not carefully considered, may lead to unrecoverable errors. The user must be sure that the Password Protection method is desired when setting the Password Mode Locking Bit. More importantly, the user must be sure that the password is correct when the Password Mode Locking Bit is set. Due to the fact that read operations are disabled, there is no means to verify what the password is afterwards. If the password is lost after setting the Password Mode Locking Bit, there will be no way to clear the PPB Lock bit. The Password Mode Locking Bit, once set, prevents reading the 64-bit password on the DQ bus and further password programming. The Password Mode Locking Bit is not erasable. Once Password Mode Locking Bit is programmed, the Persistent Sector Protection Locking Bit is disabled from programming, guaranteeing that no changes to the protection scheme are allowed. 64-bit Password The 64-bit Password is located in its own memory space and is accessible through the use of the Password Program and Verify commands (see “Password Program Command” section on page 40 and “Password Verify Command” section on page 40). The password function works in conjunction with the Password Mode Locking Bit, which when set, prevents the 20 S H E E T Password Verify command from reading the contents of the password on the pins of the device. Persistent Protection Bit Lock The Persistent Protection Bit (PPB) Lock is a volatile bit that reflects the state of the Password Mode Locking Bit after power-up reset. If the Password Mode Lock Bit is also set, after a hardware reset (RESET# asserted) or a power-up reset the ONLY means for clearing the PPB Lock Bit in Password Protection Mode is to issue the Password Unlock command. Successful execution of the Password Unlock command clears the PPB Lock Bit, allowing for sector PPBs modifications. Asserting RESET#, taking the device through a power-on reset, or issuing the PPB Lock Bit Set command sets the PPB Lock Bit to a “1”. If the Password Mode Locking Bit is not set, including Persistent Protection Mode, the PPB Lock Bit is cleared after power-up or hardware reset. The PPB Lock Bit can be set by issuing the PPB Lock Bit Set command. Once set the only means for clearing the PPB Lock Bit is by issuing a hardware or power-up reset. The Password Unlock command is ignored in Persistent Protection Mode. High Voltage Sector Protection Sector protection and unprotection may also be implemented using programming equipment. The procedure requires high voltage (V ID ) to be placed on the RESET# pin. Refer to Figure 2, “In-System Sector Protection/ Sector Unprotection Algorithms,” on page 22 for details on this procedure. Note that for sector unprotect, all unprotected sectors must be first protected prior to the first sector write cycle. Once the Password Mode Locking bit or Persistent Protection Locking bit are set, the high voltage sector protect/unprotect capability is disabled. Standby Mode When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input. The device enters the CMOS standby mode when the CE# and RESET# inputs are both held at VCC ± 0.2 V. The device requires standard access time (tCE) for read access, before it is ready to read data. If the device is deselected during erasure or programming, the device draws active current until the operation is completed. ICC3 in the “DC Characteristics” section on page 54 represents the standby current specification. Am29BDS128H/Am29BDS640H 27024B3 May 10, 2006 D A T A Automatic Sleep Mode The automatic sleep mode minimizes Flash device energy consumption. While in asynchronous mode, the device automatically enables this mode when addresses remain stable for tACC + 60 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals. Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system. While in synchronous mode, the device automatically enables this mode when either the first active CLK level is greater than tACC or the CLK runs slower than 5 MHz. Note that a new burst operation is required to provide new data. ICC6 in the “DC Characteristics” section on page 54 represents the automatic sleep mode current specification. S H E E T Embedded Algorithms) before the device is ready to read data again. If RESET# is asser ted when a program or erase operation is not executing, the reset operation is completed within a time of tREADY (not during Embedded Algorithms). The system can read data tRH after RESET# returns to VIH. Refer to the “AC Characteristics” section on page 68 for RESET# parameters and to Figure 33, “Reset Timings,” on page 68 for the timing diagram. Output Disable Mode When the OE# input is at VIH, output from the device is disabled. The outputs are placed in the high impedance state. Figure 1. Temporary Sector Unprotect Operation START RESET#: Hardware Reset Input The RESET# input provides a hardware method of resetting the device to reading array data. When RESET# is driven low for at least a period of tRP, the device immediately terminates any operation in progress, tristates all outputs, resets the configuration register, and ignores all read/write commands for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity. RESET# = VID (Note 1) Perform Erase or Program Operations RESET# = VIH Temporary Sector Unprotect Completed (Note 2) Current is reduced for the duration of the RESET# pulse. When RESET# is held at VSS ± 0.2 V, the device draws CMOS standby current (ICC4). If RESET# is held at VIL but not within VSS ± 0.2 V, the standby current will be greater. RESET# may be tied to the system reset circuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory. If RESET# is asserted during a program or erase operation, the device requires a time of t READY (during May 10, 2006 27024B3 Notes: 1. All protected sectors unprotected (If WP# = VIL, outermost boot sectors will remain protected). 2. All previously protected sectors are protected once again. Am29BDS128H/Am29BDS640H 21 D A T A S H E E T START START Protect all sectors: The indicated portion of the sector protect algorithm must be performed for all unprotected sectors prior to issuing the first sector unprotect address PLSCNT = 1 RESET# = VID Wait 1 ms Temporary Sector Unprotect Mode No PLSCNT = 1 RESET# = VID Wait 1 ms First Write No Cycle = 60h? First Write Cycle = 60h? Yes Yes Set up sector address No Sector Protect: Write 60h to sector address with A7–A0 = 00000010 All sectors protected? Yes Set up first sector address Sector Unprotect: Write 60h to sector address with A7:A0 = 01000010 Wait 150 µs Increment PLSCNT Temporary Sector Unprotect Mode Verify Sector Protect: Write 40h to sector address with A7–A0 = 00000010 Reset PLSCNT = 1 Read from sector address with A7–A0 = 00000010 Wait 1.5 ms Verify Sector Unprotect: Write 40h to sector address with A7–A0 = 00000010 Increment PLSCNT No No PLSCNT = 25? Yes Yes No Yes Device failed Read from sector address with A7–A0 = 00000010 Data = 01h? Protect another sector? No PLSCNT = 1000? No Yes Remove VID from RESET# Device failed Write reset command Sector Protect Algorithm Sector Protect complete Set up next sector address Data = 00h? Yes Last sector verified? No Yes Sector Unprotect Algorithm Remove VID from RESET# Write reset command Sector Unprotect complete Figure 2. In-System Sector Protection/ Sector Unprotection Algorithms 22 Am29BDS128H/Am29BDS640H 27024B3 May 10, 2006 D A T A SecSi™ (Secured Silicon) Sector Flash Memory Region The SecSi (Secured Silicon) Sector feature provides a Flash memory region that enables permanent part identification through an Electronic Serial Number (ESN) The 128-word SecSi sector is divided into 64 factory-lockable words that can be programmed and locked by the customer. The SecSi sector is located at addresses 000000h-00007Fh in both Persistent Protection mode and Password Protection mode. It uses in dicato r b its (DQ 6, DQ7) to indicate t he factory-locked and customer-locked status of the part. The system accesses the SecSi Sector through a command sequence (see “Enter SecSi™ Sector/Exit SecSi Sector Command Sequence”). After the system has written the Enter SecSi Sector command sequence, it may read the SecSi Sector by using the addresses normally occupied by the boot sectors. This mode of operation continues until the system issues the Exit SecSi Sector command sequence, or until power is removed from the device. On power-up, or following a hardware reset, the device reverts to sending commands to the normal address space. Factory-Locked Area (64 words) T h e fa c t o r y - l o cke d a r e a o f t h e S e c S i S e c t o r (000000h-00003Fh) is locked when the par t is shipped, whether or not the area was programmed at the factory. The SecSi Sector Factory-locked Indicator Bit (DQ7) is permanently set to a “1”. AMD offers the ExpressFlash service to program the factory-locked area with a random ESN, a customer-defined code, or any combination of the two. Because only AMD can program and protect the factory-locked area, this method ensures the security of the ESN once the product is shipped to the field. Contact an AMD representative for details on using the AMD ExpressFlash service. Table 7. SecSiTM Sector Addresses Sector Size Address Range Am29BDS128H/ Am29BDS640H 128 words 000000h–00007Fh Factory-Locked Area 64 words 000000h–00003Fh Customer-Lockable Area 64 words 000040h–00007Fh Customer-Lockable Area (64 words) The customer-lockable area of the SecSi Sector (000040h-00007Fh) is shipped unprotected, which allows the customer to program and optionally lock the area as appropriate for the application. The SecSi Sector Customer-locked Indicator Bit (DQ6) is shipped as “0” and can be permanently locked to “1” by issuing the SecSi Protection Bit Program Command. The SecSi Sector can be read any number of times, but May 10, 2006 27024B3 S H E E T can be programmed and locked only once. Note that the accelerated programming (ACC) and unlock bypass functions are not available when programming the SecSi Sector. The Customer-lockable SecSi Sector area can be protected using one of the following procedures: ■ Write the three-cycle Enter SecSi Sector Region command sequence, and then follow the in-system sector protect algorithm as shown in Figure 2, except that RESET# may be at either VIH or VID. This allows in-system protection of the SecSi Sector Region without raising any device pin to a high voltage. Note that this method is only applicable to the SecSi Sector. ■ Write the three-cycle Enter SecSi Sector Secure Region command sequence, and then use the alternate method of sector protection described in the High Voltage Sector Protection section. Once the SecSi Sector is locked and verified, the system must write the Exit SecSi Sector Region command sequence to return to reading and writing the remainder of the array. The SecSi Sector lock must be used with caution since, once locked, there is no procedure available for unlocking the SecSi Sector area and none of the bits in the SecSi Sector memory space can be modified in any way. SecSi Sector Protection Bits The SecSi Sector Protection Bits prevent programming of the SecSi Sector memory area. Once set, the SecSi Sector memory area contents are non-modifiable. Hardware Data Protection The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to Table 20, “Memory Array Command Definitions,” on page 46 for command definitions). The device offers two types of data protection at the sector level: ■ The PPB and DYB associated command sequences disables or re-enables both program and erase operations in any sector or sector group. ■ When WP# is at VIL, the four outermost sectors are locked. ■ When ACC is at VIL, all sectors are locked. The following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during VCC power-up and power-down transitions, or from system noise. Am29BDS128H/Am29BDS640H 23 D A T A Write Protect (WP#) The Write Protect feature provides a hardware method of protecting the four outermost sectors. This function is provided by the WP# pin and overrides the previously discussed Sector Protection/Unprotection method. If the system asserts VIL on the WP# pin, the device disables program and erase functions in the eight “outermost” 4 Kword boot sectors. If the system asserts VIH on the WP# pin, the device reverts to whether the boot sectors were last set to be protected or unprotected. That is, sector protection or unprotection for these sectors depends on whether they were last protected or unprotected using the method described in “PPB Program Command” section on page 43. Note that the WP# pin must not be left floating or unconnected; inconsistent behavior of the device may result. Low VCC Write Inhibit When V CC is less than V LKO, the device does not accept any write cycles. This protects data during VCC power-up and power-down. The command register and all internal program/erase circuits are disabled, and the device resets to reading array data. Subsequent writes are ignored until VCC is greater than VLKO. The system must provide the proper signals to the control inputs to prevent unintentional writes when VCC is greater than VLKO. Write Pulse “Glitch” Protection Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle. Logical Inhibit Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH or WE# = VIH. To initiate a write cycle, Table 8. 24 S H E E T CE# and WE# must be a logical zero while OE# is a logical one. Power-Up Write Inhibit If WE# = CE# = RESET# = VIL and OE# = VIH during power up, the device does not accept commands on the rising edge of WE#. The internal state machine is automatically reset to the read mode on power-up. COMMON FLASH MEMORY INTERFACE (CFI) The Common Flash Interface (CFI) specification outlines device and host system software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. Software support can then be device-independent, JEDEC ID-independent, and forward- and backward-compatible for the specified flash device families. Flash vendors can standardize their existing interfaces for long-term compatibility. This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to address 55h any time the device is ready to read array data. The system can read CFI information at the addresses given in Tables 8-11. To terminate reading CFI data, the system must write the reset command. The system can also write the CFI query command when the device is in the autoselect mode. The device enters the CFI query mode, and the system can read CFI data at the addresses given in Tables 8-11. The system must write the reset command to return the device to the autoselect mode. For further information, please refer to the CFI Specification and CFI Publication 100, available via the AMD site at the following URL: http://www.amd.com/flash/cfi. Alternatively, contact an AMD representative for copies CFI Query Identification String Addresses Data Description 10h 11h 12h 0051h 0052h 0059h Query Unique ASCII string “QRY” 13h 14h 0002h 0000h Primary OEM Command Set 15h 16h 0040h 0000h Address for Primary Extended Table 17h 18h 0000h 0000h Alternate OEM Command Set (00h = none exists) 19h 1Ah 0000h 0000h Address for Alternate OEM Extended Table (00h = none exists) Am29BDS128H/Am29BDS640H 27024B3 May 10, 2006 D A T A Table 9. S H E E T System Interface String Addresses Data Description 1Bh 0017h VCC Min. (write/erase) D7–D4: volt, D3–D0: 100 millivolt 1Ch 0019h VCC Max. (write/erase) D7–D4: volt, D3–D0: 100 millivolt 1Dh 0000h VPP Min. voltage (00h = no VPP pin present) 1Eh 0000h VPP Max. voltage (00h = no VPP pin present) 1Fh 0004h Typical timeout per single byte/word write 2N µs 20h 0000h Typical timeout for Min. size buffer write 2N µs (00h = not supported) 21h 0009h Typical timeout per individual block erase 2N ms 22h 0000h Typical timeout for full chip erase 2N ms (00h = not supported) 23h 0004h Max. timeout for byte/word write 2N times typical 24h 0000h Max. timeout for buffer write 2N times typical 25h 0004h Max. timeout per individual block erase 2N times typical 26h 0000h Max. timeout for full chip erase 2N times typical (00h = not supported) Table 10. Device Geometry Definition Addresses Data 27h 001xh Device Size = 2N byte BDS128H = 0018h; BDS640H = 0017h 28h 29h 0001h 0000h Flash Device Interface description (refer to CFI publication 100) 2Ah 2Bh 0000h 0000h Max. number of bytes in multi-byte write = 2N (00h = not supported) 2Ch 0003h Number of Erase Block Regions within device 2Dh 2Eh 2Fh 30h 0007h 0000h 0020h 0000h Erase Block Region 1 Information (refer to the CFI specification or CFI publication 100) 31h 32h 33h 34h 00xDh 0000h 0000h 0001h Erase Block Region 2 Information Address 31h: BDS128H = 00FDh; BDS640H = 007Dh 35h 36h 37h 38h 0007h 0000h 0020h 0000h Erase Block Region 3 Information 39h 3Ah 3Bh 3Ch 0000h 0000h 0000h 0000h Erase Block Region 4 Information May 10, 2006 27024B3 Description Am29BDS128H/Am29BDS640H 25 D A T A Table 11. S H E E T Primary Vendor-Specific Extended Query Addresses Data Description 40h 41h 42h 0050h 0052h 0049h Query-unique ASCII string “PRI” 43h 0031h Major version number, ASCII 44h 0033h Minor version number, ASCII 45h 000Ch Address Sensitive Unlock (Bits 1-0) 0 = Required, 1 = Not Required Silicon Technology (Bits 5-2) 0011 = 0.13 µm 26 46h 0002h Erase Suspend 0 = Not Supported, 1 = To Read Only, 2 = To Read & Write 47h 0001h Sector Protect 0 = Not Supported, X = Number of sectors in per group 48h 0000h Sector Temporary Unprotect 00 = Not Supported, 01 = Supported 49h 0007h Sector Protect/Unprotect scheme 07 = Advanced Sector Protection 4Ah 00x7h Simultaneous Operation: number of Sectors in all banks except boot block BDS128H = 00E7h; BDS640H = 0077h 4Bh 0001h Burst Mode Type 00 = Not Supported, 01 = Supported 4Ch 0000h Page Mode Type 00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page, 04 = 16 Word Page 4Dh 00B5h 4Eh 00C5h 4Fh 0001h Boot Sector Flag 50h 0000h Program Suspend. 00h = not supported 57h 0004h Bank Organization: X = Number of banks 58h 59h 5Ah 5Bh 0027h / 0017h 0060h / 0030h 0060h / 0030h 0027h / 0017h ACC (Acceleration) Supply Minimum 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV ACC (Acceleration) Supply Maximum 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV Bank A – Bank D Region Information. X = Number of sectors in bank. Address: 58h = Bank A; 59h = Bank B; 5Ah = Bank C; 5Bh = Bank D Data: BDS128H / BDS640H Am29BDS128H/Am29BDS640H 27024B3 May 10, 2006 D A T A S H E E T Table 12. Am29BDS128H Sector Address Table Bank D Sector Sector Size (x16) Address Range SA0 4 Kwords 000000h–000FFFh Bank Sector Sector Size (x16) Address Range SA39 32 Kwords 100000h–107FFFh SA1 4 Kwords 001000h–001FFFh SA40 32 Kwords 108000h–10FFFFh SA2 4 Kwords 002000h–002FFFh SA41 32 Kwords 110000h–117FFFh SA3 4 Kwords 003000h–003FFFh SA42 32 Kwords 118000h–11FFFFh SA4 4 Kwords 004000h–004FFFh SA43 32 Kwords 120000h–127FFFh SA5 4 Kwords 005000h–005FFFh SA44 32 Kwords 128000h–12FFFFh SA6 4 Kwords 006000h–006FFFh SA45 32 Kwords 130000h–137FFFh SA7 4 Kwords 007000h–007FFFh SA46 32 Kwords 138000h–13FFFFh SA8 32 Kwords 008000h–00FFFFh SA47 32 Kwords 140000h–147FFFh SA9 32 Kwords 010000h–017FFFh SA48 32 Kwords 148000h–14FFFFh SA10 32 Kwords 018000h–01FFFFh SA49 32 Kwords 150000h–157FFFh SA11 32 Kwords 020000h–027FFFh SA50 32 Kwords 158000h–15FFFFh SA12 32 Kwords 028000h–02FFFFh SA51 32 Kwords 160000h–167FFFh SA13 32 Kwords 030000h–037FFFh SA52 32 Kwords 168000h–16FFFFh SA14 32 Kwords 038000h–03FFFFh SA53 32 Kwords 170000h–177FFFh SA15 32 Kwords 040000h–047FFFh SA54 32 Kwords 178000h–17FFFFh SA16 32 Kwords 048000h–04FFFFh SA55 32 Kwords 180000h–187FFFh SA17 32 Kwords 050000h–057FFFh SA56 32 Kwords 188000h–18FFFFh SA18 32 Kwords 058000h–05FFFFh SA57 32 Kwords 190000h–197FFFh SA19 32 Kwords 060000h–067FFFh SA58 32 Kwords 198000h–19FFFFh SA20 32 Kwords 068000h–06FFFFh SA59 32 Kwords 1A0000h–1A7FFFh SA21 32 Kwords 070000h–077FFFh SA60 32 Kwords 1A8000h–1AFFFFh SA22 32 Kwords 078000h–07FFFFh SA61 32 Kwords 1B0000h–1B7FFFh SA23 32 Kwords 080000h–087FFFh SA62 32 Kwords 1B8000h–1BFFFFh SA24 32 Kwords 088000h–08FFFFh SA63 32 Kwords 1C0000h–1C7FFFh SA25 32 Kwords 090000h–097FFFh SA64 32 Kwords 1C8000h–1CFFFFh SA26 32 Kwords 098000h–09FFFFh SA65 32 Kwords 1D0000h–1D7FFFh SA27 32 Kwords 0A0000h–0A7FFFh SA66 32 Kwords 1D8000h–1DFFFFh SA28 32 Kwords 0A8000h–0AFFFFh SA67 32 Kwords 1E0000h–1E7FFFh SA29 32 Kwords 0B0000h–0B7FFFh SA68 32 Kwords 1E8000h–1EFFFFh SA30 32 Kwords 0B8000h–0BFFFFh SA69 32 Kwords 1F0000h–1F7FFFh SA31 32 Kwords 0C0000h–0C7FFFh SA70 32 Kwords 1F8000h–1FFFFFh SA32 32 Kwords 0C8000h–0CFFFFh SA33 32 Kwords 0D0000h–0D7FFFh SA34 32 Kwords 0D8000h–0DFFFFh SA35 32 Kwords 0E0000h–0E7FFFh SA36 32 Kwords 0E8000h–0EFFFFh SA37 32 Kwords 0F0000h–0F7FFFh SA38 32 Kwords 0F8000h–0FFFFFh May 10, 2006 27024B3 Bank C Bank Am29BDS128H/Am29BDS640H 27 D A T A Table 12. 28 Am29BDS128H Sector Address Table (Continued) Sector Sector Size (x16) Address Range SA71 32 Kwords SA72 SA73 SA74 SA75 Bank Sector Sector Size (x16) Address Range 200000h–207FFFh SA103 32 Kwords 300000h–307FFFh 32 Kwords 208000h–20FFFFh SA104 32 Kwords 308000h–30FFFFh 32 Kwords 210000h–217FFFh SA105 32 Kwords 310000h–317FFFh 32 Kwords 218000h–21FFFFh SA106 32 Kwords 318000h–31FFFFh 32 Kwords 220000h–227FFFh SA107 32 Kwords 320000h–327FFFh SA76 32 Kwords 228000h–22FFFFh SA108 32 Kwords 328000h–32FFFFh SA77 32 Kwords 230000h–237FFFh SA109 32 Kwords 330000h–337FFFh SA78 32 Kwords 238000h–23FFFFh SA110 32 Kwords 338000h–33FFFFh SA79 32 Kwords 240000h–247FFFh SA111 32 Kwords 340000h–347FFFh SA80 32 Kwords 248000h–24FFFFh SA112 32 Kwords 348000h–34FFFFh SA81 32 Kwords 250000h–257FFFh SA113 32 Kwords 350000h–357FFFh SA82 32 Kwords 258000h–25FFFFh SA114 32 Kwords 358000h–35FFFFh SA83 32 Kwords 260000h–267FFFh SA115 32 Kwords 360000h–367FFFh SA84 32 Kwords 268000h–26FFFFh SA116 32 Kwords 368000h–36FFFFh SA85 32 Kwords 270000h–277FFFh SA117 32 Kwords 370000h–377FFFh SA86 32 Kwords 278000h–27FFFFh SA118 32 Kwords 378000h–37FFFFh SA87 32 Kwords 280000h–287FFFh SA119 32 Kwords 380000h–387FFFh SA88 32 Kwords 288000h–28FFFFh SA120 32 Kwords 388000h–38FFFFh SA89 32 Kwords 290000h–297FFFh SA121 32 Kwords 390000h–397FFFh SA90 32 Kwords 298000h–29FFFFh SA122 32 Kwords 398000h–39FFFFh SA91 32 Kwords 2A0000h–2A7FFFh SA123 32 Kwords 3A0000h–3A7FFFh SA92 32 Kwords 2A8000h–2AFFFFh SA124 32 Kwords 3A8000h–3AFFFFh SA93 32 Kwords 2B0000h–2B7FFFh SA125 32 Kwords 3B0000h–3B7FFFh SA94 32 Kwords 2B8000h–2BFFFFh SA126 32 Kwords 3B8000h–3BFFFFh SA95 32 Kwords 2C0000h–2C7FFFh SA127 32 Kwords 3C0000h–3C7FFFh SA96 32 Kwords 2C8000h–2CFFFFh SA128 32 Kwords 3C8000h–3CFFFFh SA97 32 Kwords 2D0000h–2D7FFFh SA129 32 Kwords 3D0000h–3D7FFFh SA98 32 Kwords 2D8000h–2DFFFFh SA130 32 Kwords 3D8000h–3DFFFFh SA99 32 Kwords 2E0000h–2E7FFFh SA131 32 Kwords 3E0000h–3E7FFFh SA100 32 Kwords 2E8000h–2EFFFFh SA132 32 Kwords 3E8000h–3EFFFFh SA101 32 Kwords 2F0000h–2F7FFFh SA133 32 Kwords 3F0000h–3F7FFFh SA102 32 Kwords 2F8000h–2FFFFFh SA134 32 Kwords 3F8000h–3FFFFFh Bank C Bank C Bank S H E E T Am29BDS128H/Am29BDS640H 27024B3 May 10, 2006 D A T A Table 12. Am29BDS128H Sector Address Table (Continued) Sector Sector Size (x16) Address Range SA135 32 Kwords SA136 SA137 SA138 SA139 Sector Sector Size (x16) Address Range 400000h–407FFFh SA167 32 Kwords 500000h–507FFFh 32 Kwords 408000h–40FFFFh SA168 32 Kwords 508000h–50FFFFh 32 Kwords 410000h–417FFFh SA169 32 Kwords 510000h–517FFFh 32 Kwords 418000h–41FFFFh SA170 32 Kwords 518000h–51FFFFh 32 Kwords 420000h–427FFFh SA171 32 Kwords 520000h–527FFFh SA140 32 Kwords 428000h–42FFFFh SA172 32 Kwords 528000h–52FFFFh SA141 32 Kwords 430000h–437FFFh SA173 32 Kwords 530000h–537FFFh SA142 32 Kwords 438000h–43FFFFh SA174 32 Kwords 538000h–53FFFFh SA143 32 Kwords 440000h–447FFFh SA175 32 Kwords 540000h–547FFFh SA144 32 Kwords 448000h–44FFFFh SA176 32 Kwords 548000h–54FFFFh SA145 32 Kwords 450000h–457FFFh SA177 32 Kwords 550000h–557FFFh SA146 32 Kwords 458000h–45FFFFh SA178 32 Kwords 558000h–55FFFFh SA147 32 Kwords 460000h–467FFFh SA179 32 Kwords 560000h–567FFFh SA148 32 Kwords 468000h–46FFFFh SA180 32 Kwords 568000h–56FFFFh SA149 32 Kwords 470000h–477FFFh SA181 32 Kwords 570000h–577FFFh SA150 32 Kwords 478000h–47FFFFh SA182 32 Kwords 578000h–57FFFFh SA151 32 Kwords 480000h–487FFFh SA183 32 Kwords 580000h–587FFFh SA152 32 Kwords 488000h–48FFFFh SA184 32 Kwords 588000h–58FFFFh SA153 32 Kwords 490000h–497FFFh SA185 32 Kwords 590000h–597FFFh SA154 32 Kwords 498000h–49FFFFh SA186 32 Kwords 598000h–59FFFFh SA155 32 Kwords 4A0000h–4A7FFFh SA187 32 Kwords 5A0000h–5A7FFFh SA156 32 Kwords 4A8000h–4AFFFFh SA188 32 Kwords 5A8000h–5AFFFFh SA157 32 Kwords 4B0000h–4B7FFFh SA189 32 Kwords 5B0000h–5B7FFFh SA158 32 Kwords 4B8000h–4BFFFFh SA190 32 Kwords 5B8000h–5BFFFFh SA159 32 Kwords 4C0000h–4C7FFFh SA191 32 Kwords 5C0000h–5C7FFFh SA160 32 Kwords 4C8000h–4CFFFFh SA192 32 Kwords 5C8000h–5CFFFFh SA161 32 Kwords 4D0000h–4D7FFFh SA193 32 Kwords 5D0000h–5D7FFFh SA162 32 Kwords 4D8000h–4DFFFFh SA194 32 Kwords 5D8000h–5DFFFFh SA163 32 Kwords 4E0000h–4E7FFFh SA195 32 Kwords 5E0000h–5E7FFFh SA164 32 Kwords 4E8000h–4EFFFFh SA196 32 Kwords 5E8000h–5EFFFFh SA165 32 Kwords 4F0000h–4F7FFFh SA197 32 Kwords 5F0000h–5F7FFFh SA166 32 Kwords 4F8000h–4FFFFFh SA198 32 Kwords 5F8000h–5FFFFFh May 10, 2006 27024B3 Bank Bank B Bank B Bank S H E E T Am29BDS128H/Am29BDS640H 29 D A T A Table 12. 30 Am29BDS128H Sector Address Table (Continued) Sector Sector Size (x16) Address Range SA199 32 Kwords SA200 SA201 SA202 SA203 Bank Sector Sector Size (x16) Address Range 600000h–607FFFh SA231 32 Kwords 700000h–707FFFh 32 Kwords 608000h–60FFFFh SA232 32 Kwords 708000h–70FFFFh 32 Kwords 610000h–617FFFh SA233 32 Kwords 710000h–717FFFh 32 Kwords 618000h–61FFFFh SA234 32 Kwords 718000h–71FFFFh 32 Kwords 620000h–627FFFh SA235 32 Kwords 720000h–727FFFh SA204 32 Kwords 628000h–62FFFFh SA236 32 Kwords 728000h–72FFFFh SA205 32 Kwords 630000h–637FFFh SA237 32 Kwords 730000h–737FFFh SA206 32 Kwords 638000h–63FFFFh SA238 32 Kwords 738000h–73FFFFh SA207 32 Kwords 640000h–647FFFh SA239 32 Kwords 740000h–747FFFh SA208 32 Kwords 648000h–64FFFFh SA240 32 Kwords 748000h–74FFFFh SA209 32 Kwords 650000h–657FFFh SA241 32 Kwords 750000h–757FFFh SA210 32 Kwords 658000h–65FFFFh SA242 32 Kwords 758000h–75FFFFh SA211 32 Kwords 660000h–667FFFh SA243 32 Kwords 760000h–767FFFh SA212 32 Kwords 668000h–66FFFFh SA244 32 Kwords 768000h–76FFFFh SA213 32 Kwords 670000h–677FFFh SA245 32 Kwords 770000h–777FFFh SA214 32 Kwords 678000h–67FFFFh SA246 32 Kwords 778000h–77FFFFh SA215 32 Kwords 680000h–687FFFh SA247 32 Kwords 780000h–787FFFh SA216 32 Kwords 688000h–68FFFFh SA248 32 Kwords 788000h–78FFFFh SA217 32 Kwords 690000h–697FFFh SA249 32 Kwords 790000h–797FFFh SA218 32 Kwords 698000h–69FFFFh SA250 32 Kwords 798000h–79FFFFh SA219 32 Kwords 6A0000h–6A7FFFh SA251 32 Kwords 7A0000h–7A7FFFh SA220 32 Kwords 6A8000h–6AFFFFh SA252 32 Kwords 7A8000h–7AFFFFh SA221 32 Kwords 6B0000h–6B7FFFh SA253 32 Kwords 7B0000h–7B7FFFh SA222 32 Kwords 6B8000h–6BFFFFh SA254 32 Kwords 7B8000h–7BFFFFh SA223 32 Kwords 6C0000h–6C7FFFh SA255 32 Kwords 7C0000h–7C7FFFh SA224 32 Kwords 6C8000h–6CFFFFh SA256 32 Kwords 7C8000h–7CFFFFh SA225 32 Kwords 6D0000h–6D7FFFh SA257 32 Kwords 7D0000h–7D7FFFh SA226 32 Kwords 6D8000h–6DFFFFh SA258 32 Kwords 7D8000h–7DFFFFh SA227 32 Kwords 6E0000h–6E7FFFh SA259 32 Kwords 7E0000h–7E7FFFh SA228 32 Kwords 6E8000h–6EFFFFh SA260 32 Kwords 7E8000h–7EFFFFh SA229 32 Kwords 6F0000h–6F7FFFh SA261 32 Kwords 7F0000h–7F7FFFh SA230 32 Kwords 6F8000h–6FFFFFh SA262 4 Kwords 7F8000h–7F8FFFh SA263 4 Kwords 7F9000h–7F9FFFh SA264 4 Kwords 7FA000h–7FAFFFh SA265 4 Kwords 7FB000h–7FBFFFh SA266 4 Kwords 7FC000h–7FCFFFh SA267 4 Kwords 7FD000h–7FDFFFh SA268 4 Kwords 7FE000h–7FEFFFh SA269 4 Kwords 7FF000h–7FFFFFh Bank A Bank B Bank S H E E T Am29BDS128H/Am29BDS640H 27024B3 May 10, 2006 D A T A Table 13. Bank C Am29BDS640H Sector Address Table Sector Sector Size Address Range SA0 4 Kwords SA1 SA2 Bank Sector Sector Size Address Range 000000h–000FFFh SA36 32 Kwords 0E8000h–0EFFFFh 4 Kwords 001000h–001FFFh SA37 32 Kwords 0F0000h–0F7FFFh 4 Kwords 002000h–002FFFh SA38 32 Kwords 0F8000h–0FFFFFh SA3 4 Kwords 003000h–003FFFh SA39 32 Kwords 100000h–107FFFh SA4 4 Kwords 004000h–004FFFh SA40 32 Kwords 108000h–10FFFFh SA5 4 Kwords 005000h–005FFFh SA41 32 Kwords 110000h–117FFFh SA6 4 Kwords 006000h–006FFFh SA42 32 Kwords 118000h–11FFFFh SA7 4 Kwords 007000h–007FFFh SA43 32 Kwords 120000h–127FFFh SA8 32 Kwords 008000h–00FFFFh SA44 32 Kwords 128000h–12FFFFh SA9 32 Kwords 010000h–017FFFh SA45 32 Kwords 130000h–137FFFh SA10 32 Kwords 018000h–01FFFFh SA46 32 Kwords 138000h–13FFFFh SA11 32 Kwords 020000h–027FFFh SA47 32 Kwords 140000h–147FFFh SA12 32 Kwords 028000h–02FFFFh SA48 32 Kwords 148000h–14FFFFh SA13 32 Kwords 030000h–037FFFh SA49 32 Kwords 150000h–157FFFh SA14 32 Kwords 038000h–03FFFFh SA50 32 Kwords 158000h–15FFFFh SA15 32 Kwords 040000h–047FFFh SA51 32 Kwords 160000h–167FFFh SA16 32 Kwords 048000h–04FFFFh SA52 32 Kwords 168000h–16FFFFh SA17 32 Kwords 050000h–057FFFh SA18 32 Kwords 058000h–05FFFFh SA19 32 Kwords SA20 32 Kwords Bank C Bank D Bank S H E E T SA53 32 Kwords 170000h–177FFFh SA54 32 Kwords 178000h–17FFFFh 060000h–067FFFh SA55 32 Kwords 180000h–187FFFh 068000h–06FFFFh SA56 32 Kwords 188000h–18FFFFh SA21 32 Kwords 070000h–077FFFh SA57 32 Kwords 190000h–197FFFh SA22 32 Kwords 078000h–07FFFFh SA58 32 Kwords 198000h–19FFFFh SA23 32 Kwords 080000h–087FFFh SA59 32 Kwords 1A0000h–1A7FFFh SA24 32 Kwords 088000h–08FFFFh SA60 32 Kwords 1A8000h–1AFFFFh SA25 32 Kwords 090000h–097FFFh SA61 32 Kwords 1B0000h–1B7FFFh SA26 32 Kwords 098000h–09FFFFh SA62 32 Kwords 1B8000h–1BFFFFh SA27 32 Kwords 0A0000h–0A7FFFh SA63 32 Kwords 1C0000h–1C7FFFh SA28 32 Kwords 0A8000h–0AFFFFh SA64 32 Kwords 1C8000h–1CFFFFh SA29 32 Kwords 0B0000h–0B7FFFh SA65 32 Kwords 1D0000h–1D7FFFh SA30 32 Kwords 0B8000h–0BFFFFh SA66 32 Kwords 1D8000h–1DFFFFh SA31 32 Kwords 0C0000h–0C7FFFh SA67 32 Kwords 1E0000h–1E7FFFh SA32 32 Kwords 0C8000h–0CFFFFh SA68 32 Kwords 1E8000h–1EFFFFh SA33 32 Kwords 0D0000h–0D7FFFh SA69 32 Kwords 1F0000h–1F7FFFh SA34 32 Kwords 0D8000h–0DFFFFh SA70 32 Kwords 1F8000h–1FFFFFh SA35 32 Kwords 0E0000h–0E7FFFh May 10, 2006 27024B3 Am29BDS128H/Am29BDS640H 31 D A T A Table 13. 32 Am29BDS640H Sector Address Table Sector Size Address Range SA71 32 Kwords SA72 SA73 Bank Sector Sector Size Address Range 200000h–207FFFh SA107 32 Kwords 320000h–327FFFh 32 Kwords 208000h–20FFFFh SA108 32 Kwords 328000h–32FFFFh 32 Kwords 210000h–217FFFh SA109 32 Kwords 330000h–337FFFh SA74 32 Kwords 218000h–21FFFFh SA110 32 Kwords 338000h–33FFFFh SA75 32 Kwords 220000h–227FFFh SA111 32 Kwords 340000h–347FFFh SA76 32 Kwords 228000h–22FFFFh SA112 32 Kwords 348000h–34FFFFh SA77 32 Kwords 230000h–237FFFh SA113 32 Kwords 350000h–357FFFh SA78 32 Kwords 238000h–23FFFFh SA114 32 Kwords 358000h–35FFFFh SA79 32 Kwords 240000h–247FFFh SA115 32 Kwords 360000h–367FFFh SA80 32 Kwords 248000h–24FFFFh SA116 32 Kwords 368000h–36FFFFh SA81 32 Kwords 250000h–257FFFh SA117 32 Kwords 370000h–377FFFh SA82 32 Kwords 258000h–25FFFFh SA118 32 Kwords 378000h–37FFFFh SA83 32 Kwords 260000h–267FFFh SA119 32 Kwords 380000h–387FFFh SA84 32 Kwords 268000h–26FFFFh SA120 32 Kwords 388000h–38FFFFh SA85 32 Kwords 270000h–277FFFh SA121 32 Kwords 390000h–397FFFh SA86 32 Kwords 278000h–27FFFFh SA122 32 Kwords 398000h–39FFFFh SA87 32 Kwords 280000h–287FFFh SA123 32 Kwords 3A0000h–3A7FFFh SA88 32 Kwords 288000h–28FFFFh SA124 32 Kwords 3A8000h–3AFFFFh SA89 32 Kwords 290000h–297FFFh SA125 32 Kwords 3B0000h–3B7FFFh SA90 32 Kwords 298000h–29FFFFh SA126 32 Kwords 3B8000h–3BFFFFh SA91 32 Kwords 2A0000h–2A7FFFh SA127 32 Kwords 3C0000h–3C7FFFh SA92 32 Kwords 2A8000h–2AFFFFh SA128 32 Kwords 3C8000h–3CFFFFh SA93 32 Kwords 2B0000h–2B7FFFh SA129 32 Kwords 3D0000h–3D7FFFh SA94 32 Kwords 2B8000h–2BFFFFh SA130 32 Kwords 3D8000h–3DFFFFh SA95 32 Kwords 2C0000h–2C7FFFh SA131 32 Kwords 3E0000h–3E7FFFh SA96 32 Kwords 2C8000h–2CFFFFh SA132 32 Kwords 3E8000h–3EFFFFh SA97 32 Kwords 2D0000h–2D7FFFh SA133 32 Kwords 3F0000h–3F7FFFh SA98 32 Kwords 2D8000h–2DFFFFh SA134 4 Kwords 3F8000h–3F8FFFh SA99 32 Kwords 2E0000h–2E7FFFh SA135 4 Kwords 3F9000h–3F9FFFh SA100 32 Kwords 2E8000h–2EFFFFh SA136 4 Kwords 3FA000h–3FAFFFh SA101 32 Kwords 2F0000h–2F7FFFh SA137 4 Kwords 3FB000h–3FBFFFh SA102 32 Kwords 2F8000h–2FFFFFh SA138 4 Kwords 3FC000h–3FCFFFh SA103 32 Kwords 300000h–307FFFh SA139 4 Kwords 3FD000h–3FDFFFh SA104 32 Kwords 308000h–30FFFFh SA140 4 Kwords 3FE000h–3FEFFFh SA105 32 Kwords 310000h–317FFFh SA141 4 Kwords 3FF000h–3FFFFFh SA106 32 Kwords 318000h–31FFFFh Bank B Sector Bank A Bank B Bank S H E E T Am29BDS128H/Am29BDS640H 27024B3 May 10, 2006 D A T A S H E E T COMMAND DEFINITIONS Writing specific address and data commands or sequences into the command register initiates device operations. Table 20, “Memory Array Command Definitions,” on page 46 defines the valid register command sequences. Writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. The system must write the reset command to return the device to reading array data. Refer to the AC Characteristics section for timing diagrams. be C0h, address bits A11–A0 should be 555h, and address bits A19–A12 set the code to be latched. The device will power up or after a hardware reset with the default setting, which is in asynchronous mode. The register must be set before the device can enter synchronous mode. The configuration register can not be changed during device operations (program, erase, or sector lock). Reading Array Data Power-up/ Hardware Reset The device is automatically set to reading array data after device power-up. No commands are required to retrieve data in asynchronous mode. Each bank is ready to read array data after completing an Embedded Program or Embedded Erase algorithm. After the device accepts an Erase Suspend command, the corresponding bank enters the erase-suspend-read mode, after which the system can read data from any non-erase-suspended sector within the same bank. After completing a programming operation in the Erase Suspend mode, the system may once again read array data from any non-erase-suspended sector within the same bank. See the “Erase Suspend/Erase Resume Commands” section on page 39 for more information. The system must issue the reset command to return a bank to the read (or erase-suspend-read) mode if DQ5 goes high during an active program or erase operation, or if the bank is in the autoselect mode. See the “Reset Command” section on page 36 for more information. See also “Requirements for Asynchronous Read Operation (Non-Burst)” section on page 11 and “Requirements for Synchronous (Burst) Read Operation” section on page 11 for more information. The Asynchronous Read and Synchronous/Burst Read tables provide the read parameters, and Figure 16, “CLK Synchronous Burst Mode Read (rising active CLK),” on page 58, Figure 18, “Synchronous Burst Mode Read,” on page 59, and Figure 31, “Asynchronous Mode Read with Latched Addresses,” on page 67 show the timings. Set Configuration Register Command Sequence The device uses a configuration register to set the various burst parameters: number of wait states, burst read mode, active clock edge, RDY configuration, and synchronous mode active. The configuration register must be set before the device will enter burst mode. The configuration register is loaded with a three-cycle command sequence. The first two cycles are standard unlock sequences. On the third cycle, the data should May 10, 2006 27024B3 Asynchronous Read Mode Only Set Burst Mode Configuration Register Command for Synchronous Mode (D15 = 0) Set Burst Mode Configuration Register Command for Asynchronous Mode (D15 = 1) Synchronous Read Mode Only Figure 3. Synchronous/Asynchronous State Diagram Read Mode Setting On power-up or hardware reset, the device is set to be in asynchronous read mode. This setting allows the system to enable or disable burst mode during system operations. Address A19 determines this setting: “1” for asynchronous mode, “0” for synchronous mode. Programmable Wait State Configuration The programmable wait state feature informs the device of the number of clock cycles that must elapse after AVD# is driven active before data will be available. This value is determined by the input frequency of the device. Address bits A14–A12 determine the setting (see Table 14, “Programmable Wait State Settings,” on page 34). The wait state command sequence instructs the device to set a particular number of clock cycles for the initial access in burst mode. The number of wait states that should be programmed into the device is directly related to the clock frequency. Am29BDS128H/Am29BDS640H 33 D A T A Table 14. Programmable Wait State Settings A14 A13 A12 Total Initial Access Cycles 0 0 0 2 0 0 1 3 0 1 0 4 0 1 1 5 1 0 0 6 1 0 1 7 (default) 1 1 0 Reserved 1 1 1 Reserved Notes: 1. Upon power-up or hardware reset, the default setting is seven wait states. 2. RDY will default to being active with data when the Wait State Setting is set to a total initial access cycle of 2. It is recommended that the wait state command sequence be written, even if the default wait state value is desired, to ensure the device is set as expected. A hardware reset will set the wait state to the default setting. Reduced Wait-state Handshaking Option If the device is equipped with the reduced wait-state handshaking option, the host system should set 34 S H E E T address bits A14–A12 to 010 for the system/device to execute at maximum speed. Table 15 describes the typical number of clock cycles (wait states) for various conditions. Table 15. System Frequency Range Wait States for Reduced Wait-state Handshaking Device Speed Rating Even Initial Address Odd Initial Address 6–22 MHz 2 2 22–28 MHz 2 3 D (54 MHz) 28–43 MHz 3 4 43–54 MHz 4 5 6–28 MHz 2 2 28–35 MHz 2 3 E (66 MHz) 35–53 MHz 3 4 53–66 MHz 4 5 Notes: 1. If the latched address is 3Eh or 3Fh (or an address offset from either address by a multiple of 64), add two access cycles to the values listed. 2. In the 8-, 16-, and 32-word burst modes, the address pointer does not cross 64-word boundaries (3Fh, or addresses offset from 3Fh by a multiple of 64). 3. Typical initial access cycles may vary depending on system margin requirements. Am29BDS128H/Am29BDS640H 27024B3 May 10, 2006 D A T A Standard Handshaking Option For optimal burst mode performance on devices with the standard handshaking option, the host system must set the appropriate number of wait states in the flash device depending on the clock frequency. Table 16 describes the typical number of clock cycles (wait states) for various conditions with A14-A12 set to 101. Table 16. Wait States for Standard Handshaking Conditions at Address Initial address Initial address is 3E or 3Fh (or offset from these addresses by a multiple of 64) and is at boundary crossing* Typical No. of Clock Cycles after AVD# Low 7 7 * In the 8-, 16- and 32-word burst read modes, the address pointer does not cross 64-word boundaries (addresses which are multiples of 3Fh). The autoselect function allows the host system to determine whether the flash device is enabled for h an d s h ak i n g . S e e th e “ Au t os e l e c t C om m a n d Sequence” section on page 36 for more information. Read Mode Configuration The device supports four different read modes: continuous mode, and 8, 16, and 32 word linear wrap around modes. A continuous sequence begins at the starting address and advances the address pointer until the burst operation is complete. If the highest address in the device is reached during the continuous burst read mode, the address pointer wraps around to the lowest address. For example, an eight-word linear read with wrap around begins on the starting address written to the device and then advances to the next 8 word boundary. The address pointer then returns to the 1st word after the previous eight word boundary, wrapping through May 10, 2006 27024B3 S H E E T the starting location. The sixteen- and thirty-two linear wrap around modes operate in a fashion similar to the eight-word mode. Table 17 shows the address bits and settings for the four read modes. Table 17. Read Mode Settings Address Bits Burst Modes A16 A15 Continuous 0 0 8-word linear wrap around 0 1 16-word linear wrap around 1 0 32-word linear wrap around 1 1 Note: Upon power-up or hardware reset the default setting is continuous. Burst Active Clock Edge Configuration By default, the device will deliver data on the rising edge of the clock after the initial synchronous access time. Subsequent outputs will also be on the following rising edges, barring any delays. The device can be set so that the falling clock edge is active for all synchronous accesses. Address bit A17 determines this setting; “1” for rising active, “0” for falling active. RDY Configuration By default, the device is set so that the RDY pin will output VOH whenever there is valid data on the outputs. The device can be set so that RDY goes active one data cycle before active data. Address bit A18 determines this setting; “1” for RDY active with data, “0” for RDY active one clock cycle before valid data. In asynchronous mode, RDY is an open-drain output. Configuration Register Table 18 shows the address bits that determine the configuration register settings for various device functions. Am29BDS128H/Am29BDS640H 35 D A T A Table 18. S H E E T Configuration Register Address BIt Function Settings (Binary) A19 Set Device Read Mode A18 RDY 0 = RDY active one clock cycle before data 1 = RDY active with data (default) A17 Clock 0 = Burst starts and data is output on the falling edge of CLK 1 = Burst starts and data is output on the rising edge of CLK (default) 0 = Synchronous Read (Burst Mode) Enabled 1 = Asynchronous Mode (default) Synchronous Mode A16 A15 A14 A13 A12 Read Mode 00 = Continuous (default) 01 = 8-word linear with wrap around 10 = 16-word linear with wrap around 11 = 32-word linear with wrap around 000 = Data is valid on the 2th active CLK edge after AVD# transition to VIH 001 = Data is valid on the 3th active CLK edge after AVD# transition to VIH 010 = Data is valid on the 4th active CLK edge after AVD# transition to VIH Programmable 011 = Data is valid on the 5th active CLK edge after AVD# transition to VIH 100 = Data is valid on the 6th active CLK edge after AVD# transition to VIH Wait State 101 = Data is valid on the 7th active CLK edge after AVD# transition to VIH (default) 110 = Reserved 111 = Reserved Note:Device will be in the default state upon power-up or hardware reset. Reset Command Writing the reset command resets the banks to the read or erase-suspend-read mode. Address bits are don’t cares for this command. The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This resets the bank to which the system was writing to the read mode. Once erasure begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence before programming begins (prior to the third cycle). This resets the bank to which the system was writing to the read mode. If the program command sequence is written to a bank that is in the Erase Suspend mode, writing the reset command returns that bank to the erase-suspend-read mode. Once programming begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to the read mode. If a bank entered the autoselect mode while in the Erase Suspend mode, writing the reset command returns that bank to the erase-suspend-read mode. 36 If DQ5 goes high during a program or erase operation, writing the reset command returns the banks to the read mode (or erase-suspend-read mode if that bank was in Erase Suspend). Autoselect Command Sequence The autoselect command sequence allows the host system to access the manufacturer and device codes, and determine whether or not a sector is protected. Table 20, “Memory Array Command Definitions,” on page 46 shows the address and data requirements. The autoselect command sequence may be written to an address within a bank that is either in the read or erase-suspend-read mode. The autoselect command may not be written while the device is actively programming or erasing in the other bank. The autoselect command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle that contains the bank address and the autoselect command. The bank then enters the autoselect mode. No subsequent data will be made available if the autoselect data is read in synchronous mode. The system may read at any address within the same bank any number of times without initiating another autoselect command sequence. Read commands to other banks will return data from the array. The following table describes the address requirements for the various autoselect functions, and the resulting data. BA represents the bank address, and Am29BDS128H/Am29BDS640H 27024B3 May 10, 2006 D A T A SA represents the sector address. The device ID is read in three cycles. Table 19. Autoselect Data Description Address Read Data Manufacturer ID (BA) + 00h 0001h Device ID, Word 1 (BA) + 01h 227Eh (BDS128H) 221Eh (BDS640H) Device ID, Word 2 (BA) + 0Eh 2218h (BDS128H) 2201h (BDS640H) Device ID, Word 3 (BA) + 0Fh 2200h Sector Protection Verification (SA) + 02h 0001h (locked), 0000h (unlocked) DQ15 - DQ8 = 0 DQ7: Factory Lock Bit 1 = Locked, 0 = Not Locked DQ6: Customer Lock Bit Indicator Bits (BA) + 03h 1 = Locked, 0 = Not Locked DQ5: Handshake Bit 1 = Reduced Wait-state Handshake, 0 = Standard Handshake S H E E T next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further controls or timings. The device automatically provides internally generated program pulses and verifies the programmed cell margin. Table 20, “Memory Array Command Definitions,” on page 46 shows the address and data requirements for the program command sequence. When the Embedded Program algorithm is complete, that bank then returns to the read mode and addresses are no longer latched. The system can determine the status of the program operation by monitoring DQ7 or DQ6/DQ2. Refer to the “Write Operation Status” section on page 48 for information on these status bits. Any commands written to the device during the Embedded Program Algorithm are ignored. Note that a hardware reset immediately terminates the program operation. The program command sequence should be reinitiated once that bank has returned to the read mode, to ensure data integrity. Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from “0” back to a “1.” Attempting to do so may cause that bank to set DQ5 = 1, or cause the DQ7 and DQ6 status bit to indicate the operation was successful. However, a succeeding read will show that the data is still “0.” Only erase operations can convert a “0” to a “1.” Unlock Bypass Command Sequence The system must write the reset command to return to the read mode (or erase-suspend-read mode if the bank was previously in Erase Suspend). Enter SecSi™ Sector/Exit SecSi Sector Command Sequence The SecSi Sector region provides a secured data area containing a random, eight word electronic serial number (ESN). The system can access the SecSi Sector region by issuing the three-cycle Enter SecSi Sector command sequence. The device continues to access the SecSi Sector region until the system issues the four-cycle Exit SecSi Sector command sequence. The Exit SecSi Sector command sequence returns the device to normal operation. The SecSi Sector is not accessible when the device is executing an Embedded Program or embedded Erase algorithm. Table 20, “Memory Array Command Definitions,” on page 46 shows the address and data requirements for both command sequences. Program Command Sequence Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written May 10, 2006 27024B3 The unlock bypass feature allows the system to primarily program to a bank faster than using the standard program command sequence. The unlock bypass command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the unlock bypass command, 20h. The device then enters the unlock bypass mode. A two-cycle unlock bypass program command sequence is all that is required to program in this mode. The first cycle in this sequence contains the unlock bypass program command, A0h; the second cycle contains the program address and data. Additional data is programmed in the same manner. This mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total programming time. The host system may also initiate the chip erase and sector erase sequences in the unlock bypass mode. The erase command sequences are four cycles in length instead of six cycles. Table 20, “Memory Array Command Definitions,” on page 46 shows the requirements for the unlock bypass command sequences. The Unlock Bypass Reset command is required to return to reading array data when the bank is in the unlock bypass mode. During the unlock bypass mode, only the Read, Unlock Bypass Program, Unlock Bypass Sector Erase, Unlock Bypass Chip Erase, and Unlock Bypass Reset com- Am29BDS128H/Am29BDS640H 37 D A T A mands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset command sequence. The first cycle must contain the bank address and the data 90h. The second cycle need only contain the data 00h. The bank then returns to the read mode. The device offers accelerated program operations through the ACC input. When the system asserts VHH on this input, the device automatically enters the Unlock Bypass mode. The system may then write the t wo - c y c l e U n l o ck B y p a s s p r o g ra m c o m m a n d sequence. The device uses the higher voltage on the ACC input to accelerate the operation. Figure 4, “Program Operation,” on page 38 illustrates the algorithm for the program operation. Refer to the Erase/Program Operations table in the AC Characteristics section for parameters, and Figure 34, “Asynchronous Program Operation Timings: AVD# Latched Addresses,” on page 70 and Figure 36, “Synchronous Program Operation Timings: WE# Latched Addresses,” on page 72 for timing diagrams. Write Program Command Sequence No Yes Increment Address No Last Address? Yes Programming Completed Note: See Table 20 for program command sequence. Figure 4. Program Operation Chip Erase Command Sequence Chip erase is a six bus cycle operation. The chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the chip erase 38 When the Embedded Erase algorithm is complete, that bank returns to the read mode and addresses are no longer latched. The system can determine the status of the erase operation by using DQ7 or DQ6/DQ2. Refer to the “Write Operation Status” section on page 48 for information on these status bits. Any commands written during the chip erase operation are ignored. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the chip erase command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. Figure 5, “Erase Operation,” on page 40 illustrates the algorithm for the erase operation. Refer to the Erase/Program Operations table in the AC Characteristics section for parameters and timing diagrams. Data Poll from System Verify Data? command, which in turn invokes the Embedded Erase algorithm. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. Table 20, “Memory Array Command Definitions,” on page 46 shows the address and data requirements for the chip erase command sequence. The host system may also initiate the chip erase command sequence while the device is in the unlock bypass mode. The command sequence is two cycles cycles in length instead of six cycles. See Table 20, “Memory Array Command Definitions,” on page 46 for details on the unlock bypass command sequences. START Embedded Program algorithm in progress S H E E T Sector Erase Command Sequence Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock cycles are written, and are then followed by the address of the sector to be erased, and the sector erase command. Table 20, “Memory Array Command Definitions,” on page 46 shows the address and data requirements for the sector erase command sequence. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically programs and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. After the command sequence is written, a sector erase time-out of no less than t SEA occurs. During the time-out period, additional sector addresses and sector erase commands may be written. Loading the sector erase buffer may be done in any sequence, and the Am29BDS128H/Am29BDS640H 27024B3 May 10, 2006 D A T A number of sectors may be from one sector to all sectors. The time between these additional cycles must be less than t SEA , otherwise erasure may begin. Any sector erase address and command following the exceeded time-out, tSEA, may or may not be accepted. It is recommended that processor interrupts be disabled during this time to ensure all commands are accepted. The interrupts can be re-enabled after the last Sector Erase command is written. Any command other than Sector Erase or Erase Suspend during the time-out period resets that bank to the read mode. The system must rewrite the command sequence and any additional addresses and commands. The system can monitor DQ3 to determine if the sector erase timer has timed out (See “DQ3: Sector Erase Timer” section on page 51.) The time-out begins from the rising edge of the final WE# pulse in the command sequence. When the Embedded Erase algorithm is complete, the bank returns to reading array data and addresses are no longer latched. Note that while the Embedded Erase operation is in progress, the system can read data from the non-erasing bank. The system can determine the status of the erase operation by reading DQ7 or DQ6/DQ2 in the erasing bank. Refer to the “Write Operation Status” section on page 48 for information on these status bits. Once the sector erase operation has begun, only the Erase Suspend command is valid. All other commands are ignored. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the sector erase command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. The host system may also initiate the sector erase command sequence while the device is in the unlock bypass mode. The command sequence is four cycles cycles in length instead of six cycles. The Unlock Bypass Reset Command is required to return to reading array data when the bank is in the unlock bypass mode. Figure 5, “Erase Operation,” on page 40 illustrates the algorithm for the erase operation. Refer to the Erase/Program Operations table in the Figure , “AC Characteristics,” on page 69 for parameters and timing diagrams. May 10, 2006 27024B3 S H E E T Erase Suspend/Erase Resume Commands The Erase Suspend command, B0h, allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. The bank address is required when writing this command. This command is valid only during the sector erase operation, including the minimum tSEA time-out period during the sector erase command sequence. The Erase Suspend command is ignored if written during the chip erase operation or Embedded Program algorithm. When the Erase Suspend command is written during the sector erase operation, the device requires a maximum of tESL to suspend the erase operation. However, when the Erase Suspend command is written during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation. After the erase operation has been suspended, the bank enters the erase-suspend-read mode. The system can read data from or program data to any sector not selected for erasure. (The device “erase suspends” all sectors selected for erasure.) Reading at any address within erase-suspended sectors produces status information on DQ7–DQ0. The system can use DQ7, or DQ6 and DQ2 together, to determine if a sector is actively erasing or is erase-suspended. Refer to the Figure , “Write Operation Status,” on page 48 for information on these status bits. After an erase-suspended program operation is complete, the bank returns to the erase-suspend-read mode. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard program operation. Refer to the “Write Operation Status” section on page 48 for more information. In the erase-suspend-read mode, the system can also issue the autoselect command sequence. Refer to the “Autoselect Mode” section on page 14 and “Autoselect Command Sequence” section on page 36 for details. To resume the sector erase operation, the system must write the Erase Resume command. The bank address of the erase-suspended bank is required when writing this command. Further writes of the Resume command Am29BDS128H/Am29BDS640H 39 D A T A are ignored. Another Erase Suspend command can be written after the chip has resumed erasing. START No The Password Verify Command is used to verify the Password. The Password is verifiable only when the Password Mode Locking Bit is not programmed. If the Password Mode Locking Bit is programmed and the user attempts to verify the Password, the device will always drive all Fs onto the DQ data bus. Embedded Erase algorithm in progress Data = FFh? Yes Notes: 1. See Table 20 for erase command sequence. 2. See the section on DQ3 for information on the sector erase timer. Erase Operation Password Program Command The Password Program Command permits programming the password that is used as part of the hardware protection scheme. The actual password is 64-bits long. 4 Password Program commands are required to program the password. The user must enter the unlock cycle, password program command (38h) and the program address/data for each portion of the password when programming. There are no provisions for entering the 2-cycle unlock cycle, the password program command, and all the password data. There is no special addressing order required for programming the password. Also, when the password is undergoing programming, Simultaneous Operation is disabled. Read operations to any memory location will return the programming status. Once programming is complete, the user must issue a Read/Reset command to return the device to normal operation. Once the Password is written and verified, the Password Mode Locking Bit must be set in order to prevent verification. The Password Program Command is only capable of programming “0”s. Programming a “1” after a cell is programmed as a “0” results in a time-out by the Embedded Program Algorithm™ with the cell remain- 40 Also, the device will not operate in Simultaneous Operation when the Password Verify command is executed. Only the password is returned regardless of the bank address. The lower two address bits (A1–A0) are valid during the Password Verify. Writing the SecSi Sector Exit command returns the device back to normal operation. Password Protection Mode Locking Bit Program Command Erasure Completed Figure 5. ing as a “0”. The password is all Fs when shipped from the factory. All 64-bit password combinations are valid as a password. Password Verify Command Write Erase Command Sequence Data Poll from System S H E E T The Password Protection Mode Locking Bit Program Command programs the Password Protection Mode Locking Bit, which prevents further verifies or updates to the password. Once programmed, the Password Protection Mode Locking Bit cannot be erased and the Persistent Protection Mode Locking Bit program circuitry is disabled, thereby forcing the device to remain in the Password Protection Mode. After issuing “PL/68h” at the fourth bus cycle, the device requires a time out period of approximately 150 µs for programming the Password Protection Mode Locking Bit. Then by writing “PL/48h” at the fifth bus cycle, the device outputs verify data at DQ0. If DQ0 = 1, then the Password Protection Mode Locking Bit is programmed. If not, the system must repeat this program sequence from the fourth cycle of “PL/68h”. Exiting the Password Protection Mode Locking Bit Program command is accomplished by writing the SecSi Sector Exit command or Read/Reset command. Persistent Sector Protection Mode Locking Bit Program Command The Persistent Sector Protection Mode Locking Bit Program Command programs the Persistent Sector Protection Mode Locking Bit, which prevents the Password Mode Locking Bit from ever being programmed. By disabling the program circuitry of the Password Mode Locking Bit, the device is forced to remain in the Persistent Sector Protection mode of operation, once this bit is set. After issuing “SMPL/68h” at the fourth bus cycle, the device requires a time out period of approximately 150 µs for programming the Persistent Prote ction Mo de L ockin g Bit. Then by wr itin g “SMPL/48h” at the fifth bus cycle, the device outputs verify data at DQ0. If DQ0 = 1, then the Persistent Pro- Am29BDS128H/Am29BDS640H 27024B3 May 10, 2006 D A T A tection Mode Locking Bit is programmed. If not, the system must repeat this program sequence from the fourth cycle of “PL/68h”. Exiting the Persistent Protection Mode Locking Bit Program command is accomplished by writing the SecSi Sector Exit command or Reset command. SecSi Sector Protection Bit Program Command To protect the SecSi Sector, write the SecSi Sector Protect command sequence while in the SecSi Sector mode. After issuing “OPBP/48h” at the fourth bus cycle, the device requires a time out period of approximately 150 µs to protect the SecSi Sector. Then, by writing “OPBP/48” at the fifth bus cycle, the device outputs verify data at DQ0. If DQ0 = 1, then the SecSi Sector is protected. If not, then the system must repeat this program sequence from the fourth cycle of “OPBP/48h”. PPB Lock Bit Set Command The PPB Lock Bit Set command is used to set the PPB Lock bit if it is cleared either at reset or if the Password Unlock command was successfully executed. There is no PPB Lock Bit Clear command. Once the PPB Lock Bit is set, it cannot be cleared unless the device is taken through a power-on clear or the Password Unlock command is executed. Upon setting the PPB Lock Bit, the PPBs are latched into the DYBs. If the Password Mode Locking Bit is set, the PPB Lock Bit status is reflected as set, even after a power-on reset cycle. Exiting the PPB Lock Bit Set command is accomplished by writing the SecSi Sector Exit command, only while in the Persistent Sector Protection Mode. DYB Write Command The DYB Write command is used to set or clear a DYB for a given sector. The high order address bits (Amax–A11) are issued at the same time as the code 01h or 00h on DQ7-DQ0. All other DQ data bus pins are ignored during the data write cycle. The DYBs are modifiable at any time, regardless of the state of the PPB or PPB Lock Bit. The DYBs are cleared at power-up or hardware reset. Exiting the DYB Write May 10, 2006 27024B3 S H E E T command is accomplished by writing the Read/Reset command. Password Unlock Command The Password Unlock command is used to clear the PPB Lock Bit so that the PPBs can be unlocked for modification, thereby allowing the PPBs to become accessible for modification. The exact password must be entered in order for the unlocking function to occur. This command cannot be issued any faster than 2 µs at a time to prevent a hacker from running through the all 64-bit combinations in an attempt to correctly match a password. If the command is issued before the 2 µs execution window for each portion of the unlock, the command will be ignored. The Password Unlock function is accomplished by writing Password Unlock command and data to the device to perform the clearing of the PPB Lock Bit. The password is 64 bits long, so the user must write the Password Unlock command 4 times. A1 and A0 are used for matching. Writing the Password Unlock command is not address order specific. The lower address A1–A0= 00, the next Password Unlock command is to A1–A0= 01, then to A1–A0= 10, and finally to A1–A0= 11. Once the Password Unlock command is entered for all four words, the RDY pin goes LOW indicating that the device is busy. Approximately 1 µs is required for each portion of the unlock. Once the first portion of the password unlock completes (RDY is not driven and DQ6 does not toggle when read), the Password Unlock command is issued again, only this time with the next part of the password. Four Password Unlock commands are required to successfully clear the PPB Lock Bit. As with the first Password Unlock command, the RDY signal goes LOW and reading the device results in the DQ6 pin toggling on successive read operations until complete. It is the responsibility of the microprocessor to keep track of the number of Password Unlock commands, the order, and when to read the PPB Lock bit to confirm successful password unlock. In order to relock the device into the Password Mode, the PPB Lock Bit Set command can be re-issued. Exiting the Password Unlock Command is accomplished by writing SecSi Sector Exit command. Am29BDS128H/Am29BDS640H 41 D A T A Figure 6. 42 S H E E T PPB Program Algorithm Am29BDS128H/Am29BDS640H 27024B3 May 10, 2006 D A T A PPB Program Command The PPB Program command is used to program, or set, a given PPB. Each PPB is individually programmed (but is bulk erased with the other PPBs). The specific sector address (Amax–A12) are written at the same time as the program command 60h. If the PPB Lock Bit is set and the correspondingly PPB is set for the sector, the PPB Program command will not execute and the command will time out without programming the PPB. After issuing “SBA+WP/68h” at the fourth bus cycle, the device requires a time out period of approximately 150 µs to program the PPB. Writing “SBA+WP/48” at the fifth bus cycle produces verify data at DQ0. If DQ0 = 1, the PPB is programmed. If not, the system must repeat this program sequence from the fourth cycle of “SBA+WP/68h”. The PPB Program command does not follow the Embedded Program algorithm. Writing the SecSi Sector Exit command or Read/Reset command return the device back to normal operation. S H E E T ing a specific PPB. Unlike the PPB program, no specific sector address is required. However, when the PPB erase command is written (60h), all Sector PPBs are erased in parallel. If the PPB Lock Bit is set, the ALL PPB Erase command will not execute and the command will time-out without erasing the PPBs. After issuing “WP/60h” at the fourth bus cycle, the device requires a time out period of approximately 1.5 ms to erase the PPB. Writing “SBA+WP/40h” at the fifth bus cycle produces verify data at DQ0. If DQ0 = 0, the PPB is erased. If not, the system must repeat this program sequence from the fourth cycle of “WP/60h”. It is the responsibility of the system to preprogram all PPBs prior to issuing the All PPB Erase command. If the system attempts to erase a cleared PPB, over-erasure may occur, making it difficult to program the PPB at a later time. Also note that the total number of PPB program/erase cycles is limited to 100 cycles. Cycling the PPBs beyond 100 cycles is not guaranteed. Writing the SecSi Sector Exit command or Read/Reset command return the device to normal operation. All PPB Erase Command The All PPB Erase command is used to erase all PPBs in bulk. There is no means for individually eras- May 10, 2006 27024B3 Am29BDS128H/Am29BDS640H 43 D A T A Figure 7. 44 S H E E T PPB Erase Algorithm Am29BDS128H/Am29BDS640H 27024B3 May 10, 2006 D A T A DYB Write Command The DYB Write command is used for setting the DYB, which is a volatile bit that is cleared at hardware reset. There is one DYB per sector. If the PPB is set, the sector is protected regardless of the value of the DYB. If the PPB is cleared, setting the DYB to a 1 protects the sector from programs or erases. Since this is a volatile bit, removing power or resetting the device will clear the DYBs. Writing Read/Reset command returns the device to normal operations. PPB Status Command The programming of the PPB for a given sector can be verified by writing a PPB status verify command to the device. Writing Read/Reset command and SecSi Sec- May 10, 2006 27024B3 S H E E T tor Exit command return the device to normal operation. PPB Lock Bit Status Command The programming of the PPB Lock Bit for a given sector can be verified by writing a PPB Lock Bit status verify command to the device. Read/Reset and SecSi Sector Exit return the device to normal operation. DYB Status Command The programming of the DYB for a given sector can be verified by writing a DYB Status command to the device. Writing SecSi Sector Exit command returns the device to normal operation. Am29BDS128H/Am29BDS640H 45 D A T A S H E E T Command Definitions Table 20. Bus Cycles (Notes 1–6) Cycles Command Sequence (Notes) Memory Array Command Definitions First Second Addr Data RD Fourth Fifth Data Addr Data Addr Data 55 BA+555 90 BA+X00 0001 Asynchronous Read (7) 1 RA Reset (8) 1 XXX F0 Manufacturer ID 4 555 AA 2AA Autoselect (9) Third Addr Sixth Addr Data Addr Data BA+X0E (10)* BA+X0F (11)* 6 555 AA 2AA 55 BA+555 90 BA+X01 227E 4 555 AA 2AA 55 SA+555 90 SA+X02 (12)* Indicator Bits (13)* 4 555 AA 2AA 55 BA+555 90 BA+X03 (13)* Program 4 555 AA 2AA 55 555 A0 PA Data Chip Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10 Sector Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 SA 30 Entry 3 555 AA 2AA 55 555 20 Program (14, 15) 2 XX A0 PA PD (CR)555 C0 Unlock Bypass Mode Device ID (9, 10)* Sector Lock Verify (12)* Sector Erase (14, 15) 2 XX 80 SA 30 Erase (14, 15) 2 XX 80 XXX 10 CFI (14, 15) 1 XX 98 Reset (20) 2 XX 90 XXX 00 1 BA B0 2AA 55 Erase Suspend (16) Erase Resume (17) 1 BA 30 Set Configuration Register (18) 3 555 AA CFI Query (19) 1 55 98 * For actual hexadecimal data values, refer to the note number indicated. Legend: X = Don’t care RA = Address of the memory location to be read. RD = Data read from location RA during read operation. PA = Address of the memory location to be programmed. Addresses latch on the rising edge of the AVD# pulse or active edge of CLK which ever comes first. PD = Data to be programmed at location PA. Data latches on the rising edge of WE# or CE# pulse, whichever happens first. Notes: 1. See Table 1 for description of bus operations. 2. All values are in hexadecimal. 3. Shaded cells indicate read cycles. All others are write cycles. 4. Data bits DQ15–DQ8 are don’t care in command sequences, except for RD and PD. 5. Unless otherwise noted, address bits Amax–A12 are don’t cares. 6. Writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. The system must write the reset command to return the device to reading array data. 7. No unlock or command cycles required when bank is reading array data. 8. The Reset command is required to return to reading array data (or to the erase-suspend-read mode if previously in Erase Suspend) when a bank is in the autoselect mode, or if DQ5 goes high (while the bank is providing status information) or performing sector lock/unlock. 9. The fourth cycle of the autoselect command sequence is a read cycle. The system must provide the bank address. See the Autoselect Command Sequence section for more information. 10. BDS128H: 2218h; BDS640H: 221Eh. 11. BDS128H: 2200h; BDS640H: 2201h 12. The data is 0000h for an unlocked sector and 0001h for a locked sector 46 SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits Amax–A12 uniquely select any sector. BA = Address of the bank (BDS128H: A22–A20; BDS640H: A21–A19) for which command is being written. SLA = Address of the sector to be locked. Set sector address (SA) and either A6 = 1 for unlocked or A6 = 0 for locked. CR = Configuration Register address bits A19–A12. 13. DQ15–DQ8 = 0, DQ7: Factory Lock Bit (1 = Locked, 0 = Not Locked), DQ6: Customer Lock Bit (1 = Locked, 0 = Not Locked), DQ5: Handshake Bit (1 = Reduced wait-state Handshake, 0 = Standard Handshake), DQ4–DQ0 = 0 14. The Unlock Bypass command sequence is required prior to this command sequence. 15. The Unlock Bypass Reset command is required to return to reading array data when the bank is in the unlock bypass mode. 16. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The Erase Suspend command is valid only during a sector erase operation, and requires the bank address. 17. The Erase Resume command is valid only during the Erase Suspend mode, and requires the bank address. 18. See “Set Configuration Register Command Sequence” for details. This command is unavailable in Unlock Bypass mode. 19. Command is valid when device is ready to read array data or when device is in autoselect mode. 20. The Unlock Bypass Reset command is required to exit this mode before sending any other commands to the device. The only commands that are allowed in the Unlock Bypass mode are the Entry and exit (Reset), Program, Erase, Sector Erase and CFI. Am29BDS128H/Am29BDS640H 27024B3 May 10, 2006 D A T A Sector Protection Command Definitions Bus Cycles (Notes 1–6) First Second Data Addr Data Addr Fourth Data Fifth Addr Data 55 555 88 2AA 55 555 90 XX 00 Protection Bit Program (8, 9) 6 555 AA 2AA 55 555 60 SA+OW 68 SA+OW 48 OW RD(0) 4 555 AA 2AA 55 555 38 XX[0–3] PD[0–3] 4 555 AA 2AA 55 555 C8 XX[0–3] PD[0–3] Unlock (11) 7 555 AA 2AA 55 555 28 XX0 PD0 XX1 PD1 XX2 PD2 Program (8, 9) 6 555 AA 2AA 55 555 60 SBA+WP 68 SBA+WP 48 XX RD(0) All Erase (8, 10, 12) 6 555 AA 2AA 55 555 60 WPE 60 SBA+ WPE 40 XX RD(0) Status (13) 4 555 AA 2AA 55 BA+555 90 SBA+WP RD(0) Set 3 555 AA 2AA 55 555 78 Status (8) 4 555 AA 2AA 55 BA+555 58 SA RD(1) Write 4 555 AA 2AA 55 555 48 SA X1 PPB 2AA AA Data Verify (11) PPB Lock Bit AA 555 Addr Program (11) DYB 555 4 Data Entry Persistent Password Protection Protection 3 Exit Sixth Addr SecSi Sector Addr Third Password Command Sequence (Notes) Cycles Table 21. S H E E T Erase 4 555 AA 2AA 55 555 48 SA X0 Status 4 555 AA 2AA 55 BA+555 58 SA RD(0) Locking Bit Program (8, 9) 6 555 AA 2AA 55 555 60 PL 68 PL 48 PL RD(0) Locking Bit Program (8, 9) 6 555 AA 2AA 55 555 60 SL 68 SL 48 SL RD(0) Legend: X = Don’t care PA = Address of the memory location to be programmed. Addresses latch on the rising edge of the AVD# pulse or active edge of CLK which ever comes first. SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits Amax–A12 uniquely select any sector. BA = Address of the bank (BDS128H: A22–A20; BDS640H: A21–A19) for which command is being written. SLA = Address of the sector to be locked. Set sector address (SA) and either A6 = 1 for unlocked or A6 = 0 for locked. OW = Address (A7–A0) is (00011010). PD3–PD0 = Password Data. PD3–PD0 present four 16 bit combinations that represent the 64-bit password. Notes: 1. See Table 1 for description of bus operations. 2. All values are in hexadecimal. 3. Shaded cells indicate read cycles. All others are write cycles. 4. Data bits DQ15–DQ8 are don’t care in command sequences, except for RD, PD, WD, PWD, and PD3–PD0. 5. Unless otherwise noted, address bits Amax–A12 are don’t cares. 6. Writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. The system must write the reset command to return the device to reading array data. 7. No unlock or command cycles required when bank is reading array data. 8. Not supported in Synchronous Read Mode, command mode verify are always asynchronous read operations. May 10, 2006 27024B3 Seventh Addr Data XX3 PD3 PWA = Password Address. Address bits A1 and A0 are used to select each 16-bit portion of the 64-bit entity. PL = Address (A7–A0) is (00001010) RD(0) = DQ0 protection indicator bit. If protected, DQ0 = 1. If unprotected, DQ0 = 0. RD(1) = DQ1 protection indicator bit. If protected, DQ1 = 1. If unprotected, DQ1 = 0. SBA = Sector address block to be protected. SL = Address (A7–A0) is (00010010) WD= Write Data. See “Configuration Register” definition for specific write data WP = Address (A7–A0) is (00000010) WPE = Address (A7–A0) is (01000010) 9. The fourth cycle programs the addressed locking bit. The fifth and sixth cycles are used to validate whether the bit has been fully programmed. If DQ0 (in the sixth cycle) reads 0, the program command must be issued and verified again. 10. The fourth cycle erases all PPBs. The fifth and sixth cycles are used to validate whether the bits have been fully erased. If DQ0 (in the sixth cycle) reads 1, the erase command must be issued and verified again. 11. The entire four bus-cycle sequence must be entered for each portion of the password. 12. Before issuing the erase command, all PPBs should be programmed in order to prevent over-erasure of PPBs. 13. In the fourth cycle, 01h indicates PPB set; 00h indicates PPB not set. Am29BDS128H/Am29BDS640H 47 D A T A S H E E T WRITE OPERATION STATUS The device provides several bits to determine the status of a program or erase operation: DQ2, DQ3, DQ5, DQ6, and DQ7. Table 23, “Write Operation Status,” on page 52 and the following subsections describe the function of these bits. DQ7 and DQ6 each offers a method for determining whether a program or erase operation is complete or in progress. DQ7: Data# Polling invalid. Valid data on DQ7-DQ0 will appear on successive read cycles. Table 23, “Write Operation Status,” on page 52 shows the outputs for Data# Polling on DQ7. Figure 8, “Data# Polling Algorithm,” on page 48 shows the Data# Polling a l g o r it h m . F ig u r e 4 0 , “ D a t a # Po l l i n g T i m i n g s (During Embedded Algorithm),” on page 76 in the AC Characteristics section shows the Data# Polling timing diagram. The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Program or Erase algorithm is in progress or completed, or whether a bank is in Erase Suspend. Data# Polling is valid after the rising edge of the final WE# pulse in the command sequence. During the Embedded Program algorithm, the device outputs on DQ7 the complement of the datum programmed to DQ7. This DQ7 status also applies to programming during Erase Suspend. When the Embedded Program algorithm is complete, the device outputs the datum programmed to DQ7. The system must provide the program address to read valid status information on DQ7. If a program address falls within a protected sector, Data# Polling on DQ7 is active for approximately tPSP, then that bank returns to the read mode. During the Embedded Erase algorithm, Data# Polling produces a “0” on DQ7. When the Embedded Erase algorithm is complete, or if the bank enters the Erase Suspend mode, Data# Polling produces a “1” on DQ7. The system must provide an address within any of the sectors selected for erasure to read valid status information on DQ7. After an erase command sequence is written, if all sectors selected for erasing are protected, Data# Polling on DQ7 is active for approximately tASP, then the bank returns to the read mode. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. However, if the system reads DQ7 at an address within a protected sector, the status may not be valid. Just prior to the completion of an Embedded Program or Erase operation, DQ7 may change asynchronously with DQ6–DQ0 while Output Enable (OE#) is asserted low. That is, the device may change from providing status information to valid data on DQ7. Depending on when the system samples the DQ7 output, it may read the status or valid data. Even if the device has completed the program or erase operation and DQ7 has valid data, the data outputs on DQ6-DQ0 may be still Notes: 1. VA = Valid address for programming. During a sector erase operation, a valid address is any sector address within the sector being erased. During chip erase, a valid address is any non-protected sector address. 2. DQ7 should be rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5. Figure 8. 48 Am29BDS128H/Am29BDS640H Data# Polling Algorithm 27024B3 May 10, 2006 D A T A RDY: Ready The RDY is a dedicated output that, when the device is configured in the Synchronous mode, indicates (when at logic low) the system should wait 1 clock cycle before expecting the next word of data. The RDY pin is only controlled by CE#. Using the RDY Configuration Command Sequence, RDY can be set so that a logic low indicates the system should wait 2 clock cycles before expecting valid data. The following conditions cause the RDY output to be low: during the initial access (in burst mode), and after the boundary that occurs every 64 words beginning with the 64th address, 3Fh. When the device is configured in Asynchronous Mode, the RDY is an open-drain output pin which indicates whether an Embedded Algorithm is in progress or completed. The RDY status is valid after the rising edge of the final WE# pulse in the command sequence. If the output is low (Busy), the device is actively erasing or programming. (This includes programming in the Erase Suspend mode.) If the output is in high impedance (Ready), the device is in the read mode, the standby mode, or in the erase-suspend-read mode. Table 23, “Write Operation Status,” on page 52 shows the outputs for RDY. DQ6: Toggle Bit I Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address in the same bank, and is valid after the rising edge of the final WE# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. S H E E T cause DQ6 to toggle. When the operation is complete, DQ6 stops toggling. After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for approximately tASP, all sectors protected toggle time, then returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erase-suspended. When the device is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6 toggles. When the device enters the Erase Suspend mode, DQ6 stops toggling. However, the system must also use DQ2 to determine which sectors are erasing or erase-suspended. Alternatively, the system can use DQ7 (see the subsection on DQ7: Data# Polling). If a program address falls within a protected sector, DQ6 toggles for approximately tPSP after the program command sequence is written, then returns to reading array data. DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Program algorithm is complete. See the following for additional information: Figure 9, “Toggle Bit Algorithm,” on page 50, “DQ6: Toggle Bit I” o n p a g e 4 9 , F i g u r e 4 1 , “ To g g l e B i t T i m i n g s (During Embedded Algorithm),” on page 76 (toggle bit timing diagram), and Table 22, “DQ6 and DQ2 Indications,” on page 51. Toggle Bit I on DQ6 requires either OE# or CE# to be deasserted and reasserted to show the change in state. During an Embedded Program or Erase algorithm operation, successive read cycles to any address May 10, 2006 27024B3 Am29BDS128H/Am29BDS640H 49 D A T A S H E E T DQ2: Toggle Bit II The “Toggle Bit II” on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command sequence. START Read Byte (DQ7-DQ0) Address = VA DQ2 toggles when the system reads at addresses within those sectors that have been selected for erasure. But DQ2 cannot distinguish whether the sector is actively erasing or is erase-suspended. DQ6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for sector and mode information. Refer to Table 22, “DQ6 and DQ2 Indications,” on page 51 to compare outputs for DQ2 and DQ6. Read Byte (DQ7-DQ0) Address = VA DQ6 = Toggle? No Yes No See the following for additional information: Figure 9, “Toggle Bit Algorithm,” on page 50, “DQ6: Toggle Bit I” o n p a g e 4 9 , F i g u r e 4 1 , “ To g g l e B i t T i m i n g s (During Embedded Algorithm),” on page 76, and Table 22, “DQ6 and DQ2 Indications,” on page 51. DQ5 = 1? Yes Read Byte Twice (DQ7-DQ0) Adrdess = VA DQ6 = Toggle? No Yes FAIL PASS Note:The system should recheck the toggle bit even if DQ5 = “1” because the toggle bit may stop toggling as DQ5 changes to “1.” See the subsections on DQ6 and DQ2 for more information. Figure 9. 50 Toggle Bit Algorithm Am29BDS128H/Am29BDS640H 27024B3 May 10, 2006 D A T A S H E E T Table 22. DQ6 and DQ2 Indications If device is and the system reads then DQ6 and DQ2 programming, at any address, toggles, does not toggle. at an address within a sector selected for erasure, toggles, also toggles. at an address within sectors not selected for erasure, toggles, does not toggle. at an address within a sector selected for erasure, does not toggle, toggles. at an address within sectors not selected for erasure, returns array data, returns array data. The system can read from any sector not selected for erasure. at any address, toggles, is not applicable. actively erasing, erase suspended, programming in erase suspend Reading Toggle Bits DQ6/DQ2 DQ5: Exceeded Timing Limits Refer to Figure 9, “Toggle Bit Algorithm,” on page 50 for the following discussion. Whenever the system initially begins reading toggle bit status, it must read DQ7–DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typically, the system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on DQ7–DQ0 on the following read cycle. DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. Under these conditions DQ5 produces a “1,” indicating that the program or erase cycle was not successfully completed. However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the device did not completed the operation successfully, and the system must write the reset command to return to reading array data. The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation (Figure 9, “Toggle Bit Algorithm,” on page 50). May 10, 2006 27024B3 The device may output a “1” on DQ5 if the system tries to program a “1” to a location that was previously programmed to “0.” Only an erase operation can change a “0” back to a “1.” Under this condition, the device halts the operation, and when the timing limit has been exceeded, DQ5 produces a “1.” Under both these conditions, the system must write the reset command to return to the read mode (or to the erase-suspend-read mode if a bank was previously in the erase-suspend-program mode). DQ3: Sector Erase Timer After writing a sector erase command sequence, the system may read DQ3 to determine whether or not erasure has begun. (The sector erase timer does not apply to the chip erase command.) If additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase command. When the time-out period is complete, DQ3 switches from a “0” to a “1.” If the time between additional sector erase commands from the system can be assumed to be less than tSEA, the system need not monitor DQ3. See also “Sector Erase Command Sequence” on page 38. After the sector erase command is written, the system should read the status of DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to ensure that the device has accepted the command sequence, and then read DQ3. If DQ3 is “1,” the Embedded Erase algorithm has begun; all further commands (except Erase Suspend) are ignored until the erase operation is complete. If DQ3 is “0,” the Am29BDS128H/Am29BDS640H 51 D A T A S H E E T device will accept additional sector erase commands. To ensure the command has been accepted, the system software should check the status of DQ3 prior to and following each subsequent sector erase com- Table 23. Erase Suspend Mode Write Operation Status DQ6 DQ5 (Note 1) DQ3 DQ2 (Note 2) RDY (Note 5) DQ7# Toggle 0 N/A No toggle 0 0 Toggle 0 1 Toggle 0 Erase Suspended Sector 1 No toggle 0 N/A Toggle High Impedance Non-Erase Suspended Sector Data Data Data Data Data High Impedance DQ7# Toggle 0 N/A N/A 0 Embedded Program Algorithm Embedded Erase Algorithm Erase-SuspendRead (Note 4) Table 23 shows the status of DQ3 relative to the other status bits. DQ7 (Note 2) Status Standard Mode mand. If DQ3 is high on the second status check, the last command might not have been accepted. Erase-Suspend-Program Notes: 1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. Refer to the section on DQ5 for more information. 2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details. 3. When reading write operation status bits, the system must always provide the bank address where the Embedded Algorithm is in progress. The device outputs array data if the system addresses a non-busy bank. 4. The system may read either asynchronously or synchronously (burst) while in erase suspend. 5. The RDY pin acts a dedicated output to indicate the status of an embedded erase or program operation is in progress. This is available in the Asynchronous mode only. 52 Am29BDS128H/Am29BDS640H 27024B3 May 10, 2006 D A T A S H E E T ABSOLUTE MAXIMUM RATINGS Storage Temperature Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°C Ambient Temperature with Power Applied. . . . . . . . . . . . . . –65°C to +125°C Voltage with Respect to Ground: All Inputs and I/Os except as noted below (Note 1) . . . . . . . –0.5 V to VIO + 0.5 V 20 ns 20 ns +0.8 V –0.5 V –2.0 V VCC (Note 1) . . . . . . . . . . . . . . . . . . –0.5 V to +2.5 V 20 ns VIO . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to +2.5 V A9, RESET#, ACC (Note 1) . . . . . –0.5 V to +12.5 V Output Short Circuit Current (Note 3) . . . . . . 100 mA Notes: 1. Minimum DC voltage on input or I/Os is –0.5 V. During voltage transitions, inputs or I/Os may undershoot VSS to –2.0 V for periods of up to 20 ns. See Figure 10. Maximum DC voltage on input or I/Os is VCC + 0.5 V. During voltage transitions outputs may overshoot to VCC + 2.0 V for periods up to 20 ns. See Figure 11. 2. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second. 3. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. Figure 10. Maximum Negative Overshoot Waveform 20 ns VCC +2.0 V VCC +0.5 V 1.0 V 20 ns 20 ns Figure 11. Maximum Positive Overshoot Waveform OPERATING RANGES Industrial (I) Devices Ambient Temperature (TA) . . . . . . . . . –40°C to +85°C Supply Voltages VCC Supply Voltages . . . . . . . . . . .+1.65 V to +1.95 V . . . . . . . . . . . . . . . . . . . . . . . . . . . VCC ≥ VIO–100 mV VIO Supply Voltages . . . . . . . . . . . +1.65 V to +1.95 V Operating ranges define those limits between which the functionality of the device is guaranteed. May 10, 2006 27024B3 Am29BDS128H/Am29BDS640H 53 D A T A S H E E T DC CHARACTERISTICS CMOS COMPATIBLE Parameter Description Test Conditions Note: 1 & 2 Min Typ Max Unit ILI Input Load Current VIN = VSS to VCC, VCC = VCCmax ±1 µA ILO Output Leakage Current VOUT = VSS to VCC, VCC = VCCmax ±1 µA ICCB VCC Active burst Read Current CE# = VIL, OE# = VIH, WE# = VIH, burst length =8 54 MHz 9 17 mA CE# = VIL, OE# = VIH, WE# = VIH, burst length = 16 54 MHz 8 15.5 mA CE# = VIL, OE# = VIH, WE# = VIH, burst length = Continuous 54 MHz 7 14 mA 1 40 µA 10 MHz 20 30 mA 5 MHz 10 15 mA 1 MHz 3.5 5 mA IIO1 VIO Non-active Output OE# = VIH ICC1 VCC Active Asynchronous Read Current (Note 3) CE# = VIL, OE# = VIH, WE# = VIH ICC2 VCC Active Write Current (Note 4) CE# = VIL, OE# = VIH, ACC = VIH 15 40 mA ICC3 VCC Standby Current (Note 5) CE# = RESET# = VCC ± 0.2 V 0.2 40 µA ICC4 VCC Reset Current RESET# = VIL, CLK = VIL 1 40 µA ICC5 VCC Active Current (Read While Write) CE# = VIL, OE# = VIH 25 60 mA ICC6 VCC Sleep Current CE# = VIL, OE# = VIH 1 40 µA Accelerated Program Current (Note 6) CE# = VIL, OE# = VIH, VACC = 12.0 ± 0.5 V VACC 7 15 mA IACC VCC 5 10 mA VIL Input Low Voltage VIO = 1.8 V –0.4 0.4 V VIH Input High Voltage VIO = 1.8 V VIO – 0.4 VIO + 0.4 V VOL Output Low Voltage IOL = 100 µA, VIO = VCC = VCC min 0.1 V VOH Output High Voltage IOH = –100 µA, VIO = VCC = VCC min VID Voltage for Autoselect and Temporary Sector Unprotect VCC = 1.8 V VHH VLKO VIO – 0.1 V 11.5 12.5 V Voltage for Accelerated Program 11.5 12.5 V Low VCC Lock-out Voltage 1.0 1.4 V Note: 1. Maximum ICC specifications are tested with VCC = VCCmax. 2. VIO= VCC 3. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH. 4. ICC active while Embedded Erase or Embedded Program is in progress. 5. Device enters automatic sleep mode when addresses are stable for tACC + 60 ns. Typical sleep mode current is equal to ICC3. 6. Total current during accelerated programming is the sum of VACC and VCC currents. 54 Am29BDS128H/Am29BDS640H 27024B3 May 10, 2006 D A T A S H E E T TEST CONDITIONS Table 24. Device Under Test Test Condition All Speed Options Unit Output Load Capacitance, CL (including jig capacitance) 30 pF Input Rise and Fall Times 3 ns 0.0–VIO V Input timing measurement reference levels VIO/2 V Output timing measurement reference levels VIO/2 V Input Pulse Levels CL Figure 12. Test Specifications Test Setup KEY TO SWITCHING WAVEFORMS WAVEFORM INPUTS OUTPUTS Steady Changing from H to L Changing from L to H Don’t Care, Any Change Permitted Changing, State Unknown Does Not Apply Center Line is High Impedance State (High Z) SWITCHING WAVEFORMS All Inputs and Outputs VIO Input VIO/2 Measurement Level VIO/2 Output 0.0 V Figure 13. May 10, 2006 27024B3 Input Waveforms and Measurement Levels Am29BDS128H/Am29BDS640H 55 D A T A S H E E T AC CHARACTERISTICS VCC Power-up Parameter Description Test Setup Speed Unit tVCS VCC Setup Time Min 50 µs tVIOS VIO Setup Time Min 50 µs tRSTH RESET# Low Hold Time Min 50 µs tVCS VCCf tVIOS VIOf tRSTH RESET# Figure 14. VCC Power-up Diagram Notes: 1. VCC ≥ VIO–100 mV and VCC ramp rate exceeds 1 V/100 µs. 2. If the VCC ramp rate is less than 1 V /100 µs, a hardware reset will be required. CLK Characterization Parameter Description 66 MHz 54 MHz Unit fCLK CLK Frequency Max 66 54 MHz tCLK CLK Period Min 15 18.5 ns tCH CLK High Time Min 6.0 7.4 ns tCL CLK Low Time tCR CLK Rise Time Max 3 3 ns tCF CLK Fall Time tCLK tCH CLK tCF tCR Figure 15. 56 tCL CLK Characterization Am29BDS128H/Am29BDS640H 27024B3 May 10, 2006 D A T A S H E E T AC CHARACTERISTICS Synchronous/Burst Read Parameter JEDEC Standard Description 66 MHz 54 MHz Unit tIACC Latency (Even address in Reduced wait-state Handshaking mode) Max 56 69 ns tIACC Latency (Standard Handshaking or Odd address in Reduced wait-state Handshaking mode Max 71 87.5 ns tBACC Burst Access Time Valid Clock to Output Delay Max 11 13.5 ns tACS Address Setup Time to CLK (Note ) Min 4 5 ns tACH Address Hold Time from CLK (Note ) Min 6 7 ns tBDH Data Hold Time from Next Clock Cycle Min 3 4 ns tCR Chip Enable to RDY Valid Max 11 13.5 ns tOE Output Enable to Output Valid Max 11 13.5 ns tCEZ Chip Enable to High Z Max 8 10 ns tOEZ Output Enable to High Z Max 8 10 ns tCES CE# Setup Time to CLK Min 4 5 ns tRDYS RDY Setup Time to CLK Min 4 5 ns tRACC Ready Access Time from CLK Max 11 13.5 ns tAAS Address Setup Time to AVD# (Note ) Min 4 5 ns tAAH Address Hold Time to AVD# (Note ) Min 6 7 ns tCAS CE# Setup Time to AVD# Min 0 tAVC AVD# Low to CLK Min 4 5 ns tAVD AVD# Pulse Min 10 12 ns tACC Access Time Max 50 55 ns tCKA CLK to access resume Max 11 13.5 ns tCKZ CLK to High Z Max 8 10 ns tOES Output Enable Setup Time Min 4 5 ns tRCC Read cycle for continuous suspend Max 1 ns ms Note: Addresses are latched on the first of either the active edge of CLK or the rising edge of AVD#. May 10, 2006 27024B3 Am29BDS128H/Am29BDS640H 57 D A T A S H E E T AC CHARACTERISTICS tCES CE#f tCEZ 7 cycles for initial access shown. 1 2 3 4 5 6 7 CLK tAVC AVD# tAVD tACS tBDH Addresses Aa tBACC tACH Hi-Z Data tIACC Da Da + 1 Da + n tACC tOEZ OE# tCR RDY tRACC tOE Hi-Z Hi-Z tRDYS Notes: 1. Figure shows total number of wait states set to seven cycles. The total number of wait states can be programmed from two cycles to seven cycles. 2. If any burst address occurs at a 64-word boundary, two additional clock cycle are inserted, and is indicated by RDY. 3. The device is in synchronous mode. Figure 16. CLK Synchronous Burst Mode Read (rising active CLK) tCES CE# 1 tCEZ 4 cycles for initial access shown. 2 3 4 5 CLK tAVC AVD# tAVD tACS tBDH Addresses Aa tBACC tACH Hi-Z Data tIACC tACC Da Da + 1 Da + n tOEZ OE# Hi-Z tOE tCR tRACC Hi-Z RDY tRDYS Notes: 1. Figure shows total number of wait states set to four cycles. The total number of wait states can be programmed from two cycles to seven cycles. Clock is set for active falling edge. 2. If any burst address occurs at a 64-word boundary, two additional clock cycle are inserted, and is indicated by RDY. 3. The device is in synchronous mode. Figure 17. 58 CLK Synchronous Burst Mode Read (Falling Active Clock) Am29BDS128H/Am29BDS640H 27024B3 May 10, 2006 D A T A S H E E T AC CHARACTERISTICS tCEZ 7 cycles for initial access shown. tCAS CE# 1 2 3 4 5 6 7 CLK tAVC AVD# tAVD tAAS Addresses tBDH Aa tBACC tAAH Hi-Z Data tIACC Da Da + 1 Da + n tACC tOEZ OE# tCR RDY tRACC tOE Hi-Z Hi-Z tRDYS Notes: 1. Figure shows total number of wait states set to seven cycles. The total number of wait states can be programmed from two cycles to seven cycles. Clock is set for active rising edge. 2. If any burst address occurs at a 64-word boundary, two additional clock cycle are inserted, and is indicated by RDY. 3. The device is in synchronous mode. Figure 18. tCES Synchronous Burst Mode Read 7 cycles for initial access shown. CE# 1 2 3 4 5 6 7 CLK tAVC AVD# tAVD tACS Addresses tBDH A6 tBACC tACH Data tIACC D6 D7 D0 D1 D5 D6 tACC OE# tCR RDY tRACC tOE Hi-Z tRDYS Note: Figure assumes 7 wait states for initial access and automatic detect synchronous read. D0–D7 in data waveform indicate the order of data within a given 8-word address range, from lowest to highest. Starting address in figure is the 7th address in range (A6). See “Requirements for Synchronous (Burst) Read Operation”. The Set Configuration Register command sequence has been written with A18=1; device will output RDY with valid data. Figure 19. May 10, 2006 27024B3 8-word Linear Burst with Wrap Around Am29BDS128H/Am29BDS640H 59 D A T A S H E E T AC CHARACTERISTICS tCES tCEZ 6 wait cycles for initial access shown. CE# 1 2 3 4 5 6 CLK tAVC AVD# tAVD tACS Addresses tBDH Aa tBACC tACH Hi-Z Data tIACC Da tACC RDY Da+2 Da+3 Da + n tOEZ tRACC OE# tCR Da+1 tOE Hi-Z Hi-Z tRDYS Note: Figure assumes 6 wait states for initial access and synchronous read. The Set Configuration Register command sequence has been written with A18=0; device will output RDY one cycle before valid data. Figure 20. 60 Linear Burst with RDY Set One Cycle Before Data Am29BDS128H/Am29BDS640H 27024B3 May 10, 2006 D A T A S H E E T AC CHARACTERISTICS Suspend Resume x x+2 x+1 x+3 x+4 x+5 x+6 x+7 x+8 CLK AVD# tOES tOES Addresses tCKA tCKZ OE# Data D(20) D(20) D(21) D(22) D(23) D(23) D(23) D(24) RDY tRACC tRACC Note: Figure is for any even address other than 3Eh (or multiple thereof). Figure 21. Reduced Wait-state Handshake Burst Suspend/Resume at an Even Address Suspend Resume x x+2 x+1 x+3 x+4 x+5 x+6 x+7 x+8 CLK AVD# tOES tOES Addresses tCKZ OE# Data D(23) D(23) RDY tCKA tRACC D(24) D(25) D(25) D(25) D(26) D(27) tRACC Note: Figure is for any odd address other than 3Fh (or multiple thereof). Figure 22. May 10, 2006 27024B3 Reduced Wait-state Handshake Burst Suspend/Resume at an Odd Address Am29BDS128H/Am29BDS640H 61 D A T A S H E E T AC CHARACTERISTICS Resume Suspend x+2 x+1 x x+3 x+4 x+5 x+7 x+6 x+8 x+9 x+10 CLK AVD# tOES tOES Addresses OE# Data RDY tCKA tCKZ D(3E) D(3E) D(3F) D(3F) D(40) D(3F) D(41) D(42) D(41) D(41) D(41) tRACC tRACC Figure 23. Reduced Wait-state Handshake Burst Suspend/Resume at Address 3Eh (or Offset from 3Eh) Resume Suspend x x+2 x+1 x+3 x+4 x+5 x+7 x+6 x+8 x+9 x+10 CLK AVD# tOES tOES Addresses OE# Data RDY tRACC Figure 24. 62 tCKZ D(3F) tCKA D(3F) D(3F) D(3F) D(40) D(41) D(41) D(41) D(42) D(41) D(43) tRACC tRACC Reduced Wait-state Handshake Burst Suspend/Resume at Address 3Fh (or Offset from 3Fh by a Multiple of 64) Am29BDS128H/Am29BDS640H 27024B3 May 10, 2006 D A T A S H E E T AC CHARACTERISTICS Resume Suspend 1 CLK 2 3 6 5 4 x 7 x+2 x+1 x+3 x+4 x+6 x+5 x+7 x+8 AVD# tOES Addresses tOES A(n) tCKA OE# Data(1) tACC RDY(1) D(n) D(n+1) D(n+2) 3F 3F D(3F) D(40) D(n) D(n+1) D(n+2) D(n+3) D(n+4) D(n+5) D(n+6) tRACC Data(2) RDY(2) tRACC Note: Figure assumes 6 wait states for initial access and synchronous read. The Set Configuration Register command sequence has been written with A18=0; device will output RDY with valid data. 1) RDY goes low during the two-cycle latency during a boundary crossing. 2) RDY stays high when a burst sequence crosses no boundaries. Figure 25. Standard Handshake Burst Suspend Prior to Initial Access Resume Suspend 1 CLK 2 3 4 6 5 7 8 9 x x+2 x+1 x+3 AVD# tOES Addresses tOES tOES A(n) tCKA OE#(1) tCKA tCKZ D(n) Data(1) D(n) D(n+1) D(n+1) D(n+2) tACC tRACC RDY(1) tRACC tRACC OE#(2) Data(2) D(n) D(n+1) tRACC RDY(2) tRACC tRACC Note: Figure assumes 6 wait states for initial access and synchronous read. The Set Configuration Register command sequence has been written with A18=0; device will output RDY with valid data. 1) Burst suspend during the initial synchronous access 2) Burst suspend after one clock cycle following the initial synchronous access Figure 26. May 10, 2006 27024B3 Standard Handshake Burst Suspend at or after Initial Access Am29BDS128H/Am29BDS640H 63 D A T A S H E E T AC CHARACTERISTICS Resume Suspend CLK 1 2 3 4 6 5 7 8 x 9 x+2 x+1 x+5 x+4 x+3 AVD# tOES tOES Addresses tOES A(3D) tCKA tCKA OE# Data tCKZ D(3D) D(3E) D(3F) D(3F) D(3F) D(3F) D(4D) tACC tRACC tRACC tRACC RDY Note: Figure assumes 6 wait states for initial access and synchronous read. The Set Configuration Register command sequence has been written with A18=0; device will output RDY with valid data. Figure 27. Standard Handshake Burst Suspend at Address 3Fh (Starting Address 3Dh or Earlier) Resume Suspend CLK 1 2 3 4 5 6 AVD# Addresses(1) OE# 7 8 x tOES x+1 x+2 x+3 x+4 x+5 x+6 tOES A(3E) tOES tCKA tCKZ D(3E) D(3E) Data(1) D(3F) D(40) D(41) D(42) D(40) D(41) D(42) D(43) tACC tRACC RDY(1) Addresses(2) tRACC A(3F) Data(2) RDY(2) tRACC D(3F) D(3F) tRACC tRACC tRACC Note: Figure assumes 6 wait states for initial access and synchronous read. The Set Configuration Register command sequence has been written with A18=0; device will output RDY with valid data. 1) Address is 3Eh or offset by a multiple of 64 (40h). 2) Address is 3Fh or offset by a multiple of 64 (40h). Figure 28. 64 Standard Handshake Burst Suspend at Address 3Eh/3Fh (Without a Valid Initial Access) Am29BDS128H/Am29BDS640H 27024B3 May 10, 2006 D A T A S H E E T AC CHARACTERISTICS Suspend 1 CLK 2 3 5 4 6 7 8 Resume 9 x x+1 x+2 x+3 x+4 x+5 x+6 AVD# tOES Addresses(1) tOES A(3E) tOES OE# tCKA tCKZ Data(1) Addresses(2) D(3F) D(3E) tACC RDY(1) (Even) tRACC D(3F) tRACC D(40) D(41) D(42) D(41) D(42) D(43) tRACC A(3F) Data(2) D(3F) RDY(2) (Odd) D(40) tRACC D(40) tRACC tRACC Note: Figure assumes 6 wait states for initial access and synchronous read. The Set Configuration Register command sequence has been written with A18=0; device will output RDY with valid data. 1) Address is 3Eh or offset by a multiple of 64 (40h) 2) Address is 3Fh or offset by a multiple of 64 (40h) Figure 29. Standard Handshake Burst Suspend at Address 3Eh/3Fh (with 1 Access CLK) Resume Suspend 1 CLK 2 3 5 4 6 7 x x+2 x+1 x+3 x+4 x+5 x+6 x+7 x+8 tRCC AVD# tOES Addresses tOES A(n) tCKA OE# Data(1) RDY D(n) D(n+1) D(n+2) D(3F) D(3F) D(3F) D(40) tACC tRACC Data(2) D(n) CE# ??? ??? tRCC Note: Figure assumes 6 wait states for initial access and synchronous read. The Set Configuration Register command sequence has been written with A18=0; device will output RDY with valid data. 1) Device crosses a page boundary prior to tRCC. 2) Device neither crosses a page boundary nor latches a new address prior to tRCC. Figure 30. May 10, 2006 27024B3 Read Cycle for Continuous Suspend Am29BDS128H/Am29BDS640H 65 D A T A S H E E T AC CHARACTERISTICS Asynchronous Mode Read Parameter JEDEC Standard Description 75 MHz 66 MHz 54 MHz Unit tCE Access Time from CE# Low Max 45 50 55 ns tACC Asynchronous Access Time (Note 1) Max 45 50 55 ns tAVDP AVD# Low Time Min 10 12 ns tAAVDS Address Setup Time to Rising Edge of AVD Min 4 5 ns tAAVDH Address Hold Time from Rising Edge of AVD Min 5.5 6 7 ns tOE Output Enable to Output Valid Max 8.5 11 13.5 ns Read Min tOEH Output Enable Hold Time Toggle and Data# Polling Min 8 10 ns tOEZ Output Enable to High Z (Note 2) Max 8 10 ns tCAS CE# Setup Time to AVD# Min 0 0 ns ns Notes: 1. Asynchronous Access Time is from the last of either stable addresses or the falling edge of AVD#. 2. Not 100% tested. 66 Am29BDS128H/Am29BDS640H 27024B3 May 10, 2006 D A T A S H E E T AC CHARACTERISTICS CE# tOE OE# tOEH WE# tCE tOEZ Data Valid RD tACC RA Addresses tAAVDH tCAS AVD# tAVDP tAAVDS Note: RA = Read Address, RD = Read Data. Figure 31. Asynchronous Mode Read with Latched Addresses CE# tOE OE# tOEH WE# tCE Data tOEZ Valid RD tACC RA Addresses AVD# Note: RA = Read Address, RD = Read Data. Figure 32. May 10, 2006 27024B3 Asynchronous Mode Read Am29BDS128H/Am29BDS640H 67 D A T A S H E E T AC CHARACTERISTICS Hardware Reset (RESET#) Parameter JEDEC Std Description All Speed Options Unit tReadyw RESET# Pin Low (During Embedded Algorithms) to Read Mode (See Note) Max 20 μs tReady RESET# Pin Low (NOT During Embedded Algorithms) to Read Mode (See Note) Max 500 ns tRP RESET# Pulse Width Min 500 ns tRH Reset High Time Before Read (See Note) Min 200 ns tRPD RESET# Low to Standby Mode Min 20 μs Note: Not 100% tested. CE#, OE# tRH RESET# tRP tReady Reset Timings NOT during Embedded Algorithms Reset Timings during Embedded Algorithms CE#, OE# tReadyw RESET# tRP Figure 33. 68 Reset Timings Am29BDS128H/Am29BDS640H 27024B3 May 10, 2006 D A T A S H E E T AC CHARACTERISTICS Erase/Program Operations Parameter JEDEC Standard Description 75 MHz 66 MHz 54 MHz Unit 45 50 55 ns tAVAV tWC Write Cycle Time (Note 1) Min tAVWL tAS Address Setup Time (Notes 2, 3) Min tWLAX tAH Address Hold Time (Notes 2, 3) tAVDP AVD# Low Time Min 10 12 ns tDVWH tDS Data Setup Time Min 20 45 ns tWHDX tDH Data Hold Time Min 0 ns tGHWL tGHWL Read Recovery Time Before Write Min 0 ns tCAS CE# Setup Time to AVD# Min 0 ns tWHEH tCH CE# Hold Time Min 0 ns tWLWH tWP Write Pulse Width Min tWHWL tWPH Write Pulse Width High Min tSR/W Latency Between Read and Write Operations Min 0 ns tVID VACC Rise and Fall Time Min 500 ns tVIDS VACC Setup Time (During Accelerated Programming) Min 1 µs tVCS VCC Setup Time Min 50 µs tCS CE# Setup Time to WE# Min 0 ns tAVSW AVD# Setup Time to WE# Min 4 5 ns tAVHW AVD# Hold Time to WE# Min 4 5 ns tACS Address Setup Time to CLK (Notes 2, 3) Min 4 5 ns tACH Address Hold Time to CLK (Notes 2, 3) Min 7 ns tAVHC AVD# Hold Time to CLK Min 5 ns tCSW Clock Setup Time to WE# Min 5 ns tSEA Sector Erase Accept Timeout Max 50 µs tESL Erase Suspend Latency Max 35 µs tASP Toggle Time During Sector Protection Typ 100 µs tPSP Toggle Time During Programming within a Protected Sector Typ 1 µs tELWL Synchronous 5 ns Asynchronous 0 Synchronous 5.5 6 7 15 20 20 Min Asynchronous Notes: 1. Not 100% tested. 2. Asynchronous mode allows both Asynchronous and Synchronous program operation. Synchronous mode allows both Asynchronous and Synchronous program operation. 3. In asynchronous program operation timing, addresses are latched on the falling edge of WE# or rising edge of AVD#. In synchronous May 10, 2006 27024B3 4 ns 20 15 20 5.5 6 4 30 ns 20 ns program operation timing, addresses are latched on the first of either the falling edge of WE# or the active edge of CLK. 4. See the “Erase and Programming Performance” section for more information. 5. Does not include the preprogramming time. Am29BDS128H/Am29BDS640H 69 D A T A S H E E T AC CHARACTERISTICS Program Command Sequence (last two cycles) VIH Read Status Data CLK VIL tAVDP AVD# tAH tAS Addresses VA PA 555h Data A0h VA In Progress PD Complete tDS tDH CE#f tCH OE# tWP WE# tWHWH1 tCS tWPH tWC tVCS VCCf Notes: 1. PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits. 2. “In progress” and “complete” refer to status of program operation. 3. Amax–A12 are don’t care during command sequence unlock cycles. 4. CLK can be either VIL or VIH. 5. The Asynchronous programming operation is independent of the Set Device Read Mode bit in the Configuration Register. Figure 34. 70 Asynchronous Program Operation Timings: AVD# Latched Addresses Am29BDS128H/Am29BDS640H 27024B3 May 10, 2006 D A T A S H E E T AC CHARACTERISTICS Program Command Sequence (last two cycles) Read Status Data VIH CLK VIL tAVSW tAVHW AVD# tAVDP tAS tAH Addresses 555h VA PA Data A0h VA In Progress PD Complete tDS tDH CE#f tCH OE# tWP WE# tWHWH1 tCS tWPH tWC tVCS VCCf Notes: 1. PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits. 2. “In progress” and “complete” refer to status of program operation. 3. Amax–A12 are don’t care during command sequence unlock cycles. 4. CLK can be either VIL or VIH. 5. The Asynchronous programming operation is independent of the Set Device Read Mode bit in the Configuration Register. Figure 35. May 10, 2006 27024B3 Asynchronous Program Operation Timings: WE# Latched Addresses Am29BDS128H/Am29BDS640H 71 D A T A S H E E T AC CHARACTERISTICS Program Command Sequence (last two cycles) Read Status Data tAVCH CLK tACS tACH AVD# tAVDP Addresses VA PA 555h Data In Progress PD A0h VA Complete tDS tDH tCAS CE#f OE# tCH tCSW tWP WE# tWHWH1 tWPH tWC tVCS VCCf Notes: 1. PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits. 2. “In progress” and “complete” refer to status of program operation. 3. Amax–A12 are don’t care during command sequence unlock cycles. 4. Addresses are latched on the first of either the rising edge of AVD# or the active edge of CLK. 5. Either CE# or AVD# is required to go from low to high in between programming command sequences. 6. The Synchronous programming operation is dependent of the Set Device Read Mode bit in the Configuration Register. The Configuration Register must be set to the Synchronous Read Mode. Figure 36. 72 Synchronous Program Operation Timings: WE# Latched Addresses Am29BDS128H/Am29BDS640H 27024B3 May 10, 2006 D A T A S H E E T AC CHARACTERISTICS Program Command Sequence (last two cycles) Read Status Data tAVCH CLK tAS tAH AVD# tAVDP Addresses VA PA 555h Data In Progress PD A0h VA Complete tDS tDH tCAS CE#f OE# tCH tCSW tWP WE# tWHWH1 tWPH tWC tVCS VCCf Notes: 1. PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits. 2. “In progress” and “complete” refer to status of program operation. 3. Amax–A12 are don’t care during command sequence unlock cycles. 4. Addresses are latched on the first of either the rising edge of AVD# or the active edge of CLK. 5. Either CE# or AVD# is required to go from low to high in between programming command sequences. 6. The Synchronous programming operation is dependent of the Set Device Read Mode bit in the Configuration Register. The Configuration Register must be set to the Synchronous Read Mode. Figure 37. May 10, 2006 27024B3 Synchronous Program Operation Timings: CLK Latched Addresses Am29BDS128H/Am29BDS640H 73 D A T A S H E E T AC CHARACTERISTICS Erase Command Sequence (last two cycles) VIH Read Status Data CLK VIL tAVDP AVD# tAH tAS Addresses 555h for chip erase Data VA SA 2AAh 55h VA 10h for chip erase In Progress 30h Complete tDS tDH CE# tCH OE# tWP WE# tCS tVCS tWHWH2 tWPH tWC VCC Figure 38. Chip/Sector Erase Command Sequence Notes: 1. SA is the sector address for Sector Erase. 2. Address bits Amax–A12 are don’t cares during unlock cycles in the command sequence. 74 Am29BDS128H/Am29BDS640H 27024B3 May 10, 2006 D A T A S H E E T AC CHARACTERISTICS CE# AVD# WE# Addresses PA Don't Care Data OE# ACC 1 μs A0h Don't Care PD Don't Care tVIDS VID tVID VIL or VIH Note: Use setup and hold times from conventional program operation. Figure 39. Accelerated Programming Timing May 10, 2006 27024B3 Am29BDS128H/Am29BDS640H 75 D A T A S H E E T AC CHARACTERISTICS AVD# tCEZ tCE CE# tCH tOEZ tOE OE# tOEH WE# tACC Addresses VA VA Status Data Data Status Data Notes: 1. Status reads in figure are shown as asynchronous. 2. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is complete, and Data# Polling will output true data. 3. While in Asynchronous mode, RDY will be low while the device is in embedded erase or programming mode. Figure 40. Data# Polling Timings (During Embedded Algorithm) AVD# tCEZ tCE CE# tCH tOEZ tOE OE# tOEH WE# tACC Addresses VA Data VA Status Data Status Data Notes: 1. Status reads in figure are shown as asynchronous. 2. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is complete, the toggle bits will stop toggling. 3. While in Asynchronous mode, RDY will be low while the device is in embedded erase or programming mode. Figure 41. 76 Toggle Bit Timings (During Embedded Algorithm) Am29BDS128H/Am29BDS640H 27024B3 May 10, 2006 D A T A S H E E T AC CHARACTERISTICS CE# CLK AVD# Addresses VA VA OE# tIACC Data tIACC Status Data Status Data RDY Notes: 1. The timings are similar to synchronous read timings. 2. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is complete, the toggle bits will stop toggling. 3. RDY is active with data (A18 = 0 in the Configuration Register). When A18 = 1 in the Configuration Register, RDY is active one clock cycle before data. Figure 42. Enter Embedded Erasing WE# Synchronous Data Polling Timings/Toggle Bit Timings Erase Suspend Erase Enter Erase Suspend Program Erase Suspend Read Erase Suspend Program Erase Resume Erase Suspend Read Erase Erase Complete DQ6 DQ2 Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE# to toggle DQ2 and DQ6. Figure 43. DQ2 vs. DQ6 May 10, 2006 27024B3 Am29BDS128H/Am29BDS640H 77 D A T A S H E E T AC CHARACTERISTICS Temporary Sector Unprotect Parameter JEDEC Std Description All Speed Options Unit tVIDR VID Rise and Fall Time (See Note) Min 500 ns tVHH VHH Rise and Fall Time (See Note) Min 250 ns tRSP RESET# Setup Time for Temporary Sector Unprotect Min 4 µs tRRB RESET# Hold Time from RDY High for Temporary Sector Unprotect Min 4 µs Note: Not 100% tested. VID VID RESET# VIL or VIH VIL or VIH tVIDR tVIDR Program or Erase Command Sequence CE# WE# tRSP tRRB RDY Figure 44. Temporary Sector Unprotect Timing Diagram 78 Am29BDS128H/Am29BDS640H 27024B3 May 10, 2006 D A T A S H E E T AC CHARACTERISTICS VID VIH RESET# SA, A6, A1, A0 Valid* Valid* Sector Protect/Unprotect Data 60h 1 µs Valid* Verify 60h 40h Status Sector Protect: 150 µs Sector Unprotect: 15 ms CE# WE# OE# * For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0. Figure 45. Sector/Sector Block Protect and Unprotect Timing Diagram May 10, 2006 27024B3 Am29BDS128H/Am29BDS640H 79 D A T A S H E E T AC CHARACTERISTICS) Address boundary occurs every 64 words, beginning at address 00003Fh: 00007Fh, 0000BFh, etc.) Address 000000h is also a boundary crossing. C60 C61 C62 3C 3D 3E C63 C63 C63 C64 C65 C66 C67 3F 3F 3F 40 41 42 43 CLK Address (hex) AVD# (stays high) tRACC tRACC RDY(1) latency tRACC tRACC RDY(2) Data latency D60 D61 D62 D63 D64 D65 D66 D67 Notes: 1. RDY active with data (A18 = 0 in the Configuration Register). 2. RDY active one clock cycle before data (A18 = 1 in the Configuration Register). 3. Cxx indicates the clock that triggers Dxx on the outputs; for example, C60 triggers D60. Figure shows the device not crossing a bank in the process of performing an erase or program. 4. If the starting address latched in is either 3Eh or 3Fh (or some 64 multiple of either), there is no additional 2 cycle latency at the boundary crossing. Figure 46. 80 Latency with Boundary Crossing Am29BDS128H/Am29BDS640H 27024B3 May 10, 2006 D A T A S H E E T AC CHARACTERISTICS Address boundary occurs every 64 words, beginning at address 00003Fh: (00007Fh, 0000BFh, etc.) Address 000000h is also a boundary crossing. C60 C61 C62 3C 3D 3E C63 C63 C63 C64 3F 3F 3F 40 CLK Address (hex) AVD# (stays high) tRACC RDY(1) latency tRACC tRACC RDY(2) latency Data OE#, CE# tRACC D60 D61 D62 D63 Invalid Read Status (stays low) Notes: 1. RDY active with data (A18 = 0 in the Configuration Register). 2. RDY active one clock cycle before data (A18 = 1 in the Configuration Register). 3. Cxx indicates the clock that triggers Dxx on the outputs; for example, C60 triggers D60. Figure shows the device crossing a bank in the process of performing an erase or program. Figure 47. Latency with Boundary Crossing into Program/Erase Bank May 10, 2006 27024B3 Am29BDS128H/Am29BDS640H 81 D A T A S H E E T AC CHARACTERISTICS Data D0 D1 Rising edge of next clock cycle following last wait state triggers next burst data AVD# total number of clock cycles following AVD# falling edge OE# 1 2 3 0 1 4 5 6 7 3 4 5 CLK 2 number of clock cycles programmed Wait State Decoding Addresses: A14, A13, A12 = “111” ⇒ Reserved A14, A13, A12 = “110” ⇒ Reserved A14, A13, A12 = “101” ⇒ 5 programmed, 7 total A14, A13, A12 = “100” ⇒ 4 programmed, 6 total A14, A13, A12 = “011” ⇒ 3 programmed, 5 total A14, A13, A12 = “010” ⇒ 2 programmed, 4 total A14, A13, A12 = “001” ⇒ 1 programmed, 3 total A14, A13, A12 = “000” ⇒ 0 programmed, 2 total Note: Figure assumes address D0 is not at an address boundary, active clock edge is rising, and wait state is set to “101”. Figure 48. 82 Example of Wait States Insertion Am29BDS128H/Am29BDS640H 27024B3 May 10, 2006 D A T A S H E E T AC CHARACTERISTICS Last Cycle in Program or Sector Erase Command Sequence Read status (at least two cycles) in same bank and/or array data from other bank tWC tRC Begin another write or program command sequence tRC tWC CE# OE# tOE tOEH tGHWL WE# tWPH tWP tDS tOEZ tACC tOEH tDH Data RD PD/30h AAh RD tSR/W Addresses PA/SA RA RA 555h tAS AVD# tAH Note: Breakpoints in waveforms indicate that system may alternately read array data from the “non-busy bank” while checking the status of the program or erase operation in the “busy” bank. The system should read status twice to ensure valid information. Figure 49. Back-to-Back Read/Write Cycle Timings May 10, 2006 27024B3 Am29BDS128H/Am29BDS640H 83 D A T A S H E E T ERASE AND PROGRAMMING PERFORMANCE Parameter Typ (Note 1) Max (Note 2) Unit 32 Kword 0.4 5 4 Kword 0.2 5 128 Mb 103 s 64 Mb 54 s Sector Erase Time Comments s Excludes 00h programming prior to erasure (Note 4) Chip Erase Time Word Programming Time 9 210 µs Accelerated Word Programming Time 4 120 µs Chip Programming Time (Note 3) 128 Mb 75.5 226.5 s 64 Mb 38 114 s Accelerated Chip Programming Time 128 Mb 33 99 s 64 Mb 17 30 s Excludes system level overhead (Note 5) Excludes system level overhead (Note 5) Notes: 1. Typical program and erase times assume the following conditions: 25°C, 1.8 V VCC, 1 million cycles. Additionally, programming typicals assumes a checkerboard pattern. 2. Under worst case conditions of 90°C, VCC = 1.65 V, 1,000,000 cycles. 3. The typical chip programming time is considerably less than the maximum chip programming time listed. 4. In the pre-programming step of the Embedded Erase algorithm, all words are programmed to 00h before erasure. 5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table 20, “Memory Array Command Definitions,” on page 46 for further information on command definitions. 6. The device has a minimum erase and program cycle endurance of 1 million cycles. BGA BALL CAPACITANCE Parameter Symbol Parameter Description Test Setup Typ Max Unit CIN Input Capacitance VIN = 0 4.2 5.0 pF COUT Output Capacitance VOUT = 0 5.4 6.5 pF CIN2 Control Pin Capacitance VIN = 0 3.9 4.7 pF Notes: 1. 2. Sampled, not 100% tested. Test conditions TA = 25°C, f = 1.0 MHz. DATA RETENTION Parameter Test Conditions Min Unit 150°C 10 Years 125°C 20 Years Minimum Pattern Data Retention Time 84 Am29BDS128H/Am29BDS640H 27024B3 May 10, 2006 D A T A S H E E T PHYSICAL DIMENSIONS VBB080—80-ball Fine-Pitch Ball Grid Array (BGA) 11.5 x 9 mm Package D D1 A e 0.05 C (2X) 8 e 7 7 6 SE 5 E1 E 4 3 2 1 M L K J H G F E INDEX MARK PIN A1 CORNER 6 0.05 C (2X) B A A1 CORNER SD NXφb φ 0.08 M C φ 0.15 M C A B TOP VIEW BOTTOM VIEW 0.10 C A2 A A1 C 7 B 10 D C 0.08 C SEATING PLANE SIDE VIEW NOTES: PACKAGE VBB 080 JEDEC 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994. N/A 2. ALL DIMENSIONS ARE IN MILLIMETERS. 11.50 mm x 9.00 mm NOM PACKAGE SYMBOL MIN NOM MAX A --- --- 1.00 A1 0.20 --- --- A2 0.62 --- 0.76 3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010 (EXCEPT AS NOTED). NOTE OVERALL THICKNESS BALL HEIGHT 11.50 BSC. BODY SIZE E 9.00 BSC. BODY SIZE D1 8.80 BSC. BALL FOOTPRINT E1 5.60 BSC. BALL FOOTPRINT MD 12 ROW MATRIX SIZE D DIRECTION ME 8 ROW MATRIX SIZE E DIRECTION N 80 TOTAL BALL COUNT 0.30 0.35 0.40 BALL DIAMETER e 0.80 BSC. BALL PITCH SD / SE 0.40 BSC. SOLDER BALL PLACEMENT (A3-A6, B3-B6, L3-L6, -M3-M6) DEPOPULATED SOLDER BALLS e REPRESENTS THE SOLDER BALL GRID PITCH. 5. SYMBOL "MD" IS THE BALL ROW MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL COLUMN MATRIX SIZE IN THE "E" DIRECTION. BODY THICKNESS D φb 4. N IS THE TOTAL NUMBER OF SOLDER BALLS. 6 DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. 7 SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW PARALLEL TO THE D OR E DIMENSION, RESPECTIVELY, SD OR SE = 0.000. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 8. NOT USED. 9. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. 10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS. 3233 \ 16-038.9h Note: BSC is an ANSI standard for Basic Space Centering May 10, 2006 27024B3 Am29BDS128H/Am29BDS640H 85 D A T A S H E E T PHYSICAL DIMENSIONS VBD064—64-ball Fine-Pitch Ball Grid Array (BGA) 9 x 8 mm Package D D1 A 0.05 C (2X) 8 7 6 5 e E 7 SE 4 E1 3 2 1 H G F E D C B A INDEX MARK PIN A1 CORNER B 10 6 0.05 C (2X) TOP VIEW A1 CORNER SD NXφb φ 0.08 M C φ 0.15 M C A B BOTTOM VIEW 0.10 C A2 A A1 SEATING PLANE 0.08 C C SIDE VIEW NOTES: PACKAGE VBD 064 JEDEC 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994. N/A 2. ALL DIMENSIONS ARE IN MILLIMETERS. 8.95 mm x 7.95 mm NOM PACKAGE 3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010 (EXCEPT AS NOTED). SYMBOL MIN NOM MAX A --- --- 1.00 OVERALL THICKNESS NOTE A1 0.20 --- 0.30 BALL HEIGHT A2 0.62 --- 0.76 BODY THICKNESS D 8.95 BSC. BODY SIZE E 7.95 BSC. BODY SIZE D1 5.60 BSC. BALL FOOTPRINT E1 5.60 BSC. BALL FOOTPRINT MD 8 ROW MATRIX SIZE D DIRECTION ME 8 ROW MATRIX SIZE E DIRECTION N 64 φb 0.30 0.35 TOTAL BALL COUNT 0.40 BALL DIAMETER e 0.80 BSC. BALL PITCH SD / SE 0.40 BSC. SOLDER BALL PLACEMENT NONE DEPOPULATED SOLDER BALLS 4. e REPRESENTS THE SOLDER BALL GRID PITCH. 5. SYMBOL "MD" IS THE BALL ROW MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL COLUMN MATRIX SIZE IN THE "E" DIRECTION. N IS THE TOTAL NUMBER OF SOLDER BALLS. 6 DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. 7 SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW PARALLEL TO THE D OR E DIMENSION, RESPECTIVELY, SD OR SE = 0.000. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 8. NOT USED. 9. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. 10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS. 3246 \ 16-038.9 Note: BSC is an ANSI standard for Basic Space Centering 86 Am29BDS128H/Am29BDS640H 27024B3 May 10, 2006 D A T A S H E E T REVISION SUMMARY Revision A (November 5, 2002) command. Updated PPB Program, Erase, Status commands to require Sector Block Address (SBA). DC Characteristics Initial release. Updated IIO1, ICC1, ICC3, ICC4, ICC6 Revision B (February 2, 2004) Test Conditions Global Incorporated Am29BDS640H specifications from publication 27241. Updated Input Rise and Fall Times. VCC Power Up Removed 1.5 V VIO option. Changed 80 MHz speed grade to 75 MHz. Added Ramp Rate information. In-System Sector Protection/Sector Unprotection Algorithms Added section. Changed “Wait 15 ms” to “Wait 1.5 ms.” CLK Characterization Revision B+1 (August 10, 2004) Global Password Protection Mode Locking Bit; Persistent Sector Protection Mode Locking Bit Program Command; SecSi Sector Protection Bit Program Command; PPB Program Command; All PPB Erase Command Updated description for these sections. Incorporated Am29BDS640H specifications from publication 27241. Updated speed options offered. Revision B2 (September 30, 2005) Ordering Information Command Definitions Changed WP to (01000010). Set Configuration Register command is not available in Unlock Bypass Mode Removed Password Protection Locking Bit Read command and Persistent Protection Locking Bit Read Added package type VF (Pb-free Package (VBB080)) Revision B3 (May 10, 2006) Added migration and obsolescence information for Am29BDS640H. Removed Preliminary designation from document. Colophon The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior authorization by the respective government entity will be required for export of those products. Trademarks Copyright © 2002–2006 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies. May 10, 2006 27024B3 Am29BDS128H/Am29BDS640H 87