ANSALDO Via N. Lorenzi 8 - I 16152 GENOVA - ITALY Tel. int. +39/(0)10 6556549 - (0)10 6556488 Fax Int. +39/(0)10 6442510 Tx 270318 ANSUSE I - Ansaldo Trasporti s.p.a. Unita' Semiconduttori PHASE CONTROL THYRISTOR AT875LT Repetitive voltage up to Mean on-state current Surge current 4400 V 2200 A 25.2 kA FINAL SPECIFICATION apr 97 - ISSUE : 01 Symbol Characteristic Tj [°C] Conditions Value Unit BLOCKING V RRM Repetitive peak reverse voltage 120 4400 V V V RSM Non-repetitive peak reverse voltage 120 4500 V DRM Repetitive peak off-state voltage 120 4400 V I RRM Repetitive peak reverse current V=VRRM 120 200 mA I DRM Repetitive peak off-state current V=VDRM 120 200 mA I T (AV) Mean on-state current 180° sin, 50 Hz, Th=55°C, double side cooled 2200 A I T (AV) Mean on-state current 180° sin, 50 Hz, Tc=85°C, double side cooled I TSM Surge on-state current sine wave, 10 ms I² t I² t without reverse voltage V On-state voltage On-state current = CONDUCTING V r T 120 2000 A 25 1720 A 25.2 kA 3175 x1E3 A²s 2 V T(TO) Threshold voltage 120 1.3 T On-state slope resistance 120 0.334 mohm V SWITCHING di/dt Critical rate of rise of on-state current, min. From 75% VDRM up to 1600 A, gate 10V 5ohm 120 200 A/µs dv/dt Critical rate of rise of off-state voltage, min. Linear ramp up to 70% of VDRM 120 1000 V/µs td Gate controlled delay time, typical VD=100V, gate source 40V, 10 ohm , tr=.5 µs 25 3 tq Circuit commutated turn-off time, typical dV/dt = 20 V/µs linear up to 75% VDRM Q rr Reverse recovery charge di/dt=-20 A/µs, I= 1050 A I rr Peak reverse recovery current VR= 50 V I H Holding current, typical VD=5V, gate open circuit 25 300 mA I L Latching current, typical VD=12V, tp=30µs 25 1000 mA 400 120 µs µs µC A GATE V GT Gate trigger voltage VD=12V 25 3.5 V I GT Gate trigger current VD=12V 25 400 mA VD=2000 V 120 V GD Non-trigger gate voltage, min. 0.8 V V FGM Peak gate voltage (forward) 30 V I FGM Peak gate current 10 A V RGM Peak gate voltage (reverse) 10 V P GM Peak gate power dissipation 150 W P G Average gate power dissipation 2 W R th(j-h) Thermal impedance, DC Junction to heatsink, double side cooled R th(c-h) Thermal impedance Case to heatsink, double side cooled T F j Operating junction temperature Mounting force Mass Pulse width 100 µs MOUNTING ORDERING INFORMATION : AT875LT S 44 standard specification VDRM&VRRM/100 9.5 °C/kW 2 °C/kW -30 / 120 40.0 / 50.0 1150 °C kN g ANSALDO AT875LT PHASE CONTROL THYRISTOR FINAL SPECIFICATION apr 97 - ISSUE : 01 DISSIPATION CHARACTERISTICS SQUARE WAVE Th [°C] 120 110 100 90 30° 80 60° 90° 70 120° 180° 60 DC 50 0 500 1000 1500 2000 2500 3000 IF(AV) [A] PF(AV) [W] 7000 DC 180° 6000 120° 90° 5000 60° 4000 30° 3000 2000 1000 0 0 500 1000 1500 IF(AV) [A] 2000 2500 3000 ANSALDO AT875LT PHASE CONTROL THYRISTOR FINAL SPECIFICATION apr 97 - ISSUE : 01 DISSIPATION CHARACTERISTICS SINE WAVE Th [°C] 120 110 100 90 30° 80 60° 90° 70 120° 60 180° 50 0 500 1000 1500 2000 2500 3000 2500 3000 IF(AV) [A] PF(AV) [W] 7000 180° 6000 90° 120° 5000 60° 30° 4000 3000 2000 1000 0 0 500 1000 1500 IF(AV) [A] 2000 ANSALDO AT875LT PHASE CONTROL THYRISTOR FINAL SPECIFICATION apr 97 - ISSUE : 01 ON-STATE CHARACTERISTIC Tj = 120 °C SURGE CHARACTERISTIC Tj = 120 °C 7000 30 25 5000 20 4000 ITSM [kA] On-state Current [A] 6000 3000 15 10 2000 5 1000 0 0 0.6 1.1 1.6 2.1 2.6 3.1 3.6 1 On-state Voltage [V] 10 n° cycles TRANSIENT THERMAL IMPEDANCE DOUBLE SIDE COOLED 10.0 9.0 8.0 Zth j-h [°C/kW] 7.0 6.0 5.0 4.0 3.0 2.0 1.0 0.0 0.001 0.01 0.1 1 t[s] 10 100 Cathode terminal type DIN 46244 - A 4.8 - 0.8 Gate terminal type AMP 60598 - 1 Distributed by All the characteristics given in this data sheet are guaranteed only with uniform clamping force, cleaned and lubricated heatsink, surfaces with flatness < .03 mm and roughness < 2 µm. In the interest of product improvement ANSALDO reserves the right to change any data given in this data sheet at any time without previous notice. If not stated otherwise the maximum value of ratings (simbols over shaded background) and characteristics is reported. 100