a Quad 3000 V/s, 35 mW Current Feedback Amplifier AD8004 FEATURES High Speed 250 MHz –3 dB Bandwidth (G = +1) 3000 V/s Slew Rate 21 ns Settling Time to 0.1% 1.8 ns Rise Time for 2 V Step Low Power 3.5 mA/Amp Power Supply Current (35 mW/Amp) Single Supply Operation Fully Specified for +5 V Supply Good Video Specifications (RL = 150 ⍀, G = +2) Gain Flatness 0.1 dB to 30 MHz 0.04% Differential Gain Error 0.10ⴗ Differential Phase Error Low Distortion –78 dBc THD at 5 MHz –61 dBc THD at 20 MHz High Output Current of 50 mA Available in a 14-Lead Plastic DIP and SOIC CONNECTION DIAGRAM Plastic DIP (N) and SOIC (R) Packages OUTPUT 1 –IN 2 PRODUCT DESCRIPTION The AD8004 is a quad, low power, high speed amplifier designed to operate on single or dual supplies. It utilizes a current feedback architecture and features high slew rate of 3000 V/µs making the AD8004 ideal for handling large amplitude pulses. Additionally, the AD8004 provides gain flatness of 0.1 dB to +IN 3 +VS 4 –IN 6 11 –VS 10 +IN 2 3 9 –IN 8 OUTPUT 30 MHz while offering differential gain and phase error of 0.04% and 0.10°. This makes the AD8004 suitable for video electronics such as cameras and video switchers. The outstanding bandwidth of 250 MHz along with 3000 V/µs of slew rate make the AD8004 useful in many general purpose, high speed applications where dual power supplies of up to ± 6 V and single supplies from 4 V to 12 V are needed. The AD8004 is available in the industrial temperature range of –40°C to +85°C. –2 +5VS –3 –4 +5VS –5 65VS –0.2 –6 –0.3 –7 –0.4 –8 10 40 FREQUENCY – MHz 100 –9 500 Figure 1. Frequency Response and Flatness, G = +2 DIFF GAIN – % –1 65VS 0 1 (TOP VIEW) OUTPUT 7 0.04 0.03 0.02 0.01 0.00 –0.01 –0.02 –0.03 –0.04 DIFF PHASE – Degrees G = +2 VIN = 50mV rms RL = 100V RF = 1.10kV R PACKAGE NORMALIZED FREQUENCY RESPONSE – dB NORMALIZED FLATNESS – dB 0 –0.5 13 –IN 12 +IN AD8004 +IN 5 +1 –0.1 4 The AD8004 offers low power of 3.5 mA/amplifier and can run on a single +4 V to +12 V power supply, while being capable of delivering up to 50 mA of load current. All this is offered in a small 14-lead plastic DIP or 14-lead SOIC package. These features make this amplifier ideal for portable and battery powered applications where size and power are critical. APPLICATIONS Image Scanners Active Filters Video Switchers Special Effects +0.1 14 OUTPUT 1 0.12 0.10 0.08 0.06 0.04 0.02 0.00 –0.02 –0.04 80 IRE RL = 150V VS = 65V RF = 1.21kV 1ST 2ND 3RD 4TH 5TH 6TH 7TH 8TH 9TH 10TH 11TH 80 IRE RL = 150V VS = 65V RF = 1.21kV 1ST 2ND 3RD 4TH 5TH 6TH 7TH 8TH 9TH 10TH 11TH Figure 2. Differential Gain/Differential Phase REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1999 AD8004–SPECIFICATIONS (@ T = + 25ⴗC, V = ⴞ5 V, R = 100 ⍀, unless otherwise noted) A Parameter DYNAMIC PERFORMANCE –3 dB Bandwidth, N Package Bandwidth for 0.1 dB Flatness Slew Rate Settling Time to 0.1% Rise & Fall Time (10% to 90%) NOISE/HARMONIC PERFORMANCE Total Harmonic Distortion Crosstalk, R Package, Worst Case Crosstalk, N Package, Worst Case Input Voltage Noise Input Current Noise Differential Gain Error Differential Phase Error Differential Gain Error Differential Phase Error S L Conditions Min G = +2, RF = 698 Ω G = +1, RF = 806 Ω G = +2 G = +2, VO = 4 V Step G = –2, VO = 4 V Step G = +2, VO = 2 V Step G = +2, VO = 2 V Step fC = 5 MHz, VO = 2 V p-p, RL = 1 kΩ f = 5 MHz, G = +2, RL = 1 kΩ f = 5 MHz, G = +2, RL = 1 kΩ f = 10 kHz f = 10 kHz, +In –In NTSC, G = +2, R L = 150 Ω, RF = 1.21 kΩ NTSC, G = +2, R L = 150 Ω, RF = 1.21 kΩ NTSC, G = +2, RL = 1 kΩ, R F = 1.21 kΩ NTSC, G = +2, RL = 1 kΩ, R F = 1.21 kΩ DC PERFORMANCE Input Offset Voltage AD8004A Typ Max 185 MHz 250 MHz 30 3000 2000 21 1.8 MHz V/µs V/µs ns ns –78 –69 –64 1.5 38 38 0.04 0.10 0.01 0.04 dBc dB dB nV/√Hz pA/√Hz pA/√Hz % Degree % Degree 1.0 1.5 15 35 TMIN–TMAX Offset Drift –Input Bias Current 290 220 mV mV µV/°C ±µA ±µA ±µA ±µA kΩ kΩ 2 50 1.5 3.2 MΩ Ω pF ±V 58 1 12 dB µA/V µA/V 3.9 50 180 ±V mA mA TMIN–TMAX +Input Bias Current Open-Loop Transresistance INPUT CHARACTERISTICS Input Resistance Input Capacitance Input Common-Mode Voltage Range Common-Mode Rejection Ratio Offset Voltage –Input Current +Input Current OUTPUT CHARACTERISTICS Output Voltage Swing Output Current Short Circuit Current 40 TMIN–TMAX VO = ± 2.5 V TMIN–TMAX 170 +Input –Input +Input VCM = ± 2.5 V VCM = ± 2.5 V, TMIN–TMAX VCM = ± 2.5 V, TMIN–TMAX R L = 150 Ω 100 POWER SUPPLY Operating Range Total Quiescent Current Power Supply Rejection Ratio –Input Current +Input Current 52 ± 2.0 TMIN–TMAX ∆VS = ± 2 V TMIN–TMAX TMIN–TMAX 56 Units 14 16 62 0.5 4 3.5 5 90 110 110 120 ± 6.0 17 20 V mA mA dB µA/V µA/V Specifications subject to change without notice. –2– REV. B AD8004 (@ TA = + 25ⴗC, VS = +5 V, RL = 100 ⍀, unless otherwise noted) Parameter DYNAMIC PERFORMANCE –3 dB Bandwidth, N Package Bandwidth for 0.1 dB Flatness Slew Rate Settling Time to 0.1% Rise & Fall Time (10% to 90%) NOISE/HARMONIC PERFORMANCE Total Harmonic Distortion Crosstalk, R Package, Worst Case Crosstalk, N Package, Worst Case Input Voltage Noise Input Current Noise Differential Gain Error Differential Phase Error Differential Gain Error Differential Phase Error Conditions Min G = +2, RF = 698 Ω G = +1, RF = 806 Ω G = +2 G = +2, VO = 2 V Step G = +2, VO = 2 V Step G = +2, VO = 2 V Step fC = 5 MHz, VO = 2 V p-p, RL = 1 kΩ f = 5 MHz, G = +2, RL = 1 kΩ f = 5 MHz, G = +2, RL = 1 kΩ f = 10 kHz f = 10 kHz, +In –In NTSC, G = +2, R L = 150 Ω, RF = 1.21 kΩ NTSC, G = +2, R L = 150 Ω, RF = 1.21 kΩ NTSC, G = +2, RL = 1 kΩ, R F = 1.21 kΩ NTSC, G = +2, RL = 1 kΩ, R F = 1.21 kΩ DC PERFORMANCE Input Offset Voltage AD8004A Typ Max 150 MHz 200 MHz 30 1100 24 2.3 MHz V/µs ns ns –65 –69 –64 1.5 38 38 0.06 0.25 0.01 0.08 dBc dB dB nV/√Hz pA/√Hz pA/√Hz % Degree % Degree 1.0 1 15 20 TMIN–TMAX Offset Drift –Input Bias Current 230 170 mV mV µV/°C ±µA ±µA ±µA ±µA kΩ kΩ 2 50 1.5 3.2 MΩ Ω pF V 57 2 15 dB µA/V µA/V 0.9 to 4.1 50 95 V mA mA TMIN–TMAX +Input Bias Current Open Loop Transresistance INPUT CHARACTERISTICS Input Resistance Input Capacitance Input Common-Mode Voltage Range Common-Mode Rejection Ratio Offset Voltage –Input Current +Input Current OUTPUT CHARACTERISTICS Output Voltage Swing Output Current Short Circuit Current 35 TMIN–TMAX VO = +1.5 V to +3.5 V TMIN–TMAX +Input –Input +Input VCM = +1 V to +3 V VCM = +1 V to +3 V, TMIN –TMAX VCM = +1 V to +3 V, TMIN –TMAX 0, +4 TMIN–TMAX ∆VS = +1 V, VCM = +2.5 V TMIN –TMAX TMIN –TMAX Specifications subject to change without notice. REV. B 52 R L = 150 Ω POWER SUPPLY Operating Range Total Quiescent Current Power Supply Rejection Ratio –Input Current +Input Current 140 –3– 56 Units 13 14.5 62 1 6 2.5 3 80 100 100 115 +12 14 15.5 V mA mA dB µA/V µA/V AD8004 ABSOLUTE MAXIMUM RATINGS 1 MAXIMUM POWER DISSIPATION Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.6 V Internal Power Dissipation2 Plastic DIP Package (N) . . . . . . . . . Observe Derating Curves Small Outline Package (R) . . . . . . . . Observe Derating Curves Input Voltage (Common Mode) . . . . . . . . . . . . . . . . . . . . ± VS Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . ± 2.5 V Output Short Circuit Duration . . . . . . . . . . . . . . . . . . . . . . Observe Power Derating Curves Storage Temperature Range (N, R) . . . . . . . –65°C to +125°C Operating Temperature Range (A Grade) . . . – 40°C to +85°C Lead Temperature Range (Soldering 10 sec) . . . . . . . . +300°C The maximum power that can be safely dissipated by the AD8004 is limited by the associated rise in junction temperature. The maximum safe junction temperature for plastic encapsulated devices is determined by the glass transition temperature of the plastic, approximately +150°C. Exceeding this limit temporarily may cause a shift in parametric performance due to a change in the stresses exerted on the die by the package. Exceeding a junction temperature of +175°C for an extended period can result in device failure. NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Specification is for device in free air: 14-Lead Plastic DIP Package: θJA = 90°C/W 14-Lead SOIC Package: θJA = 140°C/W MAXIMUM POWER DISSIPATION – Watts 2.0 ORDERING GUIDE Model Temperature Range Package Description Package Option AD8004AN AD8004AR-14 AD8004AR-14-REEL AD8004AR-14-REEL7 – 40°C to +85°C – 40°C to +85°C – 40°C to +85°C – 40°C to +85°C 14-Lead Plastic DIP 14-Lead SOIC 13" Tape and Reel 7" Tape and Reel N-14 R-14 R-14 R-14 While the AD8004 is internally short circuit protected, this may not be sufficient to guarantee that the maximum junction temperature is not exceeded under all conditions. To ensure proper operation, it is necessary to observe the maximum power derating curves (shown below in Figure 3). TJ = +1508C 14-LEAD PLASTIC DIP PACKAGE 1.5 1.0 14-LEAD SOIC PACKAGE 0.5 0 –50 –40 –30 –20 –10 0 10 20 30 40 50 60 70 AMBIENT TEMPERATURE – 8C 80 90 Figure 3. Maximum Power Dissipation vs. Temperature CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD8004 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. –4– WARNING! ESD SENSITIVE DEVICE REV. B AD8004 604V 604V SCOPE INPUT 50V 249V 499V SCOPE INPUT 50V VIN 50V VIN 50V 61.9V +VS +VS 50V 0.1mF 10mF 0.1mF 10mF 0.1mF 10mF 0.1mF 10mF –VS –VS Figure 4. Test Circuit; Gain = +2 Figure 8. Test Circuit; Gain = –2 Figure 5.* 100 mV Step Response; G = +2, VS = ±2.5 V or ±5 V Figure 9.* 100 mV Step Response; G = –2, VS = ±2.5 V or ±5 V Figure 6.* Step Response; G = +2, VS = ± 5 V Figure 10.* Step Response; G = –2, VS = ± 5 V +1 G = +1, RF = 698V +1 NORMALIZED FREQUENCY RESPONSE – dB NORMALIZED FREQUENCY RESPONSE – dB +2 0 RL = 100V VIN = 50mV (G = +1, +2) VIN = 5mV (G = +10) –1 –2 G = +2, RF = 604V –3 –4 –5 G = +10, RF = 499V –6 –7 –8 1 10 40 FREQUENCY – MHz 100 VS = 65V RF = 499V VIN = 50mV rms RL = 100V N PACKAGE –1 –2 –3 G = –2 G = –10 –4 –5 –6 –7 –8 –9 500 1 Figure 7. Frequency Response; G = +1, +2, +10, VS = ± 5 V 10 40 FREQUENCY – MHz 100 500 Figure 11. Frequency Response, G = –1, –2, –10 *NOTE: VS = ± 2.5 V operation is identical to V S = +5 V single supply operation. REV. B G = –1 0 –5– AD8004 +9 +3 +6 0 1V rms –3 +3 OUTPUT LEVEL – dBV OUTPUT LEVEL – dBV 1V rms 0 –3 –6 –9 –12 G =+2 VS = 65V RF = 604V –15 –9 –12 –15 –18 –24 1 10 40 FREQUENCY – MHz –27 500 100 Figure 12. Large Signal Frequency Response; VS = ± 5.0 V, G = +2, RF = 604 Ω 1 10 40 FREQUENCY – MHz 500 –40 G = +2 VO = 2V p-p RF = 698V –50 2ND RL = 150V –60 –70 –80 2ND RL = 1kV –90 1 10 –70 –80 2ND RL = 1kV –100 1 20 10 Figure 16. Distortion vs. Frequency; VS = +5 V –10 +1 –2 –3 0 –4 –0.1 –5 +5VS 65VS –0.2 –6 –0.3 –7 –0.4 –8 –0.5 –9 500 1 10 40 FREQUENCY – MHz 100 –15 604V 50V VIN –25 VOUT 154V –20 CMRR – dB 65VS +5VS 65VS 604V NORMALIZED FREQUENCY RESPONSE – dB +0.1 –1 20 FREQUENCY – MHz Figure 13. Distortion vs. Frequency; VS = ± 5 V 0 3RD RL = 150V 3RD RL = 1kV –60 FREQUENCY – MHz G = +2 VIN = 50mV rms RL = 100V RF = 1.10kV R PACKAGE 2ND RL = 150V –90 3RD RL = 1kV –100 G = +2 VO = 2V p-p RF = 698V 3RD RL = 150V DISTORTION – dBc –50 NORMALIZED FLATNESS – dB 100 Figure 15. Large Signal Frequency Response; VS = +5.0 V, G = +2, RF = 604 Ω –40 DISTORTION – dBc G = +2 VS = +5V RF = 604V –21 –18 –21 –6 57.6V 154V +5VS –30 –35 –40 –45 –50 +5VS –55 65VS –60 0.03 0.1 1 10 FREQUENCY – MHz 100 500 Figure 17. CMRR vs. Frequency; VS = ± 5 V or +5 V, VIN = 200 mV rms, Other Sides Are Equal, RTO Figure 14. Frequency Response and Flatness, G = +2 –6– REV. B 10 9 8 7 6 5 4 1000 3 300 2 200 10 9 8 7 6 5 4 100 + OR – INPUT CURRENT NOISE 70 50 40 3 30 2 20 VOLTAGE NOISE 1 10 100 1k 10k FREQUENCY – Hz 100k –10 –20 G = +2 65VS OR 62.5VS RF = 1kV 100mV rms ON TOP OF dc BIAS +PSRR –30 PSRR – dB 500 0 INPUT CURRENT NOISE – pA/ Hz INPUT VOLTAGE NOISE – nV/ Hz AD8004 –40 –PSRR –50 –60 –70 10 1M –80 10k 100k Figure 18. Noise vs. Frequency, VS = +5 V or ± 5 VS 1M 10M FREQUENCY – Hz 100M 500M Figure 21. PSRR vs. Frequency –20 –30 10 G = +2 RF = 698V POWER = 0dBm (224mV rms) +5VS 1 –40 RbT = 50V 65VS OR +5VS CROSSTALK – dB IMPEDANCE – V 100 RbT = 0 –50 –60 G = +2 RF = 1.10kV 65VS VIN = 200mV rms INPUT TO SIDE 1 RL1 = 1kV R PACKAGE OUTPUT = SIDE 2 OUTPUT = SIDE 4 –70 –80 OUTPUT = SIDE 3 –90 65VS 0.1 –100 –110 0.01 0.03 0.1 1 10 FREQUENCY – MHz 100 –120 0.03 500 Figure 19. Output Impedance vs. Frequency 0.1 1 10 FREQUENCY – MHz 100 500 Figure 22. Crosstalk (Output to Output) vs. Frequency 110 0 GAIN +60 100 +50 90 +40 80 +20 +10 –240 VIN = –40dBm VS = 65V –50 PHASE 60 50 0 –10 30 –100 –150 20 0.1 1 10 FREQUENCY – MHz 100 10 100k 500 1M 10M FREQUENCY – Hz 100M –200 1G Figure 23. Open-Loop Transimpedance Gain Figure 20. Open-Loop Voltage Gain and Phase REV. B 70 40 –360 0.03 0 –7– PHASE – Degree +30 PHASE –180 GAIN – dBV 90 GAIN – dB PHASE – Degrees GAIN AD8004 9 G = +2 RF = 1.21kV 8 65VS 7 SWING – V p-p 6 5 4 3 +5VS 2 1 0 10 100 1000 LOAD RESISTANCE – V 10000 Figure 27. Output Voltage Swing vs. Load Figure 24. Short-Term Settling Time 10 9 G = +2 RF = 1.21kV f = 100kHz PEAK-TO-PEAK OUTPUT AT CLIPPING POINT – V 8 RL = 1kV 7 6 RL = 100V 5 4 3 2 1 0 5 6 7 8 9 10 TOTAL SUPPLY VOLTAGE – V 11 12 DIFF GAIN – % 0.03 0.04 0.03 0.02 0.01 0.00 –0.01 –0.02 –0.03 –0.04 80 IRE RL = 150V VS = 65V RF = 1.21kV 80 IRE RL = 1kV VS = 65V RF = 1.21kV 0.02 0.01 0.00 –0.01 –0.02 –0.03 1ST 2ND 3RD 4TH 5TH 6TH 7TH 0.12 0.10 0.08 0.06 0.04 0.02 0.00 –0.02 –0.04 8TH 1ST 9TH 10TH 11TH DIFF PHASE – Degrees DIFF GAIN – % 4 Figure 28. Output Swing vs. Supply Figure 25. Long-Term Settling Time DIFF PHASE – Degrees 3 80 IRE RL = 150V VS = 65V RF = 1.21kV 1ST 2ND 3RD 4TH 5TH 6TH 7TH 8TH 5TH 6TH 7TH 8TH 9TH 10TH 11TH 8TH 9TH 10TH 11TH 80 IRE RL = 1kV VS = 65V RF = 1.21kV 1ST 9TH 10TH 11TH 2ND 3RD 4TH 0.04 0.03 0.02 0.01 0.00 –0.01 –0.02 –0.03 –0.04 2ND 3RD 4TH 5TH 6TH 7TH Figure 29. Differential Gain/Phase, RL = 1 kΩ Figure 26. Differential Gain/Differential Phase –8– REV. B AD8004 THEORY OF OPERATION The more exact relationships that take into account open-loop gain errors are: The AD8004 is a member of a new family of high speed currentfeedback (CF) amplifiers offering new levels of bandwidth, distortion, and signal-swing capability vs. power. Its wide dynamic range capabilities are due to both a complementary high speed bipolar process and a new design architecture. The AD8004 is basically a two stage (Figure 30) rather than the conventional one stage design. Both stages feature the current-on-demand property associated with current feedback amplifiers. This gives an unprecedented ratio of quiescent current to dynamic performance. The important properties of slew rate, and full power bandwidth benefit from this performance. In addition the second gain stage buffers the effects of load impedance significantly reducing distortion. AV = DC AND AC CHARACTERISTICS As with traditional op amp circuits the dc closed-loop gain is defined as: noninverting operation R AV = G = − R F inverting operation N for inverting (G is negative) G 1+ R G + F AO (s) T O (s) for noninverting (G is positive) In these equations the open-loop voltage gain (AO(s)) is common to both voltage and current-feedback amplifiers and is the ratio of output voltage to differential input voltage. The openloop transimpedance gain (TO(s)) is the ratio of output voltage to inverting input current and is applicable to current-feedback amplifiers. The open-loop voltage gain and open-loop transimpedance gain (TO(s)) of the AD8004 are plotted vs. frequency in Figures 20 and 23. These plots and the basic relationships can be used to predict the first order performance of the AD8004 over frequency. At low closed-loop gains the term (RF /TO(s)) dominates the frequency response characteristics. This gives the result that bandwidth is constant with gain, a familiar property of current feedback amplifiers. A full discussion of this new amplifier architecture is available on the data sheet for the AD8011. This discussion only covers the basic principles of operation. R AV = G = 1 + R F N G R 1− G 1+ + F AO (s) T O (s) AV = An RF of 1 kΩ has been chosen as the nominal value to give optimum frequency response with acceptable peaking at gains of +2/–1. As can be seen from the above relationships, at higher closed-loop gains reducing RF has the effect of increasing closedloop bandwidth. Table I gives optimum values for RF and RG for a variety of gains. A1 CD IPP IPN IQ1 A2 C P1 Q3 CP2 Q1 ICQ + IO VN VP V O´ ZI A3 Q2 RF IE RG Q4 IQ1 A2 INP IPN A1 C P1 CD AD8004 Figure 30. Simplified Block Diagram REV. B VO RL Z2 –9– CL AD8004 region of the summing junction will cause some bandwidth extension and/or increased peaking. In noninverting gains, the effect of extra capacitance on summing junctions is far more pronounced than versus inverting gains. Figure 34 shows an example of this. Note that only 1 pF of added junction capacitance causes about a 70% bandwidth extension and additional peaking on a gain = +2. For an inverting gain = –2, 5 pF of additional summing junction capacitance caused a small 10% bandwidth extension. DRIVING CAPACITIVE LOADS The AD8004 was designed primarily to drive nonreactive loads. If driving loads with a capacitive component is desired, best settling response is obtained by the addition of a small series resistance as shown in Figure 31. The accompanying graph shows the optimum value for RSERIES vs. capacitive load. It is worth noting that the frequency response of the circuit when driving large capacitive loads will be dominated by the passive roll-off of RSERIES and CL. Extra output capacitive loading also causes bandwidth extensions and peaking. The effect is more pronounced with less resistive loading from the next stage. Figure 35 shows the effect of direct output capacitive loads for gains of +2 and –2. For both gains CLOAD was set to 10 pF or 0 pF (no extra capacitive loading). For each of the four traces in Figure 35 the resistive loads were 100 Ω. Figure 36 also shows capacitive loading effects only with a lighter output resistive load. Note that even though bandwidth is extended 2×, the flatness dramatically suffers. 1kV RSERIES AD8004 1kV RL 1kV CL Figure 31. Driving Capacitive Load 40 +2 RF = 698V +1 30 0 NORMALIZED GAIN – dB, G = +2 RSERIES – V RF = 909V 20 0 5 10 15 20 25 CL – pF Figure 32. Recommended RSERIES vs. Capacitive Load for ≤ 30 ns Settling to 0.1% +1 –1 –2 RF = 604V G = +2 –3 0 –4 –1 VIN = 50mV rms VS = 65V RL = 100V R PACKAGE –2 –3 –5 –6 RF = 845V –4 –5 RF = 1.10kV 1 10 40 FREQUENCY – MHz –7 –8 500 100 Figure 33. RFEEDBACK vs. Frequency Response, G = +1/+2 OPTIMIZING FLATNESS Printed circuit board parasitics and device lead frame parasitics also control fine scale gain flatness. The AD8004R package because of its small lead frame offers superior parasitics relative to the N package. In the printed circuit board environment, parasitics such as extra capacitance caused by two parallel and vertical flat conductors on opposite PC board sides in the +2 G = +2 CJ = 1pF CJ = 0 +2 0 –2 G = –2 NORMALIZED GAIN – dB, G = –2 The fine scale gain flatness and –3 dB bandwidth is affected by RFEEDBACK selection as is normal of current feedback amplifiers. With exception of gain = +1, the AD8004 can be adjusted for either maximal flatness with modest closed-loop bandwidth or for mildly peaked-up frequency response with much more bandwidth. Figure 33 shows the effect of three evenly spaced R F changes upon gain = +1 and gain = +2. Table I shows the recommended component values for achieving maximally flat frequency response as well as a faster slightly peaked-up frequency response. 0 –4 –6 –2 VIN = 50mV rms RL = 100V 65VS –4 –6 –8 CJ = 5.1pF –10 –12 –8 NORMALIZED GAIN – dB, G = +2 10 RF = 1.1kV GAIN – dB, G = +1 G = +1 CJ = 0 –14 –10 –12 –14 1 10 40 FREQUENCY – MHz 100 500 Figure 34. Frequency Response vs. Added Summing Junction Capacitance –10– REV. B AD8004 +2 CL = 10pF NORMALIZED GAIN – dB, G = –2 +2 CL = 0 G = –2, RF = 698V 0 0 –2 –4 –6 –2 CL = 10pF –4 VIN = 50mV 65VS RL = 100V –6 –8 –8 –10 CL = 0 –12 through R2. This current flows toward the summing junction and requires that the output be 2 V higher than the summing junction or at 3.6 V. NORMALIZED GAIN – dB, G = +2 G = +2, RF = 1.10kV When the input is at 1 V, there is 1.2 mA flowing into the summing junction through R3 and 1.2 mA flowing out through R1. These currents balance and leave no current to flow through R2. Thus the output is at the same potential as the inverting input or 1.6 V. The input of the AD876 has a series MOSFET switch that turns on and off at the sampling rate. This MOSFET is connected to a hold capacitor internal to the device. The on impedance of the MOSFET is about 50 Ω, while the hold capacitor is about 5 pF. –14 –10 –12 –14 1 10 40 FREQUENCY – MHz 100 In a worst case condition, the input voltage to the AD876 will change by a full-scale value (2 V) in one sampling cycle. When the input MOSFET turns on, the output of the op amp will be connected to the charged hold capacitor through the series resistance of the MOSFET. Without any other series resistance, the instantaneous current that flows would be 40 mA. This would cause settling problems for the op amp. 500 Figure 35. Frequency Response vs. Capacitive Loading, RL = 100 Ω Output +2 CL = 10pF NORMALIZED GAIN – dB, G = 2 0 G = +2 RL = 1kV 65VS VIN = 50mV rms RF = 1.2kV –2 –4 The series 100 Ω resistor limits the current that flows instantaneously after the MOSFET turns on to about 13 mA. This resistor cannot be made too large or the high frequency performance will be affected. CL = 0 The sampling MOSFET of the AD876 is closed for only half of each cycle or for 25 ns. Approximately seven time constants are required for settling to 10 bits. The series 100 Ω resistor along with the 50 Ω on resistance and the hold capacitor, create a 750 ps time constant. These values leave a comfortable margin for settling. Obtaining the same results with the op amp A/D combination as compared to driving with a signal generator indicates that the op amp is settling fast enough. –6 –8 –10 –12 –14 1 10 40 FREQUENCY – MHz 100 500 Overall the AD8004 provides adequate buffering for the AD876 A/D converter without introducing distortion greater than that of the A/D converter by itself. Figure 36. Flatness with 10 pF Capacitive Load DRIVING A SINGLE-SUPPLY A/D CONVERTER New CMOS A/D converters are placing greater demands on the amplifiers that drive them. Higher resolutions, faster conversion rates and input switching irregularities require superior settling characteristics. In addition, these devices run off a single +5 V supply and consume little power, so good single-supply operation with low power consumption are very important. The AD8004 is well positioned for driving this new class of A/D converters. +5V R3 1.65kV 0.1mF 10mF 0.1mF 1V 0V Figure 37 shows a circuit that uses an AD8004 to drive an AD876, a single supply, 10-bit, 20 MSPS A/D converter that requires only 140 mW. Using the AD8004 for level shifting and driving, the A/D exhibits no degradation in performance compared to when it is driven from a signal generator. +3.6V R1 499kV VIN REFT 100V 1/4 AD8004 50V AD876 3.6V 0.1mF 1.6V 1.6V REFB +1.6V Figure 37. AD8004 Driving the AD876 The analog input of the AD876 spans 2 V centered at about 2.6 V. The resistor network and bias voltages provide the level shifting and gain required to convert the 0 V to 1 V input signal to a 3.6 V to 1.6 V range that the AD876 wants to see. LAYOUT CONSIDERATIONS Biasing the noninverting input of the AD8004 at 1.6 V dc forces the inverting input to be at 1.6 V dc for linear operation of the amplifier. When the input is at 0 V, there is 3.2 mA flowing out of the summing junction via R1 (1.6 V/499 Ω). R3 has a current of 1.2 mA flowing into the summing junction (3.6 V–1.6 V)/ 1.65 kΩ. The difference of these two currents (2 mA) must flow REV. B R2 1kV 3.6V The specified high speed performance of the AD8004 requires careful attention to board layout and component selection. Table I shows the recommended component values for the AD8004 and Figures 39–41 show the layout for the AD8004 evaluation boards (14-lead DIP and SOIC). Proper RF design techniques and low parasitic component selection are mandatory. –11– AD8004 The PCB should have a ground plane covering all unused portions of the component side of the board to provide a low impedance ground path. The ground plane should be removed from the area near the input pins to reduce stray capacitance. RF RG RbT, 50V VIN VOUT RT 1/4 Chip capacitors should be used for supply bypassing (see Figure 38). One end should be connected to the ground plane and the other within 1/8 in. of each power pin. An additional (4.7 µF–10 µF) tantalum electrolytic capacitor should be connected in parallel. C1 0.1mF C3 10mF C2 0.1mF C4 10mF +VS –VS INVERTING CONFIGURATION RF RG The feedback resistor should be located close to the inverting input pin in order to keep the stray capacitance at this node to a minimum. Capacitance greater than 1 pF at the inverting input will significantly affect high speed performance when operating at low noninverting gains. An example of extra inverting input capacitance can be seen on Figure 35 plot. RbT, 50V VOUT 1/4 VIN RT C1 0.1mF C3 10mF C2 0.1mF C4 10mF +VS –VS Stripline design techniques should be used for long signal traces (greater than about 1 in.). These should be designed with the proper system characteristic impedance and be properly terminated at each end. NONINVERTING CONFIGURATION Figure 38. Inverting and Noninverting Configurations Table I. Recommended Component Values and Typical Bandwidths Gain AD8004AN (DIP) PACKAGE TYPE RF (Ω) RG (Ω) RT (Ω) Small Signal BW @ ± 5 VS (MHz) –10 –2 Alternate –2 –1 Alternate –1 +1 Alternate +1 +2 Alternate +2 +10 499 49.9 None 698 348 57.6 499 249 61.9 649 649 53.6 499 499 54.9 1.21 k – 50 806 – 50 1.10 k 1.10 k 50 698 698 50 499 54.9 50 155 125 180 135 190 150 250 115 185 135 Peaking @ ± 5 VS < 0.3 dB None 0.3 dB None 0.3 dB 1.3 dB 1.7 dB < 0.14 dB 0.4 dB < 0.3 dB 0.1 dB Flatness @ ± 5 VS (MHz) – 25 – 30 – – – 35 – – 135 105 155 120 160 130 200 95 150 120 499 49.9 None 698 348 57.6 499 249 61.9 750 750 53.6 499 499 54.9 1.10 k – 50 698 – 50 1.10 k 1.10 k 50 604 604 50 499 54.9 50 155 130 190 125 195 150 225 110 175 135 Peaking @ ± 5 VS < 0.7 dB < 0.1 dB 0.5 dB None 0.4 dB 1.3 dB 1.8 dB < 0.1 dB 0.5 dB < 0.2 dB 0.1 dB Flatness @ ± 5 VS (MHz) – 35 – 25 – – – 30 – – Small Signal BW @ +5 VS (MHz) 135 115 175 110 165 130 195 95 155 120 Small Signal BW @ +5 VS (MHz) AD8004AR (SOIC) PACKAGE TYPE RF (Ω) RG (Ω) RT (Ω) Small Signal BW @ ± 5 VS (MHz) NOTES 1 RT chosen for 50 Ω characteristic input impedance. 2 Resistor values listed are standard 1% tolerance. –12– REV. B AD8004 Figure 39. Evaluation Board Silkscreen (Top) REV. B –13– AD8004 Figure 40 Evaluation Board Layout (Top Side) Figure 41. Evaluation Board Layout (Bottom Side, Looking Through the Board) –14– REV. B AD8004 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 14 C2078a–0–8/99 14-Lead Plastic DIP (N-14) 8 0.280 (7.11) 0.240 (6.10) PIN 1 1 7 0.325 (8.25) 0.300 (7.62) 0.795 (20.19) 0.725 (18.42) 0.060 (1.52) 0.015 (0.38) 0.210 (5.33) MAX 0.130 (3.30) MIN 0.160 (4.06) 0.115 (2.93) 0.022 (0.558) 0.014 (0.356) 0.100 (2.54) BSC 0.195 (4.95) 0.115 (2.93) 0.015 (0.381) 0.008 (0.204) SEATING PLANE 0.070 (1.77) 0.045 (1.15) 14-Lead Plastic SOIC (R-14) 0.3444 (8.75) 0.3367 (8.55) 0.1574 (4.00) 0.1497 (3.80) 14 8 1 7 PIN 1 0.0098 (0.25) 0.0040 (0.10) 0.0500 (1.27) BSC 0.0688 (1.75) 0.0532 (1.35) 0.0192 (0.49) 0.0138 (0.35) 0.0099 (0.25) 0.0075 (0.19) 0.0196 (0.50) x 45° 0.0099 (0.25) 8° 0° 0.0500 (1.27) 0.0160 (0.41) PRINTED IN U.S.A. SEATING PLANE 0.2440 (6.20) 0.2284 (5.80) REV. B –15– –16– PRINTED IN U.S.A. C2078a–0–8/99