AD AD7851AR 14-bit 333 ksps serial a/d converter Datasheet

a
14-Bit 333 kSPS
Serial A/D Converter
AD7851
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Single 5 V Supply
333 kSPS Throughput Rate/62 LSB DNL—A Grade
285 kSPS Throughput Rate/61 LSB DNL—K Grade
A & K Grades Guaranteed to 1258C/238 kSPS
Throughput Rate
Pseudo-Differential Input with Two Input Ranges
System and Self-Calibration with Autocalibration on
Power-Up
Read/Write Capability of Calibration Data
Low Power: 60 mW typ
Power-Down Mode: 5 mW typ Power Consumption
Flexible Serial Interface:
8051/SPI/QSPI/ mP Compatible
24-Pin DIP, SOIC and SSOP Packages
AVDD
AGND
AGND
AIN (+)
DVDD
T/H
AIN (–)
AD7851
DGND
4.096 V
REFERENCE
REFIN/
REFOUT
BUF
COMP
AMODE
CHARGE
REDISTRIBUTION
DAC
CREF1
CREF2
APPLICATIONS
Digital Signal Processing
Speech Recognition and Synthesis
Spectrum Analysis
DSP Servo Control
Instrumentation and Control Systems
High Speed Modems
Automotive
CLKIN
SAR + ADC
CONTROL
CONVST
BUSY
SLEEP
CALIBRATION
MEMORY
AND CONTROLLER
CAL
SERIAL INTERFACE / CONTROL REGISTER
SM1
SM2
SYNC
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The AD7851 is a high speed, 14-bit ADC that operates from a
single 5 V power supply. The ADC powers-up with a set of
default conditions at which time it can be operated as a readonly ADC. The ADC contains self-calibration and systemcalibration options to ensure accurate operation over time and
temperature and has a number of power-down options for low
power applications.
1.
2.
3.
4.
5.
DIN
DOUT SCLK POLARITY
Single 5 V supply.
Operates with reference voltages from 4 V to VDD.
Analog input ranges from 0 V to VDD.
System and self-calibration including power-down mode.
Versatile serial I/O port.
The AD7851 is capable of 333 kHz throughput rate. The input
track-and-hold acquires a signal in 0.33 µs and features a
pseudo-differential sampling scheme. The AD7851 has the
added advantage of two input voltage ranges (0 V to VREF, and
–VREF/2 to +VREF/2 centered about VREF/2). Input signal range
is to VDD and the part is capable of converting full-power signals
to 20 MHz.
CMOS construction ensures low power dissipation (60 mW typ)
with power-down mode (5 µW typ). The part is available in 24pin, 0.3 inch-wide dual-in-line package (DIP), 24-lead small
outline (SOIC) and 24-lead small shrink outline (SSOP) packages.
*Patent pending.
See Page 35 for data sheet index.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
© Analog Devices, Inc., 1996
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
1, 2
(08C to +858C), f
= 285 kHz; A and K Grade: f
= 5 MHz (to +1258C), f
=
AD7851–SPECIFICATIONS
238 kHz; (AV = DV = +5.0 V 6 5%, REF /REF = 4.096 V External Reference; SLEEP = Logic High; T = T to T , unless otherwise noted)
A Grade: fCLKIN = 7 MHz (–408C to +858C), fSAMPLE = 333 kHz; K Grade: fCLKIN = 6 MHz
SAMPLE
DD
DD
IN
CLKIN
A
OUT
MIN
SAMPLE
MAX
Parameter
A1
K1
Units
Test Conditions/Comments
DYNAMIC PERFORMANCE
Signal-to-Noise + Distortion Ratio3 (SNR)
77
78
dB min
Total Harmonic Distortion (THD)
–86
–86
dB max
Peak Harmonic or Spurious Noise
Intermodulation Distortion (IMD)
Second Order Terms
Third Order Terms
Full Power Bandwidth
–87
–87
dB max
Typically SNR is 79.5 dB
VIN = 10 kHz, Sine Wave, fSAMPLE = 333 kHz
VIN = 10 kHz, Sine Wave, fSAMPLE = 333 kHz,
Typically –96 dB
VIN = 10 kHz, fSAMPLE = 333 kHz
–86
–86
20
–90
–90
20
dB typ
dB typ
MHz typ
fa = 9.983 kHz, fb = 10.05 kHz, fSAMPLE = 333 kHz
fa = 9.983 kHz, fb = 10.05 kHz, fSAMPLE = 333 kHz
@ 3 dB
DC ACCURACY
Resolution
Integral Nonlinearity
Differential Nonlinearity
Unipolar Offset Error
Positive Full-Scale Error
Negative Full-Scale Error
Bipolar Zero Error
14
±2
±2
± 10
± 10
± 10
±1
14
±1
±1
± 10
± 10
± 10
±1
Bits
LSB max
LSB max
LSB max
LSB max
LSB typ
LSB typ
ANALOG INPUT
Input Voltage Ranges
0 V to VREF 0 V to VREF
Volts
± VREF/2
± VREF/2
Volts
±1
20
±1
20
µA max
pF typ
REFERENCE INPUT/OUTPUT
REFIN Input Voltage Range
Input Impedance
REFOUT Output Voltage
REFOUT Tempco
4/VDD
150
3.696/4.496
50
4/VDD
150
3.696/4.496
50
V min/max
kΩ typ
V min/max
ppm/°C typ
LOGIC INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
Input Capacitance, CIN5
VDD – 1.0
0.4
± 10
10
VDD – 1.0
0.4
± 10
10
V min
V max
µA max
pF max
Leakage Current
Input Capacitance
LOGIC OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
Floating-State Leakage Current
Floating-State Output Capacitance 5
Output Coding
CONVERSION RATE
Conversion Time
Conversion + T/H Acquisition Time
VDD – 0.4
VDD – 0.4
0.4
0.4
± 10
± 10
10
10
Straight (Natural) Binary
2s Complement
V min
V max
µA max
pF max
2.78
3.0
µs max
µs max
3.25
3.5
–2–
Guaranteed No Missed Codes to 14 Bits
Review: “Adjusting the Offset Calibration
Register” in the “Calibration Registers” section
of the data sheet.
i.e., AIN(+) – AIN(–) = 0 V to VREF, AIN(–) can be
biased up but AIN(+) cannot go below AIN(–).
i.e., AIN(+) – AIN(–) = –VREF/2 to +VREF/2, AIN(–)
should be biased up and AIN(+) can go below
AIN(–) but cannot go below 0 V.
Functional from 1.2 V
Resistor Connected to Internal Reference Node
VIN = 0 V or VDD
ISOURCE = 200 µA
ISINK = 0.8 mA
Unipolar Input Range
Bipolar Input Range
19.5 CLKIN Cycles
21 CLKIN Cycles Throughput Rate
REV. A
AD7851
Parameter
POWER PERFORMANCE
AVDD, DVDD
IDD
Normal Mode5
Sleep Mode6
With External Clock On
With External Clock Off
Normal Mode Power Dissipation
Sleep Mode Power Dissipation
With External Clock On
With External Clock Off
SYSTEM CALIBRATION
Offset Calibration Span7
Gain Calibration Span7
A1
K1
Units
+4.75/+5.25
+4.75/+5.25
V min/max
17
17
mA max
AVDD = DVDD = 4.75 V to 5.25 V. Typically
12 mA.
20
20
µA typ
600
600
µA typ
10
10
µA max
300
300
µA typ
89.25
89.25
mW max
Full Power-Down. Power management bits
in control register set as PMGT1 = 1, PMGT0 = 0.
Partial Power-Down. Power management bits in
control register set as PMGT1 = 1, PMGT0 = 1.
Typically 1 µA. Full Power-Down. Power
management bits in control register set as
PMGT1 = 1, PMGT0 = 0.
Partial Power-Down. Power management bits in
control register set as PMGT1 = 1, PMGT0 = 1.
VDD = 5.25 V: Typically 63 mW; SLEEP = VDD.
105
52.5
105
52.5
µW typ
µW max
VDD = 5.25 V; SLEEP = 0 V
VDD = 5.25 V; Typically 5.25 µW; SLEEP = 0 V
V max/min
V max/min
Allowable Offset Voltage Span for Calibration
Allowable Full-Scale Voltage Span for Calibratio n
+0.05 × VREF/–0.05 × VREF
+1.025 × VREF/–0.975 × VREF
Test Conditions/Comments
NOTES
1
Temperature ranges as follows: A Version, –40°C to +125°C; K Version, 0°C to +125°C.
2
Specifications apply after calibration.
3
SNR calculation includes distortion and noise components.
4
Sample tested @ +25°C to ensure compliance.
5
All digital inputs @ DGND except for CONVST, SLEEP, CAL, and SYNC @ DVDD. No load on the digital outputs. Analog inputs @ AGND.
6
CLKIN @ DGND when external clock off. All digital inputs @ DGND except for CONVST, SLEEP, CAL, and SYNC @ DVDD. No load on the digital outputs.
Analog inputs @ AGND.
7
The offset and gain calibration spans are defined as the range of offset and gain errors that the AD7851 can calibrate. Note also that these are voltage spans and are
not absolute voltages (i.e., the allowable system offset voltage presented at AIN(+) for the system offset error to be adjusted out will be AIN(–) ± 0.05 × VREF, and the
allowable system full-scale voltage applied between AIN(+) and AIN(–) for the system full-scale voltage error to be adjusted out will be VREF ± 0.025 × VREF). This is
explained in more detail in the calibration section of the data sheet.
Specifications subject to change without notice.
REV. A
–3–
AD7851
TIMING SPECIFICATIONS1 (AV
DD =
DVDD = +5.0 V 6 5%; fCLKIN = 6 MHz, TA = TMIN to TMAX, unless otherwise noted)
Limit at TMIN, TMAX
A, K
Units
Description
kHz min
MHz max
MHz max
MHz max
ns min
ns max
µs max
ns min
ns min/max
ns min
ns max
ns max
ns max
ns min
ns min
ns min
ns min
ns min
ns min/max
ns max
ns max
ns max
ns max
ns max
ns max
ms typ
Master Clock Frequency
t11A
t127
t13
t148
t15
t16
tCAL9
500
7
10
fCLK IN
100
50
3.25
–0.4 tSCLK
± 0.4 tSCLK
0.6 tSCLK
30
30
45
30
20
0.4 tSCLK
0.4 tSCLK
30
30/0.4 tSCLK
50
50
90
50
2.5 tCLKIN
2.5 tCLKIN
41.7
tCAL19
37.04
ms typ
tCAL29
4.63
ms typ
tDELAY
65
ns max
Parameter
fCLKIN2
fSCLK3
t1 4
t2
tCONVERT
t3
t4
t5 5
t5A5
t6 5
t7
t8
t9 6
t106
t11
Interface Modes 1, 2, 3 (External Serial Clock)
Interface Modes 4, 5 (Internal Serial Clock)
CONVST Pulse Width
CONVST↓ to BUSY↑ Propagation Delay
Conversion Time = 20 tCLKIN
SYNC↓ to SCLK↓ Setup Time (Noncontinuous SCLK Input)
SYNC↓ to SCLK↓ Setup Time (Continuous SCLK Input)
SYNC↓ to SCLK↓ Setup Time. Interface Mode 4 Only
Delay from SYNC↓ until DOUT 3-State Disabled
Delay from SYNC↓ until DIN 3-State Disabled
Data Access Time After SCLK↓
Data Setup Time Prior to SCLK↑
Data Valid to SCLK Hold Time
SCLK High Pulse Width (Interface Modes 4 and 5)
SCLK Low Pulse Width (Interface Modes 4 and 5)
SCLK↑ to SYNC↑ Hold Time (Noncontinuous SCLK)
(Continuous SCLK) Does Not Apply to Interface Mode 3
SCLK↑ to SYNC↑ Hold Time
Delay from SYNC↑ until DOUT 3-State Enabled
Delay from SCLK↑ to DIN Being Configured as Output
Delay from SCLK↑ to DIN Being Configured as Input
CAL↑ to BUSY↑ Delay
CONVST↓ to BUSY↑ Delay in Calibration Sequence
Full Self-Calibration Time, Master Clock Dependent (250026
tCLKIN)
Internal DAC Plus System Full-Scale Cal Time, Master Clock
Dependent (222228 tCLKIN)
System Offset Calibration Time, Master Clock Dependent
(27798 tCLKIN)
Delay from CLK to SCLK
NOTES
Descriptions that refer to SCLK↑ (rising) or SCLK↓ (falling) edges here are with the POLARITY pin HIGH. For the POLARITY pin LOW then the opposite edge of
SCLK will apply.
1
Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V DD) and timed from a voltage level of 1.6 V. See
Table X and timing diagrams for different interface modes and calibration.
2
Mark/Space ratio for the master clock input is 40/60 to 60/40.
3
For Interface Modes 1, 2, 3 the SCLK max frequency will be 10 MHz. For Interface Modes 4 and 5 the SCLK will be an output and the frequency will be f CLKIN.
4
The CONVST pulse width will here only apply for normal operation. When the part is in power-down mode, a different CONVST pulse width will apply (see PowerDown section).
5
Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.4 V.
6
For self-clocking mode (Interface Modes 4, 5) the nominal SCLK high and low times will be 0.5 t SCLK = 0.5 t CLKIN.
7
t12 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t 12, quoted in the timing characteristics is the true bus relinquish
time of the part and is independent of the bus loading.
8
t14 is derived form the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time quoted in the timing characteristics is the true delay of the part in
turning off the output drivers and configuring the DIN line as an input. Once this time has elapsed the user can drive the DIN line knowing that a bus conflict will
not occur.
9
The typical time specified for the calibration times is for a master clock of 6 MHz.
Specifications subject to change without notice.
–4–
REV. A
AD7851
TYPICAL TIMING DIAGRAMS
IOL
1.6mA
Figures 2 and 3 show typical read and write timing diagrams.
Figure 2 shows the reading and writing after conversion in Interface Modes 2 and 3. To attain the maximum sample rate of
285 kHz in Interface Modes 2 and 3, reading and writing must
be performed during conversion. Figure 3 shows the timing diagram for Interface Modes 4 and 5 with sample rate of 285 kHz.
At least 330 ns acquisition time must be allowed (the time from
the falling edge of BUSY to the next rising edge of CONVST)
before the next conversion begins to ensure that the part is
settled to the 14-bit level. If the user does not want to provide
the CONVST signal, the conversion can be initiated in software
by writing to the control register.
TO
OUTPUT
PIN
+2.1V
CL
50pF
IOH
200µA
Figure 1. Load Circuit for Digital Output Timing
Specifications
tCONVERT = 3.25µs MAX, t1 = 100ns MIN,
t5 = 30ns MAX, t7 = 30ns MIN
POLARITY PIN LOGIC HIGH
t1
CONVST (I/P)
tCONVERT
t2
BUSY (O/P)
SYNC (I/P)
t3
5
6
16
t10
t5
t6
t6
3-STATE
DOUT (O/P)
t11
t9
1
SCLK (I/P)
DB15
t12
DB11
DB0
3-STATE
t7
t8
DIN (I/P)
DB15
DB0
DB11
Figure 2. AD7851 Timing Diagram (Typical Read and Write Operation for Interface Modes 2, 3)
tCONVERT = 3.25µs MAX, t1 = 100ns MIN,
t5 = 30ns MAX, t7 = 30ns MIN
POLARITY PIN LOGIC HIGH
t1
CONVST (I/P)
tCONVERT
t2
BUSY (O/P)
SYNC (O/P)
t4
SCLK (O/P)
t11
t9
1
5
6
16
t10
t5
t12
t6
DOUT (O/P)
3-STATE
DB15
DB11
DB0
3-STATE
t7
t8
DIN (I/P)
DB15
DB0
DB11
Figure 3. AD7851 Timing Diagram (Typical Read and Write Operation for Interface Modes 4, 5)
REV. A
–5–
AD7851
PINOUT FOR DIP, SOIC AND SSOP
ABSOLUTE MAXIMUM RATINGS 1
(TA = +25°C unless otherwise noted)
AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
AVDD to DVDD . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
Analog Input Voltage to AGND . . . . –0.3 V to AVDD + 0.3 V
Digital Input Voltage to DGND . . . . –0.3 V to DVDD + 0.3 V
Digital Output Voltage to DGND . . . –0.3 V to DVDD + 0.3 V
REFIN/REFOUT to AGND . . . . . . . . . –0.3 V to AVDD + 0.3 V
Input Current to Any Pin Except Supplies2 . . . . . . . . ± 10 mA
Operating Temperature Range
Commercial (A, K Versions) . . . . . . . . . . –40°C to +125°C
Storage Temperature Range . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
Plastic DIP Package, Power Dissipation . . . . . . . . . . 450 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . 105°C/W
θJC Thermal Impedance . . . . . . . . . . . . . . . . . . . . 34.7°C/W
Lead Temperature, (Soldering, 10 secs) . . . . . . . . . . +260°C
SOIC, SSOP Package, Power Dissipation . . . . . . . . . 450 mW
θJA Thermal Impedance . . . 75°C/W (SOIC) 115°C/W (SSOP)
θJC Thermal Impedance . . . . 25°C/W (SOIC) 35°C/W (SSOP)
Lead Temperature, Soldering
Vapor Phase (60 secs) . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 secs) . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >1.5 kV
CONVST
1
24 SYNC
BUSY
2
23 SCLK
SLEEP
3
22 CLKIN
21 DIN
REFIN/REFOUT 4
AVDD
5
AD7851
20 DOUT
AGND
6
19 DGND
CREF1
7
TOP VIEW
(Not to Scale)
CREF2
8
17 CAL
AIN(+)
9
16 SM2
AIN(–) 10
15 SM1
18 DVDD
14 POLARITY
NC 11
13 AMODE
AGND 12
NOTES
1
Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
2
Transient currents of up to 100 mA will not cause SCR latch-up.
ORDERING GUIDE1
Model
AD7851AN
AD7851KN
AD7851AR
AD7851KR
AD7851ARS
EVAL-AD7851CB4
EVAL-CONTROL BOARD5
Temp
Range
Linearity
Error
(LSB)2
Throughput
Rate
Throughput
@ +1258C
Package
Options3
–40°C to +85°C
0°C to +85°C
–40°C to +85°C
0°C to +85°C
–40°C to +85°C
±2
±1
±2
±1
±2
333 kSPS
285 kSPS
333 kSPS
285 kSPS
333 kSPS
238 kSPS
238 kSPS
238 kSPS
238 kSPS
238 kSPS
N-24
N-24
R-24
R-24
RS-24
NOTES
1
Both A and K Grades are guaranteed up to 125°C, but at a lower throughput of 238 kHz (5 MHz)..
2
Linearity error refers to the integral linearity error.
3
N = Plastic DIP; R = SOIC; RS = SSOP.
4
This can be used as a stand-alone evaluation board or in conjunction with the EVAL-CONTROL BOARD for evaluation/demonstration
purposes.
5
This board is a complete unit allowing a PC to control and communicate with all Analog Devices, Inc. evaluation boards ending in the
CB designators.
–6–
REV. A
AD7851
TERMINOLOGY
Integral Nonlinearity
This is the maximum deviation from a straight line passing
through the endpoints of the ADC transfer function. The endpoints of the transfer function are zero scale, a point 1/2 LSB
below the first code transition, and full scale, a point 1/2 LSB
above the last code transition.
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the rms sum of
harmonics to the fundamental. For the AD7851, it is defined as:
V 2 +V 2 +V 2 +V 2 +V 2 
3
4
5
6 
 2
THD(dB ) = 20log
V1
Differential Nonlinearity
This is the difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
where V1 is the rms amplitude of the fundamental and V2, V3,
V4, V5 and V6 are the rms amplitudes of the second through the
sixth harmonics.
Total Unadjusted Error
This is the deviation of the actual code from the ideal code taking all errors into account (Gain, Offset, Integral Nonlinearity,
and other errors) at any point along the transfer function.
Peak Harmonic or Spurious Noise
Peak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to fS/2 and excluding dc) to the rms value of the
fundamental. Normally, the value of this specification is determined by the largest harmonic in the spectrum, but for parts
where the harmonics are buried in the noise floor, it will be a
noise peak.
Unipolar Offset Error
This is the deviation of the first code transition (00 . . . 000 to
00 . . . 001) from the ideal AIN(+) voltage (AIN(–) + 1/2 LSB)
when operating in the unipolar mode.
Positive Full-Scale Error
This applies to the unipolar and bipolar modes and is the deviation of the last code transition from the ideal AIN(+) voltage
(AIN(–) + Full Scale – 1.5 LSB) after the offset error has been
adjusted out.
Negative Full-Scale Error
This applies to the bipolar mode only and is the deviation of the
first code transition (00 . . . 000 to 00 . . . 001) from the ideal
AIN(+) voltage (AIN(–) – VREF/2 + 0.5 LSB).
Bipolar Zero Error
This is the deviation of the midscale transition (all 0s to all 1s)
from the ideal AIN(+) voltage (AIN(–) – 1/2 LSB).
Track/Hold Acquisition Time
The track/hold amplifier returns into track mode and the end of
conversion. Track/Hold acquisition time is the time required for
the output of the track/hold amplifier to reach its final value,
within ± 1/2 LSB, after the end of conversion.
Signal to (Noise + Distortion) Ratio
This is the measured ratio of signal to (noise + distortion) at the
output of the A/D converter. The signal is the rms amplitude of
the fundamental. Noise is the sum of all nonfundamental signals up to half the sampling frequency (fS/2), excluding dc. The
ratio is dependent on the number of quantization levels in the
digitization process; the more levels, the smaller the quantization noise. The theoretical signal to (noise + distortion) ratio for
an ideal N-bit converter with a sine wave input is given by:
Signal to (Noise + Distortion) = (6.02 N +1.76) dB
Thus for a 14-bit converter, this is 86 dB.
REV. A
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products at sum and difference frequencies of mfa ± nfb where
m, n = 0, 1, 2, 3, etc. Intermodulation distortion terms are
those for which neither m nor n are equal to zero. For example,
the second order terms include (fa + fb) and (fa – fb), while the
third order terms include (2fa + fb), (2fa – fb), (fa + 2fb) and
(fa – 2fb).
Testing is performed using the CCIF standard where two input
frequencies near the top end of the input bandwidth are used. In
this case, the second order terms are usually distanced in frequency from the original sine waves while the third order terms
are usually at a frequency close to the input frequencies. As a
result, the second and third order terms are specified separately.
The calculation of the intermodulation distortion is as per the
THD specification where it is the ratio of the rms sum of the
individual distortion products to the rms amplitude of the sum
of the fundamentals expressed in dBs.
Power Supply Rejection Ratio
Power Supply Rejection Ratio (PSRR) is defined as the ratio of
the power in ADC output at frequency f to the power of the fullscale sine wave applied to the supply voltage (VDD). The units
are in LSB, %of FS per % of supply voltage, or expressed logarithmically, in dB (PSRR (dB) = 10 log(Pf/Pfs)).
Full Power Bandwidth
The Full Power Bandwidth (FPBW) is that frequency at which
the amplitude of the reconstructed (using FFTs) fundamental
(neglecting harmonics and SNR) is reduced by 3 dB for a fullscale input.
–7–
AD7851
PIN FUNCTION DESCRIPTION
Pin
Mnemonic
Description
1
CONVST
Convert Start. Logic input. A low to high transition on this input puts the track/hold into its hold mode and
starts conversion. When this input is not used, it should be tied to DVDD.
2
BUSY
Busy Output. The busy output is triggered high by the falling edge of CONVST or rising edge of CAL, and
remains high until conversion is completed. BUSY is also used to indicate when the AD7851 has completed
its on-chip calibration sequence.
3
SLEEP
Sleep Input/Low Power Mode. A logic 0 initiates a sleep and all circuitry is powered down including the internal voltage reference provided there is no conversion or calibration being performed. Calibration data is
retained. A logic 1 results in normal operation. See Power-Down section for more details.
4
REFIN/
REFOUT
Reference Input/Output. This pin is connected to the internal reference through a series resistor and is the
reference source for the analog-to-digital converter. The nominal reference voltage is 4.096 V and this appears at the pin. This pin can be overdriven by an external reference or can be taken as high as AVDD.
When this pin is tied to AVDD, then the CREF1 pin should also be tied to AVDD.
5
AVDD
Analog Positive Supply Voltage, +5.0 V ± 5%.
6, 12 AGND
Analog Ground. Ground reference for track/hold, reference and DAC.
7
CREF1
Reference Capacitor (0.01 µF ceramic disc in parallel with a 470 nF NPO type). This external capacitor is
used as a charge source for the internal DAC. The capacitor should be tied between the pin and AGND.
8
CREF2
Reference Capacitor (0.01 µF ceramic disc in parallel with a 470 nF NPO type). This external capacitor is
used in conjunction with the on-chip reference. The capacitor should be tied between the pin and AGND.
9
AIN(+)
Analog Input. Positive input of the pseudo-differential analog input. Cannot go below AGND or above
AVDD at any time, and cannot go below AIN(–) when the unipolar input range is selected.
10
AIN(–)
Analog Input. Negative input of the pseudo-differential analog input. Cannot go below AGND or above
AVDD at any time.
11
NC
No Connect Pin.
13
AMODE
Analog Mode Pin. This pin allows two different analog input ranges to be selected. A logic 0 selects range 0
to VREF (i.e., AIN(+) – AIN(–) = 0 to VREF). In this case AIN(+) cannot go below AIN(–) and
AIN(–) cannot go below AGND. A logic 1 selects range –VREF/2 to +VREF/2 (i.e., AIN(+) – AIN(–) =
–VREF /2 to +VREF/2). In this case AIN(+) cannot go below AGND so that AIN(–) needs to be biased to
+VREF/2 to allow AIN(+) to go from 0 V to +VREF V.
14
POLARITY
Serial Clock Polarity. This pin determines the active edge of the serial clock (SCLK). Toggling this pin will
reverse the active edge of the serial clock (SCLK). A logic 1 means that the serial clock (SCLK) idles high
and a logic 0 means that the serial clock (SCLK) idles low. It is best to refer to the timing diagrams and
Table X for the SCLK active edges.
15
SM1
Serial Mode Select Pin. This pin is used in conjunction with the SM2 pin to give different modes of operation as described in Table XI.
16
SM2
Serial Mode Select Pin. This pin is used in conjunction with the SM1 pin to give different modes of operation as described in Table XI.
17
CAL
Calibration Input. This pin has an internal pull-up current source of 0.15 µA. A logic 0 on this pin resets all
logic and initiates a calibration on its rising edge. There is the option of connecting a 10 nF capacitor from
this pin to AGND to allow for an automatic self calibration on power-up. This input overrides all other
internal operations.
18
DVDD
Digital Supply Voltage, +5.0 V ± 5%.
19
DGND
Digital Ground. Ground reference point for digital circuitry.
20
DOUT
Serial Data Output. The data output is supplied to this pin as a 16-bit serial word.
21
DIN
Serial Data Input. The data to be written is applied to this pin in serial form (16-bit word). This pin can act
as an input pin or as a I/O pin depending on the serial interface mode the part is in (see Table XI).
22
CLKIN
Master Clock Signal for the device (6 MHz or 7 MHz). Sets the conversion and calibration times.
23
SCLK
Serial Port Clock. Logic input/output. The SCLK pin is configured as an input or output, dependent on the
type of serial data transmission (self-clocking or external-clocking) that has been selected by the SM1 and
SM2 pins. The SCLK idles high or low depending on the state of the POLARITY pin.
24
SYNC
This pin can be an input level triggered active low (similar to a chip select in one case and to a frame sync
in the other) or an output (similar to a frame sync) pin depending on SM1, SM2 (see Table XI).
–8–
REV. A
AD7851
AD7851 ON-CHIP REGISTERS
The AD7851 powers up with a set of default conditions, and the user need not ever write to the device. In this case the AD7851 will
operate as a Read-Only ADC. The AD7851 still retains the flexibility for performing a full power-down, and a full self-calibration.
Note that the DIN pin should be tied to DGND for operating the AD7851 as a Read-Only ADC.
Extra features and flexibility such as performing different power-down options, different types of calibrations including system calibration, and software conversion start can be selected by writing to the part.
The AD7851 contains a Control register, ADC output data register, Status register, Test register and 10 Calibration registers. The control register is write-only, the ADC output data register and the status register are read-only, and the test and calibration registers are both read/write registers. The test register is used for testing the part and should not be written to.
Addressing the On-Chip Registers
Writing
A write operation to the AD7851 consists of 16 bits. The two MSBs, ADDR0 and ADDR1, are decoded to determine which register
is addressed, and the subsequent 14 bits of data are written to the addressed register. It is not until all 16 bits are written that the
data is latched into the addressed register. Table I shows the decoding of the address bits, while Figure 4 shows the overall write register hierarchy.
Table I. Write Register Addressing
ADDR1
ADDR0
Comment
0
0
1
0
1
0
1
1
This combination does not address any register so the subsequent 14 data bits are ignored.
This combination addresses the TEST REGISTER. The subsequent 14 data bits are written to the test register.
This combination addresses the CALIBRATION REGISTERS. The subsequent 14 data bits are written
to the selected calibration register.
This combination addresses the CONTROL REGISTER. The subsequent 14 data bits are written to the
control register.
Reading
To read from the various registers the user must first write to Bits 6 and 7 in the Control Register, RDSLT0 and RDSLT1. These
bits are decoded to determine which register is addressed during a read operation. Table II shows the decoding of the read address
bits while Figure 5 shows the overall read register hierarchy. The power-up status of these bits is 00 so that the default read will be
from the ADC output data register.
Once the read selection bits are set in the control register all subsequent read operations that follow will be from the selected register
until the read selection bits are changed in the control register.
Table II. Read Register Addressing
RDSLT1
RDSLT0
Comment
0
0
0
1
1
1
0
1
All successive read operations will be from ADC OUTPUT DATA REGISTER. This is the power-up default setting. There will always be four leading zeros when reading from the ADC output data register.
All successive read operations will be from TEST REGISTER.
All successive read operations will be from CALIBRATION REGISTERS.
All successive read operations will be from STATUS REGISTER.
RDSLT1, RDSLT0
DECODE
ADDR1, ADDR0
DECODE
01
10
TEST
REGISTER
GAIN (1)
OFFSET (1)
DAC (8)
CALSLT1, CALSLT0
DECODE
00
GAIN (1)
OFFSET (1)
01
00
11
CALIBRATION
REGISTERS
OFFSET (1)
10
ADC OUTPUT
DATA REGISTER
CONTROL
REGISTER
11
CALSLT1, CALSLT0
DECODE
10
TEST
REGISTER
GAIN (1)
OFFSET (1)
DAC (8)
GAIN (1)
00
11
CALIBRATION
REGISTERS
GAIN (1)
OFFSET (1)
01
OFFSET (1)
10
STATUS
REGISTER
GAIN (1)
11
Figure 5. Read Register Hierarchy/Address Decoding
Figure 4. Write Register Hierarchy/Address Decoding
REV. A
01
–9–
AD7851
CONTROL REGISTER
The arrangement of the control register is shown below. The control register is a write only register and contains 14 bits of data. The
control register is selected by putting two 1s in ADDR1 and ADDR0. The function of the bits in the control register are described
below. The power-up status of all bits is 0.
MSB
ZERO
ZERO
ZERO
ZERO
PMGT1
PMGT0
PMGT1
RDSLT0
2/3 MODE
CONVST
CALMD
CALST1
CALSLT0
STCAL
LSB
Control Register Bit Function Description
Bit
Mnemonic
Comment
13
12
11
10
ZERO
ZERO
ZERO
ZERO
These four bits must be set to 0 when writing to the control register.
9
8
PMGT1
PMGT0
Power Management Bits. These two bits are used with the SLEEP pin for putting the part into various
power-down modes (see Power-Down section for more details).
7
6
RDSLT1
RDSLT0
Theses two bits determine which register is addressed for the read operations. See Table II.
5
2/3 MODE
Interface Mode Select Bit. With this bit set to 0, Interface Mode 2 is enabled. With this bit set to 1,
Interface Mode 1 is enabled where DIN is used as an output as well as an input. This bit is set to 0 by
default after every read cycle; thus when using Interface Mode 1, this bit needs to be set to 1 in every
write cycle.
4
CONVST
Conversion Start Bit. A logic one in this bit position starts a single conversion, and this bit is automatically reset to 0 at the end of conversion. This bit may also used in conjunction with system calibration
(see Calibration section on page 21).
3
CALMD
Calibration Mode Bit. A 0 here selects self-calibration and a 1 selects a system calibration (see Table III).
2
1
0
CALSLT1
CALSLT0
STCAL
Calibration Selection Bits and Start Calibration Bit. These bits have two functions.
With the STCAL bit set to 1, the CALSLT1 and CALSLT0 bits determine the type of calibration performed by the part (see Table III). The STCAL bit is automatically reset to 0 at the end of calibration.
With the STCAL bit set to 0, the CALSLT1 and CALSLT0 bits are decoded to address the calibration
register for read/write of calibration coefficients (see section on the calibration registers for more details).
Table III. Calibration Selection
CALMD
CALSLT1
CALSLT0
Calibration Type
0
0
0
A full internal calibration is initiated where the internal DAC is calibrated followed by the
internal gain error and finally the internal offset error is calibrated out. This is the default setting.
0
0
1
Here the internal gain error is calibrated out followed by the internal offset error calibrated
out.
0
1
0
This calibrates out the internal offset error only.
0
1
1
This calibrates out the internal gain error only.
1
0
0
A full system calibration is initiated here where first the internal DAC is calibrated, followed by the system gain error, and finally the system offset error is calibrated out.
1
0
1
Here the system gain error is calibrated out followed by the system offset error.
1
1
0
This calibrates out the system offset error only.
1
1
1
This calibrates out the system gain error only.
–10–
REV. A
AD7851
STATUS REGISTER
The arrangement of the status register is shown below. The status register is a read-only register and contains 16 bits of data. The
status register is selected by first writing to the control register and putting two 1s in RDSLT1 and RDSLT0. The function of the
bits in the status register are described below. The power-up status of all bits is 0.
START
WRITE TO CONTROL REGISTER
SETTING RDSLT0 = RDSLT1 = 1
READ STATUS REGISTER
Figure 6. Flowchart for Reading the Status Register
MSB
ZERO
BUSY
ZERO
ZERO
ZERO
ZERO
PMGT1
PMGT0
RDSLT1
RDSLT0
2/3 MODE
X
CALMD
CALSLT1
CALSLT0
STCAL
LSB
Status Register Bit Function Description
Bit
Mnemonic
15
ZERO
This bit is always 0.
14
BUSY
Conversion/Calibration Busy Bit. When this bit is 1, this indicates that there is a conversion or calibration
in progress. When this bit is 0, there is no conversion or calibration in progress.
13
12
11
10
ZERO
ZERO
ZERO
ZERO
These four bits are always 0.
9
8
PMGT1
PMGT0
Power Management Bits. These bits along with the SLEEP pin will indicate if the part is in a power-down
mode or not. See Table VI in Power-Down Section for description.
7
6
ONE
ONE
Both these bits are always 1 indicating it is the status register that is being read. See Table II.
5
2/3 MODE
Interface Mode Select Bit. With this bit 0, the device is in Interface Mode 2. With this bit 1, the device is in
Interface Mode 1. This bit is reset to 0 after every read cycle.
4
X
Don’t care bit.
3
CALMD
Calibration Mode Bit. A 0 in this bit indicates a self-calibration is selected, and a 1 in this bit indicates a
system calibration is selected (see Table III).
2
1
0
CALSLT1
CALSLT0
STCAL
Calibration Selection Bits and Start Calibration Bit. The STCAL bit is read as a 1 if a calibration is in
progress and as a 0 if there is no calibration in progress. The CALSLT1 and CALSLT0 bits indicate
which of the calibration registers are addressed for reading and writing (see section on the Calibration
Registers for more details).
REV. A
Comment
–11–
AD7851
CALIBRATION REGISTERS
The AD7851 has 10 calibration registers in all, 8 for the DAC, 1 for the offset and 1 for gain. Data can be written to or read from all
10 calibration registers. In self and system calibration the part automatically modifies the calibration registers; only if the user needs
to modify the calibration registers should an attempt be made to read from and write to the calibration registers.
Addressing the Calibration Registers
The calibration selection bits in the control register CALSLT1 and CALSLT0 determine which of the calibration registers are addressed (see Table IV). The addressing applies to both the read and write operations for the calibration registers. The user should
not attempt to read from and write to the calibration registers at the same time.
Table IV. Calibration Register Addressing
CALSLT1
0
0
1
1
CALSLT0
0
1
0
1
Comment
This combination addresses the Gain (1), Offset (1) and DAC Registers (8). Ten registers in total.
This combination addresses the Gain (1) and Offset (1) Registers. Two registers in total.
This combination addresses the Offset Register. One register in total.
This combination addresses the Gain Register. One register in total.
Writing to/Reading from the Calibration Registers
For writing to the calibration registers a write to the control register is required to set the CALSLT0 and CALSLT1 bits. For
reading from the calibration registers a write to the control register is required to set the CALSLT0 and CALSLT1 bits, but
also to set the RDSLT1 and RDSLT0 bits to 10 (this addresses
the calibration registers for reading). The calibration register
pointer is reset on writing to the control register setting the
CALSLT1 and CALSLT0 bits, or upon completion of all the
calibration register write/read operations. When reset it points
to the first calibration register in the selected write/read
sequence. The calibration register pointer will point to the gain
calibration register upon reset in all but one case, this case being where the offset calibration register is selected on its own
(CALSLT1 = 1, CALSLT0 = 0). Where more than one calibration register is being accessed, the calibration register
pointer will be automatically incremented after each calibration
register write/read operation. The order in which the 10 calibration registers are arranged is shown in Figure 7. The user may
abort at any time before all the calibration register write/read
operations are completed, and the next control register write
operation will reset the calibration register pointer. The flowchart in Figure 8 shows the sequence for writing to the calibration registers and Figure 9 for reading.
When reading from the calibration registers there will always be
two leading zeros for each of the registers. When operating in
serial Interface Mode 1, the read operations to the calibration
registers cannot be aborted. The full number of read operations
must be completed (see section on serial Interface Mode 1 timing for more detail).
GAIN REGISTER
(1)
OFFSET REGISTER
(2)
DAC 1st MSB REGISTER
(3)
WRITE TO CONTROL REGISTER SETTING STCAL = 0
AND CALSLT1, CALSLT0 = 00, 01, 10, 11
CAL REGISTER POINTER IS
AUTOMATICALLY RESET
WRITE TO CAL REGISTER
(ADDR1 = 1, ADDR0 = 0)
CAL REGISTER POINTER IS
AUTOMATICALLY INCREMENTED
LAST
REGISTER
WRITE
OPERATION
OR
ABORT
?
CALIBRATION REGISTERS
CAL REGISTER
ADDRESS POINTER
START
NO
YES
FINISHED
DAC 8th MSB REGISTER
(10)
CALIBRATION REGISTER ADDRESS POINTER POSITION IS
DETERMINED BY THE NUMBER OF CALIBRATION REGISTERS
ADDRESSED AND THE NUMBER OF READ/WRITE OPERATIONS.
Figure 8. Flowchart for Writing to the Calibration Registers
Figure 7. Calibration Register Arrangement
–12–
REV. A
AD7851
START
WRITE TO CONTROL REGISTER SETTING STCAL = 0, RDSLT1 = 1,
RDSLT0 = 0, AND CALSLT1, CALSLT0 = 00, 01, 10, 11
CAL REGISTER POINTER IS
AUTOMATICALLY RESET
READ CAL REGISTER
CAL REGISTER POINTER IS
AUTOMATICALLY INCREMENTED
LAST
REGISTER
WRITE
OPERATION
OR
ABORT
?
NO
YES
FINISHED
Figure 9. Flowchart for Reading from the Calibration
Registers
Adjusting the Offset Calibration Register
The offset calibration register contains 16 bits, two leading zeros
and 14 data bits. By changing the contents of the offset register,
different amounts of offset on the analog input signal can be
compensated for. Increasing the number in the offset calibration
register compensates for negative offset on the analog input signal, and decreasing the number in the offset calibration register
compensates for positive offset on the analog input signal. The
default value of the offset calibration register is 0010 0000 0000
0000 approximately. This is not an exact value, but the value in
the offset register should be close to this value. Each of the 14
data bits in the offset register is binary weighted; the MSB has a
weighting of 5% of the reference voltage, the MSB-1 has a
weighting of 2.5%, the MSB-2 has a weighting of 1.25%, and so
on down to the LSB which has a weighting of 0.0006%.
REV. A
This gives a resolution of ± 0.0006% of VREF approximately.
More accurately the resolution is ± (0.05 × VREF)/213 volts =
± 0.015 mV, with a 2.5 V reference. The maximum offset that
can be compensated for is ± 5% of the reference voltage, which
equates to ± 125 mV with a 2.5 V reference and ± 250 mV with a
5 V reference.
Q. If a +20 mV offset is present in the analog input signal and the
reference voltage is 2.5 V, what code needs to be written to the
offset register to compensate for the offset?
A. 2.5 V reference implies that the resolution in the offset register is 5% × 2.5 V/213 = 0.015 mV. +20 mV/0.015 mV =
1310.72; rounding to the nearest number gives 1311. In
binary terms this is 0101 0001 1111, therefore decrease the
offset register by 0101 0001 1111.
This method of compensating for offset in the analog input signal allows for fine tuning the offset compensation. If the offset
on the analog input signal is known, there will be no need to
apply the offset voltage to the analog input pins and do a system
calibration. The offset compensation can take place in software.
Adjusting the Gain Calibration Register
The gain calibration register contains 16 bits, two leading 0s
and 14 data bits. The data bits are binary weighted as in the offset calibration register. The gain register value is effectively multiplied by the analog input to scale the conversion result over the
full range. Increasing the gain register compensates for a
smaller analog input range and decreasing the gain register compensates for a larger input range. The maximum analog input
range that the gain register can compensate for is 1.025 times
the reference voltage, and the minimum input range is 0.975
times the reference voltage.
–13–
AD7851
CIRCUIT INFORMATION
The AD7851 is a fast, 14-bit single supply A/D converter. The
part requires an external 6/7 MHz master clock (CLKIN), two
CREF capacitors, a CONVST signal to start conversion and
power supply decoupling capacitors. The part provides the user
with track/hold, on-chip reference, calibration features, A/D
converter and serial interface logic functions on a single chip.
The A/D converter section of the AD7851 consists of a conventional successive-approximation converter based around a capacitor DAC. The AD7851 accepts an analog input range of
0 V to +VDD where the reference can be tied to VDD. The reference input to the part is buffered onchip.
A major advantage of the AD7851 is that a conversion can be
initiated in software as well as applying a signal to the CONVST
pin. Another innovative feature of the AD7851 is self-calibration
on power-up, which is initiated having a 0.01 µF capacitor from
the CAL pin to AGND, to give superior dc accuracy. The part
should be allowed 150 ms after power-up to perform this automatic calibration before any reading or writing takes place. The
part is available in a 24-pin SSOP package and this offers the user
considerable space saving advantages over alternative solutions.
CONVERTER DETAILS
The master clock for the part must be applied to the CLKIN
pin. Conversion is initiated on the AD7851 by pulsing the
CONVST input or by writing to the control register and setting
the CONVST bit to 1. On the rising edge of CONVST (or at
the end of the control register write operation), the on-chip
track/hold goes from track to hold mode. The falling edge of the
CLKIN signal which follows the rising edge of the edge of
CONVST signal initiates the conversion, provided the rising
edge of CONVST occurs at least 10 ns typically before this
CLKIN edge. The conversion cycle will take 18.5 CLKIN periods from this CLKIN falling edge. If the 10 ns setup time is
not met, the conversion will take 19.5 CLKIN periods. The
maximum specified conversion time is 3.25 µs (6 MHz ) and
2.8 µs (7 MHz) for the A and K Grades respectively for the
AD7851 (19.5 tCLKIN, CLKIN = 6/7 MHz). When a conversion
is completed, the BUSY output goes low, and then the result of
the conversion can be read by accessing the data through the serial interface. To obtain optimum performance from the part,
the read operation should not occur during the conversion or
500 ns prior to the next CONVST rising edge. However, the
maximum throughput rates are achieved by reading/writing during conversion, and reading/writing during conversion is likely
to degrade the Signal to (Noise + Distortion) by only 0.5 dBs. The
AD7851 can operate at throughput rates up to 333 kHz. For the
AD7851 a conversion takes 19.5 CLKIN periods, 2 CLKIN
periods are needed for the acquisition time giving a full cycle
time of 3.59 µs (= 279 kHz, CLKIN = 6 MHz) for the K grade
and 3.08 µs (= 325 kHz, CLKIN = 7 MHz) for the A grade.
TYPICAL CONNECTION DIAGRAM
Figure 10 shows a typical connection diagram for the AD7851.
The DIN line is tied to DGND so that no data is written to the
part. The AGND and the DGND pins are connected together
at the device for good noise suppression. The CAL pin has a
0.01 µF capacitor to enable an automatic self-calibration on
power-up. The SCLK and SYNC are configured as outputs by
having SM1 and SM2 at DVDD. The conversion result is output
in a 16-bit word with 2 leading zeros followed by the MSB of
the 14-bit result. Note that after the AVDD and DVDD power-up,
the part will require 150 ms for the internal reference to settle
and for the automatic calibration on power-up to be completed.
For applications where power consumption is a major concern,
the SLEEP pin can be connected to DGND. See Power-Down
section for more detail on low power applications.
7MHz/6MHz
OSCILLATOR
ANALOG (5V)
SUPPLY
10µF
0V TO VREF
INPUT
0.01µF
AIN(+)
UNIPOLAR RANGE
333kHz/285kHz PULSE
GENERATOR
0.1µF
AVDD
CONVERSION
START INPUT
MASTER
CLOCK
INPUT
DVDD
AIN(–)
OSCILLOSCOPE
CLKIN
AMODE
SCLK
0.01µF
470nF
CREF1
CH1
SERIAL CLOCK OUTPUT
CONVST
0.01µF
47nF
CREF2
AD7851
FRAME SYNC OUTPUT
CH3
CH4
DOUT
SLEEP
DVDD
CH2
SYNC
SERIAL DATA OUTPUT
POLARITY
DIN
CAL
0.01µF
SM1
AGND
DGND
AUTO CAL ON
POWER-UP
REFIN/REFOUT
DVDD
SM2
SERIAL MODE
SELECTION BITS
DIN AT DGND
=> NO WRITING
TO DEVICE
2 LEADING ZEROS
FOR ADC DATA
INTERNAL
0.01µF REFERENCE
OPTIONAL
EXTERNAL
REFERENCE
ANALOG (5V)
SUPPLY
AD1584/REF198
10µF
0.1µF
Figure 10. Typical Circuit
–14–
REV. A
AD7851
The equivalent circuit of the analog input section is shown in
Figure 11. During the acquisition interval the switches are
both in the track position and the AIN(+) charges the 20 pF
capacitor through the 125 Ω resistance. On the rising edge of
CONVST switches SW1 and SW2 go into the hold position
retaining charge on the 20 pF capacitor as a sample of the signal
on AIN(+). The AIN(–) is connected to the 20 pF capacitor,
and this unbalances the voltage at node A at the input of the
comparator. The capacitor DAC adjusts during the remainder of
the conversion cycle to restore the voltage at node A to the correct value. This action transfers a charge, representing the analog
input signal, to the capacitor DAC which in turn forms a digital
representation of the analog input signal. The voltage on the
AIN(–) pin directly influences the charge transferred to the
capacitor DAC at the hold instant. If this voltage changes during
the conversion period, the DAC representation of the analog
input voltage will be altered. Therefore it is most important that
the voltage on the AIN(–) pin remains constant during the conversion period. Furthermore, it is recommended that the AIN(–)
pin is always connected to AGND or to a fixed dc voltage.
When no amplifier is used to drive the analog input the source
impedance should be limited to low values. The maximum
source impedance will depend on the amount of total harmonic
distortion (THD) that can be tolerated. The THD will increase
as the source impedance increases and performance will degrade.
Figure 12 shows a graph of the total harmonic distortion vs.
analog input signal frequency for different source impedances.
With the setup as in Figure 13, the THD is at the –90 dB level.
With a source impedance of 1 kΩ and no capacitor on the
AIN(+) pin, the THD increases with frequency.
–50
THD VS. FREQUENCY FOR DIFFERENT
SOURCE IMPEDANCES
–60
–70
THD – dB
ANALOG INPUT
RIN = 560Ω
–80
RIN = 10Ω, 10nF
AS IN FIGURE 13
–90
–100
125Ω
TRACK
AIN(+)
CAPACITOR
DAC
125Ω
AIN(–)
SW1
–110
1
10
20
20pF
HOLD
100
120
50
80
INPUT FREQUENCY – kHz
140
166
NODE A
Figure 12. THD vs. Analog Input Frequency
SW2
TRACK
HOLD
COMPARATOR
CREF2
Figure 11. Analog Input Equivalent Circuit
Acquisition Time
The track and hold amplifier enters its tracking mode on the falling edge of the BUSY signal. The time required for the track and
hold amplifier to acquire an input signal will depend on how
quickly the 20 pF input capacitance is charged. The acquisition
time is calculated using the formula:
tACQ = 9 × (RIN + 125 Ω) × 20 pF
where RIN is the source impedance of the input signal, and
125 Ω, 20 pF is the input R, C.
In a single supply application (5 V), the V+ and V– of the op
amp can be taken directly from the supplies to the AD7851
which eliminates the need for extra external power supplies.
When operating with rail-to-rail inputs and outputs at frequencies greater than 10 kHz, care must be taken in selecting the
particular op amp for the application. In particular, for single
supply applications the input amplifiers should be connected in
a gain of –1 arrangement to get the optimum performance. Figure 13 shows the arrangement for a single supply application
with a 10 Ω and 10 nF low-pass filter (cutoff frequency 320
kHz) on the AIN(+) pin. Note that the 10 nF is a capacitor with
good linearity to ensure good ac performance. Recommended
single supply op amp is the AD820.
+5V
DC/AC Applications
10kΩ
VIN
–VREF/2 TO +VREF/2
10kΩ
10kΩ
–15–
V+
10Ω
10kΩ
VREF/2
For ac applications, removing high frequency components from
the analog input signal is recommended by use of an RC lowpass filter on the AIN(+) pin, as shown in Figure 13. In applications where harmonic distortion and signal to noise ratio are
critical, the analog input should be driven from a low impedance
source. Large source impedances will significantly affect the ac
performance of the ADC. This may necessitate the use of an input buffer amplifier. The choice of the op amp will be a function
of the particular application.
REV. A
0.1µF
10µF
For dc applications high source impedances are acceptable, provided there is enough acquisition time between conversions to
charge the 20 pF capacitor. The acquisition time can be calculated from the above formula for different source impedances.
For example with RIN = 5 kΩ, the required acquisition time will
be 922 ns.
IC1
V–
AD820
10nF
(NPO)
Figure 13. Analog Input Buffering
TO AIN(+) OF
AD7851
AD7851
Input Ranges
4.096 V/16384 = 0.25 mV when VREF = 4.096 V. The ideal input/output transfer characteristic for the unipolar range is shown
in Figure 16.
The analog input range for the AD7851 is 0 V to VREF in both
the unipolar and bipolar ranges.
The only difference between the unipolar range and the bipolar
range is that in the bipolar range the AIN(–) has to be biased up
to +VREF/2 and the output coding is 2s complement (See Table
V and Figures 14 and 15). The unipolar or bipolar mode is selected by the AMODE pin (0 for the unipolar range and 1 for
the bipolar range).
OUTPUT
CODE
111...111
111...110
111...101
111...100
Table V. Analog Input Connections
Analog Input
Range
0 V to VREF1
± VREF/22
Input Connections Connection
AIN(+) AIN(–) Diagram
AMODE
VIN
VIN
AGND
VREF/2
Figure 8
Figure 9
000...011
1LSB =
FS
16384
000...010
DGND
DVDD
000...001
000...000
0V 1LSB
NOTES
1
Output code format is straight binary.
2
Range is ± VREF/2 biased about V REF/2. Output code format is 2s complement.
+FS –1LSB
VIN = (AIN(+) – AIN(–)), INPUT VOLTAGE
Note that the AIN(–) pin on the AD7851 can be biased up
above AGND in the unipolar mode also, if required. The advantage of biasing the lower end of the analog input range away
from AGND is that the user does not have to have the analog
input swing all the way down to AGND. This has the advantage
in true single supply applications that the input amplifier does
not have to swing all the way down to AGND. The upper end of
the analog input range is shifted up by the same amount. Care
must be taken so that the bias applied does not shift the upper
end of the analog input above the AVDD supply. In the case
where the reference is the supply, AVDD, the AIN(–) must be
tied to AGND in unipolar mode.
Figure 16. AD7851 Unipolar Transfer Characteristic
Figure 15 shows the AD7851’s ± VREF/2 bipolar analog input
configuration (where AIN(+) cannot go below 0 V so for the full
bipolar range then the AIN(–) pin should be biased to +VREF/2).
Once again the designed code transitions occur midway between
successive integer LSB values. The output coding is 2s complement with 1 LSB = 16384 = 4.096 V/16384 = 0.25 mV. The
ideal input/output transfer characteristic is shown in
Figure 17.
OUTPUT
CODE
011...111
011...110
VIN = 0 TO VREF
AIN(+)
TRACK AND HOLD
AMPLIFIER
DOUT
AIN(–)
UNIPOLAR
ANALOG
INPUT RANGE
SELECTED
STRAIGHT
BINARY
FORMAT
(VREF/2) –1 LSB
000...001
000...000
AD7851
0V
+ FS – 1 LSB
111...111
AMODE
(VREF/2) +1 LSB
FS = VREFV
1LSB = FS
16384
100...010
Figure 14. 0 V to VREF Unipolar Input Configuration
100...001
100...000
Transfer Functions
For the unipolar range the designed code transitions occur midway between successive integer LSB values (i.e., 1/2 LSB,
3/2 LSBs, 5/2 LSBs . . . FS –3/2 LSBs). The output coding is
straight binary for the unipolar range with 1 LSB = FS/16384 =
AIN(+)
VIN = 0 TO VREF
TRACK AND HOLD
AMPLIFIER
DOUT
AIN(–)
VREF/2
DVDD
UNIPOLAR
ANALOG
INPUT RANGE
SELECTED
VREF/2
VIN = (AIN(+) – AIN(–)), INPUT VOLTAGE
Figure 17. AD7851 Bipolar Transfer Characteristic
2S
COMPLEMENT
FORMAT
AD7851
AMODE
Figure 15. ±VREF/2 about VREF/2 Bipolar Input Configuration
–16–
REV. A
AD7851
REFERENCE SECTION
AD7851 PERFORMANCE CURVES
For specified performance, it is recommended that when using
an external reference this reference should be between 4 V and
the analog supply AVDD. The connections for the relevant reference pins are shown in the typical connection diagrams. If the
internal reference is being used, the REFIN/REFOUT pin should
have a 100 nF capacitor connected to AGND very close to the
REFIN/REFOUT pin. These connections are shown in Figure 18.
Figure 20 shows a typical FFT plot for the AD7851 at 333 kHz
sample rate and 10 kHz input frequency.
0
If the internal reference is required for use external to the ADC,
it should be buffered at the REFIN/REFOUT pin and a 100 nF
connected from this pin to AGND. The typical noise performance
for the internal reference, with 5 V supplies is 150 nV/√Hz @
1 kHz and dc noise is 100 µV p-p.
ANALOG
SUPPLY
+5V
AVDD = DVDD = 5V
FSAMPLE = 333 kHz
FIN = 10kHz
SNR = 79.5dB
THD = –95.2
–20
SNR – dB
–40
–60
–80
10Ω
–100
0.01µF
10µF
0.1µF
–120
AVDD
DVDD
0
20
40
60
FREQUENCY – kHz
CREF1
0.01µF
470nF
Figure 20. FFT Plot
Figure 21 shows the SNR versus Frequency for 5 V supply and
a 4.096 external references (5 V reference is typically 1 dB better performance).
AD7851
CREF2
0.01µF
100
80
47nF
REFIN/REFOUT
0.1µF
79
Figure 18. Relevant Connections When Using Internal
Reference
ANALOG
SUPPLY
+5V
10Ω
0.1µF
0.01µF
10µF
AVDD
470nF
0.01µF
47nF
10Ω
CREF2
AD7851
75
0
10
20
80
100
50
120
INPUT FREQUENCY – kHz
140
166
Figure 21. SNR vs. Frequency
Figure 22 shows the Power Supply Rejection Ratio versus
Frequency for the part. The Power Supply Rejection Ratio is
defined as the ratio of the power in ADC output at frequency f
to the power of a full-scale sine wave.
PSRR (dB) = 10 log (Pf/Pfs)
Pf = Power at frequency f in ADC output, Pfs = power of a fullscale sine wave. Here a 100 mV peak-to-peak sine wave is
coupled onto the AVDD supply while the digital supply is left
unaltered.
REFIN/REFOUT
0.1µF
Figure 19. Relevant Connections When Using AVDD as the
Reference
REV. A
77
76
DVDD
CREF1
0.01µF
S(N+D) RATIO – dB
The other option is that the REFIN/REFOUT pin be overdriven
by connecting it to an external reference. This is possible due to
the series resistance from the REFIN/REFOUT pin to the internal
reference. This external reference can have a range that includes
AVDD. When using AVDD as the reference source, the 100 nF
capacitor from the REFIN/REFOUT pin to AGND should be as
close as possible to the REFIN/REFOUT pin, and also the CREF1
pin should be connected to AVDD to keep this pin at the same
level as the reference. The connections for this arrangement are
shown in Figure 19. When using AVDD it may be necessary to
add a resistor in series with the AVDD supply. This will have the
effect of filtering the noise associated with the AVDD supply.
78
–17–
AD7851
–72
–74
–76
a long power-down period when using the on-chip reference
(See Power-Up Times—Using On-Chip Reference).
AVDD = DVDD = 5.0V
100mV pk-pk SINEWAVE ON AVDD
REFIN = 4.098 EXT REFERENCE
When using the SLEEP pin, the power management bits
PMGT1 and PMGT0 should be set to zero (default status on
power-up). Bringing the SLEEP pin logic high ensures normal
operation, and the part does not power down at any stage. This
may be necessary if the part is being used at high throughput
rates when it is not possible to power down between conversions. If the user wishes to power down between conversions at
lower throughput rates (i.e., <100 kSPS for the AD7851) to
achieve better power performances, then the SLEEP pin should
be tied logic low.
PSRR – dB
–78
–80
–82
–84
–86
–88
–90
0.91
13.4
25.7
38.3
50.3
63.5
74.8
INPUT FREQUENCY – kHz
87.4
If the power-down options are to be selected in software only,
then the SLEEP pin should be tied logic high. By setting the
power management bits PMGT1 and PMGT0 as shown in
Table VI, a Full Power-Down, Full Power-Up, Full PowerDown Between Conversions, and a Partial Power-Down
Between Conversions can be selected.
100
Figure 22. PSRR vs. Frequency
POWER-DOWN OPTIONS
The AD7851 provides flexible power management to allow the
user to achieve the best power performance for a given throughput rate. The power management options are selected by programming the power management bits, PMGT1 and PMGT0,
in the control register and by use of the SLEEP pin. Table VI
summarizes the power-down options that are available and how
they can be selected by using either software, hardware or a
combination of both. The AD7851 can be fully or partially powered down. When fully powered down, all the on-chip circuitry
is powered down and IDD is 1 µA typ. If a partial power-down is
selected, then all the on-chip circuitry except the reference is
powered down and IDD is 400 µA typ. The choice of full or partial power-down does not give any significant improvement in
throughput with a power-down between conversions. This is discussed in the next section—Power-Up Times. But a partial
power-down does allow the on-chip reference to be used externally even though the rest of the AD7851 circuitry is powered
down. It also allows the AD7851 to be powered up faster after
ANALOG
(+5V)
SUPPLY
A combination of hardware and software selection can also be
used to achieve the desired effect.
Table VI. Power Management Options
PMGT1
Bit
PMGT0
Bit
SLEEP
Pin
0
0
0
Full Power-Down Between
Conversions (HW/SW)
0
0
0
1
1
X
Full Power-Up (HW/SW)
Full Power-Down Between
Conversions (SW)
1
1
0
1
X
X
Full Power-Down (SW)
Partial Power-Down Between
Conversions (SW)
NOTE
SW = Software selection, HW = Hardware selection.
CURRENT, I = 12mA TYP
6/7MHz
OSCILLATOR
0.01µF
10µF
0V TO VREF
INPUT
AIN(+)
285/ 333kHz PULSE
GENERATOR
0.1µF
AVDD
MASTER
CLOCK
INPUT
DVDD
AIN(–)
UNIPOLAR RANGE
Comment
CLKIN
AMODE
SCLK
0.01µF
470nF
CONVST
CREF2
47nF
SERIAL CLOCK OUTPUT
CREF1
AD7851
CONVERSION
START INPUT
SYNC
LOW POWER
µC/µP
0.01µF
DOUT
SLEEP
AUTO POWERDOWN AFTER
CONVERSION
DVDD
SERIAL DATA OUTPUT
DIN
POLARITY
DIN AT DGND
=> NO WRITING
TO DEVICE
CAL
0.01µF
AUTO CAL ON
POWER-UP
OPTIONAL
EXTERNAL
REFERENCE
AGND
DGND
SM1
REFIN/REFOUT
SM2
SERIAL MODE
SELECTION BITS
INTERNAL
0.01µF REFERENCE
3-WIRE MODE
SELECTED
REF198
Figure 23. Typical Low Power Circuit
–18–
REV. A
AD7851
POWER-UP TIMES
Using An External Reference
When the AD7851 are powered up, the parts are powered up
from one of two conditions. First, when the power supplies are
initially powered up and, secondly, when the parts are powered
up from either a hardware or software power-down (see last
section).
When AVDD and DVDD are powered up, the AD7851 enters a
mode whereby the CONVST signal initiates a timeout followed
by a self-calibration. The total time taken for this time-out and
calibration is approximately 35 ms—see Calibration on Power-Up
in the calibration section of this data sheet. During power-up
the functionality of the SLEEP pin is disabled, i.e., the part will
not power down until the end of the calibration if SLEEP is tied
logic low. The power-up calibration mode can be disabled if the
user writes to the control register before a CONVST signal is
applied. If the time out and self-calibration are disabled, then
the user must take into account the time required by the
AD7851 to power up before a self-calibration is carried out.
This power-up time is the time taken for the AD7851 to power
up when power is first applied (300 µs typ) or the time it takes
the external reference to settle to the 14-bit level—whichever is
the longer.
The AD7851 powers up from a full hardware or software
power-down in 5 µs typ. This limits the throughput which the
part is capable of to 120 kSPS for the K Grade and 126 kSPS
for the A Grade when powering down between conversions. Figure 24 shows how power-down between conversions is implemented using the CONVST pin. The user first selects the
power-down between conversions option by using the SLEEP
pin and the power management bits, PMGT1 and PMGT0, in
the control register. See last section. In this mode the AD7851
automatically enters a full power-down at the end of a conversion, i.e., when BUSY goes low. The falling edge of the next
CONVST pulse causes the part to power up. Assuming the external reference is left powered up, the AD7851 should be ready
for normal operation 5 µs after this falling edge. The rising edge
of CONVST initiates a conversion so the CONVST pulse
should be at least 5 µs wide. The part automatically powers
down on completion of the conversion. Where the software convert start is used, the part may be powered up in software before
a conversion is initiated.
START CONVERSION ON RISING EDGE
POWER-UP ON FALLING EDGE
5µs
3.25µs
CONVST
tCONVERT
BUSY
POWER-UP
NORMAL
FULL
TIME
OPERATION POWER-DOWN
POWER-UP
TIME
Figure 24. Using the CONVST Pin to Power Up the AD7851
for a Conversion
Using The Internal (On-Chip) Reference
When using the on-chip reference and powering up when AVDD
and DVDD are first connected, it is recommended that the
power-up calibration mode be disabled as explained above.
When using the on-chip reference, the power-up time is effectively the time it takes to charge up the external capacitor on the
REFIN /REFOUT pin. This time is given by the equation:
tUP = 9 × R × C
where R ≈ 150K and C = external capacitor.
The recommended value of the external capacitor is 100 nF;
this gives a power-up time of approximately 135 ms before a
calibration is initiated and normal operation should commence.
When CREF is fully charged, the power-up time from a hardware
or software power-down reduces to 5 µs. This is because an
internal switch opens to provide a high impedance discharge
path for the reference capacitor during power-down—see Figure
25. An added advantage of the low charge leakage from the
reference capacitor during power-down is that even though the
reference is being powered down between conversions, the reference capacitor holds the reference voltage to within 0.5 LSBs
with throughput rates of 100 samples/second and over with a
full power-down between conversions. A high input impedance
op amp like the AD707 should be used to buffer this reference
capacitor if it is being used externally. Note, if the AD7851 is
left in its powered-down state for more than 100 ms, the charge
on CREF will start to leak away and the power-up time will
increase. If this long power-up time is a problem, the user can
use a partial power-down for the last conversion so the reference
remains powered up.
SWITCH OPENS
DURING POWER-DOWN
REFIN/REFOUT
ON-CHIP
REFERENCE
EXTERNAL
CAPACITOR
BUF
TO OTHER
CIRCUITRY
Figure 25. On-Chip Reference During Power-Down
POWER VS. THROUGHPUT RATE
The main advantage of a full power-down after a conversion is
that it significantly reduces the power consumption of the part
at lower throughput rates. When using this mode of operation,
the AD7851 is only powered up for the duration of the conversion. If the power-up time of the AD7851 is taken to be 5 µs
and it is assumed that the current during power up is 12 mA
typ, then power consumption as a function of throughput can
easily be calculated. The AD7851 has a conversion time of
3.25 µs with a 6 MHz external clock. This means the AD7851
consumes 12 mA typ for 8.25 µs in every conversion cycle if the
parts are powered down at the end of a conversion. The graph,
Figure 26, shows the power consumption of the AD7851 as a
function of throughput. Table VII lists the power consumption for various throughput rates.
As in the case of an external reference, the AD7851 can power
up from one of two conditions, power-up after the supplies are
connected or power-up from hardware/software power-down.
REV. A
AD7851
–19–
AD7851
Table VIII. Calibration Times (AD7851 with 6 MHz CLKIN)
Table VII. Power Consumption vs. Throughput
Throughput Rate
Power
AD7851
1 kSPS
2 kSPS
9 mW
18 mW
100
POWER – mW
Time
Full
Gain + Offset
Offset
Gain
41.7 ms
9.26 ms
4.63 ms
4.63 ms
Automatic Calibration on Power-On
10
1
0.1
0.01
Type of Self- or System Calibration
0
200
400
600 800 1000 1200 1400 1600 1800 2000
THROUGHPUT RATE – Hz
Figure 26. Power vs. Throughput AD7851
NOTE
When setting the power-down mode by writing to the part, it is
recommended to be operating in an interface mode other than
Interface Modes 4, and 5. This way the user has more control to
initiate power-down, and power-up commands.
CALIBRATION SECTION
Calibration Overview
The automatic calibration that is performed on power-up ensures that the calibration options covered in this section will not
be required in a significant amount of applications. The user
will not have to initiate a calibration unless the operating conditions change (CLKIN frequency, analog input mode, reference
voltage, temperature, and supply voltages). The AD7851 have a
number of calibration features that may be required in some applications and there are a number of advantages in performing
these different types of calibration. First, the internal errors in
the ADC can be reduced significantly to give superior dc performance; and second, system offset and gain errors can be removed.
This allows the user to remove reference errors (whether it be
internal or external reference) and to make use of the full dynamic range of the AD7851 by adjusting the analog input range
of the part for a specific system.
There are two main calibration modes on the AD7851, self-calibration and system calibration. There are various options in
both self-calibration and system calibration as outlined previously in Table III. All the calibration functions can be initiated
by pulsing the CAL pin or by writing to the control register and
setting the STCAL bit to 1. The timing diagrams that follow involve using the CAL pin.
The CAL pin has a 0.15 µA pull-up current source connected to
it internally to allow for an automatic full self-calibration on
power-on. A full self-calibration will be initiated on power-on if
a 10 nF capacitor is connected from the CAL pin to AGND.
The internal current source connected to the CAL pin charges
up the external capacitor and the time required to charge the external capacitor will be 100 ms approximately. This time is large
enough to ensure that the internal reference is settled before the
calibration is performed. However, if an external reference is being used, this reference must have stabilized before the automatic calibration is initiated (if larger time than 100 ms is
required then a larger capacitor on the CAL pin should be
used). After this 100 ms has elapsed, the calibration will be performed which will take 42 ms/36 ms (6 MHz /7 MHz CLKIN).
Therefore 142 ms/136 ms should be allowed before operating
the part. After calibration, the part is accurate to the 14-bit level
and the specifications quoted on the data sheet apply. There will
be no need to perform another calibration unless the operating
conditions change or unless a system calibration is required.
Self-Calibration Description
There are a four different calibration options within the selfcalibration mode. There is a full self-calibration where the
DAC, internal offset, and internal gain errors are calibrated out.
Then, there is the (Gain + Offset) self-calibration which calibrates out the internal gain error and then the internal offset errors. The internal DAC is not calibrated here. Finally, there are
the self-offset and self-gain calibrations which calibrate out the
internal offset errors and the internal gain errors respectively.
The internal capacitor DAC is calibrated by trimming each of
the capacitors in the DAC. It is the ratio of these capacitors to
each other that is critical, and so the calibration algorithm ensures that this ratio is at a specific value by the end of the calibration routine. For the offset and gain there are two separate
capacitors, one of which is trimmed when an offset or gain calibration is performed. Again it is the ratio of these capacitors to
the capacitors in the DAC that is critical and the calibration algorithm ensures that this ratio is at a specified value for both the
offset and gain calibrations.
In bipolar mode the midscale error is adjusted for an offset
calibration and the positive full-scale error is adjusted for the
gain calibration; in unipolar mode the zero-scale error is adjusted for an offset calibration and the positive full-scale error is
adjusted for a gain calibration.
The duration of each of the different types of calibrations is
given in Table VIII for the AD7851 with a 6 MHz/7 MHz master clock. These calibration times are master clock dependent.
–20–
REV. A
AD7851
Self-Calibration Timing
The diagram of Figure 27 shows the timing for a full selfcalibration. Here the BUSY line stays high for the full length of
the self-calibration. A self-calibration is initiated by bringing the
CAL pin low (which initiates an internal reset) and then high
again or by writing to the control register and setting the
STCAL bit to 1 (note that if the part is in a power-down mode, the
CAL pulse width must take account of the power-up time). The
BUSY line is triggered high from the rising edge of CAL (or the
end of the write to the control register if calibration is initiated
in software), and BUSY will go low when the full self-calibration
is complete after a time tCAL as shown in Figure 27.
MAX SYSTEM FULL SCALE
IS ±2.5% FROM V REF
VREF + SYS OFFSET
VREF – 1LSB
VREF – 1LSB
SYSTEM OFFSET
ANALOG
INPUT
RANGE
ANALOG
INPUT
RANGE
CALIBRATION
SYS OFFSET
AGND
SYS OFFSET
AGND
MAX SYSTEM OFFSET
IS ±5% OF V REF
MAX SYSTEM OFFSET
IS ±5% OF V REF
Figure 28. System Offset Calibration
t1 = 100ns MIN,
t15 = 2.5 tCLKIN MAX,
tCAL = 250026 tCLKIN
t1
CAL (I/P)
t15
Figure 29 shows a system gain calibration (assuming a system
full scale greater than the reference voltage) where the analog
input range has been increased after the system gain calibration
is completed. A system full-scale voltage less than the reference
voltage may also be accounted for a by a system gain calibration.
BUSY (O/P)
MAX SYSTEM FULL SCALE
IS ±2.5% FROM V REF
tCAL
Figure 27. Timing Diagram for Full Self-Calibration
For the self-(gain + offset), self-offset and self-gain calibrations,
the BUSY line will be triggered high by the rising edge of the
CAL signal (or the end of the write to the control register if calibration is initiated in software) and will stay high for the full duration of the self-calibration. The length of time that the BUSY
is high for will depend on the type of self-calibration that is initiated. Typical figures are given in Table IX. The timing diagrams for the other self-calibration options will be similar to that
outlined in Figure 27.
System Calibration Description
System calibration allows the user to take out system errors
external to the AD7851 as well as calibrate the errors of the
AD7851 itself. The maximum calibration range for the system
offset errors is ± 5% of VREF and for the system gain errors is
± 2.5% of VREF. This means that the maximum allowable system
offset voltage applied between the AIN(+) and AIN(–) pins for
the calibration to adjust out this error is ± 0.05 × VREF (i.e., the
AIN(+) can be 0.05 × VREF above AIN(–) or 0.05 × VREF below
AIN(–)). For the system gain error the maximum allowable
system full-scale voltage, in unipolar mode, that can be applied
between AIN(+) and AIN(–) for the calibration to adjust out
this error is VREF ± 0.025 × VREF (i.e., the AIN(+) can be VREF +
0.025 × VREF above AIN(–) or VREF – 0.025 × VREF above
AIN(–)). If the system offset or system gain errors are outside
the ranges mentioned, the system calibration algorithm will
reduce the errors as much as the trim range allows.
Figures 28 through 30 illustrate why a specific type of system
calibration might be used. Figure 29 shows a system offset calibration (assuming a positive offset) where the analog input
range has been shifted upwards by the system offset after the
system offset calibration is completed. A negative offset may
also be accounted for by a system offset calibration.
REV. A
MAX SYSTEM FULL SCALE
IS ±2.5% FROM V REF
SYS FULL S.
SYS FULL S.
VREF – 1LSB
VREF – 1LSB
SYSTEM GAIN
ANALOG
INPUT
RANGE
ANALOG
INPUT
RANGE
CALIBRATION
AGND
AGND
Figure 29. System Gain Calibration
Finally in Figure 30 both the system offset and gain are accounted
for by the system offset followed by a system gain calibration.
First the analog input range is shifted upwards by the positive
system offset and then the analog input range is adjusted at the
top end to account for the system full scale.
MAX SYSTEM FULL SCALE
IS ±2.5% FROM V REF
MAX SYSTEM FULL SCALE
IS ±2.5% FROM V REF
VREF + SYS OFFSET
SYS F.S.
SYS F.S.
VREF – 1LSB
VREF – 1LSB
ANALOG
INPUT
RANGE
SYS OFFSET
AGND
MAX SYSTEM OFFSET
IS ±5% OF V REF
SYSTEM OFFSET
CALIBRATION
FOLLOWED BY
ANALOG
INPUT
RANGE
SYSTEM GAIN
CALIBRATION
SYS OFFSET
AGND
MAX SYSTEM OFFSET
IS ±5% OF V REF
Figure 30. System (Gain + Offset) Calibration
–21–
AD7851
System Gain and Offset Interaction
The inherent architecture of the AD7851 leads to an interaction
between the system offset and gain errors when a system calibration is performed. Therefore it is recommended to perform the
cycle of a system offset calibration followed by a system gain
calibration twice. Separate system offset and system gain calibrations reduce the offset and gain errors to at least the 14-bit
level. By performing a system offset calibration first and a system gain calibration second, priority is given to reducing the
gain error to zero before reducing the offset error to zero. If the
system errors are small, a system offset calibration would be performed, followed by a system gain calibration. If the systems errors are large (close to the specified limits of the calibration
range), this cycle would be repeated twice to ensure that the offset and gain errors were reduced to at least the 14-bit level. The
advantage of doing separate system offset and system gain calibrations is that the user has more control over when the analog
inputs need to be at the required levels, and the CONVST signal does not have to be used.
Alternatively, a system (gain + offset) calibration can be performed. It is recommended to perform three system (gain + offset) calibrations to reduce the offset and gain errors to the 14-bit
level. For the system (gain + offset) calibration priority is given
to reducing the offset error to zero before reducing the gain error to zero. Thus if the system errors are small then two system
(gain + offset) calibrations will be sufficient. If the system errors
are large (close to the specified limits of the calibration range),
three system (gain + offset) calibrations may be required to reduced the offset and gain errors to at least the 14-bit level.
There will never be any need to perform more than three system
(offset + gain) calibrations.
In Bipolar Mode the midscale error is adjusted for an offset calibration and the positive full-scale error is adjusted for the gain
calibration; in Unipolar Mode the zero-scale error is adjusted
for an offset calibration and the positive full-scale error is adjusted for a gain calibration.
System Calibration Timing
The calibration timing diagram in Figure 31 is for a full system
calibration where the falling edge of CAL initiates an internal
reset before starting a calibration (note that if the part is in powerdown mode the CAL pulse width must take account of the power-up
time). If a full system calibration is to be performed in software,
it is easier to perform separate gain and offset calibrations so
that the CONVST bit in the control register does not have to be
programmed in the middle of the system calibration sequence.
The rising edge of CAL starts calibration of the internal DAC
and causes the BUSY line to go high. If the control register is
set for a full system calibration, the CONVST must be used
also. The full-scale system voltage should be applied to the analog input pins from the start of calibration. The BUSY line will
go low once the DAC and system gain calibration are complete.
Next the system offset voltage is applied to the AIN pin for a
minimum setup time (tSETUP) of 100 ns before the rising edge of
the CONVST and remain until the BUSY signal goes low. The
rising edge of the CONVST starts the system offset calibration
section of the full system calibration and also causes the BUSY
signal to go high. The BUSY signal will go low after a time tCAL2
when the calibration sequence is complete.
The timing for a system (gain + offset) calibration is very similar
to that of Figure 31, the only difference being that the time
tCAL1 will be replaced by a shorter time of the order of tCAL2 as
the internal DAC will not be calibrated. The BUSY signal will
signify when the gain calibration is finished and when the part is
ready for the offset calibration.
t1 = 100ns MIN, t14 = 50 MAX,
t15 = 4 tCLKIN MAX, tCAL1 = 222228 tCLKIN MAX,
tCAL2 = 27798 tCLKIN
t1
CAL (I/P)
t15
BUSY (O/P)
tCAL2
tCAL1
t16
CONVST (I/P)
tSETUP
AIN (I/P)
VOFFSET
VSYSTEM FULL SCALE
Figure 31. Timing Diagram for Full System Calibration
The timing diagram for a system offset or system gain calibration is shown in Figure 32. Here again the CAL is pulsed and
the rising edge of the CAL initiates the calibration sequence (or
the calibration can be initiated in software by writing to the control register). The rising edge of the CAL causes the BUSY line
to go high and it will stay high until the calibration sequence is
finished. The analog input should be set at the correct level for
a minimum setup time (tSETUP) of 100 ns before the rising edge
of CAL and stay at the correct level until the BUSY signal goes
low.
t1
CAL (I/P)
t15
BUSY (O/P)
tSETUP
AIN (I/P)
tCAL2
VSYSTEM FULL SCALE OR VSYSTEM OFFSET
Figure 32. Timing Diagram for System Gain or System
Offset Calibration
–22–
REV. A
AD7851
SERIAL INTERFACE SUMMARY
Table IX details the five interface modes and the serial clock
edges from which the data is clocked out by the AD7851
(DOUT Edge) and that the data is latched in on (DIN Edge).
The logic level of the POLARITY pin is shown and it is clear
that this reverses the edges.
In Interface Modes 4 and 5 the SYNC always clocks out the
first data bit and SCLK will clock out the subsequent bits.
In Interface Modes 1, 2, and 3 the SYNC is gated with the
SCLK and the POLARITY pin. Thus the SYNC may clock out
the MSB of data. Subsequent bits will be clocked out by the serial clock, SCLK. The conditions for the SYNC clocking out
the MSB of data is as follows:
and SM2. Interface Mode 1 may only be set by programming
the control register (see section on control register). External
SCLK and SYNC signals (SYNC may be hardwired low) are
required for Interfaces Modes 1, 2, and 3. In Interface Modes 4
and 5 the AD7851 generates the SCLK and SYNC.
Some of the more popular µProcessors, µControllers, and the
DSP machines that the AD7851 will interface to directly are
mentioned here. This does not cover all µCs, µPs and DSPs.
The interface mode of the AD7851 that is mentioned here for a
specific µC, µP, or DSP is only a guide and in most cases another interface mode may work just as well.
A more detailed timing description on each of the interface
modes follows.
With the POLARITY pin high the falling edge of SYNC will clock
out the MSB if the serial clock is low when the SYNC goes low.
With the POLARITY pin low the falling edge of SYNC will clock
out the MSB if the serial clock is high when the SYNC goes low.
Table IX. SCLK Active Edge for Different Interface Modes
Interface
Mode
POLARITY
Pin
DOUT
Edge
DIN
Edge
1, 2, 3
0
1
SCLK ↑
SCLK ↓
SCLK ↓
SCLK ↑
4, 5
0
1
SCLK ↓
SCLK ↑
SCLK ↑
SCLK ↓
Table X. Interface Mode Description
SM1
Pin
SM2
Pin
mProcessor/
mController
Interface
Mode
0
0
8XC51
8XL51
PIC17C42
1 (2-Wire)
(DIN is an Input/
Output pin)
0
0
68HC11
68L11
2 (3-Wire, SPI/QSPI)
(Default Mode)
0
1
68HC16
PIC16C64
ADSP-21xx
DSP56000
DSP56001
DSP56002
DSP56L002
TMS320C30
3 (QSPI)
(External Serial
Clock, SCLK, and
External Frame Sync,
SYNC, are required)
1
0
68HC16
4 (DSP is Slave)
(AD7851
generates a
noncontinuous
(16 clocks) Serial
Clock, SCLK, and the
Frame Sync, SYNC)
1
1
ADSP-21xx
DSP56000
DSP56001
DSP56002
DSP56L002
TMS320C20
TMS320C25
TMS320C30
TMS320C5X
TMS320LC5X
5 (DSP is Slave)
(AD7851
generates a
continuous Serial
Clock, SCLK, and the
Frame Sync, SYNC)
Resetting the Serial Interface
When writing to the part via the DIN line there is the possibility
of writing data into the incorrect registers, such as the test register for instance, or writing the incorrect data and corrupting the
serial interface. The SYNC pin acts as a reset. Bringing the
SYNC pin high resets the internal shift register. The first data
bit after the next SYNC falling edge will now be the first bit of a
new 16-bit transfer. It is also possible that the test register contents were altered when the interface was lost. Therefore, once
the serial interface is reset, it may be necessary to write the 16bit word 0100 0000 0000 0010 to restore the test register to its
default value. Now the part and serial interface are completely
reset. It is always useful to retain the ability to program the
SYNC line from a port of the µController/DSP to have the ability to reset the serial interface.
Table X summarizes the interface modes provided by the
AD7851. It also outlines the various µP/µC to which the particular interface is suited.
The interface mode is determined by the serial mode selection
pins SM1 and SM2. Interface mode 2 is the default mode. Note
that Interface Mode 1 and 2 have the same combination of SM1
REV. A
–23–
AD7851
DETAILED TIMING SECTION
MODE 1 (2-Wire 8051 Interface)
The read and writing takes place on the DIN line and the conversion is initiated by pulsing the CONVST pin (note that in
every write cycle the 2/3 MODE bit must be set to 1). The conversion may be started by setting the CONVST bit in the control register to 1 instead of using the CONVST line.
Below in Figure 33 and in Figure 34 are the timing diagrams for
Interface Mode 1 in Table XI where we are in the 2-wire interface mode. Here the DIN pin is used for both input and output
as shown. The SYNC input is level triggered active low and can
be pulsed (Figure 33) or can be constantly low (Figure 34).
In Figure 33 the part samples the input data on the rising edge
of SCLK. After the 16th rising edge of SCLK the DIN is configured as an output. When the SYNC is taken high the DIN is
3-stated. Taking SYNC low disables the 3-state on the DIN pin
and the first SCLK falling edge clocks out the first data bit.
Once the 16 clocks have been provided the DIN pin will automatically revert back to an input after a time t14. Note that a
continuous SCLK shown by the dotted waveform in Figure 33
can be used provided that the SYNC is low for only 16 clock
pulses in each of the read and write cycles. The POLARITY pin
may be used to change the SCLK edge which the data is
sampled on and clocked out on.
In Figure 34 the SYNC line is tied low permanently and this results in a different timing arrangement. With SYNC tied low
permanently the DIN pin will never be 3-stated. The 16th rising
edge of SCLK configures the DIN pin as an input or an output
as shown in the diagram. Here no more than 16 SCLK pulses
must occur for each of the read and write operations.
If reading from and writing to the calibration registers in this interface mode, all the selected calibration registers must be read
from or written to. The read and write operations cannot be
aborted. When reading from the calibration registers, the DIN
pin will remain as an output for the full duration of all the calibration register read operations. When writing to the calibration
registers, the DIN pin will remain as an input for the full duration of all the calibration register write operations.
t3 = –0.4 tSCLK MIN (NONCONTINUOUS SCLK) –/+0.4 tSCLK MIN/MAX (CONTINUOUS SCLK),
t6 = 45 MAX, t7 = 30ns MIN, t8 = 20 MIN
POLARITY PIN
LOGIC HIGH
SYNC (I/P)
t3
1
SCLK (I/P)
t7
DIN (I/O)
16
DB15
1
16
t5A
t12
t8
t11
t3
t11
DB0
t14
t6
t6
DB15
DB0
3-STATE
DATA READ
DATA WRITE
DIN BECOMES AN OUTPUT
DIN BECOMES AN INPUT
Figure 33. Timing Diagram for Read/Write Operation with DIN as an Input/Output (i.e., Interface Mode 1, SM1 = SM2 = 0)
t6 = 45 MAX, t7 = 30ns MIN, t8 = 20 MIN,
t13 = 90 MAX, t14 = 50ns MAX
POLARITY PIN
LOGIC HIGH
1
SCLK (I/P)
t7
DIN (I/O)
16
t13
t8
DB15
6
1
DB0
t6
16
t6
DB15
t14
DB0
DATA READ
DATA WRITE
DIN BECOMES AN INPUT
Figure 34. Timing Diagram for Read/Write Operation with DIN as an Input/Output and SYNC Input Tied Low
(i.e., Interface Mode 1, SM1 = SM2 = 0)
–24–
REV. A
AD7851
MODE 2 (3-Wire SPI/QSPI Interface Mode)
This is the DEFAULT INTERFACE MODE.
MODE 3 (QSPI Interface Mode)
Figure 36 shows the timing diagram for Interface Mode 3. In
this mode the DSP is the master and the part is the slave. Here
the SYNC input is edge triggered from high to low, and the 16
clock pulses are counted from this edge. Since the clock pulses
are counted internally then the SYNC signal does not have to go
high after the 16th SCLK rising edge as shown by the dotted
SYNC line in Figure 36. Thus a frame sync that gives a high
pulse, of one SCLK cycle minimum duration, at the beginning
of the read/write operation may be used. The rising edge of
SYNC enables the 3-state on the DOUT pin. The falling edge
of SYNC disables the 3-state on the DOUT pin, and data is
clocked out on the falling edge of SCLK. Once SYNC goes
high, the 3-state on the DOUT pin is enabled. The data input is
sampled on the rising edge of SCLK and thus has to be valid a
time t7 before this rising edge. The POLARITY pin may be
used to change the SCLK edge which the data is sampled on
and clocked out on. If resetting the interface is required, the
SYNC must be taken high and then low.
In Figure 35 below we have the timing diagram for Interface
Mode 2 which is the SPI/QSPI interface mode. Here the SYNC
input is active low and may be pulsed or tied permanently low.
If SYNC is permanently low 16 clock pulses must be applied to
the SCLK pin for the part to operate correctly, and with a
pulsed SYNC input a continuous SCLK may be applied provided SYNC is low for only 16 SCLK cycles. In Figure 35 the
SYNC going low disables the three-state on the DOUT pin.
The first falling edge of the SCLK after the SYNC going low
clocks out the first leading zero on the DOUT pin. The DOUT
pin is 3-stated again a time t12 after the SYNC goes high. With
the DIN pin the data input has to be set up a time t7 before the
SCLK rising edge as the part samples the input data on the
SCLK rising edge in this case. The POLARITY pin may be
used to change the SCLK edge which the data is sampled on
and clocked out on. If resetting the interface is required, the
SYNC must be taken high and then low.
t3 = –0.4 tCLKIN MIN (NONCONTINUOUS SCLK) –/+0.4 tSCLK MIN/MAX (CONTINUOUS SCLK),
t6 = 45 MAX, t7 = 30ns MIN, t8 = 20 MIN, t11 = 30 MIN (NONCONTINUOUS SCLK) ,
30/0.4 tSCLK = ns MIN/MAX (CONTINUOUS SCLK)
POLARITY PIN
LOGIC HIGH
SYNC (I/P)
t9
t3
1
SCLK (I/P)
t5
DOUT (O/P)
2
3
DB15
t7
DIN (I/P)
4
5
t10
t6
3-STATE
t11
6
t6
DB14
DB13
DB12
t12
DB11
DB10
DB0
3-STATE
t8
t8
DB15
16
DB14
DB13
DB12
DB11
DB10
DB0
Figure 35. SPI/QSPI Mode 2 Timing Diagram for Read/Write Operation with DIN Input, DOUT Output and SYNC Input
(SM1 = SM2 = 0)
t3 = –0.4 tCLKIN MIN (NONCONTINUOUS SCLK) –/+0.4 tSCLK MIN/MAX (CONTINUOUS SCLK),
t6 = 45 MAX, t7 = 30ns MIN, t8 = 20 MIN, t11 = 30 MIN
POLARITY PIN
LOGIC HIGH
SYNC (I/P)
t9
t3
1
SCLK (I/P)
t5
DOUT (O/P)
2
DB15
t7
DIN (I/P)
3
DB15
4
5
t10
t6
3-STATE
t11
DB14
6
16
t6
DB13
DB12
t12
DB11
DB10
DB0
3-STATE
t8
t8
DB14
DB13
DB12
DB11
DB10
DB0
Figure 36. QSPI Mode 3 Timing Diagram for Read/Write Operation with SYNC Input Edge Triggered (SM1 = 0, SM2 = 1)
REV. A
–25–
AD7851
MODE 4 and 5 (Self-Clocking Modes)
the rising edge of CONVST assuming a 6 MHz CLKIN). At this
time the conversion will be complete, the SYNC will go high,
and the BUSY will go low. The next falling edge of the
CONVST must occur at least 330 ns after the falling edge of
BUSY to allow the track/hold amplifier adequate acquisition
time as shown in Figure 38. This gives a throughput time of
3.68 µs. The maximum throughput rate in this case is 272 kHz.
The timing diagrams in Figure 38 and Figure 39 are for Interface Modes 4 and 5. Interface Mode 4 has a noncontinuous
SCLK output and Interface Mode 5 has a continuous SCLK
output (SCLK is switched off internally during calibration for
both Modes 4 and 5). These modes of operation are especially
different to all the other modes since the SCLK and SYNC are
outputs. The SYNC is generated by the part as is the SCLK.
The master clock at the CLKIN pin is routed directly to the
SCLK pin for Interface Mode 5 (Continuous SCLK) and the
CLKIN signal is gated with the SYNC to give the SCLK
(noncontinuous) for Interface Mode 4.
OUTPUT SERIAL SHIFT
REGISTER IS RESET
t1
CONVST
(I/P)
BUSY
(O/P)
The most important point about these two modes of operation
mode is that the result of the current conversion is clocked out during
the same conversion and a write to the part during this conversion
is for the next conversion. The arrangement is shown in Figure
37. Figure 38 and Figure 39 show more detailed timing for the
arrangement of Figure 37.
SYNC
(O/P)
SCLK
(O/P)
tCONVERT = 3.25µs
CONVERSION IS INITIATED
AND TRACK/HOLD GOES
INTO HOLD
THE CONVERSION RESULT DUE TO
WRITE N+1 IS READ HERE
WRITE N+1
WRITE N+2
WRITE N+3
READ N
READ N+1
READ N+2
t1 = 100ns MIN
CONVERSION N
3.25µs
CONVERSION N+1
READ OPERATION
SHOULD END 500ns
PRIOR TO NEXT RISING
EDGE OF CONVST
CONVERSION ENDS
3.25µs LATER
Figure 38. Mode 4, 5 Timing Diagram (SM1 = 1, SM2 = 1
and 0)
CONVERSION N+2
3.25µs
400ns MIN
SERIAL READ
AND WRITE
OPERATIONS
3.25µs
In these interface modes the part is now the master and the
DSP is the slave. Figure 39 is an expansion of Figure 38. The
AD7851 will ensure SYNC goes low after the rising edge C of
the continuous SCLK (Interface Mode 5) in Figure 39. Only in
the case of a noncontinuous SCLK (Interface Mode 4) will
the time t4 apply. The first data bit is clocked out from the
falling edge of SYNC. The SCLK rising edge clocks out all
subsequent bits on the DOUT pin. The input data present on
the DIN pin is clocked in on the rising edge of the SCLK. The
POLARITY pin may be used to change the SCLK edge which
the data is sampled on and clocked out on. The SYNC will go
high after the 16th SCLK rising edge and before the rising edge
D of the continuous SCLK in Figure 39. This ensures the part
will not clock in an extra bit from the DIN pin or clock out an
Figure 37.
In Figure 38 the first point to note is that the BUSY, SYNC,
and SCLK are all outputs from the AD7851 with the CONVST
being the only input signal. Conversion is initiated with the
CONVST signal going low. This CONVST falling edge also
triggers the BUSY to go high. The CONVST signal rising edge
triggers the SYNC to go low after a short delay (2.5 tCLKIN to
3.5 tCLKIN typically) after which the SCLK will clock out the
data on the DOUT pin during conversion. The data on the DIN
pin is also clocked in to the AD7851 by the same SCLK for the
next conversion. The read/write operations must be complete
after sixteen clock cycles (which takes 3.25 µs approximately from
t4 = 0.6 tSCLK (NONCONTINUOUS SCLK), t6 = 45ns MAX,
t7 = 30ns MIN, t8 = 20ns MIN , t11A = 50ns MAX
POLARITY PIN
LOGIC HIGH
SYNC (O/P)
t4
C
2
3
3-STATE
DB15
t7
DIN (I/P)
4
5
t10
t5
DOUT (O/P)
t11A
t9
1
SCLK (O/P)
DB15
DB14
6
t12
t6
DB13
DB12
DB11
DB10
DB0
3-STATE
t8
t8
DB14
D
16
DB13
DB12
DB11
DB10
DB0
Figure 39. Timing Diagram for Read/Write with SYNC Output and SCLK Output (Continuous and Noncontinuous)
(i.e., Operating Mode Numbers 4 and 5, SM1 = 1, SM2 = 1 and 0)
–26–
REV. A
AD7851
extra bit on the DOUT pin.
If the user has control of the CONVST pin but does not want to
exercise it for every conversion, the control register may be used
to start a conversion. Setting the CONVST bit in the control
register to 1 starts a conversion. If the user does not have control of the CONVST pin, a conversion should not initiated by
writing to the control register. The reason for this is that the
user may get “locked out” and not be able to perform any further write/read operations. When a conversion is started by writing to the control register, the SYNC goes low and read/write
operations take place while the conversion is in progress. However, once the conversion is complete, there is no way of writing
to the part unless the CONVST pin is exercised. The CONVST
signal triggers the SYNC signal low which allows read/write operations to take place. SYNC must be low to perform read/write
operations. The SYNC is triggered low by the CONVST signal
rising edge or setting the CONVST bit in the control register to
1. Therefore if there is not full control of the CONVST pin the
user may end up getting “locked out.”
CONFIGURING THE AD7851
AD7851 as a Read-Only ADC
The AD7851 contains fourteen on-chip registers which can be
accessed via the serial interface. In the majority of applications it
will not be necessary to access all of these registers. Figure 40
outlines a flowchart of the sequence which is used to configure
the AD7851 as a Read-Only ADC. In this case there is no writing to the on-chip registers and only the conversion result data is
read from the part. Interface Mode 1 cannot be used in this case
as it is necessary to write to the control register to set Interface
Mode 1. Here the CLKIN signal is applied directly after poweron, the CLKIN signal must be present to allow the part to perform a calibration. This automatic calibration will be completed
approximately 150 ms after power-on.
START
DIN CONNECTED TO DGND
POWER-ON, APPLY CLKIN SIGNAL,
WAIT 150ms FOR AUTOMATIC CALIBRATION
SERIAL
INTERFACE
MODE
?
4, 5
2, 3
PULSE CONVST PIN
PULSE CONVST PIN
READ
DATA
DURING
CONVERSION
?
YES
NO
SYNC AUTOMATICALLY GOES LOW
AFTER CONVST RISING EDGE
WAIT APPROXIMATELY 200ns
AFTER CONVST RISING EDGE
WAIT FOR BUSY SIGNAL
TO GO LOW
SCLK AUTOMATICALLY ACTIVE, READ
CONVERSION RESULT ON DOUT PIN
APPLY SYNC (IF REQUIRED), SCLK AND READ
CONVERSION RESULT ON DOUT PIN
Figure 40. Flowchart for Setting Up and Reading from the AD7851
REV. A
–27–
AD7851
Writing to the AD7851
For accessing the on-chip registers it is necessary to write to the
part. To enable Serial Interface Mode 1, the user must also write
to the part. Figure 41 through 43 outline flowcharts of how to
configure the AD7851 for each of the different serial interface
modes. The continuous loops on all diagrams indicate the sequence for more than one conversion. The options of using a
hardware (pulsing the CONVST pin) or software (setting the
CONVST bit to 1) conversion start, and reading/writing during
or after conversion are shown in Figures 41 and 42. If the
CONVST pin is never used then it should be tied to DVDD permanently. Where reference is made to the BUSY bit equal to a
logic 0, to indicate the end of conversion, the user in this case
would poll the BUSY bit in the status register.
Interface Modes 2 and 3 Configuration
Figure 41 shows the flowchart for configuring the part in Interface Modes 2 and 3. For these interface modes, the read and
write operations take place simultaneously via the serial port.
Writing all 0s ensures that no valid data is written to any of the
registers. When using the software conversion start and transferring data during conversion, Note must be obeyed.
START
POWER-ON, APPLY CLKIN SIGNAL,
WAIT 150ms FOR AUTOMATIC CALIBRATION
NOTE:
WHEN USING THE SOFTWARE CONVERSION START AND TRANSFERRING
DATA DURING CONVERSION THE USER MUST ENSURE THE CONTROL
REGISTER WRITE OPERATION EXTENDS BEYOND THE FALLING EDGE OF
BUSY. THE FALLING EDGE OF BUSY RESETS THE CONVST BIT TO 0 AND
ONLY AFTER THIS TIME CAN IT BE REPROGRAMMED TO 1 TO START THE
NEXT CONVERSION.
SERIAL
INTERFACE
MODE
?
2, 3
INITIATE
CONVERSION
IN
SOFTWARE
?
YES
NO
TRANSFER
DATA DURING
CONVERSION
PULSE CONVST PIN
YES
NO
YES
WAIT APPROXIMATELY 200ns
AFTER CONVST RISING EDGE
TRANSFER
DATA
DURING
CONVERSION
?
APPLY SYNC (IF REQUIRED), SCLK, WRITE TO CONTROL
REGISTER SETTING CONVST BIT TO 1, READ PREVIOUS
CONVERSION RESULT ON DOUT PIN (SEE NOTE)
NO
WAIT FOR BUSY SIGNAL TO GO
LOW OR WAIT FOR BUSY BIT = 0
APPLY SYNC (IF REQUIRED),
SCLK, READ PREVIOUS CONVERSION
RESULT ON DOUT PIN,
AND WRITE ALL 0s ON DIN PIN
APPLY SYNC (IF REQUIRED), SCLK, WRITE TO CONTROL
REGISTER SETTING CONVST BIT TO 1, READ CURRENT
CONVERSION RESULT ON DOUT PIN
WAIT FOR BUSY SIGNAL TO GO LOW
OR WAIT FOR BUSY BIT = 0
APPLY SYNC (IF REQUIRED), SCLK, READ
CURRENT CONVERSION RESULT ON DOUT PIN,
AND WRITE ALL 0s ON DIN PIN
Figure 41. Flowchart for Setting Up, Reading, and Writing in Interface Modes 2 and 3
–28–
REV. A
AD7851
Interface Mode 1 Configuration
Interface Modes 4 and 5 Configuration
Figure 42 shows the flowchart for configuring the part in Interface Mode 1. This mode of operation can only be enabled by
writing to the control register and setting the 2/3 MODE bit.
Reading and writing cannot take place simultaneously in this
mode as the DIN pin is used for both reading and writing.
Figure 43 shows the flowchart for configuring the AD7851 in
Interface Modes 4 and 5, the self-clocking modes. In this case it
is not recommended to use the software conversion start option.
The read and write operations always occur simultaneously and
during conversion.
START
START
POWER-ON, APPLY CLKIN SIGNAL,
WAIT 150ms FOR AUTOMATIC CALIBRATION
POWER-ON, APPLY CLKIN SIGNAL,
WAIT 150ms FOR AUTOMATIC CALIBRATION
SERIAL
INTERFACE
MODE
?
SERIAL
INTERFACE
MODE
?
4, 5
1
PULSE CONVST PIN
YES
APPLY SYNC (IF REQUIRED),
SCLK, WRITE TO CONTROL REGISTER
SETTING THE TWO-WIRE MODE
AND CONVST BIT TO 1
INITIATE
CONVERSION
IN
SOFTWARE
?
SYNC AUTOMATICALLY GOES
LOW AFTER CONVST RISING EDGE
NO
SCLK AUTOMATICALLY ACTIVE, READ CURRENT
CONVERSION RESULT ON DOUT PIN, WRITE
TO CONTROL REGISTER ON DIN PIN
APPLY SYNC (IF REQUIRED),
SCLK, WRITE TO CONTROL REGISTER
SETTING THE TWO-WIRE MODE
PULSE CONVST PIN
YES
Figure 43. Flowchart for Setting Up, Reading, and Writing
in Interface Modes 4 and 5
READ
DATA
DURING
CONVERSION
?
WAIT APPROXIMATLY 200ns
AFTER CONVST RISING EDGE
OR AFTER END OF CONTROL
REGISTER WRITE
NO
WAIT FOR BUSY SIGNAL TO GO
LOW OR WAIT FOR BUSY BIT = 0
APPLY SYNC (IF REQUIRED),
SCLK, READ PREVIOUS CONVERSION
RESULT ON DIN PIN
APPLY SYNC (IF REQUIRED), SCLK, READ
CURRENT CONVERSION RESULT ON DIN PIN
Figure 42. Flowchart for Setting Up, Reading, and Writing
in Interface Mode 1
REV. A
–29–
AD7851
MICROPROCESSOR INTERFACING
OPTIONAL
In many applications, the user may not require the facility of
writing to the on-chip registers. The user may just want to
hardwire the relevant pins to the appropriate levels and read the
conversion result. In this case the DIN pin can be tied low so
that the on-chip registers are never used. Now the part will operate as a nonprogrammable analog to digital converter where
the CONVST is applied, a conversion is performed and the result may be read using the SCLK to clock out the data from the
output register on to the DOUT pin. Note that the DIN pin
cannot be tied low when using the two-wire interface mode of
operation.
7MHz/6MHz
(8XC51/L51)
/PIC17C42
CLKIN
SCLK
AD7851
SYNC
DIN
P3.0/DT
(INT0/P3.2)/INT
BUSY
SLAVE
SYNC
SM1
SM2
DVDD FOR 8XC51/L51
DGND FOR PIC17C42
POLARITY
Figure 45. 8XC51/PIC16C42 Interface
AD7851 to 68HC11/16/L11 / PIC16C42 Interface
CONVERSION
START
7 MHz/6MHz
MASTER CLOCK
SYNC SIGNAL
TO GATE
THE SCLK
DIN
DOUT
SCLK
OPTIONAL
The SCLK can also be connected to the CLKIN pin if the user
does not want to have to provide separate serial and master
clocks in Interface Modes 1, 2, and 3. With this arrangement
the SYNC signal must be low for 16 SCLK cycles in Interface
Modes 1 and 2 for the read and write operations. For Interface
Mode 3 the SYNC can be low for more than 16 SCLK cycles
for the read and write operations. Note that in Interface Modes
4 and 5 the CLKIN and SCLK cannot be tied together as the
SCLK is an output and the CLKIN is an input.
CONVST
CLKIN
P3.1/CK
MASTER
AD7851
CONVST
SERIAL DATA
OUTPUT
Figure 44. Simplified Interface Diagram with DIN
Grounded and SCLK Tied to CLKIN
AD7851 to 8XC51/PIC17C42 Interface
Figure 45 shows the AD7851 interface to the 8XC51/PIC17C42.
The 8XC51/PIC17C42 only run at 5 V. The 8XC51 is in Mode
0 operation. This is a two-wire interface consisting of the SCLK
and the DIN which acts as a bidirectional line. The SYNC is
tied low. The BUSY line can be used to give an interrupt driven
system but this would not normally be the case with the 8XC51/
PIC17C42. For the 8XC51 12 MHz version, the serial clock
will run at a maximum of 1 MHz so that the serial interface to
the AD7851 will only be running at 1 MHz. The CLKIN signal
must be provided separately to the AD7851 from a port line on
the 8XC51 or from a source other than the 8XC51. Here the
SCLK cannot be tied to the CLKIN as the 8XC51 only provides a noncontinuous serial clock. The CONVST signal can be
provided from an external timer or conversion can be started in
software if required. The sequence of events would typically be
writing to the control register via the DIN line setting a conversion start and the 2-wire interface mode (this would be performed in two 8-bit writes), wait for the conversion to be
finished (3.25 µs with 6 MHz CLKIN), read the conversion result data on the DIN line (this would be performed in two 8-bit
reads), and then repeat the sequence. The maximum serial frequency will be determined by the data access and hold times of
the 8XC51/PIC16C42 and the AD7851.
Figure 46 shows the AD7851 SPI/QSPI interface to the
68HC11/16/L11/PIC16C42. The SYNC line is not used and is
tied to DGND. The µController is configured as the master, by
setting the MSTR bit in the SPCR to 1, and thus provides the
serial clock on the SCK pin. For all the µControllers, the CPOL
bit is set to 1 and for the 68HC11/16/L11, the CPHA bit is set
to 1. The CLKIN and CONVST signals can be supplied from
the µController or from separate sources. The BUSY signal can
be used as an interrupt to tell the µController when the conversion is finished, then the reading and writing can take place. If
required the reading and writing can take place during conversion and there will be no need for the BUSY signal in this case.
For no writing to the part then the DIN pin can be tied permanently low. For the 68HC16 and the QSPI interface the SM2
pin should be tied high and the SS line tied to the SYNC pin.
The microsequencer on the 68HC16 QSPI port can be used for
performing a number of read and write operations independent
of the CPU and storing the conversion results in memory without taxing the CPU. The typical sequence of events would be
writing to the control register via the DIN line setting a conversion start and at the same time reading data from the previous
conversion on the DOUT line, wait for the conversion to be
finished (3.25 µs with 6 MHz CLKIN), and then repeat the
sequence. The maximum serial frequency will be determined by
the data access and hold times of the µControllers and the
AD7851.
–30–
OPTIONAL
7MHz/6MHz
68HC11/L11/16
DVDD
SPI
SS
MASTER
AD7851
CONVST
CLKIN
HC16, QSPI
SYNC
SCK
SCLK
MISO
DOUT
BUSY
IRQ
MOSI
OPTIONAL
DIN
SLAVE
SM1
DIN AT DGND FOR
NO WRITING TO PART
DVDDFOR HC11, SPI
DGND FOR HC16, QSPI
DVDD
SM2
POLARITY
Figure 46. 68HC11 and 68HC16 Interface
REV. A
AD7851
AD7851 to ADSP-21xx Interface
OPTIONAL
Figure 47 shows the AD7851 interface to the ADSP-21xx. The
ADSP-21xx is the slave and the AD7851 is the master. The
AD7851 is in Interface Mode 5. For the ADSP-21xx, the bits in
the serial port control register should be set up as TFSR =
RFSR = 1 (need a frame sync for every transfer), SLEN = 15
(16-bit word length), TFSW = RFSW = 1 (alternate framing
mode for transmit and receive operations), INVRFS = INVTFS
= 1 (active low RFS and TFS), IRFS = ITFS = 0 (External
RFS and TFS), and ISCLK = 0 (external serial clock). The
CLKIN and CONVST signals could be supplied from the
ADSP-21xx or from an external source. The AD7851 supplies
the SCLK and the SYNC signals to the ADSP-21xx and the
reading and writing takes place during conversion. The BUSY
signal only indicates when the conversion is finished and may
not be required. The data access and hold times of the ADSP21xx and the AD7851 allows for a CLKIN of 7 MHz/6 MHz
with a 5 V supply.
OPTIONAL
AD7851
7MHz/6MHz
ADSP-21xx
SLAVE
CONVST
CLKIN
SCK
SCLK
DR
DOUT
RFS
SYNC
TFS
IRQ
DT
OPTIONAL
OPTIONAL
DIN AT DGND FOR
NO WRITING TO PART
DVDD
7MHz/6MHz
DSP
56000/1/2/L002
SCLK
SRD
DOUT
IRQ
STD
SYNC
OPTIONAL
BUSY
OPTIONAL
DIN
SLAVE
DIN AT DGND FOR
NO WRITING TO PART
SM1
DVDD
SM2
POLARITY
Figure 48. DSP56000/1/2 Interface
AD7851 to TMS320C20/25/5x/LC5x Interface
Figure 49 shows the AD7851 to the TMS320Cxx interface. The
AD7851 is the master and operates in Interface Mode 5. For
the TMS320Cxx the CLKX, CLKR, FSX, and FSR pins
should all be configured as inputs. The CLKX and the CLKR
should be connected together as should the FSX and FSR. Since
the AD7851 is the master and the reading and writing occurs
during the conversion, the BUSY only indicates when the conversion is finished and thus may not be required. Again the data
access and hold times of the TMS320Cxx and the AD7851 allows for a CLKIN of 7 MHz/6 MHz.
BUSY
DIN
OPTIONAL
MASTER
TMS320C20/
25/5x/LC5x
SM1
SM2
POLARITY
SLAVE
Figure 47. ADSP-21xx Interface
7MHz/6MHz
CLKX
CLKIN
SCLK
DR
DOUT
FSR
SYNC
FSX
OPTIONAL
OPTIONAL
Figure 48 shows the AD7851 to DSP56000/1/2/L002 interface.
Here the DSP5600x is the master and the AD7851 is the slave.
The AD7851 is in Interface Mode 3. The setting of the bits in
the registers of the DSP5600x would be for synchronous operation (SYN = 1), internal frame sync (SCD2 = 1), Internal clock
(SCKD = 1), 16-bit word length (WL1 = 1, WL0 = 0), frames
sync only active at beginning of the transfer (FSL1 = 0, FSL0 =
1). A gated clock can be used (GCK = 1) or if the SCLK is to
be tied to the CLKIN of the AD7851, then there must be a continuous clock (GCK = 0). Again the data access and hold times
of the DSP5600x and the AD7851 should allow for an SCLK of
7 MHz/6 MHz.
AD7851
CONVST
CLKR
INT0
AD7851 to DSP56000/1/2/L002 Interface
REV. A
CLKIN
SCK
SC2
MASTER
AD7851
CONVST
MASTER
BUSY
DT
DIN
DIN AT DGND FOR
NO WRITING TO PART
SM1
DVDD
SM2
POLARITY
Figure 49. TMS320C20/25/5x Interface
–31–
AD7851
APPLICATION HINTS
Grounding and Layout
Evaluating the AD7851 Performance
The analog and digital supplies to the AD7851 are independent
and separately pinned out to minimize coupling between the
analog and digital sections of the device. The part has very good
immunity to noise on the power supplies as can be seen by the
PSRR versus Frequency graph. However, care should still be
taken with regard to grounding and layout.
The printed circuit board that houses the AD7851 should be designed such that the analog and digital sections are separated
and confined to certain areas of the board. This facilitates the
use of ground planes that can be separated easily. A minimum
etch technique is generally best for ground planes as it gives the
best shielding. Digital and analog ground planes should only be
joined in one place. If the AD7851 is the only device requiring
an AGND to DGND connection, then the ground planes should
be connected at the AGND and DGND pins of the AD7851. If
the AD7851 is in a system where multiple devices require
AGND to DGND connections, the connection should still be
made at one point only, a star ground point which should be
established as close as possible to the AD7851.
The recommended layout for the AD7851 is outlined in the
evaluation board for the AD7851. The evaluation board package includes a fully assembled and tested evaluation board,
documentation, and software for controlling the board from the
PC via the EVAL-CONTROL BOARD. The EVAL-CONTROL BOARD can be used in conjunction with the AD7851
Evaluation board, as well as many other Analog Devices evaluation boards ending in the CB designator, to demonstrate/evaluate the ac and dc performance of the AD7851.
The software allows the user to perform ac (fast Fourier transform) and dc (histogram of codes) tests on the AD7851. It also
gives full access to all the AD7851 on-chip registers allowing for
various calibration and power-down options to be programmed.
AD785x Family
All parts are 12 bits, 200 kSPS, 3.0 V to 5.5 V.
AD7853 – Single Channel Serial
AD7854 – Single Channel Parallel
AD7858 – Eight Channel Serial
AD7859 – Eight Channel Parallel
Avoid running digital lines under the device as these will couple
noise onto the die. The analog ground plane should be allowed
to run under the AD7851 to avoid noise coupling. The power
supply lines to the AD7851 should use as large a trace as possible to provide low impedance paths and reduce the effects of
glitches on the power supply line. Fast switching signals like
clocks should be shielded with digital ground to avoid radiating
noise to other sections of the board and clock signals should
never be run near the analog inputs. Avoid crossover of digital
and analog signals. Traces on opposite sides of the board should
run at right angles to each other. This will reduce the effects of
feedthrough through the board. A microstrip technique is by far
the best but is not always possible with a double-sided board. In
this technique, the component side of the board is dedicated to
ground planes while signals are placed on the solder side.
Good decoupling is also important. All analog supplies should
be decoupled with 10 µF tantalum in parallel with 0.1 µF capacitors to AGND. All digital supplies should have a 0.1 µF
disc ceramic capacitor to AGND. To achieve the best from these
decoupling components, they must be placed as close as possible
to the device, ideally right up against the device. In systems
where a common supply voltage is used to drive both the AVDD
and DVDD of the AD7851, it is recommended that the system’s
AVDD supply is used. In this case there should be a 10 Ω resistor
between the AVDD pin and DVDD pin. This supply should have
the recommended analog supply decoupling capacitors between
the AVDD pin of the AD7851 and AGND and the recommended
digital supply decoupling capacitor between the DVDD pin of the
AD7851 and DGND.
–32–
REV. A
AD7851
PAGE INDEX
Topic
Self-Calibration Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Page
System Calibration Description . . . . . . . . . . . . . . . . . . . . 21
FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
System Gain and Offset Interaction . . . . . . . . . . . . . . . . . 22
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 1
System Calibration Timing . . . . . . . . . . . . . . . . . . . . . . . 22
PRODUCT HIGHLIGHTS . . . . . . . . . . . . . . . . . . . . . . . . . 1
SERIAL INTERFACE SUMMARY . . . . . . . . . . . . . . . . . . 23
SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Resetting the Serial Interface . . . . . . . . . . . . . . . . . . . . . . 23
TIMING SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . 4
DETAILED TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
TYPICAL TIMING DIAGRAMS . . . . . . . . . . . . . . . . . . . . 5
Mode 1 (2-Wire 8051 Interface) . . . . . . . . . . . . . . . . . . . 24
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . 6
Mode 2 (3-Wire SPI/QSPI Interface Mode) . . . . . . . . . . . 25
ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Mode 3 (QSPI Interface Mode) . . . . . . . . . . . . . . . . . . . . 25
PINOUTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Mode 4 and 5 (Self-Clocking Modes) . . . . . . . . . . . . . . . 26
TERMINOLOGY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
CONFIGURING THE AD7851 . . . . . . . . . . . . . . . . . . . . . 27
PIN FUNCTION DESCRIPTION . . . . . . . . . . . . . . . . . . . 8
AD7851 as a Read-Only ADC . . . . . . . . . . . . . . . . . . . . . 27
AD7851 ON-CHIP REGISTERS . . . . . . . . . . . . . . . . . . . . . 9
Writing to the AD7851 . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Addressing the On-Chip Registers . . . . . . . . . . . . . . . . . . . 9
Interface Modes 2 and 3 Configuration . . . . . . . . . . . . . . 28
Writing/Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Interface Mode 1 Configuration . . . . . . . . . . . . . . . . . . . . 29
CONTROL REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Interface Modes 4 and 5 Configuration . . . . . . . . . . . . . . 29
STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
MICROPROCESSOR INTERFACING . . . . . . . . . . . . . . . 30
CALIBRATION REGISTERS . . . . . . . . . . . . . . . . . . . . . . 12
AD7851 – 8XC51/PIC17C42 Interface . . . . . . . . . . . . . . . . 30
Addressing the Calibration Registers . . . . . . . . . . . . . . . . 12
AD7851 – 68HC11/16/L11/PIC16C42 Interface . . . . . . . . 30
Writing to/Reading from the Calibration Registers . . . . . . 12
AD7851 – ADSP-21xx Interface . . . . . . . . . . . . . . . . . . . . . 31
Adjusting the Offset Calibration Register . . . . . . . . . . . . . 13
AD7851 – DSP56000/1/2/L002 Interface . . . . . . . . . . . . . . 31
Adjusting the Gain Calibration Registers . . . . . . . . . . . . . 13
AD7851 – TMS320C20/25/5x/LC5x Interface . . . . . . . . . . 31
CIRCUIT INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . 14
APPLICATIONS HINTS . . . . . . . . . . . . . . . . . . . . . . . . . . 32
CONVERTER DETAILS . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Grounding and Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
TYPICAL CONNECTION DIAGRAM . . . . . . . . . . . . . . . 14
Evaluating the AD7851 Performance . . . . . . . . . . . . . . . . 32
ANALOG INPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
INDEX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Acquisition Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . 34
DC/AC Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Input Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Transfer Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
REFERENCE SECTION . . . . . . . . . . . . . . . . . . . . . . . . . . 17
AD7851 PERFORMANCE CURVES . . . . . . . . . . . . . . . . 17
POWER-DOWN OPTIONS . . . . . . . . . . . . . . . . . . . . . . . . 18
POWER-UP TIMES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Using an External Reference . . . . . . . . . . . . . . . . . . . . . . 19
Using the Internal (On-Chip) Reference . . . . . . . . . . . . . 19
POWER VS. THROUGHPUT RATE . . . . . . . . . . . . . . . . 19
CALIBRATION SECTION . . . . . . . . . . . . . . . . . . . . . . . . 20
Calibration Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
TABLE INDEX
#
Title
I
Write Register Addressing . . . . . . . . . . . . . . . . . . . . . . . 9
II
Read Register Addressing . . . . . . . . . . . . . . . . . . . . . . . 9
III
Calibration Selection . . . . . . . . . . . . . . . . . . . . . . . . . . 10
IV
Calibrating Register Addressing . . . . . . . . . . . . . . . . . . 12
V
Analog Input Connections . . . . . . . . . . . . . . . . . . . . . . 16
VI
Power Management Options . . . . . . . . . . . . . . . . . . . . 18
VII Power Consumption vs. Throughput . . . . . . . . . . . . . . 20
VIII Calibration Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
IX
SCLK Active Edges . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
X
Interface Mode Description . . . . . . . . . . . . . . . . . . . . . 23
Automatic Calibration on Power-On . . . . . . . . . . . . . . . . 20
Self-Calibration Description . . . . . . . . . . . . . . . . . . . . . . . 20
REV. A
Page
–33–
AD7851
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
24-Pin Plastic DIP
(N-24)
1.275 (32.30)
1.125 (28.60)
24
13
1
12
PIN 1
0.210
(5.33)
MAX
0.200 (5.05)
0.125 (3.18)
0.280 (7.11)
0.240 (6.10)
0.325 (8.25)
0.300 (7.62) 0.195 (4.95)
0.115 (2.93)
0.060 (1.52)
0.015 (0.38)
0.150
(3.81)
MIN
0.022 (0.558)
0.014 (0.356)
0.100 (2.54)
BSC
0.070 (1.77)
0.045 (1.15)
0.015 (0.381)
0.008 (0.204)
SEATING
PLANE
24-Pin Small Outline Package
(R-24)
13
1
12
PIN 1
0.1043 (2.65)
0.0926 (2.35)
0.0500
(1.27)
BSC
0.0118 (0.30)
0.0040 (0.10)
0.4193 (10.65)
0.3937 (10.00)
24
0.2992 (7.60)
0.2914 (7.40)
0.6141 (15.60)
0.5985 (15.20)
8°
0.0192 (0.49)
0°
SEATING
0.0125 (0.32)
0.0138 (0.35) PLANE
0.0091 (0.23)
0.0291 (0.74)
x 45°
0.0098 (0.25)
0.0500 (1.27)
0.0157 (0.40)
24-Pin Shrink Small Outline Package
(RS-24)
13
1
12
0.311 (7.9)
0.301 (7.64)
24
0.078 (1.98) PIN 1
0.068 (1.73)
0.008 (0.203) 0.0256
(0.65)
0.002 (0.050) BSC
0.212 (5.38)
0.205 (5.207)
0.328 (8.33)
0.318 (8.08)
0.07 (1.78)
0.066 (1.67)
8°
0.015 (0.38)
0°
SEATING 0.009 (0.229)
0.010 (0.25) PLANE
0.005 (0.127)
–34–
0.037 (0.94)
0.022 (0.559)
REV. A
–35–
–36–
PRINTED IN U.S.A.
C2166–18–8/96