AD ADA4830-1 High speed difference amplifier with input Datasheet

FEATURES
APPLICATIONS
Automotive vision systems
Automotive infotainment
Surveillance systems
GENERAL DESCRIPTION
The ADA4830-1 (single) and ADA4830-2 (dual) are monolithic,
high speed difference amplifiers that integrate input overvoltage
(short-to-battery) protection of up to 18 V with a wide input
common-mode voltage range and excellent ESD robustness.
They are intended for use as receivers for differential or pseudo
differential CVBS and other high speed video signals in harsh,
noisy environments such as automotive infotainment and vision
systems. The ADA4830-1 and ADA4830-2 combine high speed
and precision, which allows for accurate reproduction of CVBS
video signals, yet rejects unwanted common-mode error voltages.
The short-to-battery protection that is integrated into the
ADA4830-1 and ADA4830-2 employs fast switching circuitry to
clamp and hold internal voltage nodes at a safe level when an input
overvoltage condition is detected. This protection allows the inputs
of the ADA4830-1 and ADA4830-2 to be directly connected to a
remote video source, such as a rearview camera, without the
need for large expensive series capacitors. The ADA4830-1 and
ADA4830-2 can withstand direct short-to-battery voltages as
high as 18 V on their input pins.
The ADA4830-1 and ADA4830-2 are designed to operate at supply
voltages as low as 2.9 V and as high as 5.5 V, using only 6.8 mA
of supply current per channel. These devices provide true singlesupply capability, allowing the input signal to extend 8.5 V
FUNCTIONAL BLOCK DIAGRAM
ENA
+VS
STB
+VS
ADA4830-1
R/2
VREF
×1
R
INP
VOUT
R
INN
R/2
10020-001
Input overvoltage (short-to-battery) protection of up to 18 V
Short-to-battery output flag for wire diagnostics
Wide input common-mode range with single 5 V supply
High performance video amplifier with 0.50 V/V gain
−3 dB bandwidth of 84 MHz
250 V/µs slew rate (2 V step)
Excellent video specifications
0.1 dB flatness to 28 MHz
SNR of 73 dB to 15 MHz
Differential gain/phase of 0.1%/0.1°
Wide supply range: 2.9 V to 5.5 V
Enable/output disable mode
Space saving 3 mm × 3 mm LFCSP package
Wide operating temperature range: −40°C to +125°C
Qualified for automotive applications
GND
Figure 1.
ENA1
+VS1
STB1
+VS
ADA4830-2
×1
VREF1
R/2
R
INP1
VOUT1
R
INN1
R/2
GND1
GND2
R
R/2
INN2
VOUT2
R
INP2
+VS
VREF2
×1
R/2
ENA2
+VS2
STB2
10020-102
Data Sheet
High Speed Difference Amplifier with Input
Short-to-Battery Protection
ADA4830-1/ADA4830-2
Figure 2.
below ground rail and to 8.5 V above ground on a single 5 V
supply. At the output, the amplifier can swing to within 250 mV
of either supply rail into a 150 Ω load.
The ADA4830-1 and ADA4830-2 present a gain of 0.50 V/V at their
output. This is designed to keep the video signal within the allowed
range of the video decoder, which is typically 1 V p-p or less.
The ADA4830-1W and ADA4830-2W are automotive grade
version, qualified for automotive applications. See the
Automotive Products section for more details.
The ADA4830-1 and ADA4830-2 are available in 3 mm × 3 mm
LFCSP packages, 8-lead and 16-lead, respectively, and are specified
for operation over the automotive temperature range of −40°C
to +125°C.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2011–2012 Analog Devices, Inc. All rights reserved.
ADA4830-1/ADA4830-2
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Power Supply Pins (ADA4830-2).............................................. 13
Applications ....................................................................................... 1
Applications Information .............................................................. 14
General Description ......................................................................... 1
Methods of Transmission .......................................................... 14
Functional Block Diagram .............................................................. 1
Voltage Reference (VREF Pin) ................................................. 14
Revision History ............................................................................... 2
Input Common-Mode Range ................................................... 15
Specifications..................................................................................... 3
Short-to-Battery Output Flag Pin ............................................ 15
5 V Operation ............................................................................... 3
Enable/Disable Modes (ENA Pin) ........................................... 15
3.3 V Operation ............................................................................ 4
PCB Layout ................................................................................. 15
Absolute Maximum Ratings ....................................................... 6
Exposed Paddle (EPAD) Connection ...................................... 15
Thermal Resistance ...................................................................... 6
Using the ADA4830-2 as a Low Cost Video Switch ............... 16
Maximum Power Dissipation ..................................................... 6
Driving Capacitive Loads .......................................................... 17
ESD Caution .................................................................................. 6
Typical Applications Circuits ........................................................ 18
Pin Configurations and Function Descriptions ........................... 7
Fully DC-Coupled Transmission Line .................................... 20
Typical Performance Characteristics ............................................. 9
Packaging and Ordering Information ......................................... 21
Theory of Operation ...................................................................... 13
Outline Dimensions ................................................................... 21
Core Amplifier ............................................................................ 13
Ordering Guide .......................................................................... 21
Overvoltage (Short-to-Battery) Protection ............................. 13
Automotive Products ................................................................. 22
Short-to-Battery Output Flag ................................................... 13
ESD Protection ........................................................................... 13
REVISION HISTORY
6/12—Rev. B to Rev. C
Added ADA4830-2W......................................................... Universal
Changes to Features ..................................................................................... 1
Changes to Ordering Guide..................................................................... 21
4/12—Rev. A to Rev. B
Changes to Features Section and Generation Description Section . 1
Changes to Table 1 ....................................................................................... 3
Changes to Table 2 ....................................................................................... 4
Changes to Table 4 ....................................................................................... 6
Changes to Figure 28 ................................................................................. 12
Changes to ESD Protection Section....................................................... 13
Changes to Ordering Guide..................................................................... 21
Added Automotive Products Section .................................................... 22
1/12—Rev. 0 to Rev. A
Added ADA4830-2 ............................................................. Universal
Changes to Features Section and Figure 1..................................... 1
Added Figure 2; Renumbered Sequentially .................................. 1
Changes to Table 1 ............................................................................ 3
Changes to Table 2 ............................................................................ 4
Added Supply Voltage Delta Parameter, Table 3; Renumbered
Sequentially ....................................................................................... 5
Added Figure 5 and Table 6 .............................................................7
Changes to Typical Performance Characteristics Section ...........8
Added Figure 23 ............................................................................. 10
Added Figure 24 to Figure 29 ....................................................... 11
Changes to Pseudo Differential Mode (Unbalanced Source
Termination) Section, Fully Differential Mode Section, and
Voltage Reference (VREF Pin) Section ....................................... 13
Changes to Input Common-Mode Range Section, Table 7,
Short-to-Battery Output Flag Pin Section, and Table 9 ............ 14
Added Figure 34 ............................................................................. 15
Added Driving Capacitive Loads Section and Figure 35 to
Figure 38 .......................................................................................... 16
Changes to Figure 39 and Figure 40............................................. 17
Changes Typical Application Circuits Section and Figure 41 ......... 18
Added Fully DC-Coupled Transmission Line Section ..................... 19
Changes to Figure 42 ................................................................................. 19
Updated Outline Dimensions ....................................................... 20
Changes to Ordering Guide .......................................................... 20
10/11—Revision 0: Initial Version
Rev. C | Page 2 of 22
Data Sheet
ADA4830-1/ADA4830-2
SPECIFICATIONS
5 V OPERATION
TA = 25°C, +VS = 5 V, RL = 1 kΩ, VREF = 2.5 V (floating), VINCM = +VS/2, RSTB = 5 kΩ to +VS, unless otherwise specified.
Table 1.
Parameter
DYNAMIC PERFORMANCE
−3 dB Large Signal Bandwidth
Bandwidth for 0.1 dB Flatness
Slew Rate (tR/tF)
Settling Time to 0.1%
NOISE/DISTORTION PERFORMANCE
Output Voltage Noise
Differential Gain Error (NTSC)
Differential Phase Error (NTSC)
Signal-to-Noise Ratio
DC PERFORMANCE
Nominal Gain
Test Conditions/Comments
Min
Typ
VOUT = 0.5 V p-p, RL = 150 Ω
ADA4830-1W/ADA4830-2W only TMIN to TMAX
VOUT = 0.1 V p-p, RL = 1 kΩ
VOUT = 0.1 V p-p, RL = 150 Ω
ADA4830-1W/ADA4830-2W only TMIN to TMAX
VOUT = 0.5 V p-p, RL = 150 Ω
VOUT = 2 V step
ADA4830-1W/ADA4830-2W only TMIN to TMAX
VOUT = 2 V step
64
56
71
VIN to VOUT
ADA4830-1W/ADA4830-2W only TMIN to TMAX
ADA4830-1W/ADA4830-2W only TMIN to TMAX
Common-Mode Rejection (CMR)
SHORT-TO-BATTERY CHARACTERISTICS
Input Current
Protected Input Voltage Range
Short-to-Battery Output Flag Trigger
Level
VOLTAGE REFERENCE INPUT
Input Voltage Range
Input Resistance
Gain
LOGIC OUTPUT/INPUT CHARACTERISTICS
STB VOH
STB VOL
ENA VIH
ENA VIL
196/200
164/220
f = 1 MHz
RL = 150 Ω, VIN = 1 V p-p
RL = 150 Ω, VIN = 1 V p-p
f = 100 kHz to 15 MHz, VOUT = 0.5 V p-p
Output Bias Voltage
INPUT CHARACTERISTICS
Input Resistance (Differential Mode)
Input Resistance (Common Mode)
Input Common-Mode Voltage Range
65
60
0.49
0.49
2.45
2.44
Max
25
MHz
MHz
MHz
MHz
MHz
MHz
V/µs
V/µs
ns
28
0.1
0.1
73
nV/√Hz
%
Degrees
dB
84
74
28
250/300
0.50
2.50
0.51
0.51
2.55
2.56
V/V
V/V
V
V
+9.5
+9.5
kΩ
kΩ
V
V
dB
dB
6.7
2
VREF voltage adjusted to optimized range
ADA4830-1W/ADA4830-2W only TMIN to TMAX
VIN = ±5 V
ADA4830-1W/ADA4830-2W only TMIN to TMAX
−10
−10
42
42
VIN = 18 V (short-to-battery)
ADA4830-1W/ADA4830-2W only TMIN to TMAX
Minimum VIN needed to signal an input fault
condition
ADA4830-1W/ADA4830-2W only TMIN to TMAX
65
4.1
−9
−9
9.8
Unit
10.3
9.8
+20
+20
10.8
mA
V
V
V
10.8
V
VREF to VOUT
0.2 to 3.9
20
1
V
kΩ
V/V
VIN ≤ 9.8 V (normal operation)
VIN ≥ 10.8 V (fault condition), ADA4830-1/ADA4830-2
Voltage to enable device
Voltage to disable device
5.0
110/253
≥3.0
≤1.0
V
mV
V
V
Rev. C | Page 3 of 22
ADA4830-1/ADA4830-2
Parameter
OUTPUT CHARACTERISTICS
Output Voltage Swing
Linear Output Current
Short-Circuit Current
Capacitive Load Drive
POWER SUPPLY
Operating Range
Quiescent Current per Amplifier
Power Supply Rejection Ratio (PSRR)
OPERATING TEMPERATURE RANGE
Data Sheet
Test Conditions/Comments
Min
RL = 150 Ω to ground
<1% THD at 100 kHz
Sourcing/sinking
Peaking ≤ 3 dB
Operation outside of this range results in
performance degradation
Enabled (ENA = 5 V), no load
ADA4830-1W/ADA4830-2W only TMIN to TMAX
Disabled (ENA = 0 V), no load
VIN = 18 V (short-to-battery), no load
+VS = 4.5 V to 5.5 V, VREF is forced to 2.5 V
Typ
Max
0.01 to 4.75
125
248/294
47
2.9
6.8
V
mA
mA
pF
5.5
V
10
10.4
+125
mA
mA
µA
mA
dB
°C
Max
Unit
90
5.3
53
−40
Unit
3.3 V OPERATION
TA = 25°C, +VS = 3.3 V, RL = 1 kΩ, VREF = 1.65 V (floating), VINCM = +VS/2, RSTB = 5 kΩ to +Vs, unless otherwise specified.
Table 2.
Parameter
DYNAMIC PERFORMANCE
−3 dB Large Signal Bandwidth
Bandwidth for 0.1 dB Flatness
Slew Rate (tR/tF)
Settling Time to 0.1%
NOISE/DISTORTION PERFORMANCE
Output Voltage Noise
Differential Gain Error (NTSC)
Differential Phase Error (NTSC)
Signal-to-Noise Ratio
DC PERFORMANCE
Nominal Gain
Test Conditions/Comments
Min
Typ
VOUT = 0.5 V p-p, RL = 150 Ω
ADA4830-1W/ADA4830-2W only TMIN to TMAX
VOUT = 0.1 V p-p, RL = 1 kΩ
VOUT = 0.1 V p-p, RL = 150 Ω
ADA4830-1W/ADA4830-2W only TMIN to TMAX
VOUT = 0.5 V p-p, RL = 150 Ω
VOUT = 1 V step
ADA4830-1W/ADA4830-2W only TMIN to TMAX
VOUT = 1 V step
63
58
73
VIN to VOUT
ADA4830-1W/ADA4830-2W only TMIN to TMAX
ADA4830-1W/ADA4830-2W only TMIN to TMAX
Common-Mode Rejection (CMR)
SHORT-TO-BATTERY CHARACTERISTICS
Input Current
Protected Input Voltage Range
Short-to-Battery Output Flag Trigger
Level
147/155
136/145
f = 1 MHz
RL = 150 Ω, VIN = 1 V p-p
RL = 150 Ω, VIN = 1 V p-p
f = 100 kHz to 15 MHz, VOUT = 0.5 V p-p
Output Bias Voltage
INPUT CHARACTERISTICS
Input Resistance (Differential Mode)
Input Resistance (Common Mode)
Input Common-Mode Voltage Range
64
59
0.49
0.49
1.60
1.59
25
MHz
MHz
MHz
MHz
MHz
MHz
V/µs
V/µs
ns
28
0.1
0.1
73
nV/√Hz
%
Degrees
dB
89
78
20
165/180
0.50
1.65
0.51
0.51
1.70
1.71
V/V
V/V
V
V
+6
+6
kΩ
kΩ
V
V
dB
dB
6.7
2
VREF voltage adjusted to optimized range
ADA4830-1W/ADA4830-2W only TMIN to TMAX
VIN = ±3.3 V
ADA4830-1W/ADA4830-2W only TMIN to TMAX
−8
−8
41
40
VIN = 18 V (short-to-battery)
ADA4830-1W/ADA4830-2W only TMIN to TMAX
Minimum VIN needed to signal an input fault
condition
ADA4830-1W/ADA4830-2W only TMIN to TMAX
Rev. C | Page 4 of 22
54
4.4
−9
−9
7.4
7.4
7.8
+20
+20
8.2
mA
V
V
V
8.2
V
Data Sheet
Parameter
VOLTAGE REFERENCE INPUT
Input Voltage Range
Input Resistance
Gain
LOGIC OUTPUT/INPUT CHARACTERISTICS
STB VOH
STB VOL
ENA VIH
ENA VIL
OUTPUT CHARACTERISTICS
Output Voltage Swing
Linear Output Current
Short-Circuit Current
Capacitive Load Drive
POWER SUPPLY
Operating Range
Quiescent Current per Amplifier
Power Supply Rejection Ratio (PSRR)
OPERATING TEMPERATURE RANGE
ADA4830-1/ADA4830-2
Test Conditions/Comments
Min
Typ
Max
Unit
VREF to VOUT
0.2 to 2.2
20
1
V
kΩ
V/V
VIN ≤ 7.4 V (normal operation)
VIN ≥ 8.2 V (fault condition), ADA4830-1/ADA4830-2
Voltage to enable device
Voltage to disable device
3.3
85/178
≥1.8
≤0.8
V
mV
V
V
RL = 150 Ω to ground
<1% THD at 100 kHz
Sourcing/sinking
Peaking ≤ 4 dB
0.01 to 3.08
50
85/180
47
V
mA
mA
pF
Operation outside of this range results in
performance degradation
Enabled (ENA = 3.3 V), no load
ADA4830-1W/ADA4830-2W only TMIN to TMAX
Disabled (ENA = 0 V), no load
VIN = 18 V (short-to-battery), no load
+VS = 3.0 V to 3.6 V, VREF forced to 1.65 V
2.9
5.5
V
8.0
8.4
mA
mA
µA
mA
dB
°C
60
4.3
42
−40
Rev. C | Page 5 of 22
5.5
+125
ADA4830-1/ADA4830-2
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Rating
6V
0.5 V
22 V
−10 V
+VS + 0.3 V
See Figure 3
−65°C to +150°C
−40°C to +125°C
260°C
150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for the device and its exposed paddle is soldered
to a high thermal conductivity, 4-layer (2s2p) circuit board, as
described in EIA/JESD 51-7.
Airflow increases heat dissipation, effectively reducing θJA.
Figure 3 shows the maximum power dissipation in the package vs.
the ambient temperature for the 8-lead LFCSP (116°C/W) and
the 16-lead LFCSP (54°C/W) on a JEDEC standard 4-layer board.
θJA values are approximate.
3.0
Table 4.
Package Type
8-Lead LFCSP
16-Lead LFCSP
2.5
2.0
16-LEAD LFCSP
1.5
8-LEAD LFCSP
1.0
0.5
0
θJA
50
54
θJC
5
6
Unit
°C/W
°C/W
0
10
20
30
40
50
60
70
80
AMBIENT TEMPERATURE (°C)
Figure 3. Maximum Power Dissipation vs.
Ambient Temperature for a 4-Layer Board
ESD CAUTION
MAXIMUM POWER DISSIPATION
The maximum safe power dissipation in the ADA4830-1 and
ADA4830-2 packages is limited by the associated rise in
junction temperature (TJ) on the die. At approximately 150°C,
which is the glass transition temperature, the plastic changes its
properties. Exceeding a junction temperature of 150°C for an
extended time can result in changes in the silicon devices,
potentially causing failure.
Rev. C | Page 6 of 22
90
100
10020-050
Parameter
Supply Voltage (+VS Pin)
Supply Voltage Delta
+VS1 to +VS2, ADA4830-2 Only
Input Voltage Positive Direction (INNx, INPx)
Input Voltage Negative Direction (INNx, INPx)
Reference Voltage (VREFx Pin)
Power Dissipation
Storage Temperature Range
Operating Temperature Range
Lead Temperature (Soldering, 10 sec)
Junction Temperature
The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated in the
package due to the load drive for all outputs. The quiescent
power is the supply voltage (+VS) times the quiescent current (IS).
The power dissipated due to load drive depends on the particular
application. The power due to load drive is calculated by
multiplying the load current by the associated voltage drop
across the device. RMS voltages and currents must be used
in these calculations.
MAXIMUM POWER DISSIPATION (W)
Table 3.
Data Sheet
ADA4830-1/ADA4830-2
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
8 +VS
VREF 1
INP 2
ADA4830-1
INN 3
TOP VIEW
(Not to Scale)
6 VOUT
5 STB
NOTES
1. EXPOSED PAD ON BOTTOM SIDE
OF PACKAGE. NOT CONNECTED
ELECTRICALLY, BUT SHOULD BE
SOLDERED TO A METALIZED AREA
ON THE PCB TO MINIMIZE THERMAL
RESISTANCE.
10020-003
GND 4
7 ENA
Figure 4. ADA4830-1 Pin Configuration
Table 5. ADA4830-1 Pin Function Descriptions
Pin No.
1
Mnemonic
VREF
2
3
4
5
INP
INN
GND
STB
6
7
8
VOUT
ENA
+VS
EPAD
Description
Voltage Reference Input. Sets the output dc bias voltage. Internally biased to +VS/2 when left floating. See the
Applications Information section.
Positive Input.
Negative Input.
Power Supply Ground Pin.
Short-to-Battery Indicator Output Pin. A logic low indicates an overvoltage condition (short-to-battery), whereas a
logic high indicates normal operation. An open-drain configuration requires external pull-up resistor.
Amplifier Output.
Enable Pin. Connect to +VS or float for normal operation. Connect to ground for device disable.
Positive Power Supply Pin. Bypass this pin with a 0.1 µF capacitor to ground.
Exposed Pad. The exposed pad is located on the bottom side of the package. The pad is not connected electrically
but should be soldered to a metalized area on the printed circuit board (PCB) to minimize thermal resistance.
Rev. C | Page 7 of 22
13 ENA1
15 GND1
14 +VS1
Data Sheet
16 VREF1
ADA4830-1/ADA4830-2
INP1 1
12 VOUT1
INN2 3
TOP
VIEW
10 STB2
9
VOUT2
NOTES
1. EXPOSED PAD ON BOTTOM SIDE
OF PACKAGE. NOT CONNECTED
ELECTRICALLY, BUT SHOULD BE
SOLDERED TO A METALIZED AREA
ON THE PCB TO MINIMIZE THERMAL
RESISTANCE.
10020-004
VREF2 5
INP2 4
11 STB1
+VS2 7
ENA2 8
ADA4830-2
GND2 6
INN1 2
Figure 5. ADA4830-2 Pin Configuration
Table 6. ADA4830-2 Pin Function Descriptions
Pin No.
1, 4
2, 3
5, 16
Mnemonic
INP1, INP2
INN1, INN2
VREF2, VREF1
6, 15
7, 14
GND2, GND1
+VS2, +VS1
8, 13
9, 12
10, 11
ENA2, ENA1
VOUT2, VOUT1
STB2, STB1
EPAD
Description
Positive Inputs.
Negative Inputs.
Voltage Reference Inputs. Sets the output dc bias voltage. Internally biased to +VS/2 when left floating. See
the Applications Information section.
Power Supply Ground Pins.
Positive Power Supply Pins. These pins must be connected together, to the same voltage. Bypass these pins
with a 0.1 µF capacitor to ground.
Enable Pins. Connect to +VS or float for normal operation and to ground for device disable.
Amplifier Outputs.
Short-to-Battery Indicator Output Pins. A logic low indicates an overvoltage condition (short-to-battery), whereas a
logic high indicates normal operation. An open-drain configuration requires an external pull-up resistor.
Exposed Pad. The exposed pad is located on the bottom side of the package. The pad is not connected
electrically, but should be soldered to a metalized area on the PCB to minimize thermal resistance.
Rev. C | Page 8 of 22
Data Sheet
ADA4830-1/ADA4830-2
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, +VS = 5 V, RL = 1 kΩ, VREF = 2.5 V (floating), VINCM = +VS/2, RSTB = 5 kΩ to +VS, unless otherwise specified.
3
3
RL = 1kΩ
RL = 1kΩ
0
RL = 150Ω
–3
NORMALIZED GAIN (dB)
–6
–9
–12
–6
–9
–12
–15
VIN = 200mV p-p
1
10
FREQUENCY (MHz)
100
VIN = 1V p-p
–18
0.1
10020-005
–18
0.1
Figure 6. Small Signal Frequency Response for Various Loads
1
10
FREQUENCY (MHz)
100
Figure 9. Large Signal Frequency Response for Various Loads
3
3
+VS = 3.3V
+VS = 3.3V
0
+VS = 5V
–3
NORMALIZED GAIN (dB)
–6
–9
–12
–15
+VS = 5V
–6
–9
–12
–15
VIN = 200mV p-p
1
10
FREQUENCY (MHz)
100
VIN = 1V p-p
–18
0.1
10020-006
–18
0.1
Figure 7. Small Signal Frequency Response for Various Supply Voltages
3
3
0
0
–3
–3
–6
–40°C
–9
–12
–15
+25°C
–18
100
–9
+125°C
–12
–15
+25°C
+VS = 3.3V
VIN = 1V p-p
RL = 150Ω
–24
10020-008
10
FREQUENCY (MHz)
Figure 8. Small Signal Frequency Response for Various Temperatures
100
–40°C
–21
+125°C
VIN = 200mV p-p
1
10
FREQUENCY (MHz)
–6
–18
–21
1
Figure 10. Large Signal Frequency Response for Various Supply Voltages
NORMALIZED GAIN (dB)
NORMALIZED GAIN (dB)
–3
10020-011
NORMALIZED GAIN (dB)
0
–24
10020-010
–15
RL = 150Ω
–3
1
10
FREQUENCY (MHz)
100
10020-013
NORMALIZED GAIN (dB)
0
Figure 11. Large Signal Frequency Response for Various Temperatures
Rev. C | Page 9 of 22
ADA4830-1/ADA4830-2
Data Sheet
–25
7
VIN = 200mV p-p
f = 5MHz
NO SERIES OUTPUT RESISTOR
6
COMMON-MODE REJECTION (dB)
–30
CL = 68pF
3
CL = 47pF
2
CL = 22pF
1
0
–1
CL = 10pF
VIN = 1V p-p
RL = 150Ω
–2
–3
0.1
–35
–40
–45
+VS = 3.3V
–55
–60
–65
CL = 0pF
1
10
FREQUENCY (MHz)
100
–70
–12 –10 –8
–4
–2
0
2
4
6
8
10
12
14
Figure 15. Small Signal CMR vs. VINCM for Various Supply Voltages
0.1
0
VIN = 1V p-p
ENA = 0V
–10
0
–20
–0.1
GAIN (dB)
–0.2
–30
–40
–0.3
–50
–0.4
1
10
FREQUENCY (MHz)
100
–70
0.1
10020-014
–0.5
0.1
100
Figure 16. Input-to-Output Isolation with Device Disabled
6
VIN = 1V p-p
+VS = 3.3V
RL = 1kΩ
VINCM = +8V
–40
–50
VINCM = 0V
–60
+VS = 5.0V
RL = 1kΩ
3
NORMALIZED GAIN (dB)
–30
VINCM = −8V
–70
–80
0
+VS = 5.0V
RL = 150Ω
–3
+VS = 3.3V
RL = 150Ω
–6
–9
–12
1
10
FREQUENCY (MHz)
100
10020-042
–90
0.1
10
FREQUENCY (MHz)
Figure 13. 0.1 dB Flatness
–20
1
10020-019
–60
VIN = 1V p-p
RL = 150Ω
Figure 14. CMR Frequency Response for Various Input Common-Mode
Voltages
Rev. C | Page 10 of 22
VREF = 200mV p-p
–15
0.1
1
10
FREQUENCY (MHz)
100
Figure 17. VREF to VOUT Frequency Response
10020-009
NORMALIZED GAIN (dB)
–6
INPUT COMMON-MODE VOLTAGE (V)
Figure 12. Large Signal Frequency Response for Various Capacitor Loads
COMMON-MODE REJECTION (dB)
+VS = 5.0V
–50
10020-017
4
10020-012
NORMALIZED GAIN (dB)
5
Data Sheet
ADA4830-1/ADA4830-2
40
+VS = 3.3V
VOUT = 1V p-p
RL = 1kΩ
RL = 150Ω
2.5
OUTPUT VOLTAGE (V)
OUTPUT OFFSET VOLTAGE (mV)
2.7
2.3
2.1
1.9
1.7
0
10
20
30
40
50
60
70
80
TIME (ns)
20
10
+VS = 3.3V
0
+VS = 5V
–10
–20
–12 –10 –8
10020-020
1.5
30
Figure 18. Pulse Response at +VS = 3.3 V
16
–4
–2
0
2
4
6
8
10
12
14
Figure 21. Output Offset Voltage (VOUT − VREF) vs.
Input Common-Mode Voltage
10
CSTB = 11pF
9
14
INP
SUPPLY CURRENT (mA)
10
8
RSTB = 500Ω
6
4
RSTB = 5kΩ
2
+VS = 3.3V
8
12
VOLTAGE (V)
–6
INPUT COMMON-MODE VOLTAGE (V)
10020-033
2.9
7
6
5
4
+VS = 5V
3
2
RSTB = 1kΩ
0
1
–2
0
50
100
150
200
250
300
350
400
450
500
TIME (ns)
0
0.5
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
ENABLE VOLTAGE (V)
Figure 19. Short-to-Battery Output Flag Response for Various RSTB, ADA4830-1
Figure 22. Supply Current vs. Enable Voltage
6
140
5
120
ENA
4
100
VOUT
2
80
60
1
40
0
20
–1
0
100
200
300
TIME (ns)
400
500
600
0
46
51
56
61
66
71
76
81
86
91
CMR (dB)
Figure 23. Typical Distribution of Common-Mode Rejection
Figure 20. Enable Turn-on/Turn-off Time
Rev. C | Page 11 of 22
10020-045
COUNT
3
10020-024
VOLTAGE (V)
1.0
10020-134
0
10020-022
VINP, VINN = FLOATING
ADA4830-1/ADA4830-2
Data Sheet
10.0
–45
VIN = 2V p-p
9.5
–55
9.0
SUPPLY CURRENT (mA)
–50
–65
–70
–75
–80
8.5
8.0
7.5
7.0
6.5
–85
6.0
–90
5.5
1
10
100
FREQUENCY (MHz)
5.0
–40
10020-046
–95
0.1
–25
–40
35
50
65
80
95
110
125
VOUT = 1V p-p
–50
3.5
CL = 0pF
SINGLE-ENDED INPUT
HD2
CL = 22pF
DISTORTION (dBc)
–60
3.0
VOUT (V)
20
Figure 27. Supply Current vs. Temperature
VIN = 4V p-p
CL = 10pF
5
TEMPERATURE (°C)
Figure 24. Crosstalk (Output-to-Output) vs. Frequency, ADA4830-2
4.0
–10
10020-051
CROSSTALK (dB)
–60
2.5
2.0
SINGLE-ENDED INPUT
HD3
–70
DIFFERENTIAL INPUT
HD2
–80
DIFFERENTIAL INPUT
HD3
–90
1.5
10
20
30
40
50
60
70
80
90
100
TIME (ns)
–110
0.01
0.1
1
10
FREQUENCY (MHz)
10020-028
0
10020-047
1.0
–100
Figure 28. Harmonic Distortion Vs Frequency
Figure 25. Pulse Response for Various Capacitor Loads
10
10k
+VS RIPPLE = 100mV p-p
–10
CVREF = 0.1µF
1k
PSR (dB)
–20
–30
CVREF = 4.7µF
–40
100
–50
10
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
100M
–70
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 29. PSR vs. Frequency for Various VREF Bypass Capacitors
Figure 26. Total Output Voltage Noise vs. Frequency
Rev. C | Page 12 of 22
10020-029
–60 CVREF = 10µF
10020-048
VOLTAGE NOISE (nV/√Hz)
0
Data Sheet
ADA4830-1/ADA4830-2
THEORY OF OPERATION
CORE AMPLIFIER
SHORT-TO-BATTERY OUTPUT FLAG
At the core of the ADA4830-1 and ADA4830-2 are high speed,
rail-to-rail op amps that are built on a 0.35 µm CMOS process.
Together with the core amplifier, the ADA4830-1 and ADA4830-2
combine four highly matched on-chip resistors into a difference
amplifier function. Common-mode range extension at its inputs
is achieved by employing a resistive attenuator. The closed-loop
differential to single-ended gain of the video channel is internally
fixed at 0.50 V/V (−6 dB) to ensure compatibility with video
decoders whose input range is constrained to 1 V p-p or less.
The transfer function of the ADA4830-1 and ADA4830-2 is
The short-to-battery output flag (STB pin) is functionally
independent of the short-to-battery protection. Its purpose is
to indicate an overvoltage condition on either input. Because
protection is provided passively, it is always available; the flag
merely indicates the presence or absence of a fault condition.
VOUT =
VINP − VINN
+ VREF
2
where:
VOUT is the voltage at the output pin, VOUT.
VINP and VINN are the input voltages at the INP and INN pins,
respectively.
VREF is the voltage at the VREF pin.
OVERVOLTAGE (SHORT-TO-BATTERY)
PROTECTION
Robust inputs guarantee that sensitive internal circuitry is not
subjected to extreme voltages or currents during a stressful event. A
short-to-battery condition usually consists of a voltage on either
input (or both inputs) that is significantly higher than the power
supply voltage of the amplifier. Duration may vary from a short
transient to a continuous fault.
The ADA4830-1 and ADA4830-2 can withstand voltages of up
to 18 V on the inputs. Critical internal nodes are protected from
exposure to high voltages by circuitry that clamps the inputs at a
safe level and limits internal currents. This protection is available
whether the device is enabled or disabled, even when the supply
voltage is removed.
ESD PROTECTION
All pins on the ADA4830-1 and ADA4830-2 are protected with
internal ESD protection structures connected to the power supply
pins (+VS and GND). These structures provide protection during
the handling and manufacturing process.
The inputs (INN and INP) of the ADA4830-1 and ADA4830-2
can be exposed to dc voltages well above the supply voltage;
therefore, conventional ESD structure protection cannot be used.
The ADA4830-1 and ADA4830-2 employ Analog Devices, Inc.,
proprietary ESD devices at the input pins (INN, INP) to allow
for a wide common-mode voltage range and ESD protection
well beyond the handling and manufacturing requirements.
The inputs of the ADA4830-1 and ADA4830-2 are ESD protected
to survive ±8 kV human body model (HBM)
POWER SUPPLY PINS (ADA4830-2)
As indicated in the Absolute Maximum Ratings section, the voltage
difference between the +VS1 and +VS2 pins of the ADA4830-2
cannot exceed 0.5 V. To ensure compliance with the Absolute
Maximum Ratings, it is recommended that these supply pins be
connected together to the same power supply source.
Rev. C | Page 13 of 22
ADA4830-1/ADA4830-2
Data Sheet
APPLICATIONS INFORMATION
Fully Differential Mode
Pseudo Differential Mode (Unbalanced Source
Termination)
The ADA4830-1 and ADA4830-2 can be operated in a pseudo
differential configuration with an unbalanced input signal. This
allows the receiver to be driven by a single-ended source. Pseudo
differential mode uses a single conductor to carry an unbalanced
signal and connects the negative input terminal to the ground
reference of the source.
Use the positive wire or coaxial center conductor to connect the
source output to the positive input (INP) of the ADA4830-1 or
ADA4830-2. Next, connect the negative wire or coaxial shield from
the negative input (INN) back to a ground reference on the source
printed circuit board (PCB). The input termination should match
the source impedance and be referenced to the remote ground.
An example of this configuration is shown in Figure 30.
DRIVER PCB
POSITIVE WIRE
+
INP
75Ω
−
NEGATIVE WIRE
ADA4830-1
INN
10020-034
SINGLE-ENDED
AMPLIFIER
75Ω
Figure 30. Pseudo Differential Mode
Pseudo Differential Mode (Balanced Source Impedance)
Pseudo differential signaling is typically implemented using
unbalanced source termination, as shown in Figure 30. With
this arrangement, however, common-mode signals on the
positive and negative inputs receive different attenuation due to
unbalanced termination at the source. This effectively converts
some of the common-mode signal into differential mode signal,
degrading the overall common-mode rejection of the system.
System common-mode rejection can be improved by balancing
the output impedance of the driver, as shown in Figure 31.
Splitting the source termination resistance evenly between the
hot and cold conductors results in matched attenuation of the
common-mode signals, ensuring maximum rejection.
The differential inputs of the ADA4830-1 and ADA4830-2 allow
full balanced transmission using a differential source. In this
configuration, the differential input termination is equal to twice
the source impedance of each output. For example, a source
with 37.5 Ω back termination resistors in each leg should be
terminated with a differential resistance of 75 Ω. An illustration
of this arrangement is shown in Figure 32.
DRIVER PCB
37.5Ω
DIFFERENTIAL
AMPLIFIER
POSITIVE WIRE
+
75Ω
−
NEGATIVE WIRE
INN
75Ω
ADA4830-1
INN
Figure 32. Fully Differential Mode
VOLTAGE REFERENCE (VREF PIN)
An internal reference level (VREF) determines the output voltage
when the differential input voltage is zero. A resistor divider
connected between the supply rails sets the VREF voltage. Built
with a pair of matched 40 kΩ resistors, the divider sets this
voltage to +VS/2.
The voltage reference pin (VREF) normally floats at its default
value of +VS/2. However, it can be used to vary the output
reference level from this default value. A voltage applied to VREF
appears at the output with unity gain, within the bandwidth limit
of the internal reference buffer. Figure 17 shows the frequency
response of the VREF input.
Any noise on the +VS supply rail appears at the output with only
6 dB of attenuation (the divide-by-two provided by the reference
divider). Even when this pin is floating, it is recommended that
an external capacitor be connected from the reference node to
ground to provide further attenuation of noise on the power supply
line. A 4.7 µF capacitor combined with the internal 40 kΩ resistor
sets the low-pass corner at under 1 Hz and results in better than
40 dB of supply noise attenuation at 100 Hz.
INP
37.5Ω
INP
37.5Ω
−
ADA4830-1
10020-035
37.5Ω
+
NEGATIVE WIRE
DRIVER PCB
SINGLE-ENDED
AMPLIFIER
POSITIVE WIRE
10020-036
METHODS OF TRANSMISSION
Figure 31. Pseudo Differential Mode with Balanced Source Impedance
Rev. C | Page 14 of 22
Data Sheet
ADA4830-1/ADA4830-2
INPUT COMMON-MODE RANGE
In a standard four resistor difference amplifier with 0.50 V/V
gain, the input common-mode (CM) range is three times the CM
range of the core amplifier. In the ADA4830-1 and ADA4830-2,
however, the input CM range has been extended to more than 18 V
(with a 5 V supply). The input CM range can be approximated
by using the following formulas:
For the maximum CM voltage,
5(+VS − 1.25) − 4VREF ≈ VINCM(MAX) ≤ 9.5 V
Table 8. STB Pin Function
For the minimum CM voltage,
−10 V ≤ VINCM(MIN) ≈ − (1 + 4VREF)
Approximate minimum and maximum CM voltages are shown
in Table 7 for several common supply voltages.
Table 7. Input Common-Mode Range Examples
+VS (V)
3.0
3.0
3.3
3.3
3.6
3.6
5.0
5.0
VINCM(MIN) (V)
–7.0
–4.9
–7.6
–5.6
–8.2
–6.4
–10
–9.9
VINCM(MAX) (V)
2.8
4.9
3.6
5.6
4.5
6.4
8.7
9.5
Floating (default condition).
INPUT COMMON-MODE VOLTAGE (V)
15
10
VINCM (MAX)
5
0
VINCM (MIN)
3.0
3.5
ENABLE/DISABLE MODES (ENA PIN)
The power-down, or enable/disable (ENA) pin, is internally pulled
up to +VS through a 250 kΩ resistor. When the voltage on this
pin is high, the amplifier is enabled; pulling ENA low disables
the channel. With no external connection, this pin floats high,
enabling the amplifier channel.
Table 9. ENA Pin Function
ENA Pin Input
High (Logic 1)
Low (Logic 0)
High-Z (Floating)
Device State
Enabled
Disabled
Normal operation
Connect the GND pin(s) to the ground plane with a trace that is as
short as possible. In cases where the ADA4830-1 and ADA4830-2
drive transmission lines, series terminate the outputs and use
controlled impedance traces of the shortest length possible to
connect to the signal I/O pins, which should not pass over any
voids in the ground plane.
–5
–15
2.5
Device State
Normal operation
STB fault condition
As with all high speed applications, attention to PCB layout is of
paramount importance. Adhere to standard high speed layout
practices in designs using the ADA4830-1 and ADA4830-2. A
solid ground plane is recommended, and placing a 0.1 µF surfacemount, ceramic power supply, decoupling capacitor as close as
possible to the supply pin(s) is recommended.
VREF PIN FLOATING
–10
STB Pin Output
High (Logic 1)
Low (Logic 0)
PCB LAYOUT
4.0
4.5
5.0
5.5
6.0
SUPPLY VOLTAGE (V)
10020-037
1
VREF (V)
1.51
0.97
1.651
1.15
1.81
1.34
2.51
2.22
In the falling direction, the speed with which the flag output
responds primarily depends on the external capacitance attached to
this node and the sink current that can be provided. For example, if
the load is 10 pF, and the external pull-up voltage is 3.3 V, the fall
time is a few nanoseconds. In the rising direction, the speed is
determined by external capacitance and the magnitude of the
pull-up resistor. For the case of 10 pF of external capacitance
and a pull-up of 5 kΩ, the time constant of the rising edge is
approximately 50 ns.
Figure 33. Input Common-Mode Range vs. Supply Voltage
SHORT-TO-BATTERY OUTPUT FLAG PIN
The flag output (STB) is an active low, open-drain logic
configuration. A low level on this output indicates that an
overvoltage event has been detected on either the positive or
the negative input or both. Flags from multiple chips can be
wire-OR'ed to form a single fault detection signal. The output is
driven by a grounded source NMOS device, capable of sinking
approximately 10 mA while pulling within a few hundred millivolts
above ground. The output high level is set with an external pull-up
resistor connected to the supply voltage of the logic family that is
used to monitor the state of the flag.
EXPOSED PADDLE (EPAD) CONNECTION
The ADA4830-1 and ADA4830-2 have an exposed thermal pad
(EPAD) on the bottom of the package. This pad is not electrically
connected to the die and can be left floating or connected to the
ground plane. Should heat dissipation be a concern, thermal
resistance can be minimized by soldering the EPAD to a
metalized pad on the PCB. Connect this pad to the ground
plane with multiple vias. Note that the thermal resistance (θJA)
of the device is specified with the EPAD soldered to the PCB.
Rev. C | Page 15 of 22
ADA4830-1/ADA4830-2
Data Sheet
USING THE ADA4830-2 AS A LOW COST VIDEO
SWITCH
wired together. High speed video op amps have all the key features
required to make them ideal for this function. Their high input
impedance does not affect the characteristic impedance of the
transmission line, thus allowing back termination. They also have
inherently good video specifications, including differential gain and
phase, slew rate, bandwidth, and 0.1 dB flatness.
Figure 34 shows a video multiplexer/switch using the ADA4830-2,
dual, high speed difference amplifier. This circuit allows the user
to input two remote video sources into a single channel of a video
decoder, such as the ADV7180.
Each channel of the ADA4830-2 is a high speed difference
amplifier circuit that eliminates common-mode noise and phase
noise caused by ground potential differences between the incoming
video signal and the receiver. The ADA4830-2 also offers integrated
short-to-battery protection and heightened ESD tolerance in a
small foot print. The fault detection output (the STB pins) of the
ADA4830-2 allows for proactive wire diagnostics when connected
to a microcontroller or video decoder and are used to generate
an interrupt during a fault condition.
Traditional CMOS multiplexers and switches suffer several
disadvantages at video frequencies where their on-resistance
introduces distortion, degrades differential gain and phase
performance, and interacts with the termination resistor to
attenuate the incoming video signal and affect the luminance.
System designers generally address these issues by adding
external buffers to add gain and increase drive capability.
Video multiplexing can be simplified by using high speed video
amplifiers with a disable/enable function (sometimes called powerdown). When the amplifier is disabled, its output stage goes into
a high impedance state, allowing several amplifier outputs to be
+VS
+
ENABLE1
(INPUT)
0.1µF
2.2µF
+VS
4.7µF
13
5kΩ
ENA1
GND1
14
INP1
VOUT1
INN1
STB1
5kΩ
75Ω
12
75Ω
2
11
ADA4830-2
3
INN2
STB2
INP2
VOUT2
CONNECT
TO VIDEO
DECODER
10
5
6
9
75Ω
ENA2
+VS2
4
GND2
75Ω
VREF2
75Ω
DIFFERENTIAL
INPUT 2
STB FLAGS
(OUTPUTS)
7
8
4.7µF
0.1µF
ENABLE2
(INPUT)
+VS
Figure 34. Low Cost Video Switch Using the ADA4830-2
Rev. C | Page 16 of 22
10020-049
75Ω
DIFFERENTIAL
INPUT 1
VREF1
1
15
+VS1
16
Data Sheet
ADA4830-1/ADA4830-2
DRIVING CAPACITIVE LOADS
The ADA4830-1 and ADA4830-2 are capable of driving large
capacitive loads while maintaining its rated performance.
Several performance curves vs. capacitive load are shown in
Figure 12 and Figure 25. Capacitive loads interact with an op amp’s
output impedance to create an extra delay in the feedback path.
This reduces circuit stability and can cause unwanted ringing
and oscillation.
The capacitive load drive of the ADA4830-1and ADA4830-2 can
be increased by adding a low valued resistor, RS, in series with the
capacitive load. Figure 35 shows the test circuit.
Another method of reducing the resonant peaking caused by
driving large capacitive loads at the output of the ADA4830-1
and ADA4830-2 is with the use of a R-C shunt circuit or a snubber
circuit. This method acts to resistively load the amplifier output,
thus reducing frequency response peaking. One drawback to this
approach is a slight loss of signal bandwidth. Figure 37 shows a
simple circuit representation of the implementation of the R-C
snubber circuit with RSNT and CSNT. Figure 38 shows the effects of
a R-C snubber circuit driving 47 pF, where RSNT = 73.2 Ω and CSNT
= 0.1 µF.
–
ADA4830-1
RS = 49.9Ω
ADA4830-1
RSNT = 73.2Ω
+
RL = 1kΩ
CL = 47pF
10020-053
–
CSNT = 0.1uF
RL = 1kΩ
CL = 47pF
10020-052
+
Figure 37. R-C Test Circuit
4.0
Figure 35. RS Test Circuit
3.5
+VS = 5V
RL = 1kΩ
CL = 47pF
NO RS
RSNT = 73.2Ω
CSNT = 0.1µF
3.0
VOUT (V)
Introducing a series resistor tends to isolate the capacitive load
from the feedback loop, thereby diminishing its influence. One
drawback to this approach is a slight loss of signal amplitude.
Figure 36 shows the effects of a series resistor on the capacitive
drive. For very large capacitive loads, the frequency response of
the amplifier is dominated by the roll-off of the series resistor
and capacitive load.
4.0
+VS = 5V
RL = 1kΩ
CL = 47pF
NO SNUBBER
CIRCUIT
2.5
2.0
1.5
1.0
RS = 49.9Ω
0
50
100
150
200
250
TIME (ns)
Figure 38. Pulse Response With and Without R-C Snubber Circuit
2.5
2.0
1.5
1.0
0
50
100
150
200
250
TIME (ns)
10020-135
VOUT (V)
3.0
Figure 36. Pulse Response With and Without Series Resistor
Rev. C | Page 17 of 22
10020-137
3.5
ADA4830-1/ADA4830-2
Data Sheet
TYPICAL APPLICATIONS CIRCUITS
STB FLAG
(OUTPUT)
+VS
(2.9V TO 5.5V)
ENABLE
(INPUT)
5kΩ
+
2.2µF
ENA
0.1µF
+VS
STB
+VS
VREF
DRIVER PCB
75Ω
SINGLE ENDED
AMPLIFIER
×1
4.7µF
POSITIVE WIRE
INP
+
VOUT
TO VIDEO
DECODER
75Ω
0.1µF
−
INN
NEGATIVE WIRE
10020-038
ADA4830-1
GND
Figure 39. Typical Application with Pseudo Differential Input
ENABLE
(INPUT)
STB FLAG
(OUTPUT)
+VS
(2.9V TO 5.5V)
5kΩ
+
2.2µF
ENA
0.1µF
+VS
STB
+VS
VREF
DRIVER PCB
37.5Ω
INP
+
VOUT
DIFFERENTIAL
AMPLIFIER
TO VIDEO
DECODER
75Ω
0.1µF
−
INN
ADA4830-1
GND
Figure 40. Typical Application with Fully Differential Input
Rev. C | Page 18 of 22
10020-039
37.5Ω
×1
4.7µF
Data Sheet
ENABLE
(INPUT)
ADA4830-1/ADA4830-2
STB FLAG
(OUTPUT)
+VS
(2.9V TO 5.5V)
5kΩ
2.2µF
DVDD _1.8V
+
0.1µF
ENA
AVDD _1.8V
DVDDIO
0.1µF
+VS
10nF
10nF 0.1µF
0.1µF
10nF
STB
+VS
PVDD _1.8V
DVDD _3.3V
−
23
INN
24
ADA4830-1
25
GND
RESET
KEEP VREFN AND VREFP CAPACITORS AS CLOSE AS
POSSIBLE TO THE ADV7180 AND ON THE SAME SIDE
OF THE PCB AS THE ADV7180.
21
AIN1
AIN2
P0
P1
P2
P3
P4
P5
P6
P7
AIN3
RESET
VREFN
10nF
18
22
30
0.1µF
P[0:7]
PVDD
19
0.1µF
AVDD
VOUT
75Ω
DVDD
3
INP
DVDDIO
+
14
DVDD _1.8V
AVDD _1.8V
×1
4.7µF
DVDD
VREF
16
15
10
9
8
7
6
5
P0
P1
P2
P3
P4
P5
P6
P7
YCrCb
8-BIT
656 DATA
0.1µF
20
VREFP
0.1µF
LOCATE CLOSE TO, AND
ON THE SAME SIDE AS,
THE ADV7180
13
47pF
28.63636MHz
ADV7180
XTAL
LLC
1MΩ
INTRQ
12
SFL
XTAL1
47pF
VS/FIELD
HS
DVDDIO
26
4kΩ
ALSB TIED HI
ALSB TIED LOW
11
32
4
31
1
LLC
INTRQ
SFL
VS/FIELD
HS
PVDD _1.8V
ALSB
EXTERNAL
LOOP FILTER
≥ I2C ADDRESS = 0x42
≥ I2C ADDRESS = 0x40
ELPF
10nF
17
1.69kΩ
KEEP CLOSE TO THE ADV7180 AND ON
THE SAME SIDE OF PCB AS THE ADV7180.
10020-040
DGND
SDATA
29
27
SCLK
2
SDA
28
DGND
82nF
SCLK
Figure 41. ADA4830-1 Driving an ADV7180 Video Decoder
The ADA4830-1 and ADA4830-2 are differential receivers whose
overall performance is independent of the transmitter IC used
and whether the transmission line is ac-coupled or dc-coupled.
The ADA4830-1 and ADA4830-2 are specifically designed to
perform as differential line receivers. The circuit in Figure 41
shows a detailed schematic of the ADA4830-1 and the ADV7180
configured for this function. The signal is received differentially
relative to the common of the source circuitry, and that voltage
is exactly reproduced with an attenuating gain of 0.50 V/V. This
is designed to keep the video signal within the allowed range of
the video decoder, which is typically 1 V p-p or less.
The common-mode rejection vs. frequency, shown in Figure 14,
typically 65 dB at low frequencies, enables the recovery of video
signals in the presence of large common-mode noise. The high
input impedance permits the ADA4830-1 and ADA4830-2 to
operate as a bridging amplifier across low impedance terminations
with negligible loading.
Rev. C | Page 19 of 22
ADA4830-1/ADA4830-2
Data Sheet
FULLY DC-COUPLED TRANSMISSION LINE
reference levels at the transmitter and receiver is within the
common-mode range of the receiver, very little current flow
results, and no image degradation should be anticipated.
The wide input common-mode range and high input impedance of
the ADA4830-1 and ADA4830-2 allow them to be used in fully
dc-coupled transmission line applications in which there may be a
significant discrepancy between voltage levels at the ground pins of
the driver and receiver. As long as the voltage difference between
ENABLE
(INPUT)
+VS
(2.7V TO 3.6V)
2.2µF
+
ENA
Figure 42 shows an example configuration of a completely dccoupled transmission using a low impedance differential driver.
ENABLE
(INPUT)
STB FLAG
(OUTPUT)
0.1µF
+VS
5kΩ
2.2µF
STB
STB FLAG
(OUTPUT)
+VS
(2.9V TO 5.5V)
+
ENA
0.1µF
+VS
STB
+VS
FROM
IMAGER
OR VIDEO
ENCODER
VREF
+IN
RT
LPF
–OUT
37.5Ω
−
75Ω
TWISTED
PAIR
×1
4.7µF
+
INP
VOUT
TO VIDEO
DECODER
75Ω
37.5Ω
+OUT
–IN
0.1µF
+
−
INN
ADA4830-1
LPF
GND
GND
Figure 42. Differential Video Filter Driver and ADA4830-1 Difference Amplifier
Rev. C | Page 20 of 22
10020-041
+VS
Data Sheet
ADA4830-1/ADA4830-2
PACKAGING AND ORDERING INFORMATION
OUTLINE DIMENSIONS
2.44
2.34
2.24
3.10
3.00 SQ
2.90
0.50 BSC
8
5
PIN 1 INDEX
AREA
1.70
1.60
1.50
EXPOSED
PAD
0.50
0.40
0.30
BOTTOM VIEW
SEATING
PLANE
0.30
0.25
0.20
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.203 REF
PIN 1
INDICATOR
(R 0.15)
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
01-24-2011-B
0.80
0.75
0.70
1
4
TOP VIEW
COMPLIANT TO JEDEC STANDARDS MO-229-WEED
Figure 43. 8-Lead Lead Frame Chip Scale Package [LFCSP_WD]
3 mm × 3 mm Body, Very Very Thin, Dual Lead
(CP-8-11)
Dimensions shown in millimeters
PIN 1
INDICATOR
0.30
0.23
0.18
0.50
BSC
13
PIN 1
INDICATOR
16
1
12
EXPOSED
PAD
1.75
1.60 SQ
1.45
9
TOP VIEW
0.80
0.75
0.70
0.50
0.40
0.30
4
8
0.25 MIN
BOTTOM VIEW
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
5
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-WEED-6.
08-16-2010-E
3.10
3.00 SQ
2.90
Figure 44. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
3 mm × 3 mm Body, Very Very Thin Quad
(CP-16-22)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1, 2
ADA4830-1BCP-EBZ
ADA4830-1BCPZ-R7
ADA4830-1WBCPZ-R7
ADA4830-1BCPZ-R2
ADA4830-2BCPZ-R7
ADA4830-2BCPZ-R2
ADA4830-2WBCPZ-R7
1
2
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
Evaluation Board
8-Lead Lead Frame Chip Scale Package [LFCSP_WD]
8-Lead Lead Frame Chip Scale Package [LFCSP_WD]
8-Lead Lead Frame Chip Scale Package [LFCSP_WD]
16-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
16-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
16-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
Z = RoHS Compliant Part.
W = Qualified for Automotive Applications.
Rev. C | Page 21 of 22
Package
Option
Branding
Ordering
Quantity
CP-8-11
CP-8-11
CP-8-11
CP-16-22
CP-16-22
CP-16-22
H30
4H1
H30
H31
H31
4H2
1500
1500
250
1500
250
1500
ADA4830-1/ADA4830-2
Data Sheet
AUTOMOTIVE PRODUCTS
The ADA4830-1W and ADA4830-2W models are available with controlled manufacturing to support the quality and reliability
requirements of automotive applications. Note that these automotive models may have specifications that differ from the commercial
model; therefore, designers should review the Specifications section of this data sheet carefully. Only the automotive grade products
shown are available for use in automotive applications. Contact your local Analog Devices account representative for specific product
ordering information and to obtain the specific Automotive Reliability reports for these models.
©2011–2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D10020-0-6/12(C)
www.analog.com/ADA4830-1/ADA4830-2
Rev. C | Page 22 of 22