Cadeka CLC1200 Instrumentation amplifier Datasheet

Data Sheet
Comlinear CLC1200
®
Instrumentation Amplifier
The CLC1200 is a low power, general purpose instrumentation amplifier with
a gain range of 1 to 10,000. The CLC1200 is offered in 8-lead SOIC or DIP
packages and requires only one external gain setting resistor making it smaller and easier to implement than discrete, 3-amp designs.
While consuming only 2.2mA of supply current, the CLC1200 offers a low
6.6nV/Hz input voltage noise and 0.2μVpp noise from 0.1Hz to 10Hz.
The CLC1200 offers a low input offset voltage of ±125μV that only varies
0.1μV/°C over it’s operating temperature range of -40°C to +85°C. The
CLC1200 also features 50ppm maximum nonlinearity. These features make it
well suited for use in data acquisition systems.
Functional Block Diagram
APPLICATIONS
n Bridge amplifier
n Scales
n Thermocouple amplifier
n ECG and medical instrumentation
n MRI (Magnetic Resonance Imaging)
n Patient Monitors
n Transducer interface
n Data acquisition systems
n Strain gauge amplifier
n Industrial process controls
-IN
RG
OUT
Rev 2C
REF
+IN
Competitive Comparison Plots (continued on page 9)
3
2
Competitor A
Normalized Gain (dB)
1
0
-1
CLC1200
-2
-3
-4
-5
-6
G=1
VS = ±15V
VOUT = 0.2Vpp
RL = 2kΩ
-7
0.0001
0.001
0.01
0.1
1
10
Frequency (MHz)
Ordering Information
Part Number
Package
Pb-Free
RoHS Compliant
Operating Temperature Range
Packaging Method
CLC1200ISO8
SOIC-8
Yes
Yes
-40°C to +85°C
Rail
CLC1200ISO8X
SOIC-8
Yes
Yes
-40°C to +85°C
Reel
CLC1200IDP8
DIP-8
Yes
Yes
-40°C to +85°C
Rail
Moisture sensitivity level for all parts is MSL-1.
©2008, 2010-2011 CADEKA Microcircuits LLC Comlinear CLC1200 Instrumentation Amplifier
General Description
FEATURES
n ±2.3V to ±18V supply voltage range
n Gain range of 1 to 10,000
n Gain set with one external resistor
n ±125μV maximum input offset voltage
n 0.1μV/°C input offset drift
n 700kHz bandwidth at G = 1
n 1.2V/μs slew rate
n 90dB minimum CMRR at G = 10
n 2.2mA maximum supply current
n 6.6nV/√Hz input voltage noise
n 70nV/√Hz output voltage noise
n 0.2μVpp noise (0.1Hz to 10Hz)
n DIP-8 or Pb-free SOIC-8
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Data Sheet
Pin Assignments
Pin Configuration
1
8
RG
-IN1
2
7
+VS
+IN1
3
6
OUT
-V S
4
5
REF
Pin Name
Description
1, 8
RG
RG sets gain
2
-IN
Negative input
3
+IN
Positive input
4
-VS
Negative supply
5
REF
Output is referred to the REF pin potential
6
OUT
Output
7
+VS
Positive supply
Comlinear CLC1200 Instrumentation Amplifier
RG
Pin No.
Rev 2C
©2008, 2010-2011 CADEKA Microcircuits LLC www.cadeka.com
2
Data Sheet
Electrical Characteristics
TA = 25°C, Vs = ±15V, RL = 2kΩ to GND; unless otherwise noted.
G = 1 + (49.4kΩ / RG); Total RTI Error = VOSI + (VOSO / G)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
1
Gain Range
Gain Error
-0.1
0.1
%
G = 10, VOUT = ±10V
-0.375
0.375
%
G = 100, VOUT = ±10V
-0.375
0.375
%
-0.8
0.8
%
10
50
ppm
10
95
G = 1,000, VOUT = ±10V
G = 1 - 100, VOUT = -10V to 10V, RL = 10kΩ
Nonlinearity
G = 1 - 100, VOUT = -10V to 10V, RL = 2kΩ
Gain vs. Temperature
10,000
G = 1, VOUT = ±10V
ppm
G=1
<10
ppm/°C
G>1
<-50
ppm/°C
VS = ±16.5
-0.03
0.03
%
Input Offset Voltage
VS = ±4.5 to ±16.5
-125
125
μV
Average Temperature Coefficient
VS = ±4.5 to ±16.5
Output Offset Voltage
VS = ±4.5 to ±16.5, G = 1
Average Temperature Coefficient
VS = ±4.5 to ±16.5
Reference Gain
Error(2)
Voltage Offset
VOSI
VOSO
PSR
Offset Referred to the Input vs. Supply
0.1
-1500
200
μV/°C
1500
μV
2.5
μV/°C
dB
G = 1, VS = ±2.3 to ±18V
80
100
G = 10, VS = ±2.3 to ±18V
95
120
dB
G = 100, VS = ±2.3 to ±18V
110
140
dB
G = 1,000, VS = ±2.3 to ±18V
110
140
dB
-2
0.5
Input Current
IB
VS = ±16.5
Average Temperature Coefficient
VS = ±16.5
Input Offset Current
VS = ±16.5
2
3
-1
nA
pA/°C
1
nA
Input
Input Impedance
Input Voltage Range(3)
CMRR
Common Mode Rejection Ratio
10, 2
Differential
GΩ, pF
10, 2
Common-Mode
GΩ, pF
VS = ±4.5, G = 1
-VS +1.9
+VS -1.2
V
VS = ±16.5, G = 1
-VS +1.9
+VS -1.4
V
G = 1, VS = ±16.5V
70
90
dB
G = 10, VS = ±16.5V
90
110
dB
G = 100, VS = ±16.5V
108
130
dB
G = 1,000, VS = ±16.5V
108
130
dB
Output
VOUT
Output Swing
ISC
Short Circuit Current
VS = ±2.3V to ±4.5V
-VS +1.1
VS = ±18, G = 1
-VS +1.4
+VS -1.2
V
+VS -1.2
V
±20
mA
G=1
700
kHz
G = 10
400
kHz
G = 100
100
kHz
Dynamic Performance
BW-3dB
Small Signal Bandwidth
SR
Slew Rate
G = 1,000
©2008, 2010-2011 CADEKA Microcircuits LLC G = 10, VS = ±15V
0.6
12
kHz
1.2
V/μs
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3
Rev 2C
IOS
Input Bias Current
Comlinear CLC1200 Instrumentation Amplifier
Gain
Data Sheet
Symbol
Parameter
Min
Typ
Max
Units
13
μs
G = 1,000, 5V step
110
μs
Input Voltage Noise
1kHz, G = 1,000, VS = ±15V
6.6
13
nV/√Hz
Output Voltage Noise
1kHz, G = 1, VS = ±15V
70
100
nV/√Hz
G=1
5
Settling Time to 0.01%
eni
eno
RTI, 0.1Hz to 10Hz
Current Noise
μVpp
G = 10, VS = ±15V
0.8
μVpp
G = 100, VS = ±15V
0.2
f = 1kHz
100
fA/√Hz
0.1Hz to 10Hz
10
pApp
20
kΩ
0.4
μVpp
Reference Input
RIN
Input Impedance
IIN
Input Current
VS = ±16.5V
Voltage Range
VS = ±15V
50
-VS +1.6
60
μA
+VS -1.6
V
1 ± 0.0001
Gain to Output
Power Supply
VS
IS
±2.3
Operating Range
Supply Current
VS = ±16.5V
1.3
±18
V
2.2
mA
Notes:
1. 100% tested at 25°C
2. Nominal reference voltage gain is 1.0
3. Input voltage range = CMV + (G VDIFF)/2
Comlinear CLC1200 Instrumentation Amplifier
G = 1 to 100, 5V step
tS
RTI
Conditions
Rev 2C
©2008, 2010-2011 CADEKA Microcircuits LLC www.cadeka.com
4
Data Sheet
Absolute Maximum Ratings
The safety of the device is not guaranteed when it is operated above the “Absolute Maximum Ratings”. The device should
not be operated at these “absolute” limits. Adhere to the “Recommended Operating Conditions” for proper device function. The information contained in the Electrical Characteristics tables and Typical Performance plots reflect the operating
conditions noted on the tables and plots.
Min
Max
Unit
Supply Voltage
Input Voltage Range
Differential Input Voltage, G = 1 to 10
Differential Input Voltage, G > 10
0
-Vs
±18
+Vs
25
≤ 0.05 (RG + 800) + 1
V
V
V
V
Load Resistance
0.001
Comlinear CLC1200 Instrumentation Amplifier
Parameter
kΩ
Reliability Information
Parameter
Junction Temperature
Storage Temperature Range
Lead Temperature (Soldering, 10s)
Package Thermal Resistance
8-Lead SOIC
8-Lead DIP
Min
Typ
-65
Max
Unit
150
150
260
°C
°C
°C
100
TBD
°C/W
°C/W
Notes:
Package thermal resistance (qJA), JDEC standard, multi-layer test boards, still air.
ESD Protection
Product
SOIC-8
DIP-8
1.5kV
2kV
TBD
TBD
Rev 2C
Human Body Model (HBM)
Charged Device Model (CDM)
Recommended Operating Conditions
Parameter
Min
Operating Temperature Range
Supply Voltage Range
-40
±2.3
©2008, 2010-2011 CADEKA Microcircuits LLC Typ
Max
Unit
+85
±18
°C
V
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5
Data Sheet
Typical Performance Characteristics
TA = 25°C, Vs = ±15V, RL = 2kΩ to GND; unless otherwise noted.
Input Offset Distribution (typical)
Input Bias Current Distribution (typical)
Comlinear CLC1200 Instrumentation Amplifier
Input Offset Distribution (typical)
Rev 2C
©2008, 2010-2011 CADEKA Microcircuits LLC www.cadeka.com
6
Data Sheet
Typical Performance Characteristics
TA = 25°C, Vs = ±15V, RL = 2kΩ to GND; unless otherwise noted.
Gain vs. Frequency
+VS - 1.5
60
G = 1000
Output Voltage Swing (V)
Gain (dB)
G = 100
30
20
G = 10
10
0
RL=10kΩ
0.5
0
-0.5
G=1
RL=10kΩ
-1
-10
RL=2kΩ
Referred to Supply Voltages
-VS +-1.5
-20
0.0001
0.001
0.01
RL=2kΩ
1
50
40
G = 10
0.1
1
10
0
5
Frequency (MHz)
Input Voltage Range vs. Vs
20
Output Voltage Swing vs. RL
30
Output Voltage Swing (Vpp)
G = 10
Referred to Supply Voltages
1
0
-1
20
10
0
-VS + -2
0
5
10
15
0.01
20
0.1
1
10
Load Resistance (kΩ)
Supply Voltage (+/- V)
Large Signal Pulse Response (G = 1)
Large Signal Settling Time (G = 1)
7.5
0.1
G = 1, RL=2K
G = 1, 5V Step
0.09
5
0.08
Output Settling (%)
Output Voltage (V)
15
Rev 2C
Input Voltage Swing (V)
+VS - 2
10
Supply Voltage (+/- V)
2.5
0
-2.5
0.07
0.06
0.05
0.04
0.03
0.02
0.01
-5
0
-7.5
-0.01
0
20
40
60
Time (us)
©2008, 2010-2011 CADEKA Microcircuits LLC 80
100
Comlinear CLC1200 Instrumentation Amplifier
70
Output Voltage Swing vs. Vs
0
5
10
15
20
25
30
35
40
45
Time (us)
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7
Data Sheet
Typical Performance Characteristics
TA = 25°C, Vs = ±15V, RL = 2kΩ to GND; unless otherwise noted.
Large Signal Pulse Response (G = 10)
Large Signal Settling Time (G = 10)
0.1
G = 10, RL=2K
5
0.08
Output Settling (%)
Output Voltage (V)
G = 10, 5V Step
0.09
2.5
0
-2.5
0.07
0.06
0.05
0.04
0.03
0.02
-5
0.01
-7.5
-0.01
0
0
20
40
60
80
100
0
5
10
15
Time (us)
Large Signal Pulse Response (G = 100)
25
30
35
40
45
Large Signal Settling Time (G = 100)
7.5
0.1
G = 100, RL=2K
G = 100, 5V Step
0.09
5
Output Settling (%)
0.08
2.5
0
-2.5
0.07
0.06
0.05
0.04
0.03
0.02
-5
0.01
-7.5
-0.01
Rev 2C
Output Voltage (V)
20
Time (us)
0
0
20
40
60
80
100
Time (us)
0
5
10
15
20
25
30
35
40
45
Time (us)
Large Signal Pulse Response (G = 1000)
Large Signal Settling Time (G = 1000)
7.5
G = 1000, RL=2K
Output Voltage (V)
5
2.5
0
-2.5
-5
-7.5
0
200
400
600
800
1000
Time (us)
©2008, 2010-2011 CADEKA Microcircuits LLC Comlinear CLC1200 Instrumentation Amplifier
7.5
www.cadeka.com
8
Data Sheet
Typical Performance Characteristics
TA = 25°C, Vs = ±15V, RL = 2kΩ to GND; unless otherwise noted.
Small Signal Pulse Response (G = 1)
Small Signal Pulse Response (G = 10)
0.1
G = 1, RL=2K, CL=100pF
G = 10, RL=2K, CL=100pF
0.05
Output Voltage (V)
Output Voltage (V)
0.05
0
-0.05
0
-0.05
-0.1
-0.1
0
20
40
60
80
100
0
20
Time (us)
40
60
Small Signal Pulse Response (G = 100)
100
Small Signal Pulse Response (G = 1000)
0.1
0.1
G = 100, RL=2K, CL=100pF
G = 1000, RL=2K, CL=100pF
0.05
0
-0.05
0
Rev 2C
Output Voltage (V)
0.05
Output Voltage (V)
80
Time (us)
-0.05
-0.1
-0.1
0
20
40
60
Time (us)
©2008, 2010-2011 CADEKA Microcircuits LLC 80
100
Comlinear CLC1200 Instrumentation Amplifier
0.1
0
100
200
300
400
500
Time (us)
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9
Data Sheet
Typical Competitive Comparison Plots
TA = 25°C, Vs = ±15V, RL = 2kΩ, CADEKA evaluation board; unless otherwise noted.
Frequency Response (G = 1)
Frequency Response (G = 10)
1
Competitor A
2
Normalized Gain (dB)
1
Normalized Gain (dB)
0
Competitor A
0
-1
CLC1200
-2
-3
G=1
-4
VS = ±15V
-5
VOUT = 0.2Vpp
-6
-1
CLC1200
-2
-3
-4
G = 10
-5
VS = ±15V
VOUT = 0.2Vpp
-6
RL = 2kΩ
-7
RL = 2kΩ
-7
0.0001
0.001
0.01
0.1
1
10
0.0001
0.001
0.01
Frequency (MHz)
Frequency Response (G = 100)
10
65
75
CLC1200
Normalized Gain (dB)
-1
-2
-3
Competitor A
-4
G = 100
VS = ±15V
VOUT = 0.2Vpp
-1
-2
-4
G = 1,000
-5
-6
RL = 2kΩ
-7
Competitor A
-3
Rev 2C
Normalized Gain (dB)
1
0
CLC1200
VS = ±15V
VOUT = 0.2Vpp
RL = 2kΩ
-7
0.0001
0.001
0.01
0.1
1
10
0.0001
0.001
0.01
Frequency (MHz)
0.1
Frequency (MHz)
Large Signal Settling Time (G = 1)
Large Signal Settling Time (G = 10)
0.150
0.125
Competitor A
Competitor A
0.125
0.100
0.100
Output Amplitude (V)
Output Amplitude (V)
10
1
0
-6
1
Frequency Response (G = 1,000)
1
-5
0.1
Frequency (MHz)
0.075
CLC1200
0.050
0.025
0.000
CLC1200
0.075
0.050
0.025
0.000
VOUT = 0.1Vpp
-0.025
VOUT = 0.1Vpp
CL = 100pF
CL = 100pF
-0.050
-0.025
25
35
45
55
Time (us)
©2008, 2010-2011 CADEKA Microcircuits LLC 65
75
25
Comlinear CLC1200 Instrumentation Amplifier
3
35
45
55
Time (us)
www.cadeka.com
10
Data Sheet
Application Information
Follow these guidelines for improved performance:
Basic Operation
The internal resistors are trimmed which allows the gain to
be accurately adjusted with one external resistor RG.
G=
49.4k
RG
+ 1;
RG =
49.4k
series with RG
▪▪To minimize gain drift, use low TC resistors (<10ppm/°C)
Common Mode Rejection
The CLC1200 offers high CMRR. To acheive optimal CMRR
performance:
▪▪Connect
G-1
the reference terminal (pin 5) to a low
impedance source
RG also determines the transconductance of the
preamp stage. As RG is reduced for larger gains, the
transconductance increases to that of the input transistors.
Producing the following advantages:
▪▪Open-loop
gain increases as the gain is increased,
reducing gain releated errors
▪▪Gain-bandwidth
increases as the gain is increased,
optimizing frequency response
▪▪Reduced input voltage noise which is determined by the
▪▪Minimize capacitive and resistive differences between
the inputs
In many applications, shielded cables are used to
minimize noise. Properly drive the shield for best CMRR
performance over frequency. Figures 1 and 2 show active
data guards that are configured to improve AC commonmode rejections. the capacitances of input cable shields
are “bootstrapped” to minimize the capacitance mismatch
between the inputs.
collector current and base resistance of the input devices
+VS
+ Input
Gain Selection
RG / 2
_
100
CLC1200
CLCxxx
+
The impeadance between pins 1 and 8, RG, sets the gain
of the CLC1200. Table 1 shows the required standard
table values of RG for various calculated gains. For G =
1, RG = ∞.
RG / 2
+
- Input
Caclulated
Gain
0.1% RG (Ω)
Calculated
Gain
49.9k
1.990
49.3k
2.002
12.4k
4.984
12.4k
4.984
5.49k
9.998
5.49k
9.998
2.61k
19.93
2.61k
19.93
1.00k
50.40
1.01k
49.91
499
100.0
499
100.0
249
199.4
249
199.4
100
495.0
98.8
501.0
49.9
991.0
49.3
1,003.0
REF
-V S
Figure 1: Common-mode Shield Driver
+VS
+ Input
1% RG (Ω)
Output
100
_
+
RG
100
+
-V S
- Input
CLC1200
+
Output
REF
-V S
Figure 2: Differential Shield Driver
Table 1: Recommended RG Values
©2008, 2010-2011 CADEKA Microcircuits LLC www.cadeka.com
11
Rev 2C
_
Comlinear CLC1200 Instrumentation Amplifier
The CLC1200 is a monolithic instrumentation amplifier
based on the classic three op amp solution, refer to
the Functional Block Diagram on page 1. The CLC1200
produces a single-ended output reffered to the REF pin
potential.
▪▪To maintain gain accuracy, use 0.1% to 1% resistors
▪▪To minimize gain error, avoid high parasitic resistance in
Data Sheet
Medical ECG
The CLC1200 is especially suitable for higher resistance
pressure sensors powered at lower voltages where small
size and low power become more significant.
The CLC1200 is perfect for ECG monitors because of
its low current noise. A typical applicaiton is shown in
Figure 4. The CLC1200’s low power, low supply voltage
requirements, and space-saving 8-lead SOIC package
offerings make it an excellent choice for battery-powered
data recorders.
Figure 3 shows a 3kΩ pressure transducer bridge
powered from 5V. In such a circuit, the bridge consumes
only 1.7mA. Adding the CLC1200 and a buffered voltage
divider allows the signal to be conditioned for only 3.8mA
of total supply current.
Furthermore, the low bias currents and low current noise,
coupled with the low voltage noise of the CLC1200,
improve the dynamic range for better performance.
Small size and low cost make the CLC1200 especially
attractive for voltage output pressure transducers.
Since it delivers low noise and drift, it will also serve
applications such as diagnostic noninvasive blood pressure
measurement.
The value of capacitor C1 is chosen to maintain stability
of the right leg drive loop. Proper safeguards, such as
isolation, must be added to this circuit to protect the
patient from possible harm.
5V
5V
3k
3k
5V
20k
+
G = 100
3k
CLC1200
499
3k
Ref
_
10k
+
0.1mA
AGND
CLCxxx
_
Digital
Data
Output
Rev 2C
20k
1.7mA
IN
5V
REF
1.3mA
Figure 3: Pressure Monitoring Circuits Operating on a Single 5V Supply
3V
R1
10k
Patient
Patient/Circuit
Protection/Insulation
C1
+
R3
24.9k
R2
24.9k
R4
1M
CLC1200
G=7
8.25k
0.03Hz
High-Pass
Filter
_
_
Output
1V/mV
G = 143
-3V
CLCxxx
+
Figure 4: Typical Circuit for ECG Monitor Applications
©2008, 2010-2011 CADEKA Microcircuits LLC Comlinear CLC1200 Instrumentation Amplifier
Pressure Measurement Applications
www.cadeka.com
12
Data Sheet
Grounding
Comlinear CLC1200 Instrumentation Amplifier
The output voltage of the CLC1200 is developed with
respect to the potential on the reference terminal (pin 8).
Simply tie the REF pin to the appropriate “local ground” to
resolve many grounding problems.
To isolate low level analog signals from a noisy digital
environment, many data-aquisistion components have
separate analog and digital ground pins. Use separate
ground lines (analog and digital) to minimize current flow
from sensitive areas to system ground. These ground
returns must be tied together at some point, usually best
at the ADC.
Layout Considerations
General layout and supply bypassing play major roles in
high frequency performance. CADEKA has evaluation
boards to use as a guide for high frequency layout and as
an aid in device testing and characterization. Follow the
steps below as a basis for high frequency layout:
Figure 5. CEB00x Schematic
▪▪Include 6.8µF and 0.1µF ceramic capacitors for power
supply decoupling
Rev 2C
▪▪Place the 6.8µF capacitor within 0.75 inches of the power pin
▪▪Place the 0.1µF capacitor within 0.1 inches of the power pin
▪▪Remove the ground plane under and around the part,
especially near the input and output pins to reduce
parasitic capacitance
▪▪Minimize all trace lengths to reduce series inductances
Refer to the evaluation board layouts below for more
information.
Figure 6. CEB024 Top View
Evaluation Board Information
The following evaluation boards are available to aid in the
testing and layout of these devices:
Evaluation Board #
CEB024
Products
CLC1200 in SOIC-8
Evaluation Board Schematics
Evaluation board schematics and layouts are shown in
Figures 5-7. These evaluation boards are built for dualsupply operation. Follow these steps to use the board in a
single-supply application:
1. Short -Vs to ground.
2. Use C3 and C4, if the -VS pin of the amplifier is not
directly connected to the ground plane.
©2008, 2010-2011 CADEKA Microcircuits LLC Figure 7. CEB024 Bottom View
www.cadeka.com
13
Data Sheet
Comlinear CLC1200 Instrumentation Amplifier
Rev 2C
©2008, 2010-2011 CADEKA Microcircuits LLC www.cadeka.com
14
Data Sheet
Mechanical Dimensions
SOIC-8 Package
Comlinear CLC1200 Instrumentation Amplifier
Rev 2C
For additional information regarding our products, please visit CADEKA at: cadeka.com
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T: 970.663.5452
T: 877.663.5452 (toll free)
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Microcircuits LLC. All other brand and product names may be trademarks of their respective companies.
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