Rohm BD9305AFVM Single-output step-up,high-efficiency switching regulator(controller type) Datasheet

Large Current External FET Controller Type Switching Regulators
Single-output Step-up,High-efficiency
Switching Regulator(Controller Type)
BD9306AFVM
Single-output Step-up,High-efficiency
Switching Regulator(Controller Type)
BD9305AFVM
No.09028EAT04
Description
BD9305AFVM / BD9306AFVM are 1-channel DC/DC converter controllers. Step-down DC/DC converter can be configured
by BD9305AFVM, and Step-up DC/DC converter can be configured by BD9306AFVM. In addition, the master slave function,
which is that the synchronization is possible at the time of multi-connection, is mounted.
Features
1) 1ch PWM Control DC/DC Converter Controller
2) Input Voltage Range:4.2 to 18V
3) Feed Back Voltage:1.25±1.6%
4) Oscillating Frequency Variable:100 to 800kHz
5) Built-in Soft Start Function
6) Standby Current of 0 A (Typ.)
7) Built-in Master / Slave Function
8) Protection Circuit : Under Voltage Lockout Protection Circuit
Thermal Shutdown Circuit
Short Protection Circuit of Timer Latch type
9) MSOP8 Package
Applications
・TV, Power Supply for the TFT-LCD Panels used for LCD TVs, Back Lights
・DSC, DVC, Printer, DVD ,DVD Recorder, Generally Consumer Equipments etc.
Absolute maximum ratings (Ta = 25°C)
Parameter
Power supply voltage**
Power dissipation
Operating temperature range
Storage temperature range
Maximum junction temperature
Symbol
Limit
Unit
Vcc
20
V
Pd
588*
mW
Topr
-40 to +85
℃
Tstg
-55 to +150
℃
Tjmax
150
℃
* Reduced by 4.7 mW/°C over 25°C, when mounted on a glass epoxy 4-layer board (70 mm  70 mm  1.6 mm)
** Must not exceed Pd.
Recommended Operating Ranges (Ta=-40℃ to +85℃)
Parameter
Symbol
Limit
Min
Typ
Max
4.2
12
18
Unit
Power supply voltage
Vcc
Control Voltage
VENB
－
－
Vcc
V
Timing Capacity
CT
100
－
1000
pF
Timing Resistance
RT
5
－
50
kΩ
Fosc
100
－
800
kHz
Oscillating frequency
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1/14
V
2009.05 - Rev.A
Technical Note
BD9306AFVM, BD9305AFVM
Electrical Characteristics (Unless otherwise specified Ta=25℃,VCC=12V,CT=200pF,RT=20kΩ)
Limit
Parameter
Symbol
Unit
Min
Typ
Max
Conditions
【Triangular Waveform Oscillator Block】
Oscillating frequency
FOSC
165
220
275
kHz
Charge Threshold Voltage
VOSC＋
0.80
0.85
0.90
V
Discharge Threshold Voltage
VOSC－
0.20
0.25
0.30
V
VUT
3.5
－
4.2
V
Feed Back Voltage
VFB
1.230
1.250
1.270
V
Input Bias Current
IIB
－
0.05
1
µA
Vcc=5V
【Under-voltage lockout protection circuit】
Threshold Voltage
【Error amp Block】
FB=1.5V
COMP Sink Current
IOI
35
50
65
µA
FB=1.5V COMP=1.25V
COMP Source Current
IOO
35
50
65
µA
FB=1.0V
Ron
－
5
－
Ω
Gate Drive Voltage L
VGDL
－
0
0.5
V
No Load
Gate Drive Voltage H
COMP=1.25V
【Gate Drive Block】
ON Resistance
VGDH
Vcc-0.5
Vcc
－
V
No Load
MAX Duty (BD9305AFVM)
MDT
－
－
100
%
Vcc=5V
MAX Duty (BD9306AFVM)
MDT
－
83
－
%
Vcc=5V
ON Voltage
VON
2
－
－
V
OFF Voltage
VOFF
－
－
0.3
V
ENB Sink Current
IENB
40
60
90
µA
TS
－
10
－
ms
Latch Detection COMP Voltage
VLC
1.5
1.7
1.9
V
Latch Delay OSC Count Number
CNT
－
2200
－
COUNT
Latch Delay Time
DLY
－
10
－
ms
Standby Current
ISTB
－
0
10
µA
ENB=0FF
Average Consumption Current
ICC
1.0
1.5
2.5
mA
No Switching
【Control Block】
ENB=5V
【Soft Start Block】
Soft Start Time
【Timer Latch Protection Circuit】
【Overall】
*This product is not designed for protection against radio active rays.
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© 2009 ROHM Co., Ltd. All rights reserved.
2/14
2009.05 - Rev.A
Technical Note
BD9306AFVM, BD9305AFVM
Electrical Characteristics (Unless otherwise specified,VCC=12V, Ta=25℃)
300
4
Ta=25℃ Ta=85 ℃
0
Ta=40 ℃
-0.5
Ta=25℃
2
1
Ta=-40℃
0
-1
0
1
2
3
4
0
5
Fig.1 Standby Circuit Current
10
15
20
600
400
200
2
3
4
-200
-400
-600
-800
0
5
1
2
3
4
-60
-80
-100
0.5
1
1.5
20
2
2.5
COMP VOLTAGE:VCOMP[V]
Fig.7 COMP Source Current
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© 2009 ROHM Co., Ltd. All rights reserved.
0.5
1
1.5
2
2.5
COMP VOLTAGE:VCOMP[V]
Fig.6 COMP Sink Current
0.1
1.250
1.248
1.246
1.244
0
40
0
FB CURRENT:IFB[μA]
REFERENCE VOLTAGE:VFB[V
-40
85
0
5
1.252
-20
60
60
Fig.5 GD Source Current
0
35
80
GD VOLTAGE:VGD[V]
GD VOLTAGE:VGD[V]
Fig.4 GD Sink Current
10
100
-1000
0
-15
Fig.3 Frequency vs Temperature
COMP SINK CURRENT:ICOMP[μA]
GD SOURCE CURRENT:IGD[mA]
800
1
220
AMBIENT TEMPERATURE:Ta[℃]
0
0
240
200
-40
25
Fig.2 Average Consumption Current
1000
GD SINK CURRENT:IGD[mA]
5
260
INPUT VOLTAGE:VCC[V]
INPUT VOLTAGE:VCC[V]
COMP SOURCE CURRENT:ICOMP[μA]
280
Ta=85℃
3
FERQUENCY:FSW[kHz]
0.5
AVERAGE CURRENT:ICC[uA]
STAND BY CURRENT:ICC[uA]
1
-40
-15
10
35
60
85
AMBIENT TEMPERATURE:Ta[℃]
Fig.8 Feed Back vs Temperature
3/14
0.08
0.06
0.04
0.02
0
0.0
0.5
1.0
1.5
2.0
2.5
FB VOLTAGE:VFB[V]
Fig.9 FB Input Bias Current
2009.05 - Rev.A
Technical Note
BD9306AFVM, BD9305AFVM
Electrical Characteristics (Unless otherwise specified,Ta=25℃)
Ta=25℃
150
100
50
125
100
100
75
50
2.5
5.0
7.5
10.0
0
0.0
12.5
ENB VOLTAGE:VENB[V]
90
90
88
86
MAX DUTY:MDT[%]
84
82
80
-40
0.5
1.0
1.5
2.0
50
0
0.0
2.5
0.5
1.0
10
35
60
Fig.11 COMP vs DUTY
(BD9305AFVM)
Fig.12 COMP vs DUTY
(BD9306AFVM)
ΔV=166mV
Io=1A
78
VCC=12V Vo=5V
400
600
700
800
100
90
90
80
80
70
60
50
VCC=12V Vo=5V
Io=SWEEP
Fsw=220kHz
Ta=25℃
40
30
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60
50
VCC=12V Vo=16V
Io=SWEEP
Fsw=220kHz
Ta=25℃
40
30
10
0.5
1.0
1.5
2.0
OUTPUT CURRENT[A]
© 2009 ROHM Co., Ltd. All rights reserved.
70
20
10
0
0.0
Fig.16 Load Response
(BD9306AFVM)
Fig.15 Load Response
(BD9305AFVM)
100
20
VCC=12V Vo=16V
500
Fig.14 Frequency vs MAX Duty
(BD9306AFVM)
EFFICIENCY:EF[%]
Fig.13 Temperature vs MAX Duty
(BD9306AFVM)
Io=500mA
300
SWITCHING FREQUENCY[kHz]
AMBIENT TEMPERATURE[℃]
ΔV=380mV
2.5
82
70
200
85
2.0
COMP VOLTAGE:VCOMP[V]
74
-15
1.5
COMP VOLTAGE:VCOMP[V]
EFFICIENCY:EF[%]
MAX DUTY:MDT[%]
Fig.10 ENB Input Current
86
75
25
25
Ta=-40℃
0
0.0
DUTY CYCLE:DT[%]
Ta=85℃
200
125
DUTY CYCLE:DT[%]
ENB CURRENT:IENB[μA]
250
Fig.17 Efficiency Characteristics
(BD9305AFVM)
4/14
0
0.0
0.2
0.4
0.6
0.8
1.0
OUTPUT CURRENT[A]
Fig.18 Efficiency Characteristics
(BD9306AFVM)
2009.05 - Rev.A
Technical Note
BD9306AFVM, BD9305AFVM
Block Diagram
FB
1.25V
5
Vref
Timer
Latch
UVLO
TSD
Shut Down
VCC
GND
COMP
Vcc
6
Soft
Start
Err
FB
GND
COMP
7
8
Shut Down
PWM
OSC
DRV
VCC
ENABLE
2
1
FB
GD
ENB
CT
4
ENB
GD
GND
6
COMP
7
8
RT
3
CT
RT
Vcc
5
Soft
Start
Err
1.25V
Vref
Timer
Latch
UVLO
TSD
Shut Down
Shut Down
PWM
OSC
DRV
ENABLE
2
1
3
4
ENB
CT
RT
GD
Fig19. Pin Assignment Diagram & Block Diagram (Above:BD9305AFVM / Below:BD9306AFVM)
Pin Assignment and Pin Function
Pin No
Pin Name
Function
1
RT
Timing Resistance connection Pin
2
CT
Timing Capacity connection Pin
3
ENB
Control Pin
4
GD
Gate Drive Output Pin
5
Vcc
Power Supply Pin
6
GND
Ground pin
7
COMP
8
FB
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Error amp output Pin
Error amp inversion input Pin
5/14
2009.05 - Rev.A
Technical Note
BD9306AFVM, BD9305AFVM
Block Diagram / Application Circuit
10000ｐF
VCC
5.1ｋΩ
FB
GND
COMP
8
Vcc
6
7
10uF
5
Soft
Start
Err
1.25V
0.5Ω
Vref
Timer
Latch
Shut Down
UVLO
(When Output Short,
TSD
Protect Fall VCC)
Shut Down
47uH
OSC
Vo
DRV
PWM
VCC
20uF
1ｋΩ
30ｋΩ
470pF
ENABLE
1
3
2
20kΩ
4
ENB
CT
RT
10ｋΩ
200pF
GD
10kΩ
VCC
Fig.20 Block Diagram / Application Circuit (BD9305AFVM)
10000pF
3.9kΩ
FB
GND
COMP
8
Vcc
Soft
Start
Err
1.25V
10uF
5
6
7
47uH
Vref
Timer
Latch
UVLO
TSD
Shut Down
Shut Down
Vo
PWM
OSC
DRV
20uF
200kΩ
1kΩ
100pF
15kΩ
ENABLE
3
2
1
CT
RT
20Ω
200pF
4
ENB
GD
10kΩ
VCC
Fig.21 Block Diagram / Application Circuit (BD9306AFVM)
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6/14
2009.05 - Rev.A
Technical Note
BD9306AFVM, BD9305AFVM
Block Operation
・Error amplifier (Err)
It is a circuit that compares the standard voltage of 1.25V (TYP) and the feedback voltage of output voltage.
The switching Duty is determined by the COMP terminal voltage of this comparison result.
・Oscillator (OSC)
It is a block, in which the switching frequency is determined by RT and CT, and the triangular wave is determined by RT
and CT.
・PWM
The Duty is determined by comparing the output of Error amplifier and the angular wave of Oscillator.
The switching Duty of BD9306AFVM is limited by the maximum duty ratio that is determined by the internal part, and will
not be up to 100%.
・DRV
The gate of the power FET that is connected to the outside is driven by the switching Duty determined by PWM.
・VREF
It is a block that outputs the internal standard voltage of 2.5V (TYP).
The internal circuit is entirely the bearer of this standard voltage that is turned ON / OFF by the ENB terminal.
・Protection circuits (UVLO / TSD)
UVLO (low-voltage Lock Out circuit) shuts down the circuits when the voltage is below 3.5V (MIN).
Moreover, TSD (temperature protection circuit) shuts down the IC when the temperature reaches 175℃(TYP).
・Soft Start Circuit
The Soft Start Circuit limits the current at the time of startup while ramping up the output voltage slowly.
The overshoot of output voltage and the plunging current can be prevented.
・Timer Latch
It is an output short protection circuit that detects the output short if the output of error amplifier (COMP voltage) is more
than 1.7V (TYP). If the COMP voltage becomes more than 1.7V, the counter begins to operate, the LATCH is locked when
the counter counts to 2200, and the GD output shuts down. (＊the frequency of counter is determined by RT and CT.)
Once the LATCH is locked, the GD output does not operate until it is restarted by ENB or VCC. If the output short is
removed while the Timer latch is counting, the counter is reset.
Selecting Application Components
(1) Setting the output L constant (Step Down DC/DC)
The inductance L to use for output is decided by the rated current ILR and input current maximum value IOMAX of the
inductance.
IOMAX + IL should not
IL
2
reach the rated value level
VCC
ILR
IOMAX mean
current
IL
L
Co
t
Fig.22 Coil Current Waveform (Step Down DC/DC)
Vo
Fig.23 Output Application Circuit (Step Down DC/DC)
Adjust so that IOMAX + ΔIL / 2 does not reach the rated current value ILR.
At this time, ∆IL can be obtained by the following equation.
1
Vo
1
ΔIL=
X (Vcc-Vo)X
X
[A]
L
Vcc
f
Set with sufficient margin because the inductance L value may have the dispersion of ± 30%.
If the coil current exceeds the rating current ILR of the coil, it may damage the IC internal element.
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2009.05 - Rev.A
Technical Note
BD9306AFVM, BD9305AFVM
(2) Setting the output L constant (Step Up DC/DC)
The inductance L to use for output is decided by the rated current ILR and input current maximum value IINMAX of the
inductance.
VCC
IINMAX+ΔIL should not
2
reach the rated value level
IL
L
IL
Vo
IINMAX mean
current
Co
t
Fig.24 Coil Current Waveform (Step Up DC/DC)
Fig.25 Output Application Circuit (Step Up DC/DC)
Adjust so that IINMAX + ΔIL / 2 does not reach the rated current value ILR.
At this time, ∆IL can be obtained by the following equation.
ΔIL=
1
L
Vcc X
Vo-Vcc
Vo
X
1
ｆ
[A]
Where, f is the switching frequency
Set with sufficient margin because the inductance L value may have the dispersion of ± 30%.
If the coil current exceeds the rating current ILR of the coil, it may damage the IC internal element.
(3) Setting the output capacitor
For the capacitor C to use for the output, select the capacitor which has the larger value in the ripple voltage VPP
allowance value and the drop voltage allowance value at the time of sudden load change.
Output ripple voltage is decided by the following equation.
ΔIL
Vo
1
X
X
[V]
ΔVPP = ΔIL X RESR +
2Co
Vcc
f
ΔVPP
= ILMAX X RESR +
1
fCo
X
Vcc
Vo
X (ILMAX -
(Step Down DC/DC)
ΔIL
2
) [V]
(Step Up DC/DC)
Perform setting so that the voltage is within the allowable ripple voltage range.
For the drop voltage during sudden load change; VDR, please perform the rough calculation by the following equation.
ΔI
X 10μ sec [V]
VDR =
Co
However, 10 s is the rough calculation value of the DC/DC response speed. Please set the capacitance considering the
sufficient margin so that these two values are within the standard value range.
(4)Setting of feedback resistance constant
For both BD9305AFVM (step down) and BD9306AFVM (step up), please refer to the following formula for setting of
feedback resistance.
We recommend 10kΩ~330kΩ as the setting range. If a resistance below 10kΩ is set, a drop in voltage efficiency will be
caused; if a resistance more than 330kΩ is set, the offset voltage becomes large because of the internal error amplifier’s
input bias current of 0.05µA(Typ). Please set the maximum setting voltage of BD9306AFVM (step up) in such a way that
Duty : (Vo - Vcc) / Vo is less than 70%.
Reference Voltage 1.25V
Vo
Vo ＝
R1 + R2
R2
x 1.25
R1
[V]
FB
R2
8
－
ERR
＋
Fig.26 Feedback Resistance Setting
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8/14
2009.05 - Rev.A
Technical Note
BD9306AFVM, BD9305AFVM
(5) Setting of oscillation frequency
The angular wave oscillation frequency can be set by respectively connecting resistor and condenser to RT (1 pin) and CT
(2 pins). The currents to charge and discharge the condenser of CT are determined by RT.
Please refer to the following drawing for setting the RT’s resistor and the CT’s condenser.
RT:5~50kΩ, CT:100~1000pF, and the frequency range of 100kHz~800kHz are recommended.
Please pay attention to that, the switching will stop if your setting is off this range.
Frequency [kHz]
10000
1000
Ta=25℃
VCC=12V
CT=100pF
CT=200pF
CT=470pF
CT=1000pF
100
10
1
10
100
RT [kΩ]
Fig.27 Frequency Setting
(6)Selection of input condenser
For DC/DC converter, the condenser at the input side is also necessary because peak current is flowing between input
and output. Therefore, we recommend the low ESR condenser with over 10μF and below 100mΩ as the input condenser.
If a selected condenser is off this range, excessively large ripple voltage will overlaps with the input voltage, which may
cause IC malfunction.However, this condition varies with negative overcurrent, input voltage, output voltage, inductor’s
value, and switching frequency, so please be sure to do the margin check with actual devices.
(7)Selection of output rectifier diode
We recommend the Schottky barrier diode as the diode for rectification at the output stage of DC/DC converter. Please be
careful to choose the maximum inductor current, the maximum output voltage and the power supply voltage.
＜step-down DC/DC＞
＜
Diode’s rated current
Maximum inductor current
IOMAX ＋ ⊿IL
2
Power supply voltage
＜step-up DC/DC＞
Maximum inductor current
VCC
IINMAX ＋ ⊿IL
2
＜
Diode’s rated voltage
＜
Diode’s rated current
＜
Diode’s rated voltage
Maximum output voltage
VOMAX
Furthermore, each parameter has a deviation of 30%~40%, so please design in such a way that you have left a
sufficient margin for deviation in your design.
(8)Setting of Power FET
If step-down DC/DC is configured by BD9305AFVM, Pch FET is necessary; if step-up DC/DC is configured by
BD9306AFVM, Nch FET is necessary.
Please pay attention to the following conditions when you choose.
＜step-down DC/DC＞
＜
FET’s rated current
Maximum inductor current
IOMAX ＋ ⊿IL
2
Power supply voltage
VCC
Power supply voltage
Gate capacity (※)
＜step-up DC/DC＞
Maximum inductor current
Maximum output voltage
Power supply voltage
＜
FET’s rated voltage
VCC
＞
FET’s gate ON voltage
＜
2000pF
CGATE
IINMAX ＋ ⊿IL
2
＜
FET’s rated current
VOMAX
VCC
＜
＞
FET’s rated voltage
FET’s gate ON voltage
＜
2000pF
Gate capacity (※)
CGATE
Furthermore, each parameter has a deviation of 30%~40%, so please design in such a way that you have left a sufficient
margin for deviation in your design.
(※) If Gate capacity becomes large, the switch’s switching speed gets slow, which may cause generation of heat and breakdown,
so please check thoroughly with actual devices.
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9/14
2009.05 - Rev.A
Technical Note
BD9306AFVM, BD9305AFVM
(9) Phase compensation
Phase Setting Method
The following conditions are required in order to ensure the stability of the negative feedback circuit.
Phase lag should be 150° or lower during gain 1 (0 dB) (phase margin of 30° or higher).
Because DC/DC converter applications are sampled using the switching frequency, the overall GBW should be set to 1/10
the switching frequency or lower. The target application characteristics can be summarized as follows:
Phase lag should be 150° or lower during gain 1 (0 dB) (phase margin of 30° or higher).
The GBW at that time (i.e., the frequency of a 0-dB gain) is 1/10 of the switching frequency or below.
In other words, because the response is determined by the GBW limitation, it is necessary to use higher switching
frequencies to raise response.
One way to maintain stability through phase compensation involves canceling the secondary phase lag (-180°) caused by
LC resonance with a secondary phase advance (by inserting 2 phase advances).
The GBW (i.e., the frequency with the gain set to 1) is determined by the phase compensation capacitance connected to
the error amp. Increase the capacitance if a GBW reduction is required.
(a) Standard integrator (low-pass filter)
(b) Open loop characteristics of integrator
(a)
A
＋
COMP
A
Feedback R
-20 dB/decade
Gain
[dB]
GBW(b)
0
－
FB
F
0
C
-90°
Phase
-90
[°]
Phase margin
-180°
-180
Point (a)
fa =
Fig. 28
1
2πRCA
[Hz]
Point (b)
fb = GBW =
F
Fig. 29
1
2πRC
[Hz]
The error amp performs phase compensation of types (a) and (b), making it act as a low-pass filter.
For DC/DC converter applications, R refers to feedback resistors connected in parallel.
From the LC resonance of output, the number of phase advances to be inserted is two.
LC resonant frequency fp =
Vo
R1
R4
C1
－
R2
＋
A
COMP
1
2π√LC
[Hz]
Phase advance
fz1 =
1
2πC1R1
[Hz]
Phase advance
fz2 =
1
2πC2R3
[Hz]
R3
C2
Fig. 30
Set a phase advancing frequency close to the LC resonant frequency for the purpose of canceling the LC resonance.
(※ )If high-frequency noise is generated in the output, FB is affected through condenser C1.
Therefore, please insert the resistor R4=1kΩ or so, which is in series with condenser C1.
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10/14
2009.05 - Rev.A
Technical Note
BD9306AFVM, BD9305AFVM
Example of application
※We recommend the application circuit examples with confidence, but hope that you will thoroughly check the characteristics
over again when putting them to use.
When you change the external circuit constant and use, please make a decision to leave a sufficient margin after taking
into consideration the deviation etc. of external components and ROHM IC, in terms of not only the static characteristic but
also the transient characteristic.
Moreover, please understand that our company can not confirm fully with regard to the patent right.
＜Master Slave Function＞
The master slave function, which is that the synchronous switching is possible by using these IC of BD9305AFVM /
BD9306AFVM through their multi-connection, is mounted. The following drawing shows an example of connection circuit
in which BD9305AFVM is connected on the master side and BD9306AFVM is connected on the slave side.
CTL0
VCC
GD
ENB
RT
(Slave Side)
GD
ENB
CT
RT
GND
BD9306AFVM
(Master Side)
RT
COMP
FB
GND
VCC
CTL2
BD9305AFVM
CT
CTL1
COMP
FB
VCC
Vo2
CT
Vo1
Fig.31 Master Slave Application Circuit
In the above-mentioned circuit, BD9306AFVM, which is synchronized with the switching frequency determined by RT and
CT of BD9305AFVM that is the master, operates.In addition, the ON/OFF of output can be controlled by connecting the
switch to the COMP terminal. (Refer to the following table)
Control signal correspondence table
Output state
Control signal
Vo1
Vo2
CTL0
CTL1
CTL2
OFF
OFF
Low
＊
＊
OFF
ON
High
High
Low
ON
OFF
High
Low
High
ON
ON
High
Low
Low
＊The same in either case of High / Low.
Similarly in the case of connecting three or more than three, synchronization is possible by connecting the CT terminal of
Master and the CT terminal of Slave
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© 2009 ROHM Co., Ltd. All rights reserved.
11/14
2009.05 - Rev.A
Technical Note
BD9306AFVM, BD9305AFVM
I/O Equivalent Circuit Diagram Fig.32
1.RT
4.GD
VCC
VCC
VREF
A
A:
2.CT
VCC(BD9305AFVM)
GND(BD9306AFVM)
7.COMP
VCC
VCC
VREF
VREF
3.ENB
8.FB
VCC
VREF
Fig. 32
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© 2009 ROHM Co., Ltd. All rights reserved.
12/14
2009.05 - Rev.A
Technical Note
BD9306AFVM, BD9305AFVM
Notes for use
1) Absolute maximum ratings
Use of the IC in excess of absolute maximum ratings such as the applied voltage or operating temperature range may
result in IC damage. Assumptions should not be made regarding the state of the IC (short mode or open mode) when such
damage is suffered. A physical safety measure such as a fuse should be implemented when use of the IC in a special
mode where the absolute maximum ratings may be exceeded is anticipated.
2) GND potential
Ensure a minimum GND pin potential in all operating conditions.
3) Setting of heat
Use a thermal design that allows for a sufficient margin in light of the power dissipation (Pd) in actual operating conditions.
4) Pin short and mistake fitting
Use caution when orienting and positioning the IC for mounting on printed circuit boards. Improper mounting may result in
damage to the IC. Shorts between output pins or between output pins and the power supply and GND pins caused by the
presence of a foreign object may result in damage to the IC.
5) Actions in strong magnetic field
Use caution when using the IC in the presence of a strong magnetic field as doing so may cause the IC to malfunction.
6) Testing on application boards
When testing the IC on an application board, connecting a capacitor to a pin with low impedance subjects the IC to stress.
Always discharge capacitors after each process or step. Ground the IC during assembly steps as an antistatic measure,
and use similar caution when transporting or storing the IC. Always turn the IC's power supply off before connecting it to or
removing it from a jig or fixture during the inspection process.
7) Ground wiring patterns
When using both small signal and large current GND patterns, it is recommended to isolate the two ground patterns,
placing a single ground point at the application's reference point so that the pattern wiring resistance and voltage
variations caused by large currents do not cause variations in the small signal ground voltage. Be careful not to change the
GND wiring patterns of any external components.
8) Regarding input pin of the IC
This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them isolated.
P/N junctions are formed at the intersection of these P layers with the N layers of other elements to create a variety of
parasitic elements.For example, when the resistors and transistors are connected to the pins shown as follows, a parasitic
diode or a transistor operates by inverting the pin voltage and GND voltage.
The formation of parasitic elements as a result of the relationships of the potentials of different pins is an inevitable result
of the IC's architecture. The operation of parasitic elements can cause interference with circuit operation as well as IC
malfunction and damage. For these reasons, it is necessary to use caution so that the IC is not used in a way that will
trigger the operation of parasitic elements such as by the application of voltages lower than the GND (P substrate) voltage
to input and output pins.
Example of a SimpleMonolithic IC Architecture
Resistor
Transistor (NPN)
B
C
B
E
～
～
～
～
(Pin B)
(Pin B)
～
～
(Pin A)
GND
N
N
P
P
P+
N
N
N
N
(Pin A)
P substrate
Parasitic elements
GND
Parasitic
elements
P+
～
～
P+
Parasitic elements
E
GND
N
P
P+
C
Parasitic
elements
GND
GND
Fig. 33
9) Overcurrent protection circuits
An overcurrent protection circuit designed according to the output current is incorporated for the prevention of IC damage
that may result in the event of load shorting. This protection circuit is effective in preventing damage due to sudden and
unexpected accidents. However, the IC should not be used in applications characterized by the continuous operation or
transitioning of the protection circuits. At the time of thermal designing, keep in mind that the current capacity has negative
characteristics to temperatures.
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13/14
2009.05 - Rev.A
Technical Note
BD9306AFVM, BD9305AFVM
Ordering part number
B
D
Part No.
9
3
0
6
A
F
Part No.
9306A
9305A
V
M
Package
FVM: MSOP8
-
T
R
Packaging and forming specification
TR: Embossed tape and reel
MSOP8
<Tape and Reel information>
2.8±0.1
4.0±0.2
8 7 6 5
0.6±0.2
+6°
4° −4°
0.29±0.15
2.9±0.1
(MAX 3.25 include BURR)
Tape
Embossed carrier tape
Quantity
3000pcs
Direction
of feed
TR
The direction is the 1pin of product is at the upper right when you hold
( reel on the left hand and you pull out the tape on the right hand
)
1 2 3 4
1PIN MARK
1pin
+0.05
0.145 –0.03
0.475
0.08±0.05
0.75±0.05
0.9MAX
S
+0.05
0.22 –0.04
0.08 S
Direction of feed
0.65
(Unit : mm)
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© 2009 ROHM Co., Ltd. All rights reserved.
Reel
14/14
∗ Order quantity needs to be multiple of the minimum quantity.
2009.05 - Rev.A
Notice
Notes
No copying or reproduction of this document, in part or in whole, is permitted without the
consent of ROHM Co.,Ltd.
The content specified herein is subject to change for improvement without notice.
The content specified herein is for the purpose of introducing ROHM's products (hereinafter
"Products"). If you wish to use any such Product, please be sure to refer to the specifications,
which can be obtained from ROHM upon request.
Examples of application circuits, circuit constants and any other information contained herein
illustrate the standard usage and operations of the Products. The peripheral conditions must
be taken into account when designing circuits for mass production.
Great care was taken in ensuring the accuracy of the information specified in this document.
However, should you incur any damage arising from any inaccuracy or misprint of such
information, ROHM shall bear no responsibility for such damage.
The technical information specified herein is intended only to show the typical functions of and
examples of application circuits for the Products. ROHM does not grant you, explicitly or
implicitly, any license to use or exercise intellectual property or other rights held by ROHM and
other parties. ROHM shall bear no responsibility whatsoever for any dispute arising from the
use of such technical information.
The Products specified in this document are intended to be used with general-use electronic
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While ROHM always makes efforts to enhance the quality and reliability of its Products, a
Product may fail or malfunction for a variety of reasons.
Please be sure to implement in your equipment using the Products safety measures to guard
against the possibility of physical injury, fire or any other damage caused in the event of the
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The Products are not designed or manufactured to be used with any equipment, device or
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