Precision, Dual-Channel Instrumentation Amplifier AD8222 Data Sheet OUT1 OUT2 –VS FUNCTIONAL BLOCK DIAGRAM Two channels in small 4 mm × 4 mm LFCSP Gain set with 1 resistor per amplifier (G = 1 to 10,000) Low noise 8 nV/√Hz at 1 kHz 0.25 µV p-p (0.1 Hz to 10 Hz) High accuracy dc performance (B grade) 60 µV maximum input offset voltage 0.3 µV/°C maximum input offset drift 1.0 nA maximum input bias current 126 dB minimum CMRR (G = 100) Excellent ac performance 140 kHz bandwidth (G = 100) 13 µs settling time to 0.001% Differential output option (single channel) Fully specified Adjustable common-mode output Supply range: ±2.3 V to ±18 V +VS FEATURES 16 15 14 13 AD8222 RG2 RG1 3 10 RG2 +IN1 4 9 +IN2 +VS 5 6 7 8 05947-001 –IN2 11 –VS 12 RG1 2 REF2 1 REF1 –IN1 Figure 1. APPLICATIONS Multichannel data acquisition for ECG and medical instrumentation Industrial process controls Wheatstone bridge sensors Differential drives for High resolution input ADCs Remote sensors AD8222 maintains a minimum CMRR of 80 dB to 4 kHz for all grades at G = 1. High CMRR over frequency allows the AD8222 to reject wideband interference and line harmonics, greatly simplifying filter requirements. The AD8222 also has a typical CMRR drift over temperature of just 0.07 µV/V/°C at G = 1. GENERAL DESCRIPTION The AD8222 is a dual-channel, high performance instrumentation amplifier that requires only one external resistor per amplifier to set gains of 1 to 10,000. The AD8222 is the first dual-instrumentation amplifier in the small 4 mm × 4mm LFCSP. It requires the same board area as a typical single instrumentation amplifier. The smaller package allows a 2× increase in channel density and a lower cost per channel, all with no compromise in performance. The AD8222 can also be configured as a single-channel, differential output instrumentation amplifier. Differential outputs provide high noise immunity, which can be useful when the output signal must travel through a noisy environment, such as with remote sensors. The configuration can also be used to drive differential input analog-to-digital converters (ADCs). The Rev. B The AD8222 operates on both single and dual supplies and only requires 2.2 mA maximum supply current for both amplifiers. It is specified over the industrial temperature range of −40°C to +85°C and is fully RoHS compliant. For a single-channel version, see the AD8221. Table 1. Instrumentation Amplifiers by Category1 GeneralPurpose AD8220 AD8221 AD8222 AD8224 AD8228 AD8295 1 Zero Drift AD8231 AD8290 AD8293G80 AD8553 AD8556 AD8557 Military Grade AD620 AD621 AD524 AD526 AD624 Low Power AD8235 AD8236 AD627 AD623 AD8223 AD8226 AD8227 High Speed PGA AD8250 AD8251 AD8253 See www.analog.com for the latest selection of instrumentation amplifiers. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2006–2016 Analog Devices, Inc. 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Technical Support www.analog.com AD8222* Product Page Quick Links Last Content Update: 11/01/2016 Comparable Parts Reference Materials View a parametric search of comparable parts Technical Articles • Auto-Zero Amplifiers • High-performance Adder Uses Instrumentation Amplifiers Evaluation Kits • AD8222 Evaluation Board Design Resources Documentation Application Notes • AN-1401: Instrumentation Amplifier Common-Mode Range: The Diamond Plot • AN-282: Fundamentals of Sampled Data Systems • AN-671: Reducing RFI Rectification Errors in In-Amp Circuits • AN-683: Strain Gage Measurement Using an AC Excitation Data Sheet • AD8222: Precision, Dual-Channel Instrumentation Amplifier Data Sheet Technical Books • A Designer's Guide to Instrumentation Amplifiers, 3rd Edition, 2006 • • • • AD8222 Material Declaration PCN-PDN Information Quality And Reliability Symbols and Footprints Discussions View all AD8222 EngineerZone Discussions Sample and Buy Visit the product page to see pricing options Technical Support Submit a technical question or find your regional support number Tools and Simulations • AD8222 SPICE Macro-Model * This page was dynamically generated by Analog Devices, Inc. and inserted into this data sheet. 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AD8222 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Package Considerations ............................................................. 16 Applications ....................................................................................... 1 Layout .......................................................................................... 16 Functional Block Diagram .............................................................. 1 Input Bias Current Return Path ............................................... 17 General Description ......................................................................... 1 Input Protection ......................................................................... 18 Revision History ............................................................................... 2 RF Interference ........................................................................... 18 Specifications..................................................................................... 3 Common-Mode Input Voltage Range ..................................... 18 Absolute Maximum Ratings............................................................ 6 Applications Information .............................................................. 19 Thermal Resistance ...................................................................... 6 Differential Output .................................................................... 19 ESD Caution .................................................................................. 6 Driving a Differential Input ADC ............................................ 20 Pin Configuration and Function Descriptions ............................. 7 Precision Strain Gage ................................................................. 20 Typical Performance Characteristics ............................................. 8 Driving Cabling .......................................................................... 21 Theory of Operation ...................................................................... 15 Outline Dimensions ....................................................................... 22 Amplifier Architecture .............................................................. 15 Ordering Guide .......................................................................... 23 Gain Selection ............................................................................. 15 Reference Terminal .................................................................... 16 REVISION HISTORY 5/2016—Rev. A to Rev. B Changed CP-16-13 to CP-16-26 .................................. Throughout Change to Table 5 ............................................................................. 6 Changes to Figure 2 and Table 7 ..................................................... 7 Added Figure 3; Renumbered Sequentially .................................. 7 Change to Input Protection Section ............................................. 18 Updated Outline Dimensions ....................................................... 22 Changes to Ordering Guide .......................................................... 23 2/2010—Rev. 0 to Rev. A Added LFCSP_VQ, CP-16-13 Package ............................ Universal Changes to Features Section and Table 1 ...................................... 1 Changed VIN+ to V+IN, VIN− to V−IN, and T to TA Throughout ..... 3 Change to Reference Input Parameter, Table 2 ............................. 4 Changed Output Short-Circuit Current to Output Short-Circuit Duration, Table 5 .............................................................................. 6 Changes to Thermal Resistance Section and Table 6 ...................6 Changes to Figure 2 ...........................................................................7 Changes to Figure 19...................................................................... 10 Changes to Figure 43...................................................................... 14 Changes to Reference Terminal Section, Figure 45, and Package Considerations Section .................................................................. 16 Deleted Thermal Pad Section ....................................................... 16 Added Package Without Thermal Pad and Package with Thermal Pad Sections .................................................................... 16 Changes to Figure 46...................................................................... 17 Deleted Solder Wash Section ........................................................ 17 Changes to RFI and Antialising Filter Section ........................... 20 Updated Outline Dimensions ....................................................... 22 Changes to Ordering Guide .......................................................... 23 7/2006—Revision 0: Initial Version Rev. B | Page 2 of 24 Data Sheet AD8222 SPECIFICATIONS VS = ±15 V, VREF = 0 V, TA = 25°C, G = 1, RL = 2 kΩ, unless otherwise noted. Table 2. Single-Ended and Differential 1 Output Configuration Parameter COMMON-MODE REJECTION RATIO (CMRR) CMRR DC to 60 Hz G=1 G = 10 G = 100 G = 1000 CMRR at 4 kHz G=1 G = 10 G = 100 G = 1000 CMRR Drift NOISE Voltage Noise, 1 kHz Input Voltage Noise, eNI Output Voltage Noise, eNO RTI G=1 G = 10 G = 100 to 1000 Current Noise VOLTAGE OFFSET Input Offset, VOSI Over Temperature Average TC Output Offset, VOSO Over Temperature Average TC Offset RTI vs. Supply (PSR) G=1 G = 10 G = 100 G = 1000 INPUT CURRENT (PER CHANNEL) Input Bias Current, IBIAS Over Temperature Average TC Input Offset Current, IOFFSET Over Temperature Average TC Test Conditions/Comments VCM = –10 V to +10 V Min A Grade Typ Max Min B Grade Typ Max Unit 1 kΩ source imbalance 80 100 120 130 86 106 126 140 dB dB dB dB 80 90 100 100 80 100 110 110 dB dB dB dB µV/V/°C TA = −40°C to +85°C, G = 1 0.07 RTI noise = √(eNI2 + (eNO/G)2) V+IN, V−IN, VREF = 0 V V+IN, V−IN, VREF = 0 V f = 0.1 Hz to 10 Hz 0.07 8 75 8 75 2 0.5 0.25 40 6 f = 1 kHz f = 0.1 Hz to 10 Hz RTI VOS = (VOSI) + (VOSO/G) VS = ±5 V to ±15 V TA = −40°C to +85°C 2 0.5 0.25 40 6 120 150 0.4 500 0.8 9 VS = ±5 V to ±15 V TA = −40°C to +85°C nV/√Hz nV/√Hz µV p-p µV p-p µV p-p fA/√Hz pA p-p 60 80 0.3 350 0.5 5 µV µV µV/°C µV mV µV/°C VS = ±2.3 V to ±18 V 90 110 124 130 110 120 130 140 0.5 TA = −40°C to +85°C 1 0.2 TA = −40°C to +85°C 1 Rev. B | Page 3 of 24 94 114 130 140 2.0 3.0 1 1.5 110 130 140 150 0.2 1 0.1 0.5 dB dB dB dB 1.0 1.5 0.5 0.6 2 nA nA pA/°C nA nA pA/°C AD8222 Parameter REFERENCE INPUT RIN IIN Voltage Range Reference Gain to Output Reference Gain Error GAIN Gain Range Gain Error G=1 G = 10 G = 100 G = 1000 Gain Nonlinearity G=1 G = 10 G = 100 Gain vs. Temperature G=1 G > 12 INPUT Input Impedance Differential Common Mode Input Operating Voltage Range3 Over Temperature Input Operating Voltage Range3 Over Temperature OUTPUT Output Swing Over Temperature Output Swing Over Temperature Short-Circuit Current POWER SUPPLY Operating Range Quiescent Current (per Amplifier) Over Temperature TEMPERATURE RANGE Specified Performance Operational 4 Data Sheet Test Conditions/Comments Min A Grade Typ Max 20 50 V+IN, V−IN, VREF = 0 V −VS 60 +VS Min B Grade Typ Max 20 50 −VS 1 0.01 60 +VS 1 0.01 Unit kΩ µA V V/V % G = 1 + (49.4 kΩ/RG) 1 10,000 1 10,000 V/V 0.02 0.15 0.15 0.15 % % % % VOUT ± 10 V 0.05 0.3 0.3 0.3 VOUT = –10 V to +10 V 3 7 7 10 20 20 1 7 7 5 20 20 ppm ppm ppm 3 10 −50 2 5 −50 ppm/°C ppm/°C GΩ||pF GΩ||pF V V V V 100||2 100||2 VS = ±2.3 V to ±5 V TA = −40°C to +85°C VS = ±5 V to ±18 V TA = −40°C to +85°C RL = 10 kΩ VS = ±2.3 V to ±5 V TA = −40°C to +85°C VS = ±5 V to ±18 V TA = −40°C to +85°C 100||2 100||2 −VS + 1.9 −VS + 2.0 −VS + 1.9 −VS + 2.0 +VS − 1.1 +VS − 1.2 +VS − 1.2 +VS − 1.2 −VS + 1.9 −VS + 2.0 −VS + 1.9 −VS + 2.0 +VS − 1.1 +VS − 1.2 +VS − 1.2 +VS − 1.2 −VS + 1.1 −VS + 1.4 −VS + 1.2 −VS + 1.6 +VS − 1.2 +VS − 1.3 +VS − 1.4 +VS − 1.5 −VS + 1.1 −VS + 1.4 −VS + 1.2 −VS + 1.6 +VS − 1.2 +VS − 1.3 +VS − 1.4 +VS − 1.5 V V V V mA ±18 1.1 1.2 V mA mA +85 +125 °C °C 18 VS = ±2.3 V to ±18 V ±2.3 0.9 1 TA = −40°C to +85°C −40 −40 Refers to differential configuration shown in Figure 50. Does not include the effects of external resistor, RG. 3 One input grounded. G = 1. 4 See the Typical Performance Characteristics section for expected operation between 85°C and 125°C. 1 2 Rev. B | Page 4 of 24 18 ±18 1.1 1.2 ±2.3 +85 +125 −40 −40 0.9 1 Data Sheet AD8222 VS = ±15 V, VREF = 0 V, TA = 25°C, RL = 2 kΩ, unless otherwise noted. Table 3. Single-Ended Output Configuration—Dynamic Performance (Both Amplifiers) Parameter DYNAMIC RESPONSE Small Signal −3 dB Bandwidth G=1 G = 10 G = 100 G = 1000 Settling Time 0.01% G = 1 to 100 G = 1000 Settling Time 0.001% G = 1 to 100 G = 1000 Slew Rate Test Conditions/Comments Min A Grade Typ Max B Grade Typ Max Unit 1200 750 140 15 1200 750 140 15 kHz kHz kHz kHz 10 80 10 80 µs µs 13 110 2 2.5 1.5 2 13 110 2 2.5 µs µs V/µs V/µs A Grade Typ Max Min B Grade Typ Max Unit 1000 650 140 15 1000 650 140 15 kHz kHz kHz kHz 15 80 15 80 µs µs 18 110 2 2.5 18 110 2 2.5 µs µs V/µs V/µs Min 10 V step 10 V step G=1 G = 5 to 1000 1.5 2 Table 4. Differential Output Configuration 1—Dynamic Performance Parameter DYNAMIC RESPONSE Small Signal −3 dB Bandwidth G=1 G = 10 G = 100 G =1000 Settling Time 0.01% G = 1 to 100 G = 1000 Settling Time 0.001% G = 1 to 100 G = 1000 Slew Rate 1 Test Conditions/Comments Min 10 V step 10 V step G=1 G = 5 to 1000 1.5 2 Refers to differential configuration shown in Figure 50. Rev. B | Page 5 of 24 1.5 2 AD8222 Data Sheet ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 5. Parameter Supply Voltage Output Short-Circuit Current Duration Input Voltage (Common Mode) Differential Input Voltage Storage Temperature Range Operational Temperature Range Package Glass Transition Temperature (TG) ESD Human Body Model Charge Device Model Rating ±18 V Indefinite ±VS ±VS −65°C to +130°C −40°C to +125°C 130°C 2 kV 1 kV Table 6. Package CP-16-19: LFCSP Without Thermal Pad CP-16-26: LFCSP with Thermal Pad θJA 86 48 Unit °C/W °C/W The θJA values in Table 6 assume a 4-layer JEDEC standard board. For the LFCSP with thermal pad, it is assumed that the thermal pad is soldered to a landing on the PCB board, with the landing thermally connected to a heat dissipating power plane. θJC at the exposed pad is 4.4°C/W. Maximum Power Dissipation Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. The maximum safe power dissipation for the AD8222 is limited by the associated rise in junction temperature (TJ) on the die. At approximately 130C, which is the glass transition temperature, the plastic changes its properties. Even temporarily exceeding this temperature limit may change the stresses that the package exerts on the die, permanently shifting the parametric performance of the amplifiers. Exceeding a temperature of 130°C for an extended period can result in a loss of functionality. ESD CAUTION Rev. B | Page 6 of 24 Data Sheet AD8222 +IN1 4 AD8222 TOP VIEW 13 –VS 14 OUT2 15 OUT1 16 +VS 12 –IN2 –IN1 1 11 RG2 10 RG2 9 +IN2 12 –IN2 RG1 2 AD8222 11 RG2 RG1 3 TOP VIEW (Not to Scale) 10 RG2 9 +IN2 –VS 8 REF2 7 +VS 5 REF1 6 05947-002 –VS 8 +VS 5 REF1 6 REF2 7 +IN1 4 NOTES 1. THE EXPOSED PAD MUST BE CONNECTED TO –VS. Figure 3. 16-Lead LFCSP (CP-16-26) Pin Configuration Figure 2. 16-Lead LFCSP (CP-16-19) Pin Configuration Table 7. Pin Function Descriptions Pin No. CP-16-19 1 2, 3 4 5, 16 6 7 8, 13 9 10, 11 12 14 15 Not applicable CP-16-26 1 2, 3 4 5, 16 6 7 8, 13 9 10, 11 12 14 15 0 Mnemonic −IN1 RG1 +IN1 +VS REF1 REF2 −VS +IN2 RG2 −IN2 OUT2 OUT1 EPAD 05947-102 PIN 1 INDICATOR –IN1 1 RG1 2 RG1 3 15 OUT1 14 OUT2 13 –VS 16 +VS PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS Description Negative Input In-Amp 1. Gain Resistor In-Amp 1. Positive Input In-Amp 1. Positive Supply. Reference Adjust In-Amp 1. Reference Adjust In-Amp 2. Negative Supply. Positive Input In-Amp 2. Gain Resistor In-Amp 2. Negative Input In-Amp 2. Output In-Amp 2. Output In-Amp 1. Exposed Pad. The exposed pad must be connected to −VS. Rev. B | Page 7 of 24 AD8222 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS N = 1713 500 800 NUMBER OF UNITS 300 200 600 400 –40 –30 –20 –10 0 10 20 30 40 50 CMRR (µV/V) 0 –2.0 05947-003 0 –50 INPUT COMMON-MODE RANGE (V) NUMBER OF UNITS 200 150 100 40 20 0 20 40 60 80 100 VOSI (µV) 0.5 1.0 1.5 2.0 10 VS = ±15V 5 0 VS = ±5V –5 –10 –15 –15 05947-004 10 60 0 15 250 80 –0.5 Figure 7. Typical Distribution of Input Offset Current N = 1713 0 –100 –1.0 IOFFSET (nA) Figure 4. Typical Distribution for CMRR (G = 1) 300 –1.5 05947-006 200 100 –10 –5 0 5 10 15 OUTPUT VOLTAGE (V) 05947-007 NUMBER OF UNITS 400 Figure 8. Input Common-Mode Range vs. Output Voltage, G = 1 Figure 5. Typical Distribution of Input Offset Voltage 15 N = 1713 500 400 300 200 100 0 –2.0 –1.5 –1.0 –0.5 0 0.5 1.0 1.5 IBIAS (nA) 2.0 05947-005 NUMBER OF UNITS 600 Figure 6. Typical Distribution of Input Bias Current 10 VS = ±15V 5 0 VS = ±5V –5 –10 –15 –15 –10 –5 0 5 10 15 OUTPUT VOLTAGE (V) Figure 9. Input Common-Mode Range vs. Output Voltage, G = 100 Rev. B | Page 8 of 24 05947-008 INPUT COMMON-MODE RANGE (V) 700 Data Sheet AD8222 160 150 VS = ±15V 50 0 VS = ±5V –50 –100 –150 –10 –5 0 5 10 15 COMMON-MODE VOLTAGE (V) 1.6 1.4 –PSRR (dB) 1.2 1.0 0.8 0.6 0.4 0.2 4 6 GAIN = 10 GAIN = 1 1 10 100 8 10 WARM-UP TIME (Minutes) 160 150 140 130 120 110 100 90 80 70 60 50 40 30 20 1k 10k 100k 1M GAIN = 1000 GAIN = 100 GAIN = 10 10 0 0.1 05947-010 CHANGE IN INPUT OFFSET VOLTAGE (µV) 1.8 2 GAIN = 100 Figure 13. Positive PSRR vs. Frequency, RTI (G = 1 to 1000) 2.0 0 GAIN = 1000 FREQUENCY (Hz) Figure 10. IBIAS vs. Common-Mode Voltage 0 BANDWIDTH LIMITED 10 0 0.1 05947-009 –200 –15 140 130 120 110 100 90 80 70 60 50 40 30 20 GAIN = 1 1 10 100 1k 10k 100k 1M FREQUENCY (Hz) 05947-013 100 +PSRR (dB) INPUT BIAS CURRENT (pA) 150 05947-012 200 Figure 14. Negative PSRR vs. Frequency, RTI (G = 1 to 1000) Figure 11. Change in Input Offset Voltage vs. Warm-Up Time 1000 10k NEGATIVE 600 400 200 POSITIVE 0 OFFSET CURRENT –200 –400 –600 1k GAIN = 1 100 GAIN = 10 10 GAIN = 100 GAIN = 1000 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) Figure 12. Input Bias Current and Offset Current vs. Temperature 1 1 10 100 1k 10k 100k SOURCE RESISTANCE (Ω) Figure 15. Total Drift vs. Source Resistance Rev. B | Page 9 of 24 1M 10M 05947-014 –800 –1000 –55 05947-011 INPUT BIAS CURRENT (pA) TOTAL DRIFT: 25°C TO 85°C RTI (µV) 800 AD8222 Data Sheet 70 60 20 GAIN = 1000 15 50 40 GAIN = 100 10 20 GAIN = 10 10 0 5 ∆CMR (µV/V) GAIN (dB) 30 GAIN = 1 EXAMPLE PART 1 0 –5 –10 EXAMPLE PART 2 –10 –20 1k 10k 100k 1M 10M FREQUENCY (Hz) –20 –40 05947-015 –40 100 INPUT VOLTAGE LIMIT (V) REFERRED TO SUPPLY VOLTAGES BANDWIDTH LIMITED GAIN = 1 80 70 60 100 1k 10k 100k 1M –2.0 +2.0 FROM –VS +1.6 +1.2 +0.8 2 6 10 14 18 Figure 20. Input Voltage Limit vs. Supply Voltage, G = 1 +VS–0 GAIN = 1000 OUTPUT VOLTAGE SWING (V) REFERRED TO SUPPLY VOLTAGES –0.4 140 GAIN = 100 120 GAIN = 10 100 BANDWIDTH LIMITED 90 80 70 GAIN = 1 60 RL = 10kΩ –0.8 –1.2 RL = 2kΩ –1.6 +1.6 RL = 2kΩ +1.2 +0.8 RL = 10kΩ +0.4 50 1 10 100 1k 10k 100k 1M FREQUENCY (Hz) 05947-017 CMRR (dB) –1.6 SUPPLY VOLTAGE (V) 160 40 0.1 –1.2 05947-019 10 Figure 17. CMRR vs. Frequency, RTI 110 120 FROM +VS –0.8 –VS+0 05947-016 1 FREQUENCY (Hz) 130 100 +0.4 50 150 80 Figure 18. CMRR vs. Frequency, RTI, 1 kΩ Source Imbalance –VS+0 2 6 10 14 SUPPLY VOLTAGE (V) Figure 21. Output Voltage Swing vs. Supply Voltage, G = 1 Rev. B | Page 10 of 24 18 05947-020 CMRR (dB) GAIN = 10 90 40 0.1 60 –0.4 GAIN = 100 110 100 40 +VS–0 GAIN = 1000 130 120 20 Figure 19. ΔCMR vs. Temperature, G = 1 150 140 0 TEMPERATURE (°C) Figure 16. Gain vs. Frequency 160 –20 05947-018 –15 –30 Data Sheet AD8222 30 40 NONLINEARITY (10ppm/DIV) OUTPUT VOLTAGE SWING (V p-p) 30 20 10 20 2kΩ LOAD 10 0 600Ω LOAD –10 10kΩ LOAD –20 10 100 1k 10k LOAD RESISTANCE (Ω) –40 –10 –8 VOLTAGE NOISE SPECTRAL DENSITY (nV/ Hz) –2 –3 +3 +2 SINKING +1 1 2 3 4 5 6 7 8 9 10 11 12 OUTPUT CURRENT (mA) 05947-022 OUTPUT VOLTAGE SWING (V) REFERRED TO SUPPLY VOLTAGES SOURCING 0 –2 0 2 4 6 8 10 Figure 25. Gain Nonlinearity, G = 100 +VS–0 –VS+0 –4 VOUT (V) Figure 22. Output Voltage Swing vs. Load Resistance –1 –6 1k GAIN = 1 100 GAIN = 10 GAIN = 100 10 GAIN = 1000 1 GAIN = 1000 BW LIMIT 1 10 100 1k 10k 100k FREQUENCY (Hz) Figure 26. Voltage Noise Spectral Density vs. Frequency (G = 1 to 1000) Figure 23. Output Voltage Swing vs. Output Current, G = 1 4 2 10kΩ LOAD 0 2kΩ LOAD –1 600Ω LOAD –2 –4 –10 05947-027 –3 –8 –6 –4 –2 0 2 4 VOUT (V) 6 8 10 05947-023 NONLINEARITY (1ppm/DIV) 3 1 05947-026 1 05947-021 0 05947-024 –30 Figure 24. Gain Nonlinearity, G = 1 2µV/DIV 1s/DIV Figure 27. 0.1 Hz to 10 Hz RTI Voltage Noise (G = 1) Rev. B | Page 11 of 24 AD8222 Data Sheet 30 0.1µV/DIV 25 20 15 10 5 0 1k 1s/DIV GAIN = 1 10k 100k 1M FREQUENCY (Hz) Figure 28. 0.1 Hz to 10 Hz RTI Voltage Noise (G = 1000) Figure 31. Large Signal Frequency Response 5V/DIV 100 7.4µs TO 0.01% 8.3µs TO 0.001% 1 10 100 1k 10k 100k FREQUENCY (Hz) 05947-029 20µs/DIV 10 05947-032 0.002%/DIV Figure 32. Large Signal Pulse Response and Settling Time (G = 1) Figure 29. Current Noise Spectral Density vs. Frequency 5V/DIV 4.8µs TO 0.01% 6.6µs TO 0.001% 5pA/DIV 20µs/DIV 1s/DIV Figure 33. Large Signal Pulse Response and Settling (G = 10) Figure 30. 0.1 Hz to 10 Hz Current Noise Rev. B | Page 12 of 24 05947-033 0.002%/DIV 05947-030 CURRENT NOISE SPECTRAL DENSITY (fA/ Hz) 1k 05947-031 05947-028 MAX OUTPUT VOLTAGE (V p-p) GAIN = 10, 100, 1000 Data Sheet AD8222 5V/DIV 9.2µs TO 0.01% 16.2µs TO 0.001% 20mV/DIV 4µs/DIV 05947-037 20µs/DIV 05947-034 0.002%/DIV Figure 37. Small Signal Response, G = 10, RL = 2 kΩ, CL = 100 pF Figure 34. Large Signal Pulse Response and Settling Time (G = 100) 5V/DIV 83µs TO 0.01% 112µs TO 0.001% 20mV/DIV 4µs/DIV 05947-036 Figure 35. Large Signal Pulse Response and Settling Time (G = 1000) 10µs/DIV 05947-038 20mV/DIV Figure 38. Small Signal Response, G = 100, RL = 2 kΩ, CL = 100 pF 20mV/DIV 100µs/DIV 05947-039 200µs/DIV 05947-035 0.002%/DIV Figure 39. Small Signal Response, G = 1000, RL = 2 kΩ, CL = 100 pF Figure 36. Small Signal Response, G = 1, RL = 2 kΩ, CL = 100 pF Rev. B | Page 13 of 24 AD8222 Data Sheet 15 60 GAIN = 1000 GAIN = 100 10 SETTLED TO 0.001% GAIN (dB) SETTLING TIME (µs) 40 SETTLED TO 0.01% 5 20 GAIN = 10 0 GAIN = 1 0 5 10 15 20 OUTPUT VOLTAGE STEP SIZE (V) –40 100 05947-040 0 1k 10k 100k 1M 10M FREQUENCY (Hz) Figure 40. Settling Time vs. Step Size (G = 1) 05947-043 –20 Figure 43. Differential Output Configuration: Gain vs. Frequency 100 1k OUTPUT BALANCE = 20 log 90 VDIFF_OUT VCM_OUT OUTPUT BALANCE (dB) SETTLING TIME (µs) 80 100 SETTLED TO 0.001% 10 70 LIMITED BY MEASUREMENT SYSTEM 60 50 40 30 20 SETTLED TO 0.01% 10 1k 100 GAIN Figure 41. Settling Time vs. Gain for a 10 V Step 200 SOURCE VOUT = 20V p-p CHANNEL SEPARATION (dB) 180 GAIN = 1000 SOURCE VOUT SMALLER TO AVOID SLEW RATE LIMIT THERMAL CROSSTALK VARIES WITH LOAD 120 GAIN = 1 100 1 10 100 1k 10k FREQUENCY (Hz) 100k 1M 05947-042 80 60 1 10 100 1k 10k 100k FREQUENCY (Hz) Figure 44. Differential Output Configuration: Output Balance vs. Frequency 160 140 0 Figure 42. Channel Separation vs. Frequency, RL = 2 kΩ, Source Channel at G = 1 Rev. B | Page 14 of 24 1M 05947-056 1 05947-041 10 1 Data Sheet AD8222 THEORY OF OPERATION VB I A1 IB COMPENSATION I A2 IB COMPENSATION 10kΩ C1 C2 +VS 10kΩ OUTPUT 10kΩ +VS 400Ω –IN Q1 R2 +VS R1 24.7kΩ +VS A3 +VS 24.7kΩ +VS 400Ω Q2 +IN –VS REF 10kΩ RG –VS –VS 05947-045 –VS –VS –VS Figure 45. Simplified Schematic AMPLIFIER ARCHITECTURE GAIN SELECTION The two instrumentation amplifiers of the AD8222 are based on the classic 3-op-amp topology. Figure 45 shows a simplified schematic of one of the amplifiers. The input transistors, Q1 and Q2, are biased at a fixed current. Any differential input signal forces the output voltages of A1 and A2 to change so that the differential voltage also appears across RG. The current that flows through RG must also flow through R1 and R2, resulting in a precisely amplified version of the differential input signal between the outputs of A1 and A2. Topologically, Q1 + A1 + R1 and Q2 + A2 + R2 can be viewed as precision current feedback amplifiers. The common-mode signal and the amplified differential signal are applied to a difference amplifier that rejects the common-mode voltage. The difference amplifier employs innovations that result in low output offset voltage as well as low output offset voltage drift. Placing a resistor across the RG terminals sets the gain of the AD8222, which can be calculated by referring to Table 8 or by using the following gain equation: Because the input amplifiers employ a current feedback architecture, the gain-bandwidth product of the AD8222 increases with gain, resulting in a system that does not suffer from the expected bandwidth loss of voltage feedback architectures at higher gains. The transfer function of the AD8222 is VOUT = G(V+IN − V−IN) + VREF RG G 1 Table 8. Gains Achieved Using 1% Resistors 1% Standard Table Value of RG (Ω) 49.9 k 12.4 k 5.49 k 2.61 k 1.00 k 499 249 100 49.9 Calculated Gain 1.990 4.984 9.998 19.93 50.40 100.0 199.4 495.0 991.0 The AD8222 defaults to G = 1 when no gain resistor is used. The tolerance and gain drift of the RG resistor should be added to the AD8222 specifications to determine the total gain accuracy of the system. When the gain resistor is not used, gain error and gain drift are kept to a minimum. where: G 1 49.4 kΩ 49.4 kΩ RG Rev. B | Page 15 of 24 AD8222 Data Sheet REFERENCE TERMINAL The output voltage of an AD8222 channel is developed with respect to the potential on the corresponding reference terminal. Typically, the reference terminal is connected to ground, but it can also be driven with a voltage to offset the output signal. For example, connect a voltage to the reference terminal to levelshift the output so that the AD8222 can drive a single-supply ADC. Both REF1 and REF2 are protected with ESD diodes and should not exceed either +VS or −VS by more than 0.3 V. For best performance, source impedance to a reference terminal should be kept below 1 Ω. As shown in Figure 45, the reference terminal is at one end of a 10 kΩ resistor. Additional impedance at the reference terminal adds to this 10 kΩ resistor and results in amplification of the signal connected to the positive input. The amplification from the additional RREF can be computed by 2 10 kΩ RREF 20 kΩ RREF Only the positive signal path is amplified; the negative path is unaffected. This uneven amplification degrades the CMRR of the amplifier. INCORRECT CORRECT AD8222 REF REF V This package is included primarily for legacy reasons. Because the AD8222 dissipates so little power, there is little need for the thermal pad. The thermal pad is connected internally to −VS. The pad can either be left unsoldered, soldered to an otherwise unconnected PCB landing, or soldered to a landing connected to the negative supply rail (−VS). If pin compatibility with the AD8224 is desired, the pad should not be electrically connected to any net, including −VS. The solder process can leave flux and other contaminants on the board. When these contaminants are between the AD8222 leads and thermal pad, they can create leakage paths that are larger than the bias currents of the AD8222. A thorough washing process removes these contaminants and restores the excellent bias current performance of the AD8222. The AD8222 is a high precision device. To ensure optimum performance at the PC board level, take care in the design of the board layout. The AD8222 pinout is arranged in a logical manner to aid in this task. AD8222 REF V Package with Thermal Pad LAYOUT CORRECT AD8222 in the Outline Dimensions section. This metal is connected to −VS through the device. Because of a possibility of a short, vias should not be placed underneath this exposed metal. Common-Mode Rejection Over Frequency + + OP2177 AD8222 – – 05947-054 V Figure 46. Driving the Reference Pin PACKAGE CONSIDERATIONS The AD8222 comes in a 4 mm × 4 mm LFCSP. Beware of blindly copying the footprint from another 4 mm × 4 mm LFCSP device; the landing pattern may be different. Refer to the Outline Dimensions section to verify that the PCB symbol has the correct dimensions. The AD8222 has a higher CMRR over frequency than typical in-amps, which gives it greater immunity to disturbances, such as line noise and its associated harmonics. A well-implemented layout is required to maintain this high performance. Input source impedances should be matched closely. Source resistance should be placed close to the inputs so that it interacts with as little parasitic capacitance as possible. Parasitics at the RGx pins can also affect CMRR over frequency. The PCB should be laid out so that the parasitic capacitances at each pin match. Traces from the gain setting resistor to the RGx pins should be kept short to minimize parasitic inductance. Reference The AD8222 comes in two package varieties, both with and without a thermal pad. Errors introduced at the reference terminal feed directly to the output. Take care to tie REF to the appropriate local ground. Package Without Thermal Pad The AD8222 ships with a package that does not include a thermal pad; it is the preferred package for the AD8222. Unlike chip scale packages where the pad limits routing capability, the AD8222 package allows routes and vias directly underneath the chip, so that the full space savings of the small LFCSP can be realized. Although the package has no metal in the center of the device, the manufacturing process does leave a very small section of exposed metal at each of the package corners, shown in Figure 56 Power Supplies Use a stable dc voltage to power the instrumentation amplifier. Noise on the supply pins can adversely affect performance. The AD8222 has two positive supply pins (Pin 5 and Pin 16) and two negative supply pins (Pin 8 and Pin 13). Although the device functions with only one pin from each supply pair connected, both pins should be connected for specified performance and optimum reliability. Rev. B | Page 16 of 24 Data Sheet AD8222 The AD8222 should be decoupled with 0.1 μF bypass capacitors, one for each supply. The positive supply decoupling capacitor should be placed near Pin 16, and the negative supply decoupling capacitor should be placed near Pin 8. Each supply should also be decoupled with a 10 μF tantalum capacitor. The tantalum capacitor can be placed further away from the AD8222 and can generally be shared by other precision integrated circuits. Figure 47 shows an example layout. INPUT BIAS CURRENT RETURN PATH The input bias current of the AD8222 must have a return path to common. When the source, such as a thermocouple, cannot provide a return current path, one should be created, as shown in Figure 48. INCORRECT CORRECT +VS +VS AD8222 AD8222 REF 0.1µF REF –VS –VS TRANSFORMER 16 15 14 +VS AD8222 1 12 2 11 3 10 4 9 RG2 RG1 5 TRANSFORMER 13 6 7 +VS AD8222 AD8222 REF REF 10MΩ –VS 8 –VS THERMOCOUPLE THERMOCOUPLE +VS +VS C C 0.1µF 05947-046 R 1 fHIGH-PASS = 2πRC AD8222 C REF AD8222 C REF R –VS –VS CAPACITIVELY COUPLED CAPACITIVELY COUPLED Figure 48. Creating an IBIAS Path Rev. B | Page 17 of 24 05947-047 Figure 47. Example Layout AD8222 Data Sheet INPUT PROTECTION +15V All terminals of the AD8222 are protected against ESD (2 kV, human body model). In addition, the input structure allows for dc overload conditions of about 2.5 V beyond the supplies. 0.1µF R Input Voltages Beyond the Rails CD R1 10nF 499Ω CC 1nF When operating at high gain, large differential input voltages can cause more than 6 mA of current to flow into the inputs. This condition occurs when the differential voltage exceeds the following critical voltage: VCRITICAL = (400 + RG) × (6 mA) 05947-048 Figure 49. RFI Suppression Figure 49 shows an example where the differential filter frequency is approximately 2 kHz, and the common-mode filter frequency is approximately 40 kHz. Values of R and CC should be chosen to minimize RFI. Mismatch between the R × CC at the positive input and the R × CC at negative input degrades the CMRR of the AD8222. By using a value of CD 10× larger than the value of CC, the effect of the mismatch is reduced and performance is improved. COMMON-MODE INPUT VOLTAGE RANGE This is true for differential voltages of either polarity. The maximum allowed differential voltage can be increased by adding an input protection resistor in series with each input. The value of each protection resistor should be RPROTECT = (VDIFF_MAX − VCRITICAL)/6 mA RF INTERFERENCE The 3-op-amp architecture of the AD8222 applies gain and then removes the common-mode voltage. Therefore, internal nodes in the AD8222 experience a combination of both the gained signal and the common-mode signal. This combined signal can be limited by the voltage supplies even when the individual input and output signals are not. Figure 8 and Figure 9 show the allowable common-mode input voltage ranges for various output voltages, supply voltages, and gains. RF rectification is often a problem when amplifiers are used in applications where there are strong RF signals. The disturbance can appear as a small dc offset voltage. High frequency signals can be filtered with a low-pass, RC network placed at the input of the instrumentation amplifier, as shown in Figure 49. The filter limits the input signal bandwidth according to the following relationship: 1 2 R C C 10µF –15V Differential Input Voltages at High Gains FilterFreqCM REF –IN 0.1µF For applications in which the AD8222 encounters extreme overload voltages, such as cardiac defibrillators, external series resistors and low leakage diode clamps, such as the BAV199L, the FJH1100, or the SP720, should be used. 1 2 R(2CD CC ) VOUT AD8222 R 4.02kΩ VIN VSUPPLY 400 Ω 6 mA FilterFreqDiff +IN 4.02kΩ For larger input voltages, an external resistor should be used in series with each input to limit current during overload conditions. The AD8222 can safely handle a continuous 6 mA current. The limiting resistor can be computed from RLIMIT 10µF CC 1nF where CD ≥ 10CC. Rev. B | Page 18 of 24 Data Sheet AD8222 APPLICATIONS INFORMATION DIFFERENTIAL OUTPUT Setting the Common-Mode Voltage The differential configuration of the AD8222 has the same excellent dc precision specifications as the single-ended output configuration and is recommended for applications in the frequency range of dc to 100 kHz. The output common-mode voltage is set by the average of +IN2 and REF2. The transfer function is The circuit configuration is shown in Figure 50. The differential output specifications in Table 2 and Table 4 refer to this configuration only. The circuit includes an RC filter that maintains the stability of the loop. The transfer function for the differential output is: where: 49.4 kΩ RG +OUT 10kΩ – AD8222 100pF +IN2 REF2 –OUT Figure 50. Differential Circuit Schematic Errors from the op amp are common to both outputs and are thus common mode. Errors from mismatched resistors also create a common-mode dc offset. Because these errors are common mode, they are likely to be rejected by the next device in the signal chain. +IN AD8222 +OUT –IN REF 4.99kΩ 4.99kΩ VREF + – OP2177 –OUT Figure 51. Differential Output Using Op Amp Rev. B | Page 19 of 24 05947-053 AD8222 05947-049 –IN Another differential output topology is shown in Figure 51. Instead of a second in-amp, ½ of a dual OP2177 op amp creates the inverted output. Because the OP2177 is packaged in an MSOP, this configuration allows the creation of a dual channel, precision differential output in-amp with little board area. + + RG 2-Channel Differential Output Using a Dual Op Amp – +IN +IN2 and REF2 have different properties that allow the reference voltage to be easily set for a wide variety of applications. +IN2 has high impedance but cannot swing to the supply rails of the device. REF2 must be driven with a low impedance but can go 300 mV beyond the supply rails. A common application sets the common-mode output voltage to the midscale of a differential ADC. In this case, the ADC reference voltage is sent to the +IN2 terminal, and ground is connected to the REF2 terminal. This produces a common-mode output voltage of half the ADC reference voltage. VDIFF_OUT = V+OUT − V−OUT = (V+IN − V−IN) × G G 1 VCM_OUT = (V+OUT + V−OUT)/2 = (V+IN2 + VREF2)/2 AD8222 Data Sheet +12V 10µF + 0.1µF +5V 1kΩ +IN 100pF NPO 5% 0.1µF +OUT 1000pF AD8222 –IN +IN2 100pF NPO 5% –OUT REF2 IN– 2200pF 2200pF + AD7688 GND REF 10µF X5R +12V +5V REF 10µF VDD IN+ 1kΩ (DIFF OUT) 1kΩ 1kΩ 0.1µF 0.1µF VIN –12V +5V REF VOUT ADR435 0.1µF 05947-051 GND Figure 52. Driving a Differential ADC The AD8222 can be configured in differential output mode to drive a differential analog-to-digital converter. Figure 52 illustrates several of the concepts. RFI and Antialiasing Filter The 1 kΩ resistors, 1000 pF capacitor, and 100 pF capacitors in front of the in-amp form filter circuitry that performs many functions. The 1 kΩ and 100 pF capacitors form common-mode filters that protect the amplifier from incoming radio frequency signals. Without the filtering, these RFI signals can be rectified in the in-amp. The 1 kΩ resistors provide some overvoltage protection. The 1 kΩ resistors and 1000 pF capacitor form a 76 kHz antialiasing filter for the ADC. Note that the 100 pF capacitors are 5% COG/NPO types. These capacitors match well over time and temperature, which keeps the system CMRR high over frequency. Second Antialiasing Filter A 1 kΩ resistor and 2200 pF capacitor are placed between each AD8222 output and ADC input. They create a 72 kHz low-pass filter for another stage of antialiasing protection. The 1 kΩ resistors can also protect an ADC from overvoltages. Because the AD8222 runs on wider supply voltages than a typical ADC, there is a possibility of overdriving the ADC. This is not an issue with a PulSAR® converter, such as the AD7688. Its input can handle a 130 mA overdrive, which is much higher than the short-circuit limit of the AD8222. However, other converters have less robust inputs and may need the added protection. Reference The ADR435 supplies a reference voltage to both the ADC and the AD8222. Because REF2 on the AD8222 is grounded, the common-mode output voltage is precisely half the reference voltage, exactly where it needs to be for the ADC. PRECISION STRAIN GAGE The low offset and high CMRR over frequency of the AD8222 make it an excellent candidate for both ac and dc bridge measurements. As shown in Figure 53, the bridge can be connected to the inputs of the amplifier directly. 5V 10µF 350Ω 0.1µF 350Ω +IN These four elements also improve distortion performance. The 2200 pF capacitor provides charge to the switched capacitor front end of the ADC, and the 1 kΩ resistor shields the AD8222 from driving any sharp current changes. If the application requires a lower frequency antialiasing filter and is distortion sensitive, increase the value of the capacitor rather than the resistor. Rev. B | Page 20 of 24 350Ω 350Ω + AD8222 RG –IN – Figure 53. Precision Strain Gauge 2.5V 05947-050 DRIVING A DIFFERENTIAL INPUT ADC Data Sheet AD8222 DRIVING CABLING All cables have a certain capacitance per unit length, which varies widely with cable type. The capacitive load from the cable can cause peaking in the output response of the AD8222. To reduce the peaking, use a resistor between the AD8222 and the cable. Because cable capacitance and desired output response vary widely, this resistor is best determined empirically. A good starting point is 50 Ω. AD8222 (DIFF OUT) AD8222 (SINGLE OUT) 05947-052 The AD8222 operates at a low enough frequency that transmission line effects are rarely an issue; therefore, the resistor need not match the characteristic impedance of the cable. Figure 54. Driving a Cable Rev. B | Page 21 of 24 AD8222 Data Sheet OUTLINE DIMENSIONS 4.10 4.00 SQ 3.90 0.65 BSC PIN 1 INDICATOR 16 13 1 12 EXPOSED PAD 2.60 2.50 SQ 2.40 9 0.50 0.40 0.30 TOP VIEW 0.80 0.75 0.70 4 5 8 BOTTOM VIEW 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 042709-A PIN 1 INDICATOR 0.35 0.30 0.25 COMPLIANT TO JEDEC STANDARDS MO-220-WGGC. Figure 55. 16-Lead Lead Frame Chip Scale Package [LFCSP] 4 mm × 4 mm Body and 0.75 mm Package Height (CP-16-26) Dimensions are shown in millimeters 4.10 4.00 SQ 3.90 0.60 MAX 1.95 REF 0.60 MAX 13 16 12 PIN 1 INDICATOR 3.75 BSC SQ 1 0.65 BSC 9 TOP VIEW SEATING PLANE 12° MAX 4 8 5 BOTTOM VIEW 0.80 MAX 0.65 TYP 0.35 0.30 0.25 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF COMPLIANT TO JEDEC STANDARDS MO-263-VBBC Figure 56. 16-Lead Lead Frame Chip Scale Package [LFCSP] 4 mm × 4 mm Body and 0.85 mm Package Height with Hidden Paddle (CP-16-19) Dimensions shown in millimeters Rev. B | Page 22 of 24 04-06-2012-A 1.00 0.85 0.80 0.75 0.60 0.50 Data Sheet AD8222 ORDERING GUIDE Model 1 AD8222ACPZ-R7 AD8222ACPZ-RL AD8222ACPZ-WP AD8222BCPZ-R7 AD8222BCPZ-RL AD8222BCPZ-WP AD8222HACPZ-R7 AD8222HACPZ-RL AD8222HACPZ-WP AD8222HBCPZ-R7 AD8222HBCPZ-RL AD8222HBCPZ-WP AD8222-EVALZ 1 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C Product Description Standard Grade with Exposed Pad Standard Grade with Exposed Pad Standard Grade with Exposed Pad High Performance Grade with Exposed Pad High Performance Grade with Exposed Pad High Performance Grade with Exposed Pad Standard Grade Without Exposed Pad Standard Grade Without Exposed Pad Standard Grade Without Exposed Pad High Performance Grade Without Exposed Pad High Performance Grade Without Exposed Pad High Performance Grade Without Exposed Pad Z = RoHS Compliant Part. Rev. B | Page 23 of 24 Package Description 16-Lead LFCSP, 7“ Tape and Reel 16-Lead LFCSP, 13“Tape and Reel 16-Lead LFCSP, Waffle Pack 16-Lead LFCSP, 7“ Tape and Reel 16-Lead LFCSP, 13” Tape and Reel 16-Lead LFCSP, Waffle Pack 16-Lead LFCSP, 7” Tape and Reel 16-Lead LFCSP, 13” Tape and Reel 16-Lead LFCSP, Waffle Pack 16-Lead LFCSP, 7” Tape and Reel 16-Lead LFCSP, 13” Tape and Reel 16-Lead LFCSP, Waffle Pack Evaluation Board Package Option CP-16-26 CP-16-26 CP-16-26 CP-16-26 CP-16-26 CP-16-26 CP-16-19 CP-16-19 CP-16-19 CP-16-19 CP-16-19 CP-16-19 AD8222 Data Sheet NOTES ©2006–2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05947-0-5/16(B) Rev. B | Page 24 of 24