TI1 DAC8551IDGKT 16-bit, ultra-low glitch, voltage output Datasheet

 DA
C8
DAC8551
551
SLAS429B – APRIL 2005 – REVISED OCTOBER 2006
16-BIT, ULTRA-LOW GLITCH, VOLTAGE OUTPUT
DIGITAL-TO-ANALOG CONVERTER
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Relative Accuracy: 3LSB
Glitch Energy: 0.1nV-s
MicroPower Operation:
140µA at 2.7V
Power-On Reset to Zero
Power Supply: +2.7V to +5.5V
16-Bit Monotonic Over Temperature
Settling Time: 10µs to ±0.003% FSR
Low-Power Serial Interface with
Schmitt-Triggered Inputs
On-Chip Output Buffer Amplifier with
Rail-to-Rail Operation
Power-Down Capability
Binary Input
SYNC Interrupt Facility
Drop-In Compatible With DAC8531/01
and DAC8550 (2's Complement Input)
Available in a Tiny MSOP-8 Package
APPLICATIONS
•
•
•
•
•
•
Process Control
Data Acquisition Systems
Closed-Loop Servo-Control
PC Peripherals
Portable Instrumentation
Programmable Attenuation
DESCRIPTION
The DAC8551 is a small, low-power, voltage output,
16-bit digital-to-analog converter (DAC). It is
monotonic, provides good linearity, and minimizes
undesired code-to-code transient voltages. The
DAC8551 uses a versatile 3-wire serial interface that
operates at clock rates to 30MHz and is compatible
with standard SPI™, QSPI™, Microwire™, and
digital signal processor (DSP) interfaces.
The DAC8551 requires an external reference voltage
to set its output range. The DAC8551 incorporates a
power-on-reset circuit that ensures the DAC output
powers up at 0V and remains there until a valid write
takes place to the device. The DAC8551 contains a
power-down feature, accessed over the serial
interface, that reduces the current consumption of
the device to 200nA at 5V.
The low-power consumption of this device in normal
operation makes it ideally suited for portable, batteryoperated equipment. The power consumption is
0.38mW at 2.7V, reducing to less than 1µW in
power-down mode.
The DAC8551 is available in an MSOP-8 package.
For additional flexibilty, see the DAC8550, a 2's
complement-input counterpart to the DAC8551.
FUNCTIONAL BLOCK DIAGRAM
VDD
VFB
VREF
Ref (+)
VOUT
16-Bit DAC
16
DAC Register
16
SYNC
SCLK
Shift Register
Resistor
Network
PWD Control
DIN
GND
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SPI, QSPI are trademarks of Motorola, Inc.
Microwire is a trademark of National Semiconductor.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005–2006, Texas Instruments Incorporated
DAC8551
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SLAS429B – APRIL 2005 – REVISED OCTOBER 2006
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
PACKAGING/ORDERING INFORMATION (1)
PRODUCT
MAXIMUM
RELATIVE
ACCURACY
(LSB)
MAXIMUM
DIFFERENTIAL
NONLINEARITY
(LSB)
MAXIMUM
GAIN ERROR
(% OF FSR)
PACKAGE
LEAD
PACKAGE
DESIGNATOR
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
ORDERING
NUMBER
DAC8551IDGK
Tube, 80
DAC8551
±8
±1
±0.15
MSOP-8
DGK
–40°C to +105°C
D81
DAC8551IDGKT
Tape and Reel, 250
DAC8551IDGKR
Tape and Reel, 2500
±12
DAC8551A
(1)
±1
±0.2
MSOP-8
DGK
–40°C to +105°C
D81
TRANSPORT
MEDIA, QUANTITY
DAC8551IADGK
Tube, 80
DAC8551IADGKT
Tape and Reel, 250
DAC8551IADGKR
Tape and Reel, 2500
For the most current package and ordering information, see the Package Option Addendum at the end of this data sheet, or see the TI
website at www.ti.com.
ABSOLUTE MAXIMUM RATINGS (1)
UNIT
VDD to GND
–0.3V to 6V
Digital input voltage to GND
–0.3V to +VDD + 0.3V
VOUT to GND
–0.3V to +VDD + 0.3V
Operating temperature range
–40°C to +105°C
Storage temperature range
–65°C to +150°C
Junction temperature range (TJ max)
+150°C
Power dissipation (DGK)
Thermal impedance
(1)
(TJ max – TA)/θJA
θJA
206°C/W
θJC
44°C/W
Stresses above those listed under absolute maximum ratings may cause permanent damage to the device. Exposure to absolute
maximum conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
VDD = 2.7V to 5.5V,and –40°C to +105°C range, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
±3
±8
LSB
STATIC PERFORMANCE (1)
Resolution
16
Relative accuracy
Measured by line passing through
codes 485 and 64741
Differential nonlinearity
16-bit monotonic
Zero-code error
Full-scale error
Gain error
DAC8551
DAC8551A
Measured by line passing through codes 485 and 64741
Measured by line passing through
codes 485 and 64741
(1)
2
±12
LSB
±1
LSB
±2
±12
mV
±0.05
±0.5
% of FSR
±0.02
±0.15
% of FSR
DAC8551A
±0.02
±0.2
% of FSR
Gain temperature coefficient
Power-supply rejection ratio
±3
±0.25
DAC8551
Zero-code error drift
PSRR
Bits
RL = 2kΩ, CL = 200pF
Linearity calculated using a reduced code range of 485 to 64741; output unloaded.
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±5
µV/°C
±1
ppm of
FSR/°C
0.75
mV/V
DAC8551
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SLAS429B – APRIL 2005 – REVISED OCTOBER 2006
ELECTRICAL CHARACTERISTICS (continued)
VDD = 2.7V to 5.5V,and –40°C to +105°C range, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VREF
V
10
µs
OUTPUT CHARACTERISTICS (2)
Output voltage range
Output voltage settling time
0
To ±0.003% FSR, 0200h to FD00h, RL = 2kΩ,
0pF < CL < 200pF
8
RL = 2kΩ, CL = 50 pF
Slew rate
Capacitive load stability
RL = ∞
RL = 2kΩ
12
µs
1.8
V/µs
470
pF
1000
pF
Code change glitch impulse
1LSB change around major carry
0.1
Digital feedthrough
50kΩ series resistance on digital lines
0.1
DC output impedance
At mid-code input
Short-circuit current
Power-up time
nV-s
Ω
1
VDD = 5V
50
VDD = 3V
20
Coming out of power-down mode, VDD = 5V
2.5
Coming out of power-down mode, VDD = 3V
5
mA
µs
AC PERFORMANCE
SNR
95
THD
–85
BW = 20kHz, VDD = 5V, fOUT = 1kHz, 1st 19 harmonics removed
for SNR calculation
SFDR
dB
87
SINAD
84
REFERENCE INPUT
Reference current
VREF = VDD = 5V
40
75
µA
VREF = VDD = 3.6V
30
45
µA
Reference input range
0
Reference input impedance
VDD
125
V
kΩ
LOGIC INPUTS (2)
±1
Input current
VINL
Input LOW voltage
VINH
Input HIGH voltage
µA
VDD = 5V
0.8
VDD = 3V
0.6
VDD = 5V
2.4
VDD = 3V
2.1
V
V
Pin capacitance
3
pF
5.5
V
POWER REQUIREMENTS
VDD
2.7
IDD
(normal mode)
VDD = 3.6V to 5.5V
VDD = 2.7V to 3.6V
IDD
Input code = 32768, no load, does not include reference current
VIH = VDD and VIL = GND
160
250
140
240
0.2
2
0.05
2
µA
(all power-down modes)
VDD = 3.6V to 5.5V
VIH = VDD and VIL = GND
VDD = 2.7V to 3.6V
µA
POWER EFFICIENCY
IOUT/IDD
ILOAD = 2mA, VDD = 5V
89
%
TEMPERATURE RANGE
Specified performance
(2)
–40
+105
°C
Specified by design and characterization; not production tested.
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PIN CONFIGURATION
DGK PACKAGE
MSOP-8
(Top View)
VDD
1
VREF
2
8
GND
7
DIN
DAC8551
VFB
3
6
SCLK
VOUT
4
5
SYNC
PIN DESCRIPTIONS
4
PIN
NAME
1
VDD
Power supply input, 2.7V to 5.5V.
DESCRIPTION
2
VREF
Reference voltage input.
3
VFB
Feedback connection for the output amplifier. For voltage output operation, tie to VOUT externally.
4
VOUT
Analog output voltage from DAC. The output amplifier has rail-to-rail operation.
5
SYNC
Level-triggered control input (active LOW). This is the frame synchronization signal for the input data. When SYNC goes
LOW, it enables the input shift register and data is transferred in on the falling edges of the following clocks. The DAC is
updated following the 24th clock (unless SYNC is taken HIGH before this edge, in which case the rising edge of SYNC
acts as an interrupt and the write sequence is ignored by the DAC8551). Schmitt-Trigger logic input.
6
SCLK
Serial clock input. Data can be transferred at rates up to 30MHz. Schmitt-Trigger logic input.
7
DIN
8
GND
Serial data input. Data is clocked into the 24-bit input shift register on each falling edge of the serial clock input.
Schmitt-Trigger logic input.
Ground reference point for all circuitry on the part.
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SLAS429B – APRIL 2005 – REVISED OCTOBER 2006
SERIAL WRITE OPERATION
t9
t1
SCLK
1
24
t8
t3
t4
t2
t7
SYNC
t6
t5
DIN
DB23
DB0
DB23
TIMING CHARACTERISTICS (1) (2)
VDD = 2.7V to 5.5V, all specifications –40°C to +105°C (unless otherwise noted).
PARAMETER
t1 (3)
SCLK cycle time
t2
SCLK HIGH time
t3
SCLK LOW time
t4
SYNC to SCLK rising edge setup time
t5
Data setup time
t6
Data hold time
t7
24th SCLK falling edge to SYNC rising edge
t8
Minimum SYNC HIGH time
t9
24th SCLK falling edge to SYNC falling edge
(1)
(2)
(3)
TEST CONDITIONS
MIN
VDD = 2.7V to 3.6V
50
VDD = 3.6V to 5.5V
33
VDD = 2.7V to 3.6V
13
VDD = 3.6V to 5.5V
13
VDD = 2.7V to 3.6V
22.5
VDD = 3.6V to 5.5V
13
VDD = 2.7V to 3.6V
0
VDD = 3.6V to 5.5V
0
VDD = 2.7V to 3.6V
5
VDD = 3.6V to 5.5V
5
VDD = 2.7V to 3.6V
4.5
VDD = 3.6V to 5.5V
4.5
VDD = 2.7V to 3.6V
0
VDD = 3.6V to 5.5V
0
VDD = 2.7V to 3.6V
50
VDD = 3.6V to 5.5V
33
VDD = 2.7V to 5.5V
100
TYP
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
All input signals are specified with tR = tF = 5ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
See Serial Write Operation Timing Diagram.
Maximum SCLK frequency is 30MHz at VDD = 3.6V to 5.5V and 20MHz at VDD = 2.7V to 3.6V.
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TYPICAL CHARACTERISTICS: VDD = 5 V
At TA = +25°C, unless otherwise noted.
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (-40°C)
VDD = 5V, VREF = 4.99V
6
4
2
0
-2
-4
-6
LE (LSB)
LE (LSB)
6
4
2
0
-2
-4
-6
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (+25°C)
1.0
DLE (LSB)
DLE (LSB)
1.0
0.5
0
-0.5
-1.0
6
4
2
0
-2
-4
-6
0
-0.5
8192
16384 24576 32768 40960 49152
Digital Input Code
57344 65536
0
8192
16384 24576 32768 40960 49152
Digital Input Code
Figure 1.
Figure 2.
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (+105°C)
ZERO-SCALE ERROR
vs TEMPERATURE
57344 65536
10
VDD = 5V
VREF = 4.99V
VDD = 5V, VREF = 4.99V
5
Error (mV)
LE (LSB)
0.5
-1.0
0
1.0
DLE (LSB)
VDD = 5V, VREF = 4.99V
0.5
0
0
-0.5
-1.0
-5
0
8192
16384 24576 32768 40960 49152
Digital Input Code
57344 65536
0
-40
40
Figure 3.
120
Figure 4.
FULL-SCALE ERROR
vs TEMPERATURE
0
80
Temperature (°C)
SOURCE AND SINK CURRENT CAPABILITY
6
VDD = 5V
VREF = 4.99V
5
DAC Loaded with FFFFh
VOUT (mV)
Error (mV)
4
-5
3
VDD = 5.5V
VREF = VDD - 10mV
2
1
DAC Loaded with 0000h
0
-10
-40
0
40
80
120
0
Temperature (°C)
4
6
I(SOURCE/SINK) (mA)
Figure 5.
6
2
Figure 6.
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10
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TYPICAL CHARACTERISTICS: VDD = 5 V (continued)
At TA = +25°C, unless otherwise noted.
SUPPLY CURRENT
vs DIGITAL INPUT CODE
POWER-SUPPLY CURRENT
vs TEMPERATURE
300
250
VDD = VREF = 5V
250
VREF = VDD = 5V
200
IDD (mA)
IDD (mA)
200
Reference Current Included
150
150
100
100
50
50
0
0
0
-40
8192 16384 24576 32768 40960 49152 57344 65536
80
Figure 7.
Figure 8.
SUPPLY CURRENT
vs SUPPLY VOLTAGE
POWER-DOWN CURRENT
vs SUPPLY VOLTAGE
1.0
VREF = VDD
Reference Current Included, No Load
Power-Down Current (mA)
260
240
IDD (mA)
50
110
Temperature (°C)
300
280
20
-10
Digital Input Code
220
200
180
160
140
VREF = VDD
0.8
0.6
0.4
0.2
120
100
0
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
2.7
3.1
3.5
4.3
4.7
5.1
5.5
VDD (V)
VDD (V)
Figure 9.
Figure 10.
SUPPLY CURRENT
vs LOGIC INPUT VOLTAGE
FULL-SCALE SETTLING TIME: 5V RISING EDGE
1800
TA = 25°C, SCL Input (all other inputs = GND)
VDD = VREF = 5.5V
1600
Trigger Pulse 5V/div
1400
IDD (mA)
1200
1000
VDD = 5V
VREF = 4.096V
From Code: D000
To Code: FFFF
800
600
400
Rising Edge
1V/div
200
Zoomed Rising Edge
1mV/div
0
0
1
2
3
4
5
Time (2ms/div)
VLOGIC (V)
Figure 11.
Figure 12.
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TYPICAL CHARACTERISTICS: VDD = 5 V (continued)
At TA = +25°C, unless otherwise noted.
FULL-SCALE SETTLING TIME: 5V FALLING EDGE
HALF-SCALE SETTLING TIME: 5V RISING EDGE
Trigger Pulse 5V/div
Trigger Pulse 5V/div
VDD = 5V
VREF = 4.096V
From Code: FFFF
To Code: 0000
Falling
Edge
1V/div
Rising
Edge
1V/div
Zoomed Falling Edge
1mV/div
VDD = 5V
VREF = 4.096V
From Code: 4000
To Code: CFFF
Zoomed Rising Edge
1mV/div
Time (2ms/div)
Time (2ms/div)
Figure 13.
Figure 14.
HALF-SCALE SETTLING TIME: 5V FALLING EDGE
GLITCH ENERGY: 5V, 1LSB STEP, RISING EDGE
VDD = 5V
VREF = 4.096V
From Code: CFFF
To Code: 4000
Falling
Edge
1V/div
VOUT (500mV/div)
Trigger Pulse 5V/div
VDD = 5V
VREF = 4.096V
From Code: 7FFF
To Code: 8000
Glitch: 0.08nV-s
Zoomed Falling Edge
1mV/div
8
Time (400ns/div)
Figure 15.
Figure 16.
GLITCH ENERGY: 5V, 1LSB STEP, FALLING EDGE
GLITCH ENERGY: 5V, 16LSB STEP, RISING EDGE
VDD = 5V
VREF = 4.096V
From Code: 8000
To Code: 7FFF
Glitch: 0.16nV-s
Measured Worst Case
VOUT (500mV/div)
VOUT (500mV/div)
Time (2ms/div)
VDD = 5V
VREF = 4.096V
From Code: 8000
To Code: 8010
Glitch: 0.04nV-s
Time (400ns/div)
Time (400ns/div)
Figure 17.
Figure 18.
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TYPICAL CHARACTERISTICS: VDD = 5 V (continued)
At TA = +25°C, unless otherwise noted.
GLITCH ENERGY: 5V, 16LSB STEP, FALLING EDGE
GLITCH ENERGY: 5V, 256LSB STEP, RISING EDGE
VOUT (5mV/div)
VOUT (500mV/div)
VDD = 5V
VREF = 4.096V
From Code: 8010
To Code: 8000
Glitch: 0.08nV-s
VDD = 5V
VREF = 4.096V
From Code: 8000
To Code: 80FF
Glitch: Not Detected
Theoretical Worst Case
Time (400ns/div)
Time (400ns/div)
Figure 19.
Figure 20.
GLITCH ENERGY: 5V, 256LSB STEP, FALLING EDGE
TOTAL HARMONIC DISTORTION
vs OUTPUT FREQUENCY
-40
VDD = 5V
VREF = 4.9V
-1dB FSR Digital Input
fS = 1MSPS
Measurement Bandwidth = 20kHz
-50
-60
THD (dB)
VOUT (5mV/div)
VDD = 5V
VREF = 4.096V
From Code: 80FF
To Code: 8000
Glitch: Not Detected
Theoretical Worst Case
-70
THD
-80
-90
2nd Harmonic
3rd Harmonic
-100
Time (400ns/div)
0
1
2
3
4
5
fOUT (kHz)
98
Figure 22.
SIGNAL-TO-NOISE RATIO
vs OUTPUT FREQUENCY
POWER SPECTRAL DENSITY
VREF = VDD = 5V
-1dB FSR Digital Input
fS = 1MSPS
Measurement Bandwidth = 20kHz
96
94
VDD = 5V
VREF = 4.096V
fOUT = 1kHz
f
= 1MSPS
-10
-30
CLK
Gain (dB)
SNR (dB)
Figure 21.
92
90
-50
-70
88
-90
86
-110
84
-130
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.5
0
5
10
fOUT (kHz)
Frequency (kHz)
Figure 23.
Figure 24.
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20
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TYPICAL CHARACTERISTICS: VDD = 5 V (continued)
At TA = +25°C, unless otherwise noted.
OUTPUT NOISE DENSITY
350
VDD = 5V
VREF = 4.99V
Code = 7FFFh
No Load
Voltage Noise (nV/ÖHz)
300
250
200
150
100
100
1k
10k
Frequency (Hz)
Figure 25.
10
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TYPICAL CHARACTERISTICS: VDD = 2.7 V
At TA = +25°C, unless otherwise noted.
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (-40°C)
6
4
2
0
-2
-4
-6
VDD = 2.7V, VREF = 2.69V
LE (LSB)
LE (LSB)
6
4
2
0
-2
-4
-6
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (+25°C)
1.0
DLE (LSB)
DLE (LSB)
1.0
0.5
0
-0.5
-1.0
6
4
2
0
-2
-4
-6
0
-0.5
8192
16384 24576 32768 40960 49152
Digital Input Code
57344 65536
0
8192
16384 24576 32768 40960 49152
Digital Input Code
Figure 26.
Figure 27.
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (+105°C)
ZERO-SCALE ERROR
vs TEMPERATURE
57344 65536
10
VDD = 2.7V
VREF = 2.69V
VDD = 2.7V, VREF = 2.69V
5
Error (mV)
LE (LSB)
0.5
-1.0
0
1.0
DLE (LSB)
VDD = 2.7V, VREF = 2.69V
0.5
0
0
-0.5
-1.0
-5
0
8192
16384 24576 32768 40960 49152
Digital Input Code
57344 65536
0
-40
40
80
120
Temperature (°C)
Figure 28.
Figure 29.
FULL-SCALE ERROR
vs TEMPERATURE
SOURCE AND SINK CURRENT CAPABILITY
5
3.0
VDD = 2.7V
VREF = 2.69V
2.5
DAC Loaded with FFFFh
0
VOUT (mV)
Error (mV)
2.0
1.5
VDD = 2.7V
VREF = VDD - 10mV
1.0
-5
0.5
DAC Loaded with 0000h
0
-10
-40
0
40
80
120
0
Temperature (°C)
2
4
6
8
10
I(SOURCE/SINK) (mA)
Figure 30.
Figure 31.
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TYPICAL CHARACTERISTICS: VDD = 2.7 V (continued)
At TA = +25°C, unless otherwise noted.
SUPPLY CURRENT
vs DIGITAL INPUT CODE
POWER-SUPPLY CURRENT
vs TEMPERATURE
180
250
VDD = VREF = 2.7V
160
VREF = VDD = 2.7V
200
140
Reference Current Included
IDD (mA)
IDD (mA)
120
100
80
150
100
60
40
50
20
0
0
8192 16384 24576 32768 40960 49152 57344 65536
0
-40
-10
20
50
80
110
Temperature (°C)
Digital Input Code
Figure 32.
Figure 33.
SUPPLY CURRENT
vs LOGIC INPUT VOLTAGE
FULL-SCALE SETTLING TIME: 2.7V RISING EDGE
800
TA = 25°C, SCL Input (all other inputs = GND)
VDD = VREF = 2.7V
700
Trigger Pulse 2.7V/div
600
Rising
Edge
0.5V/div
IDD (mA)
500
400
VDD = 2.7V
VREF = 2.5V
From Code: 0000
To Code: FFFF
300
200
Zoomed Rising Edge
1mV/div
100
0
0
0.5
1.0
1.5
2.0
Time (2ms/div)
2.5 2.7
VLOGIC (V)
Figure 34.
Figure 35.
FULL-SCALE SETTLING TIME: 2.7V FALLING EDGE
HALF-SCALE SETTLING TIME: 2.7V RISING EDGE
Trigger Pulse 2.7V/div
Trigger Pulse 2.7V/div
VDD = 2.7V
VREF = 2.5V
From Code: FFFF
To Code: 0000
Falling
Edge
0.5V/div
Zoomed Falling Edge
1mV/div
Rising
Edge
0.5V/div
Time (2ms/div)
Zoomed Rising Edge
1mV/div
Time (2ms/div)
Figure 36.
12
VDD = 2.7V
VREF = 2.5V
From Code: 4000
To Code: CFFF
Figure 37.
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SLAS429B – APRIL 2005 – REVISED OCTOBER 2006
TYPICAL CHARACTERISTICS: VDD = 2.7 V (continued)
At TA = +25°C, unless otherwise noted.
HALF-SCALE SETTLING TIME: 2.7V FALLING EDGE
GLITCH ENERGY: 2.7V, 1LSB STEP, RISING EDGE
VDD = 2.7V
VREF = 2.5V
From Code: CFFF
To Code: 4000
Falling
Edge
0.5V/div
VOUT (200mV/div)
Trigger Pulse 2.7V/div
VDD = 2.7V
VREF = 2.5V
From Code: 7FFF
To Code: 8000
Glitch: 0.08nV-s
Zoomed Falling Edge
1mV/div
Time (400ns/div)
Figure 38.
Figure 39.
GLITCH ENERGY: 2.7V, 1LSB STEP, FALLING EDGE
GLITCH ENERGY: 2.7V, 16LSB STEP, RISING EDGE
VDD = 2.7V
VREF = 2.5V
From Code: 8000
To Code: 7FFF
Glitch: 0.16nV-s
Measured Worst Case
VOUT (200mV/div)
VOUT (200mV/div)
Time (2ms/div)
VDD = 2.7V
VREF = 2.5V
From Code: 8000
To Code: 8010
Glitch: 0.04nV-s
Time (400ns/div)
Figure 40.
Figure 41.
GLITCH ENERGY: 2.7V, 16LSB STEP, FALLING EDGE
GLITCH ENERGY: 2.7V, 256LSB STEP, RISING EDGE
VOUT (200mV/div)
VDD = 2.7V
VREF = 2.5V
From Code: 8010
To Code: 8000
Glitch: 0.12nV-s
VOUT (5mV/div)
Time (400ns/div)
VDD = 2.7V
VREF = 2.5V
From Code: 8000
To Code: 80FF
Glitch: Not Detected
Theoretical Worst Case
Time (400ns/div)
Time (400ns/div)
Figure 42.
Figure 43.
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13
DAC8551
www.ti.com
SLAS429B – APRIL 2005 – REVISED OCTOBER 2006
TYPICAL CHARACTERISTICS: VDD = 2.7 V (continued)
At TA = +25°C, unless otherwise noted.
VOUT (5mV/div)
GLITCH ENERGY: 2.7V, 256LSB STEP, FALLING EDGE
VDD = 2.7V
VREF = 2.5V
From Code: 80FF
To Code: 8000
Glitch: Not Detected
Theoretical Worst Case
Time (400ns/div)
Figure 44.
14
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DAC8551
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SLAS429B – APRIL 2005 – REVISED OCTOBER 2006
THEORY OF OPERATION
DAC SECTION
VREF
The DAC8551 architecture consists of a string DAC
followed by an output buffer amplifier. Figure 45
shows a block diagram of the DAC architecture.
VREF
50kW
RDIVIDER
VREF
2
50kW
VFB
R
62kW
DAC
Register
REF (+)
Register String
REF (-)
VOUT
R
To Output Amplifier
(2x Gain)
GND
Figure 45. DAC8551 Architecture
The input coding to the DAC8551 is straight binary,
so the ideal output voltage is given by:
DIN
V OUT +
V REF
65536
(1)
R
where DIN = decimal equivalent of the binary code
that is loaded to the DAC register; it can range from
0 to 65535.
R
RESISTOR STRING
The resistor string section is shown in Figure 46. It is
simply a string of resistors, each of value R. The
code loaded into the DAC register determines at
which node on the string the voltage is tapped off to
be fed into the output amplifier by closing one of the
switches connecting the string to the amplifier.
Monotonicity is ensured because of the string
resistor architecture.
OUTPUT AMPLIFIER
The output buffer amplifier is capable of generating
rail-to-rail voltages on its output, giving an output
range of 0V to VDD. It is capable of driving a load of
2kΩ in parallel with 1000pF to GND. The source and
sink capabilities of the output amplifier can be seen
in the Typical Characteristics. The slew rate is
1.8V/µs with a full-scale setting time of 8µs with the
output unloaded.
The inverting input of the output amplifier is brought
out to the VFB pin. This configuration allows for better
accuracy in critical applications by tying the VFB point
and the amplifier output together directly at the load.
Other signal conditioning circuitry may also be
connected between these points for specific
applications.
Figure 46. Resistor String
SERIAL INTERFACE
The DAC8551 has a 3-wire serial interface (SYNC,
SCLK, and DIN), which is compatible with SPI, QSPI,
and Microwire interface standards, as well as most
DSPs. See the Serial Write Operation Timing
Diagram for an example of a typical write sequence.
The write sequence begins by bringing the SYNC
line LOW. Data from the DIN line are clocked into the
24-bit shift register on each falling edge of SCLK.
The serial clock frequency can be as high as 30MHz,
making the DAC8551 compatible with high-speed
DSPs. On the 24th falling edge of the serial clock,
the last data bit is clocked in and the programmed
function is executed (that is, a change in DAC
register contents and/or a change in the mode of
operation).
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15
DAC8551
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At this point, the SYNC line may be kept LOW or
brought HIGH. In either case, it must be brought
HIGH for a minimum of 33ns before the next write
sequence so that a falling edge of SYNC can initiate
the next write sequence. As previously mentioned, it
must be brought HIGH again just before the next
write sequence.
INPUT SHIFT REGISTER
The input shift register is 24 bits wide, as shown in
Figure 47. The first six bits are don't care bits. The
next two bits (PD1 andPD0) are control bits that
control which mode of operation the part is in
(normal mode or any one of three power-down
modes). A more complete description of the various
modes is located in the Power-Down Modes section.
The next 16 bits are the data bits. These bits are
transferred to the DAC register on the 24th falling
edge of SCLK.
SYNC INTERRUPT
In a normal write sequence, the SYNC line is kept
LOW for at least 24 falling edges of SCLK and the
DAC is updated on the 24th falling edge. However, if
SYNC is brought HIGH before the 24th falling edge,
it acts as an interrupt to the write sequence. The shift
register is reset, and the write sequence is seen as
invalid. Neither an update of the DAC register
contents nor a change in the operating mode occurs,
as shown in Figure 48.
POWER-ON RESET
The DAC8551 contains a power-on-reset circuit that
controls the output voltage during power up. On
power up, the DAC registers are filled with zeros and
the output voltages are 0V; they remain that way
until a valid write sequence is made to the DAC. The
power-on reset is useful in applications where it is
important to know the state of the output of the DAC
while it is in the process of powering up.
DB23
X
DB0
X
X
X
X
X
PD1
PD0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
Figure 47. DAC8551 Data Input Register Format
24th Falling Edge
24th Falling Edge
CLK
SYNC
DIN
DB23
DB80
DB23
DB80
Valid Write Sequence: Output Updates
on the 24th Falling Edge
Figure 48. SYNC Interrupt Facility
16
Submit Documentation Feedback
D1
D0
DAC8551
www.ti.com
SLAS429B – APRIL 2005 – REVISED OCTOBER 2006
POWER-DOWN MODES
The DAC8551 supports four separate modes of
operation. These modes are programmable by
setting two bits (PD1 and PD0) in the control
register. Table 1 shows how the state of the bits
corresponds to the mode of operation of the device.
power-down mode. There are three different options.
The output is connected internally to GND through a
1kΩ resistor, a 100kΩ resistor, or it is left
open-circuited (High-Z). The output stage is
illustrated in Figure 49.
VFB
Table 1. Operating Modes
PD1
(DB17)
PD0
(DB16)
0
0
Normal operation
–
–
Power-down modes
0
1
Output typically 1kΩ to GND
1
0
Output typically 100kΩ to GND
1
1
High-Z
OPERATING MODE
Resistor
String
DAC
Amplifier
Power-Down
Circuitry
When both bits are set to '0', the device works
normally with its typical current consumption of
200µA at 5V. However, for the three power-down
modes, the supply current falls to 200nA at 5V (50nA
at 3V). Not only does the supply current fall, but the
output stage is also internally switched from the
output of the amplifier to a resistor network of known
values. This configuration has the advantage that the
output impedance of the device is known while it is in
VOUT
Resistor
Network
Figure 49. Output Stage During Power-Down
All analog circuitry is shut down when the
power-down mode is activated. However, the
contents of the DAC register are unaffected when in
power-down. The time to exit power-down is typically
2.5µs for VDD = 5V, and 5µs for VDD = 3V. See the
Typical Characteristics for more information.
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DAC8551
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SLAS429B – APRIL 2005 – REVISED OCTOBER 2006
MICROPROCESSOR INTERFACING
MicrowireTM
DAC8551 to 8051 Interface
See Figure 50 for a serial interface between the
DAC8551 and a typical 8051-type microcontroller.
The setup for the interface is as follows: TXD of the
8051 drives SCLK of the DAC8551, while RXD
drives the serial data line of the device. The SYNC
signal is derived from a bit-programmable pin on the
port of the 8051. In this case, port line P3.3 is used.
When data are to be transmitted to the DAC8551,
P3.3 is taken LOW. The 8051 transmits data in 8-bit
bytes; thus, only eight falling clock edges occur in
the transmit cycle. To load data to the DAC, P3.3 is
left LOW after the first eight bits are transmitted, then
a second write cycle is initiated to transmit the
second byte of data. P3.3 is taken HIGH following
the completion of the third write cycle. The 8051
outputs the serial data in a format that has the LSB
first. The DAC8551 requires data with the MSB as
the first bit received. The 8051 transmit routine must
therefore take this into account, and mirror the data
as needed.
80C51/80L51(1)
DAC8554(1)
P3.3
SYNC
TXD
SCLK
RXD
DIN
NOTE: (1) Additional pins omitted for clarity.
Figure 50. DAC8551 to 80C51/80L51 Interface
DAC8551 to Microwire Interface
Figure 51 shows an interface between the DAC8551
and any Microwire-compatible device. Serial data are
shifted out on the falling edge of the serial clock and
is clocked into the DAC8551 on the rising edge of
the SK signal.
18
DAC8554(1)
CS
SYNC
SK
SCLK
SO
DIN
NOTE: (1) Additional pins omitted for clarity.
Figure 51. DAC8551 to Microwire Interface
DAC8551 to 68HC11 Interface
Figure 52 shows a serial interface between the
DAC8551 and the 68HC11 microcontroller. SCK of
the 68HC11 drives the SCLK of the DAC8551, while
the MOSI output drives the serial data line of the
DAC. The SYNC signal is derived from a port line
(PC7), similar to the 8051 diagram.
68HC11(1)
DAC8551(1)
PC7
SYNC
SCK
SCLK
MOSI
DIN
NOTE: (1) Additional pins omitted for clarity.
Figure 52. DAC8551 to 68HC11 Interface
The 68HC11 should be configured so that its CPOL
bit is '0' and its CPHA bit is '1'. This configuration
causes data appearing on the MOSI output to be
valid on the falling edge of SCK. When data are
being transmitted to the DAC, the SYNC line is held
LOW (PC7). Serial data from the 68HC11 are
transmitted in 8-bit bytes with only eight falling clock
edges occurring in the transmit cycle. (Data are
transmitted MSB first.) In order to load data to the
DAC8551, PC7 is left LOW after the first eight bits
are transferred, then a second and third serial write
operation are performed to the DAC. PC7 is taken
HIGH at the end of this procedure.
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DAC8551
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SLAS429B – APRIL 2005 – REVISED OCTOBER 2006
APPLICATION INFORMATION
The total typical current required (with a 5kΩ load on
the DAC output) is:
200mA ) 5V + 1.2mA
5kW
(2)
USING THE REF02 AS A POWER SUPPLY
FOR THE DAC8551
Due to the extremely low supply current required by
the DAC8551, an alternative option is to use the
REF02 (+5 V precision voltage reference) to supply
the required voltage to the device, as illustrated in
Figure 53.
The load regulation of the REF02 is typically
0.005%/mA, resulting in an error of 299µV for the
1.2mA current drawn from it. This value corresponds
to a 3.9LSB error.
+15V
BIPOLAR OPERATION USING THE DAC8551
The DAC8551 has been designed for single-supply
operation, but a bipolar output range is also possible
using the circuit in Figure 54. The circuit shown gives
an output voltage range of ±VREF. Rail-to-rail
operation at the amplifier output is achievable using
an OPA703 as the output amplifier.
+5V
REF02
285mA
SYNC
Three-Wire
Serial
Interface
SCLK
DAC8551
The output voltage for any input code can be
calculated as follows:
VOUT = 0V to 5V
ƪ
D Ǔ
ǒ65536
V O + VREF
DIN
ǒR R) R Ǔ * V
1
2
1
ǒRR Ǔƫ
2
REF
1
(3)
where D represents the input code in decimal
(0–65535).
Figure 53. REF02 as a Power Supply to the
DAC8551
With VREF = 5V, R1 = R2 = 10kΩ.
V O + 10 D * 5V
65536
This configuration is especially useful if the power
supply is quite noisy or if the system supply voltages
are at some value other than 5V. The REF02 outputs
a steady supply voltage for the DAC8551. If the
REF02 is used, the current it needs to supply to the
DAC8551 is 200µA. This configuration is with no
load on the output of the DAC. When a DAC output
is loaded, the REF02 also needs to supply the
current to the load.
ǒ
Ǔ
(4)
Using this example, an output voltage range of ±5V
with 0000h corresponding to a –5V output and
FFFFh corresponding to a 5V output can be
achieved. Similarly, using VREF = 2.5V, a ±2.5V
output voltage range can be achieved.
VREF
R2
10kW
+6V
R1
10kW
OPA703
5V
VFB
VREF
10mF
DAC8551
VOUT
–6V
0.1mF
Three-Wire
Serial Interface
Figure 54. Bipolar Output Range
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19
DAC8551
www.ti.com
SLAS429B – APRIL 2005 – REVISED OCTOBER 2006
LAYOUT
A precision analog component requires careful
layout,
adequate
bypassing,
and
clean,
well-regulated power supplies.
The DAC8551 offers single-supply operation, and it
often is used in close proximity with digital logic,
microcontrollers, microprocessors, and digital signal
processors. The more digital logic present in the
design and the higher the switching speed, the more
difficult it is to keep digital noise from appearing at
the output.
Due to the single ground pin of the DAC8551, all
return currents, including digital and analog return
currents for the DAC, must flow through a single
point. Ideally, GND would be connected directly to an
analog ground plane. This plane would be separate
from the ground connection for the digital
components until they were connected at the
power-entry point of the system.
20
The power applied to VDD should be well-regulated
and low-noise. Switching power supplies and dc/dc
converters often have high-frequency glitches or
spikes riding on the output voltage. In addition, digital
components can create similar high-frequency
spikes. This noise can easily couple into the DAC
output voltage through various paths between the
power connections and analog output.
As with the GND connection, VDD should be
connected to a 5V power-supply plane or trace that
is separate from the connection for digital logic until
they are connected at the power-entry point. In
addition, a 1µF to 10µF capacitor and 0.1µF bypass
capacitor are strongly recommended. In some
situations, additional bypassing may be required,
such as a 100µF electrolytic capacitor or even a Pi
filter made up of inductors and capacitors—all
designed to essentially low-pass filter the 5V supply,
removing the high-frequency noise.
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PACKAGE OPTION ADDENDUM
www.ti.com
18-Oct-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
DAC8551IADGKR
ACTIVE
VSSOP
DGK
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 105
D81
DAC8551IADGKRG4
ACTIVE
VSSOP
DGK
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 105
D81
DAC8551IADGKT
ACTIVE
VSSOP
DGK
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 105
D81
DAC8551IADGKTG4
ACTIVE
VSSOP
DGK
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 105
D81
DAC8551IDGKR
ACTIVE
VSSOP
DGK
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 105
D81
DAC8551IDGKRG4
ACTIVE
VSSOP
DGK
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 105
D81
DAC8551IDGKT
ACTIVE
VSSOP
DGK
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 105
D81
DAC8551IDGKTG4
ACTIVE
VSSOP
DGK
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 105
D81
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
(4)
18-Oct-2013
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jun-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
DAC8551IADGKR
VSSOP
DGK
8
DAC8551IADGKT
VSSOP
DGK
DAC8551IDGKR
VSSOP
DGK
DAC8551IDGKT
VSSOP
DGK
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
8
250
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
8
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
8
250
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jun-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
DAC8551IADGKR
VSSOP
DGK
8
2500
367.0
367.0
35.0
DAC8551IADGKT
VSSOP
DGK
8
250
367.0
367.0
35.0
DAC8551IDGKR
VSSOP
DGK
8
2500
367.0
367.0
35.0
DAC8551IDGKT
VSSOP
DGK
8
250
367.0
367.0
35.0
Pack Materials-Page 2
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