Cypress CY25811SCT Spread spectrum clock generator Datasheet

CY25811/12/14
Spread Spectrum Clock Generator
Features
Applications
■
4 to 32 MHz input frequency range
■
Printers and MFPs
■
4 to 128 MHz output frequency range
■
LCD panels
■
Accepts clock, crystal, and resonator inputs
■
Digital copiers
■
1x, 2x, and 4x frequency multiplication:
❐ CY25811: 1x; CY25812: 2x; CY25814: 4x
■
PDAs
■
CD-ROM, VCD, and DVD
■
Center and down spread modulation
■
Networking, LAN/WAN
■
Low power dissipation:
❐ 3.3V = 52 mW-typ at 6 MHz
❐ 3.3V = 60 mW-typ at12 MHz
❐ 3.3V = 72 mW-typ at 24 MHz
■
Scanners
■
Modems
■
Embedded digital systems
■
Low cycle to cycle jitter:
❐ 8 MHz = 480 ps-max
❐ 16 MHz = 400 ps-max
❐ 32 MHz = 450 ps-max
Benefits
■
Available in 8 pin SOIC and TSSOP packages
■
Commercial and industrial temperature ranges
■
Peak EMI reduction by 8 to 16 dB
■
Fast time to market
■
Cost reduction
Logic Block Diagram
300K
XIN 1
8pF
REFERENCE
DIVIDER
PD and
CP
LF
MODULATION
CONTROL
VCO
COUNTE
R
VCO
XOUT 8
8pF
VDD 7
INPUT
DECODER
LOGIC
VSS 2
Cypress Semiconductor Corporation
Document Number: 38-07112 Rev. *F
•
6
3
4
FRSEL
S1
S0
198 Champion Court
COUNTER
and
MUX
•
5
SSCLK
San Jose, CA 95134-1709
•
408-943-2600
Revised September 21, 2007
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CY25811/12/14
Pinouts
Figure 1. Pin Diagram - 8 Pin SOIC/TSSOP
XIN/CLKIN 1
VSS 2
S1 3
CY25811
CY25812
CY25814
S0 4
Table 1. Pin Definition - 8 Pin SOIC/TSSOP
Pin No.
Name
Type
8
XOUT
7
VDD
6
FRSEL
5
SSCLK
Description
1
Xin/CLK
2
VSS
3
S1
Digital Spread% control pin. 3-Level input (H-M-L). Default = M.
4
S0
Digital Spread% control pin. 3-Level input (H-M-L). Default = M.
5
SSCLK
Spread Spectrum output clock.
6
FRSEL
Input frequency range selection digital control input. 3-Level input (H-M-L). Default = M.
7
VDD
8
XOUT
Crystal, ceramic resonator or clock input pin
Power supply ground.
Positive power supply.
Crystal or ceramic resonator output pin.
Functional Description
The CY25811/12/14 products are Spread Spectrum Clock
Generator (SSCG) ICs used for the purpose of reducing electromagnetic interference (EMI) found in today’s high speed digital
electronic systems.
The devices use a Cypress proprietary phase-locked loop (PLL)
and Spread Spectrum Clock (SSC) technology to synthesize and
modulate the frequency of the input clock. By frequency
modulating the clock, the measured EMI at the fundamental and
harmonic frequencies is greatly reduced.
This reduction in radiated energy can significantly reduce the
cost of complying with regulatory agency requirements and
improve time to market without degrading system performance.
The input frequency range is 4 to 32 MHz and accepts clock,
crystal and ceramic resonator inputs. The output clock can be
selected to produce 1x, 2x, or 4x multiplication of the input
frequency with Spread Spectrum Frequency Modulation.
The use of 2x or 4x frequency multiplication eliminates the need
for higher order crystals and enables the user to generate up to
128 MHz Spread Spectrum Clock (SSC) by using only first order
crystals. This reduces the cost while improving the system clock
accuracy, performance and complexity.
Document Number: 38-07112 Rev. *F
Center Spread or Down Spread frequency modulation can be
selected by the user based on four discrete values of Spread %
for each Spread mode with the option of a Non Spread mode for
system test and verification purposes.
The CY25811/12/14 products are available in an 8 pin SOIC (150
mil.) package with a commercial operating temperature range of
0 to 70°C and Industrial Temperature range of –40 to 85°C. Refer
to CY25568 for multiple clock output options such as modulated
and unmodulated clock outputs or Power-down function. For
Automotive applications, refer to CY25811/12/14SE data sheets.
Input Frequency Range and Selection
The CY25811/12/14 input frequency range is 4 to 32 MHz. This
range is divided into three segments and controlled by a 3-Level
FRSEL pin as given in Table 2.
Table 2. Input Frequency Selection
FRSEL
Input Frequency Range
0
4.0 to 8.0 MHz
1
8.0 to 16.0 MHz
M
16.0 to 32.0 MHz
Page 2 of 12
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CY25811/12/14
Spread% Selection
The CY25811/12/14 SSCG products provide Center-Spread, Down-Spread and No-Spread functions. The amount of Spread% is
selected by using 3-Level. S0 and S1 digital inputs and Spread% values are given in Table 3.
Table 3. Spread% Selection
XIN
(MHz)
FRSEL
S1 = 0
S0 = 0
S1 = 0
S0 = M
S1 = 0
S0 = 1
S1 = M
S0 = 0
S1 = 1
S0 = 1
S1 = 1
S0 = 0
S1 = M
S0 = 1
S1 = 1
S0 = M
S1 = M
S0 = M
Center
(%)
Center
(%)
Center
(%)
Center
(%)
Down
(%)
Down
(%)
Down
(%)
Down
(%)
No Spread
4-5
0
±1.4
± 1.2
± 0.6
± 0.5
–3.0
–2.2
–1.9
–0.7
0
5-6
0
±1.3
± 1.1
± 0.5
± 0.4
–2.7
–1.9
–1.7
–0.6
0
6-7
0
±1.2
± 0.9
± 0.5
± 0.4
–2.5
–1.8
–1.5
–0.6
0
7-8
0
±1.1
± 0.9
± 0.4
± 0.3
–2.3
–1.7
–1.4
–0.5
0
8-10
1
±1.4
±1.2
± 0.6
± 0.5
–3.0
–2.2
–1.9
–0.7
0
10-12
1
±1.3
±1.1
± 0.5
± 0.4
–2.7
–1.9
–1.7
–0.6
0
12-14
1
±1.2
± 0.9
± 0.5
± 0.4
–2.5
–1.8
–1.5
–0.6
0
14-16
1
±1.1
± 0.9
± 0.4
± 0.3
–2.3
–1.7
–1.4
–0.5
0
16-20
M
±1.4
±1.2
± 0.6
± 0.5
–3.0
–2.2
–1.9
–0.7
0
20-24
M
±1.3
±1.1
± 0.5
± 0.4
–2.7
–1.9
–1.7
–0.6
0
24-28
M
±1.2
± 0.9
± 0.5
± 0.4
–2.5
–1.8
–1.5
–0.6
0
28-32
M
±1.1
± 0.9
± 0.4
± 0.3
–2.3
–1.7
–1.4
–0.5
0
3-Level Digital Inputs
Modulation Rate
S0, S1, and FRSEL digital inputs are designed to sense 3
different logic levels designated as High “1”, Low “0” and Middle
“M”. With this 3-Level digital input logic, the 3-Level Logic is able
to detect 9 different logic states.
S0, S1 and FRSEL pins include an on chip 20K (10K/10K)
resistor divider. No external application resistors are needed to
implement the 3-Level logic levels as shown below:
Spread Spectrum Clock Generators utilize frequency modulation
(FM) to distribute energy over a specific band of frequencies. The
maximum frequency of the clock (fmax), and minimum frequency
of the clock (fmin) determine this band of frequencies. The time
required to transition from fmin to fmax and back to fmin is the
period of the Modulation Rate. The Modulation Rate of SSCG
clocks are generally referred to in terms of frequency, or:
Logic Level “0”: 3–Level logic pin connected to GND.
fmod = 1/Tmod.
Logic Level “M”: 3–Level logic pin left floating (no connection).
The input clock frequency, fin, and the internal divider determine
the Modulation Rate.
Logic Level “1”: 3–Level logic pin connected to VDD.
Figure 2 illustrates how to implement 3–Level Logic.
In the case of CY25811/2/4 devices, the (Spread Spectrum)
modulation Rate, fmod, is given by the following formula:
Figure 2. 3–Level Logic
fmod = fin/DR
LOGIC
MIDDLE (M)
LOGIC
LOW (0)
S0, S1
and
FRSEL
UNCONNECTED
S0, S1
and
FRSEL
to VSS
VSS
Document Number: 38-07112 Rev. *F
LOGIC
HIGH (H)
S0, S1
and
FRSEL
to VDD
where: fmod is the Modulation Rate; fin is the Input Frequency;
and DR is the Divider Ratio as given in Table 4. Notice that Input
Frequency Range is set by FRSEL.
Table 4. Modulation Rate Divider Ratios
FRSEL
Input Frequency Range
(MHz)
Divider Ratio
(DR)
0
4 to 8
128
1
8 to 16
256
M
16 to 32
512
Page 3 of 12
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CY25811/12/14
Input and Output Frequency Selection
The relationship between input frequency versus output frequency in terms of device selection and FRSEL setting is given in Table 5.
As shown, the input frequency range is selected by FRSEL and is the same for CY25811, CY25812, and CY25814. The selection of
CY25811 (1x), CY25812 (2x) or CY25814 (4x) determines the frequency multiplication at the output (SSCLK, Pin 5) with respect to
input frequency (XIN, Pin-1).
Table 5. Input and Output Frequency Selection
Input Frequency Range
(MHz)
FRSEL
Product
Multiplication
Output Frequency Range
(MHz)
4 to 8
0
CY25811
1x
4 to 8
8 to 16
1
CY25811
1x
8 to 16
16 to 32
M
CY25811
1x
16 to 32
4 to 8
0
CY25812
2x
8 to 16
8 to 16
1
CY25812
2x
16 to 32
16 to 32
M
CY25812
2x
32 to 64
4 to 8
0
CY25814
4x
16 to 32
8 to 16
1
CY25814
4x
32 to 64
16 to 32
M
CY25814
4x
64 to 128
Document Number: 38-07112 Rev. *F
Page 4 of 12
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CY25811/12/14
Absolute Maximum Conditions (both Commercial and Industrial Grades)[1,2]
Parameter
Description
Condition
Min
Max
Unit
VDD
Supply Voltage
–0.5
4.6
V
VIN
Input Voltage
Relative to V SS
–0.5
VDD + 0.5
VDC
TS
Temperature, Storage
Non Functional
–65
150
°C
TA1
Temperature, Operating Ambient
Functional, C-Grade
0
70
°C
TA2
Temperature, Operating Ambient
Functional, I-Grade
–40
85
°C
TJ
Temperature, Junction
Functional
–
150
°C
–
V
Max
Unit
3.97
3.63
V
0
0.15VDD
V
ESDHBM
ESD Protection (Human Body Model) MIL-STD-883, Method 3015
UL-94
Flammability Rating
MSL
Moisture Sensitivity Level
2000
@1/8 in.
V–0
1
DC Electrical Specifications (Commercial Grade)
Parameter
Description
Condition
Min
VDD
3.3 Operating Voltage
3.3 ± 10%
VIL
Input Low Voltage
S0, S1 and FRSEL Inputs
VIM
Input Middle Voltage
S0, S1 and FRSEL Inputs
0.40VDD 0.60VDD
V
VIH
Input High Voltage
S0, S1 and FRSEL Inputs
0.85VDD
VDD
V
VOL1
Output Low Voltage
IOL = 4 ma, SSCLK Output
–
0.4
V
VOL2
Output Low Voltage
IOL = 10 ma, SSCLK Output
–
1.2
V
VOH1
Output High Voltage
IOH = 4 ma, SSCLK Output
2.4
–
V
VOH2
Output High Voltage
IOH = 6 ma, SSCLK Output
2.0
–
V
CIN1
Input Pin Capacitance
XIN (Pin 1) and XOUT (Pin 8)
3.5
9.0
pF
CIN2
Input Pin Capacitance
All Digital Inputs
2.8
6.0
pF
CL
Output Load Capacitor
SSCLK Output
–
15
pF
IDD1
Dynamic Supply Current
Fin = 12 MHz, no load
–
28
mA
IDD2
Dynamic Supply Current
Fin = 24 MHz, no load
–
33
mA
IDD3
Dynamic Supply Current
Fin = 32 MHz, no load
–
40
mA
Notes
1. Operation at any Absolute Maximum Rating is not implied.
2. Single Power Supply: The voltage on any input or I/O pin cannot exceed the power pin during power up.
Document Number: 38-07112 Rev. *F
Page 5 of 12
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CY25811/12/14
AC Electrical Specifications (Commercial Grade)
Parameter
Description
Condition
Min
Max
Unit
FIN
Input Frequency Range
Clock, Crystal, or Ceramic Resonator Input
4
32
MHz
TR1
Clock Rise Time
SSCLK, CY25811 and CY25812
2.0
5.0
ns
TF1
Clock Fall Time
SSCLK, CY25811 and CY25812
1.6
4.4
ns
TR2
Clock Rise Time
SSCLK, only CY25814 when FRSEL = M
1.0
2.2
ns
TF2
Clock Fall Time
SSCLK, only CY25814 when FRSEL = M
0.8
2.2
ns
TDCIN
Input Clock Duty Cycle
XIN
40
60
%
TDCOUT
Output Clock Duty Cycle
SSCLK
40
60
%
TCCJ1
Cycle to Cycle Jitter, Spread on
Fin = 4 MHz, Fout = 4 MHz, CY25811
–
800
ps
TCCJ2
Cycle to Cycle Jitter, Spread on
Fin = 8 MHZ, Fout = 8 MHz, CY25811
–
480
ps
TCCJ3
Cycle to Cycle Jitter, Spread on
Fin = 8 MHz, Fout = 16 MHz, CY25812
–
400
ps
TCCJ4
Cycle to Cycle Jitter, Spread on
Fin = 16 MHz, Fout = 32 MHz, CY25812
–
450
ps
TCCJ5
Cycle to Cycle Jitter, Spread on
Fin = 16 MHz, Fout = 64 MHz, CY25814
–
550
ps
TCCJ6
Cycle to Cycle Jitter, Spread on
Fin = 32 MHz, Fout = 128 MHz, CY25814
–
380
ps
TSU
PLL Lock Time
Fom VDD 3.0V to valid SSCLK
–
3
ms
DC Electrical Specifications (Industrial Grade)
Parameter
Description
VDD
3.3 Operating Voltage
Condition
3.3 ± 5%
Min
Max
Unit
3.135
3.465
V
0
0.13VDD
V
0.40VDD 0.60VDD
0.85VDD
VDD
V
VIL
Input Low Voltage
S0, S1 and FRSEL Inputs
VIM
Input Middle Voltage
S0, S1 and FRSEL Inputs
VIH
Input High Voltage
S0, S1 and FRSEL Inputs
VOL1
Output Low Voltage
IOL = 4 ma, SSCLK Output
VOL2
Output Low Voltage
VOH1
Output High Voltage
VOH2
Output High Voltage
IOH = 6 ma, SSCLK Output
2.0
–
V
CIN1
Input Pin Capacitance
XIN (Pin 1) and XOUT (Pin 8)
3.5
9.0
pF
CIN2
Input Pin Capacitance
All Digital Inputs
2.8
6.0
pF
CL
Output Load Capacitor
SSCLK Output
–
15
pF
IDD1
Dynamic Supply Current
Fin = 12 MHz, no load
–
28
mA
IDD2
Dynamic Supply Current
Fin = 24 MHz, no load
–
33
mA
IDD3
Dynamic Supply Current
Fin = 32 MHz, no load
–
41
mA
Min
Max
Unit
V
–
0.4
V
IOL = 10 ma, SSCLK Output
–
1.2
V
IOH = 4 ma, SSCLK Output
2.4
–
V
AC Electrical Specifications (Industrial Grade)
Parameter
Description
Condition
FIN
Input Frequency Range
Clock, Crystal or Ceramic Resonator Input
4
32
MHz
TR1
Clock Rise Time
SSCLK, CY25811, and CY25812
2.0
5.0
ns
TF1
Clock Fall Time
SSCLK, CY25811, and CY25812
1.6
4.4
ns
TR2
Clock Rise Time
SSCLK, only CY25814 when FRSEL = M
1.0
2.2
ns
TF2
Clock Fall Time
SSCLK, only CY25814 when FRSEL = M
0.8
2.2
ns
TDCIN
Input Clock Duty Cycle
XIN
40
60
%
TDCOUT
Output Clock Duty Cycle
SSCLK
40
60
%
TCCJ1
Cycle to Cycle Jitter, Spread on
Fin = 6MHz, CY25811/12/14
–
650
ps
Document Number: 38-07112 Rev. *F
Page 6 of 12
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CY25811/12/14
AC Electrical Specifications (Industrial Grade)
Parameter
Description
Condition
Min
Max
Unit
TCCJ2
Cycle-to-Cycle Jitter, Spread on
Fin = 12MHZ, CY25811/12/14
–
630
ps
TCCJ3
Cycle-to-Cycle Jitter, Spread on
Fin = 24MHz, CY25811/12/14
–
520
ps
TSU
PLL Lock Time
From VDD 3.0V to valid SSCLK
–
4
ms
Characteristic Curves
The following curves demonstrate the characteristic behavior of the CY25811/12/14 when tested over a number of environmental and
application specific parameters. These are typical performance curves and are not meant to replace any parameter specified in DC
and AC Specification tables.
Figure 3. Characteristic Curves
600
2.75
6.0 MHz
32.0 MHz
500
2.5
BW %
CCJ (ps)
400
300
2.25
200
2
100
1.75
0
4
8
12
16
20
24
28
32
-40
-25
-10
5
20
Jitter vs. Input Frequency (No Load)
FRSEL = M
16 - 32 MHz
BW (%)
IDD (mA)
24
FRSEL = 1
8 - 16 MHz
20
18
16
FRSEL = 0
4 - 8 MHz
14
12
10
4
4.5
5
5.5
6
65
80
95
110
125
3
2.9
2.8
2.7
28
22
50
Bandwidth % vs. Temperature
30
26
35
Temp (C)
Input Frequency (MHz)
6.5
7
7.5
Frequency (MHz), no load, normalized to FRSEL = 0, (4 - 8 MHz).
IDD vs. Frequency (FRSEL = 0, 1, M)
8
2.6
2.5
2.4
2.3
2.2
2.1
2
1.9
1.8
2.8
4.0 MHz
8.0 MHz
2.9
3
3.1
3.2
3.3
3.4
3.5
3.6
3.7
VDD (volts)
Bandwidth % vs. VDD
.
Document Number: 38-07112 Rev. *F
Page 7 of 12
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CY25811/12/14
SSCG Profiles
CY25811/12/14 SSCG products use a non-linear “optimized” frequency profile as shown In Figure 4. The use of Cypress proprietary
“optimized” frequency profile maintains flat energy distribution over the fundamental and higher order harmonics. This results in
additional EMI reduction in electronic systems.
Figure 4. Spread Spectrum Profiles (Frequency vs. Time)
Xin = 6.0 MHz
S1, S0 = 0
FRSEL = 0
Xin = 12.0 MHz
S1, S0 = 0
FRSEL = 1
SSCLK1 = 6.0 MHz
P/N = CY25811
SSCLK1 = 48.0 MHz
P/N = CY25814
Document Number: 38-07112 Rev. *F
Xin = 24.0 MHz
S1, S0 = 0
FRSEL = M
Xin = 24.0 MHz
S1, S0 = 0
FRSEL = M
SSCLK1 = 24.0 MHz
P/N = CY25811
SSCLK1 = 96.0 MHz
P/N = CY25814
Page 8 of 12
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CY25811/12/14
Application Schematic
VDD
C3
0.1 uF
7
C2
1
XIN
VDD
5
27 pF
Y1
25 MHz
8
C3
SSCLK
25 MHz (CY25811)
50 MHz (CY25812)
100 MHz (CY25814)
XOUT
27 pF
CY25811
CY25812
CY25814
3
S1
6
N/C
FRSEL
S0
4
VSS
2
Document Number: 38-07112 Rev. *F
Page 9 of 12
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CY25811/12/14
Ordering Information
Part Number
Package Type
Product Flow
CY25811SCT
8-pin SOIC – Tape and Reel
Commercial, 0° to 70°C
CY25811SI
8-pin SOIC
Industrial, –40° to 85°C
CY25811SIT
8-pin SOIC – Tape and Reel
Industrial, –40° to 85°C
CY25812SC
8-pin SOIC
Commercial, 0° to 70°C
CY25812SCT
8-pin SOIC – Tape and Reel
Commercial, 0° to 70°C
CY25812ZC
8-pin TSSOP
Commercial, 0° to 70°C
CY25812ZCT
8-pin TSSOP – Tape and Reel
Commercial, 0° to 70°C
CY25814SCT
8-pin SOIC – Tape and Reel
Commercial, 0° to 70°C
8-pin SOIC
Commercial, 0° to 70°C
Pb Free Devices
CY25811SXC
CY25811SXCT
8-pin SOIC – Tape and Reel
Commercial, 0° to 70°C
CY25811SXI
8-pin SOIC
Industrial, –40° to 85°C
CY25811SXIT
8-pin SOIC – Tape and Reel
Industrial, –40° to 85°C
CY25811ZXC
8-pin TSSOP
Commercial, 0° to 70°C
CY25811ZXCT
8-pin TSSOP – Tape and Reel
Commercial, 0° to 70°C
CY25812SXC
8-pin SOIC
Commercial, 0° to 70°C
CY25812SXCT
8-pin SOIC – Tape and Reel
Commercial, 0° to 70°C
CY25812SXI
8-pin SOIC
Industrial, –40° to 85°C
CY25812SXIT
8-pin SOIC – Tape and Reel
Industrial, –40° to 85°C
CY25812ZXC
8-pin TSSOP
Commercial, 0° to 70°C
CY25812ZXCT
8-pin TSSOP – Tape and Reel
Commercial, 0° to 70°C
CY25814SXC
8-pin SOIC
Commercial, 0° to 70°C
CY25814SXCT
8-pin SOIC – Tape and Reel
Commercial, 0° to 70°C
CY25814SXI
8-pin SOIC
Industrial, –40° to 85°C
CY25814SXIT
8-pin SOIC – Tape and Reel
Industrial, –40° to 85°C
CY25814ZXC
8-pin TSSOP
Commercial, 0° to 70°C
CY25814ZXCT
8-pin TSSOP – Tape and Reel
Commercial, 0° to 70°C
Document Number: 38-07112 Rev. *F
Page 10 of 12
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CY25811/12/14
Package Drawing and Dimensions
Figure 5. 8-Pb (150-Mil) SOIC S8
PIN 1 ID
4
1
1. DIMENSIONS IN INCHES[MM] MIN.
MAX.
2. PIN 1 ID IS OPTIONAL,
ROUND ON SINGLE LEADFRAME
RECTANGULAR ON MATRIX LEADFRAME
0.150[3.810]
0.157[3.987]
3. REFERENCE JEDEC MS-012
0.230[5.842]
0.244[6.197]
4. PACKAGE WEIGHT 0.07gms
PART #
S08.15 STANDARD PKG.
5
SZ08.15 LEAD FREE PKG.
8
0.189[4.800]
0.196[4.978]
0.010[0.254]
0.016[0.406]
SEATING PLANE
X 45°
0.061[1.549]
0.068[1.727]
0.004[0.102]
0.050[1.270]
BSC
0.004[0.102]
0.0098[0.249]
0°~8°
0.0075[0.190]
0.0098[0.249]
0.016[0.406]
0.035[0.889]
0.0138[0.350]
0.0192[0.487]
51-85066-*C
Figure 6. 8-Pb Thin Shrunk Small Outline Package (4.40 MM Body) Z8
PIN 1 ID
1
DIMENSIONS IN MM[INCHES] MIN.
MAX.
6.25[0.246]
6.50[0.256]
4.30[0.169]
4.50[0.177]
8
0.65[0.025]
BSC.
0.19[0.007]
0.30[0.012]
1.10[0.043] MAX.
0.25[0.010]
BSC
GAUGE
PLANE
0°-8°
0.076[0.003]
0.85[0.033]
0.95[0.037]
0.05[0.002]
0.15[0.006]
2.90[0.114]
3.10[0.122]
Document Number: 38-07112 Rev. *F
SEATING
PLANE
0.50[0.020]
0.70[0.027]
51-85093-*A
0.09[[0.003]
0.20[0.008]
Page 11 of 12
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CY25811/12/14(s)
Document History Page
Document Title: CY25811/12/14 Spread Spectrum Clock Generator
Document Number: 38-07112
REV. ECN NO.
**
107516
Issue
Date
Orig. of
Change
06/14/02
NDP
Converted from IMI to Cypress
Description of Change
*A
108002
06/29/02
NDP
Deleted Junction Temp. in Absolute Maximum Ratings
*B
121578
01/29/03
RGL
Converted from Word to FrameMaker
Added 8-pin TSSOP package in Commercial Temp. only
Added an Industrial Temperature Range to all existing 8-pin SOIC packages
*C
125550
05/14/03
RGL
Changed IDD values from 19.6/22/27.2 to 25/30/35 in Commercial Grade DC Specs
table
Changed IDD values from 24/26.5/33 to 26/32/37 in Industrial grade DC Specs table
Changed TCCJ1/2 values from 675/260 to 800/450 in Commercial grade AC Specs table
Changed TCCJ1 value from 350 to 650 in Industrial grade AC Specs table
*D
131941
12/24/03
RGL
Removed automotive in the Applications section
Changed the Output Clock Duty Cycle (TDCOUT) from min. 45 and max. 55 to 40 and
60% respectively for both industrial and commercial grade
Changed the min. Input Low Voltage (VIL) from 0.15VDD to 0.13VDD
Removed preliminary from the industrial AC/DC Electrical Specifications table
*E
231057
See ECN
RGL
Added Pb Free Devices
*F
1499165 See ECN
KVM
Updated Ordering Information table
Corrected jitter values in features section on page 1
Changed:VDD from ±5% to ±10%, CIN1 min from 6 to 3.5 pF, CIN2 min from 3.5 to 2.8
pF, TF1 min from 2 to 1.6 ns, and TF2 min from 1.0 to 0.8 ns.
Commercial grade: IDD1 max from 25 to 28 mA, IDD2 max from 30 to 33 mA, IDD3
max from 35 to 40 mA, TCCJ2 from 450 to 480 ps, TCCJ4 from 380 to 450 ps, and
TCCJ5 from 380 to 550 ps
Industrial grade: IDD1 max from 26 to 28 mA, IDD2 max from 32 to 33 mA, IDD3 max
from 37 to 41 mA, TCCJ2 from 400 to 630 ps,and TCCJ3 from 400 to 520 ps
© Cypress Semiconductor Corporation, 2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any
circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical,
life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical
components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-07112 Rev. *F
Revised September 21, 2007
Page 12 of 12
Intel and Pentium are registered trademarks of Intel Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders.
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