Cypress CY2SSTV855ZIT Differential clock buffer/driver Datasheet

CY2SSTV855
Differential Clock Buffer/Driver
Features
Functional Description
• Phase-locked loop (PLL) clock distribution for Double
Data Rate Synchronous DRAM applications
• 1:5 differential outputs
• External feedback pins (FBINT, FBINC) are used to
synchronize the outputs to the clock input
• SSCG: Spread Aware™ for electromagnetic
interference (EMI) reduction
• 28-pin TSSOP package
The CY2SSTV855 is a high-performance, very-low-skew,
very-low-jitter zero-delay buffer that distributes a differential
clock input pair (SSTL_2) to four differential (SSTL_2) pairs of
clock outputs and one differential pair of feedback clock
outputs. In support of low power requirements, when
power-down is HIGH, the outputs switch in phase and
frequency with the input clock. When power-down is LOW, all
outputs are disabled to a high-impedance state and the PLL is
shut down.
The device supports a low-frequency power-down mode.
When the input is < 20 MHz, the PLL is disabled and the
outputs are put in the Hi-Z state. When the input frequency is
> 20 MHz, the PLL and outputs are enabled.
• Conform to JEDEC DDR specifications
When AVDD is tied to ground, the PLL is turned off and
bypassed with the input reference clock gated to the outputs.
The Cypress CY2SSTV855 is Spread Aware and supports
tracking of Spread Spectrum clock inputs to reduce EMI
Pin Configuration
Block Diagram
GND
YC0
YT0
VDDQ
YT0
YC0
PWRDWN
YT1
YC1
GND
CLKINT
CLKINC
YT2
YC2
VDDQ
AVDD
AGND
CLKINT
CLKINC
FBINT
FBINC
PLL
VDDQ
YT1
YT3
YC3
YC1
GND
FBOUTT
FBOUTC
28
27
26
25
24
23
22
21
20
19
18
17
16
15
CY2SSTV855
AVDD
Powerdown
and test
logic
1
2
3
4
5
6
7
8
9
10
11
12
13
14
GND
YC3
YT3
VDDQ
PWRDWN
FBINT
FBINC
VDDQ
FBOUTC
FBOUTT
VDDQ
YT2
YC2
GND
28 pin TSSOP
Cypress Semiconductor Corporation
Document #: 38-07459 Rev. *D
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised May 07, 2004
CY2SSTV855
Pin Definition[1, 2]
Pin
Name
I/O
Description
6
CLKINT
I
True Clock Input. Low Voltage Differential True Clock Input.
7
CLKINC
I
Complementary Clock Input. Low Voltage Differential Complementary Clock Input.
22
FBINC
I
Feedback Complementary Clock Input. Differential Input Connect to FBOUTC for
accessing the PLL.
23
FBINT
I
Feedback True Clock Input. Differential Input Connect to FBOUTT for accessing the
PLL.
3,12,17,26
YT(0:3)
O
True Clock Outputs. Differential Outputs.
2,13,16,27
YC(0:3)
O
Complementary Clock Outputs. Differential Outputs.
19
FBOUTT
O
Feedback True Clock Output. Differential Outputs. Connect to FBINT for normal operation. A bypass delay capacitor at this output will control Input Reference/Output Clocks
phase relationships.
20
FBOUTC
O
Feedback Complementary Clock Output. Differential Outputs. Connect to FBINC for
normal operation. A bypass delay capacitor at this output will control Input
Reference/Output Clocks phase relationships.
24
PWRDWN
I
Control input to turn device in the power-down mode.
4,8,11,18,21,25
VDDQ
2.5V Power Supply for Output Clock Buffers.2.5V Nominal.
9
AVDD
2.5V Power Supply for PLL. 2.5V Nominal.
1,5,14,15,28
GND
Ground
10
AGND
Analog Ground. 2.5V Analog Ground.
Zero-delay Buffer
When used as a zero-delay buffer the CY2SSTV855 will likely
be in a nested clock tree application. For these applications
the CY2SSTV855 offers a differential clock input pair as a PLL
reference. The CY2SSTV855 then can lock onto the reference
and translate with near zero delay to low-skew outputs. For
normal operation, the external feedback differential input,
FBINT/C, is connected to the feedback output, FBOUTT/C. By
connecting the feedback output to the feedback input the
propagation delay through the device is eliminated. The PLL
works to align the output edge with the input reference edge
thus producing a near zero delay. The reference frequency
affects the static phase offset of the PLL and thus the relative
delay between the inputs and outputs.
When AVDD is strapped LOW, the PLL is turned off and
bypassed for test purposes.
Function Table
Inputs
Outputs
AVDD
PWRDWN
CLKINT
CLKINC
YT(0:3)
YC(0:3)
FBOUTT
FBOUTC
PLL
GND
H
L
H
L
H
L
H
BYPASSED/OFF
GND
H
H
L
H
L
H
L
BYPASSED/OFF
2.5V
H
L
H
L
H
L
H
On
2.5V
H
H
L
H
L
H
L
On
2.5V
X
< 20 MHz
< 20 MHz
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Off
Notes:
1. PU = internal pull-up.
2. A bypass capacitor (0.1µF) should be placed as close as possible to each positive power pin (< 0.2”). If these bypass capacitors are not close to the pins their
high frequency filtering characteristic will be cancelled by the lead inductance of the traces.
Document #: 38-07459 Rev. *D
Page 2 of 7
CY2SSTV855
Differential Parameter Measurement Information
CLKINT
CLKINC
FBINT
FBINC
t(∅) n+1
t(∅)n
t(∅)n =
Σ 1=N
n
t(∅)n
N (is large number of samples)
N
Figure 1. Static Phase Offset
CLKINT
CLKINC
FBINT
FBINC
td(∅)
t(∅)
td(∅)
td(∅)
t( ∅ )
td(∅)
Figure 2. Dynamic Phase Offset
Y[0:3], FBOUTT
YC[0:3], FBOUTC
Y[0:3], FBOUTT
YC[0:3], FBOUTC
tsk(o)
Figure 3. Output Skew
Document #: 38-07459 Rev. *D
Page 3 of 7
CY2SSTV855
Differential Parameter Measurement Information (continued)
YT[0:3], FBOUTT
YC[0:3], FBOUTC
t(hper_N+1)
t(hper_n)
1
f(o)
tjit(hper) = thper(n) - 1
2x fo
Figure 4. Half-period Jitter
YT[0:3], FBOUTT
YC[0:3], FBOUTC
t c(n)
t c(n)
tjit(cc) = tc(n)-tc(n+1)
Figure 5. Cycle-to-cycle Jitter
VDD
VDD
V D D /2
16pF
C LKT
60 O hm
VTR
R T = 120 O hm
C LKC
60 O hm
16pF
VCP
R e c e iv e r
V D D /2
Figure 6. Differential Signal Using Direct Termination Resistor
Document #: 38-07459 Rev. *D
Page 4 of 7
CY2SSTV855
Absolute Maximum Conditions[3]
Input Voltage Relative to VSS:...............................VSS – 0.3V
Input Voltage Relative to VDDQ or AVDD: ............. VDD + 0.3V
Storage Temperature: ................................ –65°C to + 150°C
Operating Temperature: ................................ –40°C to +85°C
Maximum Power Supply: ................................................3.5V
precautions should be taken to avoid application of any
voltage higher than the maximum rated voltages to this circuit.
For proper operation, Vin and Vout should be constrained to the
range:
VSS < (Vin or Vout) < VDD.
Unused inputs must always be tied to an appropriate logic
voltage level (either VSS or VDD).
This device contains circuitry to protect the inputs against
damage due to high static voltages or electric field; however,
DC Electrical Specifications (AVDD = VDDQ = 2.5V ± 5%, TA = –40°C to +85°C)[4]
Parameter
Description
Conditions
[5]
Min.
Typ.
Max.
Unit
VID
Differential Input Voltage
CLKINT, FBINT
0.36
VDDQ + 0.6
V
VIX
Differential Input Crossing
Voltage[6]
CLKTIN, FBINT
(VDDQ/2) –
0.2
VDDQ/2
(VDDQ/2) + 0.2
V
IIN
Input Current
VIN = 0V or VIN = VDDQ, CLKINT,
FBINT
–10
–
10
µA
IOL
Output Low Current
VDDQ = 2.375V, VOUT = 1.2V
26
35
–
mA
IOH
Output High Current
VDDQ = 2.375V, VOUT = 1V
–18
–32
–
mA
VOL
Output Low Voltage
VDDQ = 2.375V, IOL = 12 mA
–
0.6
V
VOH
Output High Voltage
VDDQ = 2.375V, IOH = –12 mA
VOUT
Output Voltage Swing[7]
VOC
Output Crossing Voltage[8]
IOZ
High-Impedance Output
Current
IDDQ
Dynamic Supply Current[9] VDDQ = 170 MHz
–
IDD
PLL Supply Current
Cin
Input Pin Capacitance
1.7
–
–
V
1.1
–
VDDQ – 0.4
V
(VDDQ/2) – 0.2 VDDQ/2
VO = GND or VO = VDDQ
(VDDQ/2) + 0.2
V
10
µA
235
300
mA
–
9
12
mA
–
4
–
pF
–10
AVDD only
AC Electrical Specifications (AVDD = VDDQ = 2.5V±5%, TA = –40°C to +85°C)[10, 11]
Parameter
Description
Conditions
AVDD = 2.5V ± 0.2V
Min.
Typ.
Max.
Unit
60
170
MHz
40
60
%
fCLK
Operating Clock Frequency
tDC
Input Clock Duty Cycle[12]
tLOCK
Maximum PLL lock Time
tSL(O)
Output Clocks Slew Rate
tPZL, tPZH
Output Enable Time (all outputs)[13]
30
ns
tPLZ, tPHZ
Output Disable Time (all outputs)[13]
10
ns
tCCJ
Cycle to Cycle Jitter
f > 66 MHz
–100
100
ps
tJITT(H-PER)
Half-period jitter
f > 66 MHz
–100
100
ps
tPLH
Low-to-High Propagation Delay, CLKINT to YT[0:3]
6
ns
20% to 80% of VOD
1
1.5
3.5
100
µs
2
V/ns
Notes:
3. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
4. Unused inputs must be held HIGH or LOW to prevent them from floating.
5. Differential input signal voltage specifies the differential voltage |VTR – VCP| required for switching, where VTR is the true input level and VCP is the complementary input level.
6. Differential cross-point input voltage is expected to track VDDQ and is the voltage at which the differential signals must be crossing.
7. For load conditions see Figure 6.
8. The value of VOC is expected to be |VTR + VCP|/2. In case of each clock directly terminated by a 120Ω resistor. See Figure 6.
9. All outputs switching loaded with 16 pF in 60Ω environment. See Figure 6.
10. Parameters are guaranteed by design and characterization. Not 100% tested in production.
11. PLL is capable of meeting the specified parameters while supporting SSC synthesizers with modulation frequency between 30 kHz and 33.3 kHz with a
downspread of –0.5%
12. While the pulse skew is almost constant over frequency, the duty cycle error increases at higher frequencies. This is due to the formula: duty cycle = tWH/tC,
where the cycle time (tC) decreases as the frequency goes up.
13. Refers to transition of non-inverting output.
14. All differential input and output terminals are terminated with 120Ω/16 pF as shown in Figure 6.
Document #: 38-07459 Rev. *D
Page 5 of 7
CY2SSTV855
AC Electrical Specifications (AVDD = VDDQ = 2.5V±5%, TA = –40°C to +85°C)[10, 11] (continued)
Parameter
Description
Conditions
tPHL
High-to-Low Propagation Delay, CLKINT to YT[0:3]
tSK(0)
Any Output to Any Output Skew[14]
[14]
t(Ø)
Static Phase Offset
tD(Ø)
Dynamic Phase Offset
f > 66 MHz
Min.
Typ.
Max.
Unit
1.5
–
3.5
6
ns
–
100
ps
–150
–
150
ps
–150
–
150
ps
Ordering Information
Part Number
Package Type
CY2SSTV855ZC
28-pin TSSOP
Product Flow
Commercial, 0° to 70°C
CY2SSTV855ZCT
28-pin TSSOP – Tape and Reel
Commercial, 0° to 70°C
CY2SSTV855ZI
28-pin TSSOP
Industrial, –40° to 85°C
CY2SSTV855ZIT
28-pin TSSOP – Tape and Reel
Industrial,–40° to 85°C
Package Drawing and Dimensions
28-Lead Thin Shrunk Small Outline Package (4.40-mm Body) Z28.173
DIMENSIONS IN MM[INCHES] MIN.
MAX.
PIN 1 ID
1
REFERENCE JEDEC MO-153
PACKAGE WEIGHT 0.16 gms
4.30[0.169]
4.50[0.177]
6.25[0.246]
6.50[0.256]
PART #
Z28.173 STANDARD PKG.
ZZ28.173 LEAD FREE PKG.
28
0.65[0.025]
BSC.
0.19[0.007]
0.30[0.012]
1.10[0.043] MAX.
0.25[0.010]
BSC
GAUGE
PLANE
0°-8°
0.076[0.003]
0.85[0.033]
0.95[0.037]
9.60[0.378]
9.80[0.386]
0.05[0.002]
0.15[0.006]
SEATING
PLANE
0.50[0.020]
0.70[0.027]
0.09[[0.003]
0.20[0.008]
51-85120-*A
Spread Aware is a trademark of Cypress Semiconductor. All product and company names mentioned in this document may be
the trademarks of their respective holders.
Document #: 38-07459 Rev. *D
Page 6 of 7
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges
CY2SSTV855
Document History Page
Document Title: CY2SSTV855 Differential Clock Buffer/Driver
Document #: 38-07459
REV.
ECN NO.
Issue Date
Orig. of
Change
Description of Change
**
117544
09/09/02
HWT
*A
122934
12/18/02
RBI
Add power up requirements to maximum ratings information
*B
124087
04/23/03
RGL
Changed the package drawing and dimension from Z28 to Z29
Corrected the block diagram
Changed the Output Enable/Disable time from 3/3 to 30/10 ns
Eliminated Dynamic Phase Offset spec.
Changed the Phase Error Jitter spec. from ±50 to ±150 ps
*C
215389
See ECN
RGL
Added an Industrial Grade Devices (temp from –40°C to 85).
*D
224444
See ECN
RGL
Removed “PRELIMINARY”
Document #: 38-07459 Rev. *D
New data sheet
Page 7 of 7
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