CD54AC112, CD74AC112 DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCHS325 – JANUARY 2003 D D D D D D CD54AC112 . . . F PACKAGE CD74AC112 . . . E OR M PACKAGE (TOP VIEW) AC Types Feature 1.5-V to 5.5-V Operation and Balanced Noise Immunity at 30% of the Supply Voltage Speed of Bipolar F, AS, and S, With Significantly Reduced Power Consumption Balanced Propagation Delays ±24-mA Output Drive Current – Fanout to 15 F Devices SCR-Latchup-Resistant CMOS Process and Circuit Design Exceeds 2-kV ESD Protection Per MIL-STD-883, Method 3015 1CLK 1K 1J 1PRE 1Q 1Q 2Q GND 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC 1CLR 2CLR 2CLK 2K 2J 2PRE 2Q description/ordering information The ’AC112 devices contain two independent J-K negative-edge-triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the J and K inputs meeting the setup-time requirements is transferred to the outputs on the negative-going edge of the clock pulse (CLK). Clock triggering occurs at a voltage level and is not directly related to the fall time of the clock pulse. Following the hold-time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by tying J and K high. ORDERING INFORMATION PDIP – E –55°C 55°C to 125°C ORDERABLE PART NUMBER PACKAGE† TA SOIC – M Tube CD74AC112E Tube CD74AC112M Tape and reel CD74AC112M96 TOP-SIDE MARKING CD74AC112E AC112M CDIP – F Tube CD54AC112F3A CD54AC112F3A † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2003, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 CD54AC112, CD74AC112 DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCHS325 – JANUARY 2003 FUNCTION TABLE (each flip-flop) INPUTS OUTPUTS PRE CLR CLK J K Q Q L H X X X H L H L X X X L H L L X X X H† H† H H ↓ L L Q0 Q0 H H ↓ H L H L H H ↓ L H L H H H ↓ H H H H H X X Toggle Q0 Q0 † Output states are unpredictable if PRE and CLR go high simultaneously after both being low at the same time. logic diagram (positive logic) Q Q PRE CLR J K CLK absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6 V Input clamp current, IIK (VI < 0 V or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO < 0 V or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous output current, IO (VO > 0 V or VO < VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA Package thermal impedance, θJA (see Note 2): E package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W M package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 CD54AC112, CD74AC112 DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCHS325 – JANUARY 2003 recommended operating conditions (see Note 3) –55°C to 125°C TA = 25°C VCC Supply voltage VIH High-level input voltage UNIT MIN MAX MIN MAX MIN MAX 1.5 5.5 1.5 5.5 1.5 5.5 VCC = 1.5 V VCC = 3 V 1.2 1.2 1.2 2.1 2.1 2.1 VCC = 5.5 V VCC = 1.5 V 3.85 VIL Low-level input voltage VI VO Input voltage 0 Output voltage 0 IOH IOL High-level output current ∆t/∆v Input transition rise or fall rate 3.85 VCC = 3 V VCC = 5.5 V Low-level output current –40°C to 85°C V 3.85 0.3 0.3 0.3 0.9 0.9 0.9 1.65 VCC VCC 1.65 0 0 V VCC VCC V 1.65 0 0 VCC VCC V V VCC = 4.5 V to 5.5 V VCC = 4.5 V to 5.5 V –24 –24 –24 mA 24 24 24 mA VCC = 1.5 V to 3 V VCC = 3.6 V to 5.5 V 50 50 50 20 20 20 ns/V NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN IOH = –50 µA VOH VI = VIH or VIL IOH = –4 mA IOH = –24 mA IOH = –50 mA† IOH = –75 mA† IOL = 50 µA VOL II ICC VI = VIH or VIL VI = VCC or GND VI = VCC or GND, –55°C to 125°C TA = 25°C MAX MIN –40°C to 85°C MAX MIN 1.5 V 1.4 1.4 1.4 3V 2.9 2.9 2.9 4.5 V 4.4 4.4 4.4 3V 2.58 2.4 2.48 4.5 V 3.94 3.7 3.8 5.5 V UNIT MAX V 3.85 5.5 V 3.85 1.5 V 0.1 0.1 0.1 3V 0.1 0.1 0.1 4.5 V 0.1 0.1 0.1 IOL = 12 mA IOL = 24 mA IOL = 50 mA† 3V 0.36 0.5 0.44 4.5 V 0.36 0.5 0.44 IOL = 75 mA† 5.5 V 5.5 V 5.5 V IO = 0 5.5 V Ci V 1.65 1.65 ±0.1 ±1 ±1 µA 4 80 40 µA 10 10 10 pF † Test one output at a time, not exceeding 1-second duration. Measurement is made by forcing indicated current and measuring voltage to minimize power dissipation. Test verifies a minimum 50-Ω transmission-line drive capability at 85°C and 75-Ω transmission-line drive capability at 125°C. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 CD54AC112, CD74AC112 DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCHS325 – JANUARY 2003 timing requirements over recommended operating free-air temperature range, VCC = 1.5 V (unless otherwise noted) –55°C to 125°C MIN fclock Clock frequency tw Pulse duration tsu th trec –40°C to 85°C MAX MIN UNIT MAX 8 9 MHz CLK high or low 63 55 CLR or PRE low 56 49 Setup time, before CLK↓ J or K 50 44 ns Hold time, after CLK↓ J or K 0 0 ns Recovery time, before CLK↓ CLR↑ or PRE↑ 31 27 ns ns timing requirements over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) –55°C to 125°C MIN fclock Clock frequency tw Pulse duration tsu th trec –40°C to 85°C MAX MIN UNIT MAX 71 81 MHz CLK high or low 7 6 CLR or PRE low 6.3 5.5 Setup time, before CLK↓ J or K 5.6 4.9 ns Hold time, after CLK↓ J or K 0 0 ns Recovery time, before CLK↓ CLR↑ or PRE↑ 3.5 3..1 ns ns timing requirements over recommended operating free-air temperature0 range, VCC = 5 V ± 0.5 V (unless otherwise noted) –55°C to 125°C MIN 4 fclock Clock frequency tw Pulse duration tsu th Setup time, before CLK↓ Hold time, after CLK↓ trec Recovery time, before CLK↓ CLR↑ or PRE↑ MAX –40°C to 85°C MIN 100 POST OFFICE BOX 655303 UNIT MAX 114 MHz CLK high or low 5 4.4 CLR or PRE low 4.5 3.9 J or K 4 3.5 ns J or K 0 0 ns 2.5 2.2 ns • DALLAS, TEXAS 75265 ns CD54AC112, CD74AC112 DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCHS325 – JANUARY 2003 switching characteristics over recommended operating free-air temperature range, VCC = 1.5 V, CL = 50 pF (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) –55°C to 125°C MIN fmax tPLH tPHL MAX –40°C to 85°C MIN 8 CLK Q or Q CLR or PRE CLK Q or Q CLR or PRE UNIT MAX 9 MHz 129 117 153 139 129 117 153 139 ns ns switching characteristics over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V, CL = 50 pF (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) fmax tPLH tPHL –55°C to 125°C MIN MAX MIN 3.6 14.4 3.7 13.1 4.3 17.1 4.4 15.5 3.6 14.4 3.7 13.1 4.3 17.1 4.4 15.5 71 CLK Q or Q CLR or PRE CLK Q or Q CLR or PRE –40°C to 85°C UNIT MAX 81 MHz ns ns switching characteristics over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V, CL = 50 pF (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) fmax tPLH tPHL –55°C to 125°C MIN MAX 100 CLK Q or Q CLR or PRE CLK Q or Q CLR or PRE –40°C to 85°C MIN UNIT MAX 114 MHz 2.6 10.3 2.7 9.4 3.1 12.2 3.2 11.1 2.6 10.3 2.7 9.4 3.1 12.2 3.2 11.1 ns ns operating characteristics, VCC = 5 V, TA = 25°C PARAMETER Cpd Power dissipation capacitance POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TYP UNIT 56 pF 5 CD54AC112, CD74AC112 DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCHS325 – JANUARY 2003 PARAMETER MEASUREMENT INFORMATION S1 R1 = 500 Ω† From Output Under Test 2 × VCC Open GND CL = 50 pF (see Note A) R2 = 500 Ω† TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND tw VCC † When VCC = 1.5 V, R1 = R2 = 1 kΩ Input 50% VCC 50% VCC 0V LOAD CIRCUIT VOLTAGE WAVEFORMS PULSE DURATION CLR Input VCC Reference Input VCC 50% VCC 50% VCC 0V 0V tsu trec Data 50% Input 10% VCC 50% VCC CLK 90% VOLTAGE WAVEFORMS RECOVERY TIME tf VCC 50% VCC 50% VCC tPLH tPHL 50% 10% 90% 90% tr tPHL Out-of-Phase Output VCC 50% VCC 10% 0 V VOLTAGE WAVEFORMS SETUP AND HOLD AND INPUT RISE AND FALL TIMES 0V In-Phase Output 90% tr 0V Input th 90% VOH 50% VCC 10% VOL tf Output Waveform 1 S1 at 2 × VCC (see Note B) tPLH 50% VCC 10% tf 50% 10% 90% tr VOH VOL VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES VCC Output Control 50% VCC 50% VCC 0V tPLZ tPZL 50% VCC tPHZ tPZH Output Waveform 2 S1 at GND (see Note B) ≈VCC 20% VCC VOL 50% VCC VOH 80% VCC ≈0 V VOLTAGE WAVEFORMS OUTPUT ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and test-fixture capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns. Phase relationships between waveforms are arbitrary. D. For clock inputs, fmax is measured with the input duty cycle at 50%. E. The outputs are measured one at a time with one input transition per measurement. F. tPLH and tPHL are the same as tpd. G. tPZL and tPZH are the same as ten. H. tPLZ and tPHZ are the same as tdis. I. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 6-Dec-2006 PACKAGING INFORMATION Orderable Device Status (1) Package Type CD54AC112F3A ACTIVE CDIP J 16 1 TBD A42 SNPB N / A for Pkg Type CD74AC112E ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type CD74AC112EE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type CD74AC112M ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74AC112M96 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74AC112M96E4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74AC112ME4 ACTIVE SOIC D 16 CU NIPDAU Level-1-260C-UNLIM Package Drawing Pins Package Eco Plan (2) Qty 40 Green (RoHS & no Sb/Br) Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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