ESD11A3.3DT5G SERIES Transient Voltage Suppressors ESD Protection Diodes in Ultra Small SOT−1123 Package The ESD11A Series is designed to protect voltage sensitive components from damage due to ESD. These parts provide excellent ESD clamping capability and fast response time to enhance the immunity of the end application from system level ESD stress such as IEC61000−4−2. Two uni−directional TVS diodes are housed in the ultra small SOT−1123 package, making these parts ideal for ESD protection on designs where board space is at a premium, such as cell phones, MP3 players and many other portable handheld electronic devices. http://onsemi.com PIN 1. CATHODE 2. CATHODE 3. ANODE 1 3 2 MARKING DIAGRAM Specification Features: • Low Clamping Voltage • Small Body Outline Dimensions: • • • • • • • XM SOT−1123 CASE 524AA 0.039” x 0.024” (1.0 mm x 0.6 mm) Low Body Height: 0.016″ (0.4 mm) Stand−off Voltage: 3.3 V − 5 V Low Leakage Response Time is Typically < 1 ns IEC61000−4−2 Level 4 ESD Protection AEC−Q101 Qualified and PPAP Capable These are Pb−Free Devices X = Specific Device Code M = Date Code ORDERING INFORMATION Device Package Shipping† ESD11AxxDT5G SOT−1123 (Pb−Free) 8000/Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Mechanical Characteristics: CASE: Void-free, transfer-molded, thermosetting plastic Epoxy Meets UL 94 V−0 LEAD FINISH: 100% Matte Sn (Tin) MOUNTING POSITION: Any DEVICE MARKING INFORMATION QUALIFIED MAX REFLOW TEMPERATURE: 260°C See specific marking information in the device marking column of the table on page 2 of this data sheet. Device Meets MSL 1 Requirements Table 1. MAXIMUM RATINGS Rating IEC 61000−4−2 (ESD) Symbol Contact Value Unit ±15 kV Total Power Dissipation on FR−5 Board (Note 1) @ TA = 25°C °PD° 150 mW Storage Temperature Range Tstg −55 to +150 °C Junction Temperature Range TJ −55 to +125 °C Lead Solder Temperature − Maximum (10 Second Duration) TL 260 °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. FR−5 = 1.0 x 0.75 x 0.62 in. See Application Note AND8308/D for further description of ESD maximum ratings. © Semiconductor Components Industries, LLC, 2013 January, 2013 − Rev. 3 1 Publication Order Number: ESD11A3.3D/D ESD11A3.3DT5G SERIES Table 2. ELECTRICAL CHARACTERISTICS I (TA = 25°C unless otherwise noted) Symbol IF Parameter IPP Maximum Reverse Peak Pulse Current VC Clamping Voltage @ IPP VRWM IR VBR Working Peak Reverse Voltage IR VF IT Maximum Reverse Leakage Current @ VRWM V Breakdown Voltage @ IT IT Test Current IF Forward Current VF Forward Voltage @ IF Ppk Peak Power Dissipation C VC VBR VRWM IPP Uni−Directional TVS Capacitance @VR = 0 and f = 1 MHz Table 3. ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted, VF = 0.9 V Max. @ IF = 10 mA for all types) Device Device Marking VRWM (V) IR (mA) @ VRWM VBR (V) @ IT (Note 2) C (pF), uni−directional (Note 3) IT Max Max Min mA Typ VC (V) @ IPP = 1 A (Note 5) VC (V) IEC61000−4−2 (Note 6) Max Max Typ ESD11A3.3DT5G 2* 3.3 1.0 5.2 1.0 25 35 7.8 Figures 1 thru 4 ESD11A5.0DT5G 3* 5.0 0.1 6.2 1.0 20 30 9.5 Figures 1 thru 4 *Rotated 90° clockwise. 2. VBR is measured with a pulse test current IT at an ambient temperature of 25°C. 3. Uni−directional capacitance at f = 1 MHz, VR = 0 V, TA = 25°C (pin1 to pin 3; pin 2 to pin 3). 4. Bi−directional capacitance at f = 1 MHz, VR = 0 V, TA = 25°C (pin1 to pin 2). 5. Surge current waveform per Figure 7. 6. Typical waveform. For test procedure see Figures 5 and 6 and Application Note AND8307/D. http://onsemi.com 2 ESD11A3.3DT5G SERIES Figure 1. ESD11A3.3D Clamping Voltage Screenshot Positive 8 kV contact per IEC 61000−4−2 Figure 2. ESD11A3.3D Clamping Voltage Screenshot Negative 8 kV contact per IEC 61000−4−2 Figure 3. ESD11A5.0D Clamping Voltage Screenshot Positive 8 kV contact per IEC 61000−4−2 Figure 4. ESD11A5.0D Clamping Voltage Screenshot Negative 8 kV contact per IEC 61000−4−2 http://onsemi.com 3 ESD11A3.3DT5G SERIES IEC61000−4−2 Waveform IEC 61000−4−2 Spec. Ipeak Level Test Voltage (kV) First Peak Current (A) Current at 30 ns (A) Current at 60 ns (A) 1 2 7.5 4 2 2 4 15 8 4 3 6 22.5 12 6 4 8 30 16 8 100% 90% I @ 30 ns I @ 60 ns 10% tP = 0.7 ns to 1 ns Figure 5. IEC61000−4−2 Spec ESD Gun Oscilloscope TVS 50 W Cable 50 W Figure 6. Diagram of ESD Test Setup The following is taken from Application Note AND8308/D − Interpretation of Datasheet Parameters for ESD Devices. systems such as cell phones or laptop computers it is not clearly defined in the spec how to specify a clamping voltage at the device level. ON Semiconductor has developed a way to examine the entire voltage waveform across the ESD protection diode over the time domain of an ESD pulse in the form of an oscilloscope screenshot, which can be found on the datasheets for all ESD protection diodes. For more information on how ON Semiconductor creates these screenshots and how to interpret them please refer to AND8307/D. ESD Voltage Clamping For sensitive circuit elements it is important to limit the voltage that an IC will be exposed to during an ESD event to as low a voltage as possible. The ESD clamping voltage is the voltage drop across the ESD protection diode during an ESD event per the IEC61000−4−2 waveform. Since the IEC61000−4−2 was written as a pass/fail spec for larger % OF PEAK PULSE CURRENT 100 PEAK VALUE IRSM @ 8 ms tr 90 PULSE WIDTH (tP) IS DEFINED AS THAT POINT WHERE THE PEAK CURRENT DECAY = 8 ms 80 70 60 HALF VALUE IRSM/2 @ 20 ms 50 40 30 tP 20 10 0 0 20 40 t, TIME (ms) 60 Figure 7. 8 X 20 ms Pulse Waveform http://onsemi.com 4 80 ESD11A3.3DT5G SERIES PACKAGE DIMENSIONS SOT−1123 CASE 524AA ISSUE C −X− D NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL. 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS. MILLIMETERS DIM MIN MAX A 0.34 0.40 b 0.15 0.28 b1 0.10 0.20 c 0.07 0.17 D 0.75 0.85 E 0.55 0.65 0.35 0.40 e HE 0.95 1.05 L 0.185 REF L2 0.05 0.15 −Y− 1 3 E 2 TOP VIEW A c HE SIDE VIEW 3X b L2 STYLE 4: PIN 1. CATHODE 2. CATHODE 3. ANODE 0.08 X Y e 2X 3X b1 L BOTTOM VIEW SOLDERING FOOTPRINT* 1.20 3X 0.34 0.26 1 0.38 2X 0.20 PACKAGE OUTLINE DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. 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