DS90C032QML www.ti.com SNLS203D – MARCH 2006 – REVISED APRIL 2013 DS90C032QML LVDS Quad CMOS Differential Line Receiver Check for Samples: DS90C032QML FEATURES DESCRIPTION • The DS90C032 is a quad CMOS differential line receiver designed for applications requiring ultra low power dissipation and high data rates. 1 2 • • • • • • • Single Event Latchup (SEL) Immune 120 MeVcm2/mg High Impedance LVDS Inputs with Power-Off. Accepts Small Swing (330 mV) Differential Signal Levels Low Power Dissipation Low Differential Skew Low Chip to Chip Skew Pin Compatible with DS26C32A Compatible with IEEE 1596.3 SCI LVDS Standard The DS90C032 accepts low voltage differential input signals and translates them to CMOS (TTL compatible) output levels. The receiver supports a TRI-STATE function that may be used to multiplex outputs. The receiver also supports OPEN Failsafe and terminated (100Ω) input Failsafe with the addition of external failsafe biasing. Receiver output will be HIGH for both Failsafe conditions. The DS90C032 provides power-off high impedance LVDS inputs. This feature assures minimal loading effect on the LVDS bus lines when VCC is not present. The DS90C032 and companion line driver (DS90C031) provide a new alternative to high power pseudo-ECL devices for high speed point-to-point interface applications. Connection Diagrams Figure 1. Dual-In-Line See Package Number NAD0016A & NAC0016A Figure 2. LCCC Package See Package Number NAJ0020A 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2006–2013, Texas Instruments Incorporated DS90C032QML SNLS203D – MARCH 2006 – REVISED APRIL 2013 www.ti.com Functional Diagram and Truth Table Block Diagram Receiver ENABLES EN EN* L H All other combinations of ENABLE inputs 2 INPUTS OUTPUT RI+ − RI− RO X Z VID ≥ 0.1V H VID ≤ −0.1V L Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: DS90C032QML DS90C032QML www.ti.com SNLS203D – MARCH 2006 – REVISED APRIL 2013 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) −0.3V to +6V Supply Voltage (VCC) Input Voltage (RI+, RI−) Enable Input Voltage −0.3V to +5.8V −0.3V to (VCC +0.3V) (EN, EN*) Output Voltage (RO) −0.3V to (VCC +0.3V) Storage Temperature Range (TStg) −65°C ≤ TA ≤ +150°C Maximum Lead Temperature, Soldering (4 seconds) Maximum Package Power Dissipation at +25°C +260°C (2) LCCC Package 1830 mW CLGA (NAD) 1400 mW CLGA (NAC) 1400 mW Thermal Resistance θJA LCCC Package 82°C/W CLGA (NAD) 145°C/W CLGA (NAC) 145°C/W θJC LCCC Package 20°C/W CLGA (NAD) 20°C/W CLGA (NAC) 20°C/W ESD Rating (1) (2) (3) (3) 2KV Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. Derate LCCC at 12.2mW/°C above +25°C. Derate CLGA at 6.8mW/°C above +25°C Human body model, 1.5 kΩ in series with 100 pF. Recommended Operating Conditions Supply Voltage (VCC) Receiver Input Voltage Min Typ Max +4.5V +5.0V +5.5V +25°C +125°C Gnd −55°C Operating Free Air Temperature (TA) 2.4V Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: DS90C032QML 3 DS90C032QML SNLS203D – MARCH 2006 – REVISED APRIL 2013 www.ti.com Quality Conformance Inspection Table 1. Mil-Std-883, Method 5005 - Group A 4 Subgroup Description 1 Static tests at Temp (°C) +25 2 Static tests at +125 3 Static tests at -55 4 Dynamic tests at +25 5 Dynamic tests at +125 6 Dynamic tests at -55 7 Functional tests at +25 8A Functional tests at +125 8B Functional tests at -55 9 Switching tests at +25 10 Switching tests at +125 11 Switching tests at -55 12 Settling time at +25 13 Settling time at +125 14 Settling time at -55 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: DS90C032QML DS90C032QML www.ti.com SNLS203D – MARCH 2006 – REVISED APRIL 2013 DS90C032 Electrical Characteristics, DC Parameters (1) Symbol Parameter Conditions Notes Min Max Units Subgroups VThL Differential Input Low Threshold VCM = +1.2V See (2) -100 mV 1, 2, 3 VThH Differential Input High Threshold VCM = +1.2V See (2) 100 mV 1, 2, 3 IIn Input Current ( Input Pins) VCC=5.5V, VI = 2.4V ±10 µA 1, 2, 3 VCC = 5.5V, VI = 0 ±10 µA 1, 2, 3 VCC = 0.0V, VI = 2.4V ±10 µA 1, 2, 3 ±10 µA 1, 2, 3 V 1, 2, 3 0.3 V 1, 2, 3 -100 mA 1, 2, 3 ±10 µA 1, 2, 3 VCC = 0.0V, VI = 0.0V VOH Output High Voltage VCC= 4.5V, IOH = -0.4 mA, VID = 200mV VOL Output Low Voltage VCC = 4.5, IOL = 2 mA, VID = -200mV IOS Output Short Circuit Current Enabled, VO = 0V IOZ Output TRI-STATE Current Disabled, VO = 0V or VCC 3.8 -15 (2) VIH Input High Voltage See VIL Input Low Voltage See (2) II Input Current (Enable Pins) VCL ICC ICCZ (1) (2) V 1, 2, 3 0.8 V 1, 2, 3 VCC = 5.5V ±10 µA 1, 2, 3 Input Clamp Voltage ICl = -18mA -1.5 V 1, 2, 3 No Load Supply Current EN, EN* = VCC or Gnd, Inputs Open 11 mA 1, 2, 3 EN, EN* = 2.4 or 0.5, Inputs Open 11 mA 1, 2, 3 EN = Gnd, EN* = VCC , Inputs Open 11 mA 1, 2, 3 No Load Supply Current Receivers Disabled 2.0 Pre and post irradiation limits are identical to those listed under AC and DC electrical characteristics except as listed in the “Post Radiation Limits” table. Radiation end point limits for the noted parameters are ensured only for the conditions, as specified. Tested during VOH and VOL tests. Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: DS90C032QML 5 DS90C032QML SNLS203D – MARCH 2006 – REVISED APRIL 2013 www.ti.com DS90C032 Electrical Characteristics, AC Parameters (1) The following conditions apply, unless otherwise specified. AC: VCC = 4.5V / 5.0V / 5.5V, CL = 20pF Symbol Parameter Conditions Notes Min Max Units Subgroups tPHLD Differential Propagation Delay High to Low VID = 200mV, Input pulse = 1.1V to 1.3V, VI = 1.2V (0V differential) to VO = 1/2 VCC 1.0 8.0 ns 9, 10, 11 tPLHD Differential Propagation Delay Low to High VID = 200mV, Input pulse = 1.1V to 1.3V, VI = 1.2V (0V differential) to VO = 1/2 VCC 1.0 8.0 ns 9, 10, 11 tSkD Differential Skew |tPHLD - tPLHD| CL = 20pF, VID = 200mV 3.0 ns 9, 10, 11 tSk1 Channel to Channel Skew CL = 20pF, VID = 200mV See (2) 3.0 ns 9, 10, 11 tSk2 Chip to Chip Skew CL = 20pF, VID = 200mV See (3) 7.0 ns 9, 10, 11 tPLZ Disable Time Low to Z Input pulse = 0V to 3.0V, VO = VOL+ 0.5V, RL = 1KΩ to VCC, VI = 1.5V 20 ns 9, 10, 11 tPHZ Disable Time High to Z Input pulse = 0V to 3.0V, VI = 1.5V, VO = VOH- 0.5V, RL = 1KΩ to Gnd 20 ns 9, 10, 11 tPZH Enable Time Z to High Input pulse = 0V to 3.0V, VI = 1.5V, VO = 50%, RL = 1KΩ to Gnd 20 ns 9, 10, 11 tPZL Enable Time Z to Low Input pulse = 0V to 3.0V, VI = 1.5V, VO = 50%, RL = 1KΩ to VCC 20 ns 9, 10, 11 (1) Pre and post irradiation limits are identical to those listed under AC and DC electrical characteristics except as listed in the “Post Radiation Limits” table. Radiation end point limits for the noted parameters are ensured only for the conditions, as specified. Channel-to-Channel Skew is defined as the difference between the propagation delay of one channel and that of the others on the same chip with an event on the inputs. Chip-to-Chip Skew is defined as the difference between the minimum and maximum specified differential propagation delays. (2) (3) DS90C032 Electrical Characteristics, AC/DC Post Radiation Limits (1) Symbol ICC ICCZ (1) 6 Parameter No Load Supply Current No Load Supply Current Receivers Disabled Max Units Subgroups EN, EN* = VCC or Gnd, Inputs Open 20 mA 1 EN, EN* = 2.4 or 0.5, Inputs Open 20 mA 1 EN = Gnd, EN* = VCC, Inputs Open 20 mA 1 Conditions Notes Min Pre and post irradiation limits are identical to those listed under AC and DC electrical characteristics except as listed in the “Post Radiation Limits” table. Radiation end point limits for the noted parameters are ensured only for the conditions, as specified. Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: DS90C032QML DS90C032QML www.ti.com SNLS203D – MARCH 2006 – REVISED APRIL 2013 Parameter Measurement Information Figure 3. Figure 4. Receiver Propagation Delay and Transition Time Test Circuit Figure 5. Receiver Propagation Delay and Transition Time Waveforms A. CL includes load and test jig capacitance. B. S1 = VCC for tPZL and tPLZ measurements. C. S1 = Gnd for tPZH and tPHZ measurements. Figure 6. Receiver TRI-STATE Delay Test Circuit Figure 7. Receiver TRI-STATE Delay Waveforms Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: DS90C032QML 7 DS90C032QML SNLS203D – MARCH 2006 – REVISED APRIL 2013 www.ti.com Typical Performance Characteristics 8 Output High Voltage vs Power Supply Voltage Output High Voltage vs Ambient Temperature Figure 8. Figure 9. Output Low Voltage vs Power Supply Voltage Output Low Voltage vs Ambient Temperature Figure 10. Figure 11. Output Short Circuit Current vs Power Supply Voltage Output Short Circuit Current vs Ambient Temperature Figure 12. Figure 13. Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: DS90C032QML DS90C032QML www.ti.com SNLS203D – MARCH 2006 – REVISED APRIL 2013 Typical Performance Characteristics (continued) Differential Propagation Delay vs Power Supply Voltage Differential Propagation Delay vs Ambient Temperature Figure 14. Figure 15. Differential Skew vs Power Supply Voltage Differential Skew vs Ambient Temperature Figure 16. Figure 17. Transition Time vs Power Supply Voltage Transition Time vs Ambient Temperature Figure 18. Figure 19. Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: DS90C032QML 9 DS90C032QML SNLS203D – MARCH 2006 – REVISED APRIL 2013 www.ti.com TYPICAL APPLICATION Figure 20. Point-to-Point Application APPLICATIONS INFORMATION LVDS drivers and receivers are intended to be primarily used in an uncomplicated point-to-point configuration as is shown in Figure 20. This configuration provides a clean signaling environment for the quick edge rates of the drivers. The receiver is connected to the driver through a balanced media which may be a standard twisted pair cable, a parallel pair cable, or simply PCB traces. Typically the characteristic impedance of the media is in the range of 100Ω. A termination resistor of 100Ω should be selected to match the media, and is located as close to the receiver input pins as possible. The termination resistor converts the current sourced by the driver into a voltage that is detected by the receiver. Other configurations are possible such as a multi-receiver configuration, but the effects of a mid-stream connector(s), cable stub(s), and other impedance discontinuities as well as ground shifting, noise margin limits, and total termination loading must be taken into account. The DS90C032 differential line receiver is capable of detecting signals as low as 100 mV, over a ±1V commonmode range centered around +1.2V. This is related to the driver offset voltage which is typically +1.2V. The driven signal is centered around this voltage and may shift ±1V around this center point. The ±1V shifting may be the result of a ground potential difference between the driver's ground reference and the receiver's ground reference, the common-mode effects of coupled noise, or a combination of the two. Both receiver input pins should honor their specified operating input voltage range of 0V to +2.4V (measured from each pin to ground), exceeding these limits may turn on the ESD protection circuitry which will clamp the bus voltages. Receiver Failsafe The LVDS receiver is a high gain, high speed device that amplifies a small differential signal (20mV) to CMOS logic levels. Due to the high gain and tight threshold of the receiver, care should be taken to prevent noise from appearing as a valid signal. The receiver’s internal failsafe circuitry is designed to source/sink a small amount of current, providing failsafe protection (a stable known state of HIGH output voltage) for floating and terminated (100Ω) receiver inputs in low noise environment (differential noise < 10mV). • Open Input Pins TheDS90C032 is a quad receiver device, and if an application requires only 1, 2 or 3 receivers, the unused channel(s) inputs should be left OPEN. Do not tie unused receiver inputs to ground or any other voltages. The input is biased by internal high value pull up and pull down resistors to set the output to a HIGH state. This internal circuitry will ensure a HIGH, stable output state for open inputs. • Terminated Input The DS90C032 requires external failsafe biasing for terminated input failsafe. Terminated input failsafe is the case of a receiver that has a 100Ω termination across its inputs and the driver is in the following situations. Unplugged from the bus, or the driver output is in TRI-STATE or in power-off condition. The use of external biasing resistors provide a small bias to set the differential input voltage while the line is un-driven, and therefore the receiver output will be in HIGH state. If the driver is removed from the bus but the cable is still present and floating, the unplugged cable can become a floating antenna that can pick up noise. The LVDS receiver is designed to detect very small amplitude and width signals and recover them to standard logic levels. Thus, if the cable picks up more than 10mV of differential noise, the receiver may respond. To insure that any noise is seen as commonmode and not differential, a balanced interconnect and twisted pair cables is recommended, as they help to ensure that noise is coupled common to both lines and rejected by the receivers. • Operation in environment with greater than 10mV differential noise 10 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: DS90C032QML DS90C032QML www.ti.com SNLS203D – MARCH 2006 – REVISED APRIL 2013 TI recommends external failsafe biasing on its LVDS receivers for a number of system level and signal quality reasons. First, only an application that requires failsafe biasing needs to employ it. Second, the amount of failsafe biasing is now an application design parameter and can be custom tailored for the specific application. In applications in low noise environments, they may choose to use a very small bias if any. For applications with less balanced interconnects and/or in high noise environments they may choose to boost failsafe further. TI's "LVDS Owner’s Manual provides detailed calculations for selecting the proper failsafe biasing resistors. Third, the common-mode voltage is biased by the resistors during the un-driven state. This is selected to be close to the nominal driver offset voltage (VOS). Thus when switching between driven and un-driven states, the common-mode modulation on the bus is held to a minimum. For additional Failsafe Biasing information, please refer to Application Note AN-1194 (SNLA051) for more detail. Pin Descriptions Pin No. (SOIC) Name 2, 6, 10, 14 RI+ Description Non-inverting receiver input pin 1, 7, 9, 15 RI− Inverting receiver input pin 3, 5, 11, 13 RO Receiver output pin 4 EN Active high enable pin, OR-ed with EN* 12 EN* Active low enable pin, OR-ed with EN 16 VCC Power supply pin, +5V ± 10% 8 Gnd Ground pin Radiation Environments Careful consideration should be given to environmental conditions when using a product in a radiation environment. Total Ionizing Dose Radiation hardness assured (RHA) products are those part numbers with a total ionizing dose (TID) level specified in the Ordering Information table on the front page. Testing and qualification of these products is done on a wafer level according to MIL-STD-883G, Test Method 1019.7, Condition A and the “Extended room temperature anneal test” described in section 3.11 for application environment dose rates less than 0.19 rad(Si)/s. Wafer level TID data is available with lot shipments. Single Event Latch-Up and Functional Interrupt One time single event latch-up (SEL) and single event functional interrupt (SEFI) testing was preformed according to EIA/JEDEC Standard, EIA/JEDEC57. The linear energy transfer threshold (LETth) shown in the Features on the front page is the maximum LET tested. A test report is available upon request. Single Event Upset A report on single event upset (SEU) is available upon request. Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: DS90C032QML 11 DS90C032QML SNLS203D – MARCH 2006 – REVISED APRIL 2013 www.ti.com Table 2. Revision History Released 12 Revision Section Changes 3/01/06 A New Release, Corporate format 1 MDS data sheet converted into Corp. data sheet format. MNDS90C032-X-RH Rev 1B1 will be archived. 10/10/06 B Applications Information - Pg. 10, Physical Dimensions - Pg. 12 Deleted Shorted Inputs paragraph - page 10. Updated Physical Dimensions package drawings E20A, W16A to current revision - page 12. Revision A will be Archived. 9/28/2010 C Receiver Table - Pg. 2, Application Information - Pg. 9 & 10 Order Information Table, General Description, Applications Information section Deleted Full Fail-safe OPEN/SHORT or terminated Page 2. & Paragraph RECEIVER FAIL-SAFE and 1, 2, 3 - Page 9 & 10. Revision B will be Archived. Copied general description and Receiver Failsafe from commercial d/s DS90C032B, dated Sept. 2003. Removed Code K devices. Added Radiation Environments paragraph to data sheet. Revision C will be Archived. 4/12/2013 D New revision Changed layout of National Data Sheet to TI format Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: DS90C032QML PACKAGE OPTION ADDENDUM www.ti.com 12-Apr-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) 5962-9583401Q2A ACTIVE LCCC NAJ 20 50 TBD Call TI Call TI -55 to 125 DS90C032E -QML Q 5962-95834 01Q2A ACO 01Q2A >T 5962-9583401VFA ACTIVE CFP NAD 16 19 TBD Call TI Call TI -55 to 125 DS90C032WQMLV Q 5962-95834 01VFA ACO 01VFA >T 5962L9583401VFA ACTIVE CFP NAD 16 19 TBD Call TI Call TI -55 to 125 DS90C032WL QMLV Q 5962L95834 01VFA ACO 01VFA >T 5962L9583401VZA ACTIVE CFP NAC 16 42 TBD Call TI Call TI -55 to 125 DS90C032WGL QMLV Q 5962L95834 01VZA ACO 01VZA >T DS90C032E-QML ACTIVE LCCC NAJ 20 50 TBD Call TI Call TI -55 to 125 DS90C032E -QML Q 5962-95834 01Q2A ACO 01Q2A >T DS90C032W-QMLV ACTIVE CFP NAD 16 19 TBD Call TI Call TI -55 to 125 DS90C032WQMLV Q 5962-95834 01VFA ACO 01VFA >T DS90C032WGLQMLV ACTIVE CFP NAC 16 42 TBD Call TI Call TI -55 to 125 DS90C032WGL QMLV Q 5962L95834 01VZA ACO 01VZA >T DS90C032WLQMLV ACTIVE CFP NAD 16 19 TBD Call TI Call TI -55 to 125 DS90C032WL QMLV Q 5962L95834 Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 12-Apr-2013 Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) 01VFA ACO 01VFA >T (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. 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OTHER QUALIFIED VERSIONS OF DS90C032QML, DS90C032QML-SP : • Military: DS90C032QML • Space: DS90C032QML-SP Addendum-Page 2 Samples PACKAGE OPTION ADDENDUM www.ti.com 12-Apr-2013 NOTE: Qualified Version Definitions: • Military - QML certified for Military and Defense Applications • Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application Addendum-Page 3 MECHANICAL DATA NAJ0020A E20A (Rev F) www.ti.com MECHANICAL DATA NAD0016A W16A (Rev T) www.ti.com MECHANICAL DATA NAC0016A WG16A (RevG) www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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