Cirrus CDB5014 Evaluation board Datasheet

CDB5012 CDB5012A
CDB5014 CDB5016
Semiconductor Corporation
Evaluation Board for CS5012, CS5012A, CS5014,
CS5016 ADC’s
Features
General Description
•
The CDB5012/4/6 is an evaluation board that eases the
laboratory characterization of any of the CS5012,
CS5012A, CS5014 and CS5016 A/D converters. The
board can be easily reconfigured to simulate any combination of sampling, master clock, calibration, and input
range conditions.
Compatible with CS5012, CS5012A,
CS5014, CS5016
Header Connection
• PC/µP-Compatible
16-Bit Parallel Data
End-of-Conversion Output
CS, RD, and A0 Control Inputs
The converter’s parallel output data are available at a
40 pin strip header allowing easy interfacing to PC’s or
microprocessor busses. Output data is also available in
serial form at SCLK and SDATA coaxial BNC connectors.
Selectable:
• DIP-Switch
Unipolar/Bipolar Input Range
Burst & Interleave Calibration Modes
Continuous Conversion
• Adjustable Voltage Reference
• Serial Data and Clock BNC Connections
from Internally-Generated or
• Operation
Externally-Supplied Master Clock
Evaluation can also be performed over a wide range of
input spans using the on-board reference circuitry. Furthermore, the CDB5012, CDB5012A, CDB5014,
CDB5016 features DIP-switch selectable unipolar/bipolar input ranges and the interleave calibration mode.
Calibration can be initiated at any time by momentarily
depressing a reset pushbutton.
ORDERING INFORMATION: CDB5012, CDB5012A,
CDB5014, CDB5016
D0 - D15
AIN
EOC
HOLD
CLKIN
RESET
CS5012
CS5012A
CS5014
CS5016
A/D
Converter
A0
RD
CS
H
E
A
D
E
R
SCLK
SDATA
VOLTAGE
REFERENCE
+5V
Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445 7222 FAX: (512) 445 7581
GND -5V
Copyright  Crystal Semiconductor Corporation 1995
(All Rights Reserved)
MAR ’95
DS14DB11
1
CDB5012, CDB5012A, CDB5014, CDB5016
Analog Input
The analog input to the A/D converter is supplied
through the BNC coaxial connector labeled AIN.
Analog input polarity is controlled by the first
position switch on the DIP-switch, SW-1. If it is
on, the input is unipolar ranging from GND to
VREF. If the switch is off, the input range is bipolar with the magnitude of the reference voltage
defining both zero- and full-scale (±VREF).
+
VA-
VD+
C11
+
C6
C5
The A/D converter’s internal analog input buffer
requires a source impedance of less than 400 Ω
at 1MHz for stability. Acquisition and throughput
are specified assuming a dc source impedance of
less than 200 Ω. Infinitely large dc source impedances can be accommodated by adding capacitance (typically 1000pF) from the analog input to
ground. However, high dc source resistances degrade acquisition time and consequently throughput.
VA+
R10
SW1-4
C10
27
25
37 EOT
1 HOLD
39 SCLK
40 SDATA
26 AIN
CS5012
CS5012A 20 CLKIN
CS5014
CS5016
30
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
EOC
CS
RD
A0
2
3
4
5
6
7
8
9
12
13
14
15
16
17
18
19
38
21
22
23
R23 (optional)
VD+
VA+
VAVD-
R2
+5V
-5V
R1
R3
31 TST
C12
28 VREF
32 RESET
29 REFBUF
C7
U1
24
35
34
33
R8
Reset
R9
VD+
SW2
VA-
BP/UP
CAL
INTLV
BW
SW1-1
SW1-2
SW1-3
R4 R5 R7
36
C3
10
C1
+
VD+
VD-
C4
C2
+
11
R12
R13
R11
R6
VD+
Figure 1. CDB5012, CDB5012A, CDB5014, CDB5016 Schematic
(Reference Circuitry Appears in Figure 3)
DS14DB11
2
CDB5012, CDB5012A, CDB5014, CDB5016
ON
OFF
Position 1
Bipolar
Position 2
Burst Cal *
Position 3
Normal
Position 4
Unipolar
Normal Operation
Interleaved Cal
Continuous Conversion
Normal
* NOTE: Use of BURST CAL is not recommended.
Figure 2. DIP-Switch Definitions
Initiating Conversions
The CDB5012, CDB5012A, CDB5014,
CDB5016 is shipped from the factory without the
HOLD BNC input terminated for operation with
an external sampling clock. However, location
R23 is reserved for the insertion of a 51 Ω resistor to eliminate reflections of the incoming clock
signal.
A negative transition on the converter’s HOLD
pin places the device’s analog input into the hold
mode and initiates a conversion cycle. On the
CDB5012, CDB5012A, CDB5014, CDB5016,
this input can be generated by one of two means.
First, it can be supplied through the BNC coaxial
connector appropriately labeled HOLD. Alternatively, switch position 4 of the DIP-switch can be
placed in the on position, thus looping the converter’s EOT output back to HOLD. This results
in continuous conversions at a fraction of the
master clock frequency (see "synchronous operation" in the converter’s data sheet).
Voltage Reference Circuitry
The CDB5012, CDB5012A, CDB5014,
CDB5016 features an adjustable voltage reference which allows characterization over a wide
range of reference voltages. The circuitry consists
of a 2.5V voltage reference (1403) and an adjustable gain block with a discrete output stage (Figure
3). The output stage minimizes the output’s headroom requirements allowing the reference voltage to
come within 300mV of the positive supply.
The A/D converter’s EOT output is an indicator
of its acquisition status; it falls when the analog
input has been acquired to the specified accuracy.
If an external sampling clock is applied to the
HOLD BNC connector, care must similarly be
taken to obey the converter’s acquisition and
maximum sampling rate requirements. A more
detailed discussion of acquisition and throughput
can be found in the converter’s data sheet.
VA+
The coarse and fine trim potentiometers are factory calibrated to a reference voltage of 4.5V (a
table of output code values for a reference voltage of 4.5V appears in the CS5012, CS5012A,
CS5014, CS5016 data sheets). When calibrating
the reference, the voltage should be measured directly at the VREF input (pin 28) or at the ungrounded lead of decoupling capacitor C9.
Q1
R18
VREF
R14
U2
1403
R15
C13
Coarse
Adjust
R19
R17
R16
U3
+ OP-07
C14
R20
Fine
Trim
R21
+
C8
C9
R22
Figure 3. Voltage Reference Circuitry
3
DS14DB11
CDB5012, CDB5012A, CDB5014, CDB5016
Reset/Self-Calibration Modes
DGND
The A/D converter will usually reset itself upon
power-up. Since this function is not guaranteed,
the converter must be reset upon power-up in
system operation. The converter can be reset on
the CDB5012, CDB5012A, CDB5014, CDB5016
board by momentarily depressing push-button
SW-2 thus initiating a full calibration cycle;
1,443,840 master clock cycles later the converter
is ready for normal operation.
The converters also feature two other calibration
modes: burst and interleave. The use of Burst
calibration is not recommended. Interleave can be
initiated by setting switch position 3 to the on
position. In the interleave mode (INTRLV low),
the converter appends one small portion of a calibration cycle (20 master clock cycles) to each
conversion cycle. Thus, a full calibration cycle
completes every 72,192 conversion cycles. The
Interleave calibration mode should not be used
intermittently.
A more detailed discussion of the converters’
calibration modes and capabilities can be found
in their data sheets.
DGND
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
EOC
A0
RD
CS
Figure 4. Header Pin Definitions
The converter’s EOC and data outputs are not
buffered on the CDB5012, CDB5012A,
CDB5014, CDB5016. Therefore, careful attention
should be paid to the load presented by any cabling, especially if the 3-state output buffers are
to be exercised at speed. Twisted ribbon cable is
typically specified at 10pF/ft, so several feet can
generally be accommodated.
Parallel Output Data/Microprocessor Interface
Serial Output Data
The converter’s outputs D0-D15, its CS, RD, and
A0 inputs, and its EOC output are available at
the 40 pin header. The CS and RD inputs are
pulled low through 10 kΩ resistors placing
the converter in a microprocessor-independent
mode. Control input A0 is pulled up, insuring the
converter’s output word, rather than the status
register, appears at the header.
The converter’s 3-state output buffers and microprocessor interface can be exercised by driving
the CS and/or RD inputs at the header. Similarly,
the converter’s 8-bit status register can be obtained on D0-D7 by driving A0 low.
DS14DB1
Serial output data is available at the two BNC
connections SCLK and SDATA. Data appears
MSB first, LSB last, and is valid on the rising
edge of SCLK.
Master Clock
The A/D converter operates from a master clock
which can either be internally-generated or externally-supplied. For operation with an external
clock, the BNC connector labeled CLKIN
should be driven with a TTL clock signal. The
CDB5012, CDB5012A, CDB5014, CDB5016 is
shipped from the factory with the CLKIN input
4
CDB5012, CDB5012A, CDB5014, CDB5016
terminated by a 51 Ω resistor to eliminate line
reflections of the incoming clock. If the CLKIN
BNC input is left floating, this resistor pulls the
converter’s clock input down to ground, thus activating its internal oscillator.
Decoupling
The CDB5012, CDB5012A, CDB5014,
CDB5016’s decoupling scheme was designed to
insure accurate evaluation of the converter’s per-
formance independent of the quality of the power
supplies. Each supply is decoupled at the converter with a 10µF electrolytic capacitor to filter
low frequency noise and a 0.1µF ceramic capacitor to handle higher frequencies. The auto-zeroing action of the converter’s comparator provides
extremely good power supply rejection at low
frequencies. Depending on the quality of the system’s power supplies, the decoupling scheme
could be relaxed in actual use.
COMPONENT LIST
10 Ω resistor
51 Ω resistor
4.7 Ω resistor
1 kΩ resistor
560 Ω resistor
10 kΩ resistor
2.43 kΩ resistor
3.3 kΩ resistor
240 kΩ resistor
50 kΩ potentiometer
50 kΩ potentiometer
0.068 µF capacitor
0.1 µF capacitor
10 µF capacitor
CS501X/511X A/D converter
1403 2.5V reference
OP07 op amp
2N2907A transistor
4 pos. SPST DIP switch
N.O. SPST push-button
20 pin header
bulkhead BNC
red banana jack
black banana jack
green banana jack
1" 4-40 spacer
3/8" 4-40 screw
5
R1, R2
R3
R18
R9, R14
R17
R4, R5, R6, R7, R8, R10, R11, R12, R13
R19, R20
R16
R21
R15
R22
C14
C1, C3, C5, C7, C9, C10, C12
C2, C4, C6, C8, C11, C13
U1
U2
U3
Q1
SW1
SW2
CON1
CON2, CON3, CON4, CON5, CON6
CON7
CON8
CON9
POST1, POST2, POST3, POST4, POST5, POST6
SC1, SC2, SC3, SC4, SC5, SC6
DS14DB11
CDB5012, CDB5012A, CDB5014, CDB5016
PCB5012-201D
TOP
SDATA
SCLK
J1
GND
+5
-5
R23
R14
SW2
C13
COARSE
ADJ
R8
U1
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
EOC
AO
RD
CS
P1
C
3
HOLD
C
4
R C12
6 R9
R
10 R1 R2
R15
ON
SW1
SMART Analog
1234
C5
R11
R12
R13
C1
C6
C2
C7
CDB501X
Evaluation Board
C9
U3
U2
R16
Q1
R17
R18
C8
C14
C10
C11
CLKIN
R20
R19
R21
AIN
R22
R
3
R
4
R
5
R
7
FINE ADJ
ADJUSTABLE
REFERENCE
Figure 5. Board Layout
DS14DB1
6
Smart AnalogTM is a Trademark of Crystal Semiconductor Corporation
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