Catalyst CAT5132ZI-10-GT3 16 volt digitally programmable potentiometer Datasheet

CAT5132
16 Volt Digitally Programmable Potentiometer (DPP™)
with 128 Taps and 2-wire Interface
FEATURES
DESCRIPTION
■ Single linear DPP with 128 taps
The CAT5132 is a high voltage Digitally Programmable
Potentiometer (DPP) with non-volatile wiper setting
memory, operating like a mechanical potentiometer.
The tap points between the 127 equal resistive elements
are connected to the wiper output via CMOS switches.
The switches are controlled by a 7-bit Wiper Control
Register (WCR). The wiper setting can be stored in a
7-bit non-volatile Data Register (DR). The WCR is
accessed via the 2-wire serial bus.
Ω, 50kΩ
Ω or 100kΩ
Ω
■ End-to-end resistance of 10kΩ
■ 2-wire (I2C-like) interface
■ Fast Up/Down wiper control mode
■ Non-volatile wiper setting storage
■ Automatic wiper setting recall at power-up
■ Digital Supply range (VCC): 2.7V to 5.5V
■ Analog Supply range (V+): +8V to +16V
Upon power-up, the WCR is set to mid-scale (1000000).
After the power supply is stable, the contents of the DR
are transferred to the WCR and the wiper is returned to
the memorized setting.
■ Low Standby Current: 15µA
■ 100 Year wiper setting memory
■ Industrial Temperature range: -40oC to +85oC
The CAT5132 has two voltage supplies: VCC, the digital
supply and V+, the analog supply. V+ can be much
higher than VCC, allowing for 16V analog operations.
■ RoHS-compliant 10-pin MSOP package
APPLICATIONS
The CAT5132 can be used as a potentiometer or as a
two-terminal variable resistor.
■ LCD screen adjustment
■ Volume control
■ Mechanical potentiometer replacement
■ Gain adjustment
■ Line impedance matching
■ VCOM setting adjustments
For Ordering Information details, see page 13.
BLOCK DIAGRAM
VCC
V+
SDA
127
SCL
RH
A1
128 TAP POSITION
DECODE CONTROL
7-BIT
NONVOLATILE
MEMORY
REGISTER
(DR)
7-BIT WIPER
CONTROL
REGISTER
(WCR)
0
ELEMENTS
A0
127 RESISTIVE
CONTROL LOGIC AND
ADDRESS DECODE
RL
RW
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 25092, Rev. 04
CAT5132
PIN CONFIGURATION
SDA
GND
VCC
A1
A0
1
2
3
4
5
10
9
8
7
6
SCL
V+
RL
RW
RH
MSOP 10-Pin Package
Doc. No. 25092, Rev. 04
PIN DESCRIPTION
Pin
Number
Name
1
SDA
Serial Data Input/Output - Bidirectional Serial Data pin
used to transfer data into and out of the CAT5132. This
is an Open-Drain I/O and can be wire OR'd with other
Open-Drain (or Open Collector) I/Os.
2
GND
Ground
Description
3
VCC
Digital Supply Voltage (2.7V to 5.5V)
4
A1
Address Select Input to select slave address for
2-wire bus.
5
A0
Address Select Input to select slave address for
2-wire bus.
6
RH
High Reference Terminal for the potentiometer
7
RW
Wiper Terminal for the potentiometer
8
RL
Low Reference Terminal for the potentiometer
9
V+
Analog Supply Voltage for the potentiometer (+8.0V to
16.0V)
10
SCL
Serial Bus Clock input for the 2-wire Serial Bus. This
clock is used to clock all data transfers into and out of
the CAT5132
2
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT5132
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED OPERATING CONDITIONS
Temperature Under Bias....................-55˚C to +125˚C
VCC = +2.7V to +5.5V
V+ = +8.0V to +16V
Operating Temperature Range: -40˚C to +85˚C
Storage Temperature ........................ -65˚C to +150˚C
Voltage on any SDA, SCL, A0 & A1 pins with respect
to Ground (1) ................................. -0.3V to VCC + 0.3V
COMMENT
Voltage on RH, RL & RW pins with respect
to Ground ................................................................ V+
Stresses above those listed under “Absolute Maximum Ratings” may
cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions
outside of those listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for extended periods
may affect device performance and reliability.
VCC with respect to Ground .................... -0.3V to +6V
V+ with respect to Ground ................. -0.3V to +16.5V
Wiper Current (10 sec) ...................................... +6mA
Notes:
1. Latch-up protection is provided for stresses up to 100mA on
address and data pins from -0.3V to VCC +0.3V.
Lead Soldering temperature (10 sec) .............. +300˚C
POTENTIOMETER CHARACTERISTICS
(Over recommended operating conditions unless otherwise stated.)
Symbol
Parameter
Test Conditions
Limits
Min
Typ
Max
Units
RPOT
Potentiometer Resistance (100kΩ)
100
kΩ
RPOT
Potentiometer Resistance (50kΩ)
50
kΩ
RPOT
Potentiometer Resistance (10kΩ)
10
kΩ
RTOL
Potentiometer Resistance Tolerance
Power Rating
IW
RW
25° C
Wiper Current
Wiper Resistance
VTERM
Voltage on RW, RH or RL
RES
Resolution
ALIN
Absolute Linearity
RLIN
Relative Linearity
+20
%
50
mW
+3
IW = +1mA @ V+ = 12V
70
150
mA
Ω
IW = +1mA @ V+ = 8V
110
200
Ω
GND = 0V; V+ = 8V to 16V
GND
V+
0.78
(2)
(3)
V
%
VW(n)(actual) - VW(n)(expected) (5), (6)
+1
LSB
(4)
VW(n+1) - [VW(n)+LSB](5), (6)
+0.5
LSB
(4)
TCRPOT
Temperature Coefficient of RPOT
(1)
TCRatio
Ratiometric Temperature Coefficient
(1)
Potentiometer Capacitances
(1)
10/10/25
pF
RPOT = 50kΩ
0.4
MHz
CH/CL/CW
fc
Frequency Response
+300
ppm/° C
30
ppm/° C
Notes:
1. This parameter is tested initially and after a design or process change that affects the parameter.
2. Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a
potentiometer.
3. Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer.
4. LSB = (RHM - RLM)/127; where RHM and RLM are the highest and lowest measured values on the wiper terminal.
5. n = 1, 2, ..., 127
6. V+ @ RH; 0V @ RL; VW measured @ RW with no load.
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
3
Doc No. 25092, Rev. 04
CAT5132
D.C. ELECTRICAL CHARACTERISTICS
(Over recommended operating conditions unless otherwise stated.)
Symbol
Parameter
Test Conditions
Min
Max
Units
ICC1
Power Supply Current
(Volatile Write/Read)
FSCL = 400kHz, SDA Open,
VCC = 5.5V, Input = GND
1
mA
ICC2
Power Supply Current
(Nonvolatile WRITE)
FSCL = 400kHz, SDA Open,
VCC = 5.5V, Input = GND
3.0
mA
ISB(VCC)
Standby Current (VCC = 5V)
VIN = GND or VCC , SDA = VCC
5
µA
ISB(V+)
V+ Standby Current
VCC = 5V, V+ = 16V
10
µA
ILI
Input Leakage Current
VIN = GND to VCC
10
µA
ILO
Output Leakage Current
VOUT = GND to VCC
10
µA
VIL
Input Low Voltage
-1
VCC x 0.3
V
VIH
Input High Voltage
VCC x 0.7
VCC + 1.0
V
VOL1
Output Low Voltage (VCC = 3.0)
0.4
V
Max
Units
IOL = 3mA
CAPACITANCE
TA = 25˚C, f = 1.0MHz, VCC = 5.0V
Symbol
Parameter
Test Conditions
Min
CI/O
Input/Output Capacitance (SDA)
VI/O = 0V (1)
8
pF
CIN
Input Capacitance (A0, A1, SCL)
VIN = 0V (1)
6
pF
A.C. CHARACTERISTICS
VCC = 2.7 - 5.5V
Symbol
Min
Parameter (see Fig. 1)
Max
Units
FSCL
Clock Frequency
400
kHz
TI (1)
Noise Suppression Time Constant at SCL & SDA Inputs
50
ns
tAA
SLC Low to SDA Data Out and ACK Out
1
µs
tBUF
(1)
Time the bus must be free before a new transmission can start
1.2
µs
Start Condition Hold Time
0.6
µs
tLOW
Clock Low Period
1.2
µs
tHIGH
Clock High Period
0.6
µs
tSU:STA
Start Condition Setup Time (for a Repeated Start Condition)
0.6
µs
tHD:DAT
Data in Hold Time
0
ns
tHD:STA
tR
(1)
SDA and SCL Rise Time
0.3
µs
tF
(1)
SDA and SCL Fall Time
300
ns
tSU:STO
tDH
Stop Conditions Setup Time
0.6
µs
Data Out Hold Time
100
ns
Notes:
1. This parameter is tested initially and after a design or process change that affects the parameter.
Doc. No. 25092, Rev. 04
4
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT5132
POWER UP TIMING (1)(2)
Symbol
Parameter
Min
Max
Units
tPUR
Power-up to Read Operation
1
ms
tPUW
Power-up to Write Operation
1
ms
XDCP TIMING
Symbol
Parameter
Min
Max
Units
tWRPO
Wiper Response Time After Power Supply Stable
5
10
µs
tWRL
Wiper Response Time After Instruction Issued
5
10
µs
Min
Max
Units
5
ms
WRITE CYCLE LIMITS
Symbol
Parameter
Write Cycle Time (see Fig. 2)
tWR
The write cycle is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle.
During the write cycle, the bus interface circuits are disabled, SDA is allowed to remain high and the device does not
respond to its slave address.
RELIABILITY CHARACTERISTICS
Symbol
Parameter
Reference Test Method
Min
Max
Units
NEND (1)
Endurance
MIL-STD-883, Test Method 1033
100,000
Cycles
TDR (1)
Data Retention
MIL-STD-883, Test Method 1008
100
Years
Notes:
1. This parameter is tested initially and after a design or process change that affects the parameter.
2. tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.
TYPICAL PERFORMANCE CHARACTERISTICS
Resistance between RW and RL
12.000
400
Vcc=2.7V; V+=8v
Vcc=5.5V; V+=16V
10.000
350
300
8.000
Icc2 (uA)
RWL (Kohm)
Icc2 (NV write) vs Temperature
6.000
4.000
250
200
150
Vcc = 2.7V
100
2.000
Vcc = 5.5V
50
0
0.000
0
16
32
48
64
80
96
112
-50
128
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
-30
-10
10
30
50
70
90
110 130
Temperature (°C)
Tap position
5
Doc No. 25092, Rev. 04
CAT5132
TYPICAL PERFORMANCE CHARACTERISTICS (CONT)
Relative Linearity Error
Absolute Linearity Error per Tap Position
1.000
Tamb = 25 C
Rtotal = 10K
0.800
0.300
RLIN Error (LSB)
0.400
0.200
0.000
-0.200
-0.400
0.100
0.000
-0.100
-0.200
-0.300
-0.800
-0.400
0
16
32
48
64
80
96
112
Vcc=5.5V; V+=16V
0.200
-0.600
-1.000
Vcc=2.7V; V+=8V
Tamb = 25 C
Rtotal = 10K
0.400
Vcc=5.5V; V+=16V
0.600
ALIN Error (LSB)
0.500
Vcc=2.7V; V+=8v
-0.500
128
0
16
Tap position
32
48
64
80
96
112
128
Tap position
tF
tHIGH
tLOW
tR
tLOW
SCL
tSU:STA
tHD:DAT
tHD:STA
tSU:DAT
tSU:STO
SDA IN
tAA
tBUF
tDH
SDA OUT
Figure 1. Bus Timing
SCL
SDA
8TH BIT
ACK
BYTE n
tWR
STOP
CONDITION
START
CONDITION
ADDRESS
Figure 2. Write Cycle Timing
Doc. No. 25092, Rev. 04
6
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT5132
Acknowledge
SERIAL BUS PROTOCOL
After a successful data transfer, each receiving device
is required to generate an acknowledge. The
acknowledging device pulls down the SDA line during
the ninth clock cycle, signaling that it received the 8 bits
of data (see Fig. 4).
The following defines the features of the 2-wire bus
protocol:
(1) Data transfer may be initiated only when the bus is
not busy.
(2) During a data transfer, the data line must remain
stable whenever the clock line is high. Any changes
in the data line while the clock is high will be
interpreted as a START or STOP condition.
The CAT5132 responds with an acknowledge after
receiving a START condition and its slave address. If
the device has been selected along with a write operation,
it responds with an acknowledge after receiving each
8-bit byte.
The device controlling the transfer is a master, typically
a processor or controller, and the device being controlled
is the slave. The master will always initiate data transfers
and provide the clock for both transmit and receive
operations. Therefore, the CAT5132 will be considered
a slave device in all applications.
When the CAT5132 is in a READ mode it transmits 8 bits
of data, releases the SDA line, and monitors the line for
an acknowledge. Once it receives this acknowledge,
the CAT5132 will continue to transmit data. If no
acknowledge is sent by the Master, the device terminates
data transmission and waits for a STOP condition.
START Condition
Acknowledge Polling
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of
SDA when SCL is HIGH. The CAT5132 monitors the
SDA and SCL lines and will not respond until this
condition is met (see Fig. 3).
The disabling of the inputs can be used to take advantage
of the typical write cycle time. Once the STOP condition
is issued to indicate the end of the write operation, the
CAT5132 initiates the internal write cycle. ACK polling
can be initiated immediately. This involves issuing the
START condition followed by the slave address. If the
CAT5132 is still busy with the write operation, no ACK
will be returned. If the CAT5132 has completed the write
operation, an ACK will be returned and the host can then
proceed with the next instruction operation.
STOP Condition
A LOW to HIGH transition of SDA when SCL is HIGH
determines the STOP condition. All operations must end
with a STOP condition (see Fig. 3).
SCL
SDA
START
CONDITION
STOP
CONDITION
Figure 3. Start/Stop Condition
BUS RELEASE DELAY (TRANSMITTER)
SCL FROM
MASTER
1
8
BUS RELEASE DELAY (RECEIVER)
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACK SETUP (≥ tSU:DAT)
ACK DELAY (≤ tAA)
Figure 4. Acknowledge Condition
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
7
Doc No. 25092, Rev. 04
CAT5132
The next two bits, A1 and A0, are the internal slave
address and must match the physical device address
which is defined by the state of the A1 and A0 input pins.
Only the device with slave address matching the input
byte will be accessed by the master. This allows up to 4
devices to reside on the same bus. The A1 and A0 inputs
can be actively driven by CMOS input signals or tied to
VCC or Ground.
DEVICE DESCRIPTION
Access Control Register
The volatile register WCR and the non-volatile register
DR are accessed only by addressing the volatile Access
Register AR first, using the 3 byte I2C protocol for all read
and write operations (see Table 1). The first byte is the
slave address/instruction byte (see details below). The
second byte contains the address (02h) of the AR
register. The data in the third byte controls which register
WCR (80h) or DR (00h) is being addressed (see Figure
5).
The last bit is the READ/WRITE bit and determines the
function to be performed. If it is a “1” a read command is
initiated and if it is a “0” a write is initiated. For the AR
register only write is allowed.
Slave Address Instruction Byte Description
After the Master sends a START condition and the slave
address byte, the CAT5132 monitors the bus and
responds with an acknowledge when its address matches
the transmitted slave address.
The first byte sent to the CAT5132 from the master
processor is called the Slave/DPP Address Byte. The
most significant five bits of the slave address are a
device type identifier. For the CAT5132 these bits are
fixed at 01010 (refer to Table 2).
Table 1. Access Control Register
ID2
ID1
ID0
A1
A0
Wb
ACK
ACK
STOP
ST
0
1
0
1
0
0
0
0
A
0
0
0
0
0
0
1
0
A
1
0
0
0
0
0
0
0
A
SP
ST
0
1
0
1
0
0
0
0
A
0
0
0
0
0
0
1
0
A
0
0
0
0
0
0
0
0
A
SP
ACK
ID3
3rd byte
ID4
2nd byte
START
1st byte
A R address - 02h
WCR(80h) / DR (00h) selection
Table 2. Byte 1 Slave Address and Instruction Byte
Device Type Identifier
Read/Write
Slave Address
ID4
ID3
ID2
ID1
ID0
A1
A0
R/W
0
1
0
1
0
X
X
X
(MSB)
(LSB)
BUS ACTIVITY:
MASTER
SDA LINE
SLAVE
ADDRESS
S
T & INSTRUCTION
A
R
FIXED
T
AR REGISTER
ADDRESS
WCR/DR
SELECTION
S
T
O
P
P
S
VARIABLE
A
C
K
A
C
K
A
C
K
Figure 5. Access Register Addressing Using 3 Bytes
Doc. No. 25092, Rev. 04
8
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT5132
Wiper Control Register (WCR) Description
The CAT5132 contains a 7-bit Wiper Control Register
which is decoded to select one of the 128 switches along
its resistor array. The WCR is a volatile register and is
written with the contents of the nonvolatile Data Register
(DR) on power-up. The Wiper Control Register loses its
contents when the CAT5132 is powered-down. The
contents of the WCR may be read or changed directly by
the host using a READ/WRITE command after addressing
the WCR (see Table 1 to access WCR). Since the
CAT5132 will only make use of the 7 LSB bits (The first
data bit, or MSB, is ignored) on write instructions and will
always come back as a “0” on read commands.
A write operation (see Table 3) requires a Start condition, followed by a valid slave address byte, a valid address byte
00h, a data byte and a STOP condition. After each of the three bytes the CAT5132 responds with an acknowledge.
At this time the data is written only to volatile registers, then the device enters its standby state.
Table 3. WCR Write Operation
0
ST
slave address byte
0
1
0
1
0
0
A
AR address - 02h
0
0
0
0
A
0
0
0
0
1
0
WCR address - 00h
0
0
0
0
0
0
A
WCR(80h) selection
1
0
0
0
0
A
0
0
0
0
0
X
X
X
data byte
X
X
X
X
X
STOP
Wb
0
A
SP
STOP
A0
0
ACK
A1
0
ACK
ID0
1
ACK
ID1
0
3rd byte
ACK
ID2
1
ACK
ID3
0
2nd byte
ACK
ID4
ST
START
START
1st byte
A
SP
An increment operation (see Table 4) requires a Start condition, followed by a valid increment address byte (01011),
a valid address byte 00h. After each of the two bytes, the CAT5132 responds with an acknowledge. At this time if the
data is high then the wiper is incremented or if the data is low the wiper is decremented at each clock. Once the stop
is issued then the device enters its standby state with the WCR data as being the last inc/dec position. Also, the wiper
position does not roll over but is limited to min and max positions.
Table 4. WCR Increment/Decrement Operation
Wb
0
0
ST
slave address byte
0
1
0
1
1
0
A
AR address - 02h
0
0
0
0
A
0
0
0
0
1
0
WCR address - 00h
0
0
0
0
0
0
A
WCR(80h) selection
1
0
0
A
0
0
0
0
0
0
0
STOP
A0
0
A
SP
STOP
A1
0
ACK
ID0
1
ACK
ID1
0
3rd byte
ACK
ID2
1
ACK
ID3
0
2nd byte
ACK
ID4
ST
START
START
1st byte
increment (1) / decrement (0) bits
1
1
1
1
0
0
0
SP
0
A read operation (see Table 5) requires a Start condition, followed by a valid slave address byte for write, a valid address
byte 00h, a second START and a second slave address byte for read. After each of the three bytes, the CAT5132
responds with an acknowledge and then the device transmits the data byte. The master terminates the read operation
by issuing a STOP condition following the last bit of Data byte.
Table 5. WCR Read Operation
A0
Wb
0
0
0
slave address byte
0
1
START
ST
ST
0
1
0
0
A
0
0
0
0
A
0
1
0
1
0
0
0
0
1
0
0
0
0
0
0
0
0
0
X
X
X
data byte
0
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
A
A
1
0
0
0
0
0
0
0
A
SP
WCR address - 00h
slave address byte
0
0
STOP
A1
0
ACK
ID0
1
ACK
ID1
0
3rd byte
WCR(80h) selection
STOP
ID2
1
ACK
ID3
0
2nd byte
AR address - 02h
ACK
ID4
ST
START
START
1st byte
0
X
X
X
X
9
SP
Doc No. 25092, Rev. 04
CAT5132
Data Register (DR)
being performed. During the internal non-volatile write
cycle, the device ignores transitions at the SDA and SCL
pins, and the SDA output is at a high impedance state.
The WCR is also written during a write to DR. After a DR
WRITE is complete the DR and WCR will contain the
same wiper position.
The Data Register (DR) is a nonvolatile register and its
contents are automatically written to the Wiper Control
Register (WCR) on power-up. It can be read at any time
without effecting the value of the WCR. The DR, like the
WCR, only stores the 7 LSB bits and will report the MSB
bit as a “0”. Writing to the DR is performed in the same
fashion as the WCR except that a time delay of up to 5ms
is experienced while the nonvolatile store operation is
To write or read to the DR, first the access to DR is selected, see table 1 then the data is written or read using the
following sequences.
A write operation (see Table 6) requires a Start condition, followed by a valid slave address byte, a valid address byte
00h, a data byte and a STOP condition. After each of the three bytes the CAT5132 responds with an acknowledge.
At this time the data is written both to volatile and non-volatile registers, then the device enters its standby state.
A0
Wb
0
0
0
slave address byte
0
1
0
1
0
0
0
0
ACK
START
ST
A
0
0
A
0
0
0
0
1
0
DR address - 00h
0
0
0
0
0
0
A
DR(00h) selection
0
0
0
0
0
A
0
0
0
0
0
X
X
X
data byte
X
X
X
X
X
STOP
A1
0
A
SP
STOP
ID0
1
ACK
ID1
0
ACK
ID2
1
3rd byte
ACK
ID3
0
2nd byte
AR address - 02h
ACK
ID4
ST
1st byte
ACK
START
Table 6. DR Write Operation
A
SP
A read operation (see Table 7) requires a Start condition, followed by a valid slave address byte, a valid address byte
00h, a second Start and a second slave address byte for read. After each of the three bytes the CAT5132 responds
with an acknowledge and then the device transmits the data byte. The master terminates the read operation by issuing
a STOP condition following the last bit of Data byte.
ID0
A1
A0
Wb
1
0
0
0
0
0
1
ST
0
1
0
0
0
0
ACK
START
slave address byte
START
ST
A
0
0
A
0
1
0
Doc. No. 25092, Rev. 04
1
0
0
0
0
1
0
0
0
0
0
0
0
0
0
X
X
X
data byte
0
1
A
A
0
0
0
0
0
0
0
0
A
SP
DR address - 00h
slave address byte
0
0
DR(00h) selection
STOP
ID1
0
AR address - 02h
ACK
ID2
1
3rd byte
ACK
ID3
0
2nd byte
STOP
ID4
ST
1st byte
ACK
START
Table 7. DR Read Operation
0
X
X
X
X
10
SP
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT5132
POTENTIOMETER OPERATION
Power-On
The CAT5132 is a 128-position, digital controlled
potentiometer. When applying power to the CAT5132,
VCC must be suplied prior to or simultaneously with V+.
At the sametime, the signals on RH, RW and RL terminals
should not exceed V+. If V+ is applied before VCC, The
electronic switches of the DPP are powered in the
absence of the switch control signals, that could result in
multiple switches being turned on. This causes
unexpected wiper settings and possible current overload
of the potentiometer. When VCC is applied the device
turns on at the mid-point wiper location (64) until the
wiper register can be loaded with the nonvolatile memory
location previously stored in the device. After the
nonvolatile memory data is loaded into the wiper register
the wiper location will change to the previously stored
wiper position.
10kΩ potentiometer ~79Ω is the resistance between
each wiper position. However in addition to the ~79Ω for
each resistive segment of the potentiometer, a wiper
resistance offset must be considered. Table 8 shows the
effect of this value and how it would appear on the wiper
terminal.
This offset will appear in each of the CAT5132 end-toend resistance values in the same way as the 10kΩ
example. However resistance between each wiper
position for the 50kΩ version will be ~395Ω and for the
100kΩ version will be ~790Ω.
Table 8. Potentiometer Resistance and Wiper
Resistance Offset Effects
Position
At power-down, it is recommended to turn-off first the
signals on RH, RW and RL, followed by V+ and, after that,
VCC, in order to avoid unexpected transmistions of the
wipper and uncontrolled current overload of the
potentiometer.
The end-to-end nominal resistance of the potentiometer
has 128 contact points linearly distributed across the
total resistor. Each of these contact points is addressed
by the 7 bit wiper register which is decoded to select one
of these 128 contact points.
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
00
70Ω or
0Ω + 70Ω
01
149Ω or
79Ω + 70Ω
63
5,047Ω or
4,977Ω + 70Ω
127
10,070Ω or
10,000Ω + 70Ω
Position
Each contact point generates a linear resistive value
between the 0 position and the 127 position. These
values can be determined by dividing the end-to-end
value of the potentiometer by 127. In the case of the
11
Typical RW to RL Resistance for
10kΩ DPP
Typical RW to RH Resistance for
10kΩ DPP
00
10,070Ω or
10,000Ω + 70Ω
64
5,047Ω or
4,977Ω + 70Ω
126
149Ω or
79Ω + 70Ω
127
70Ω or
0Ω + 70Ω
Doc No. 25092, Rev. 04
CAT5132
PACKAGE OUTLINES
10-LEAD MSOP
E1
E
e
D
A2
b
SYMBOL
MIN
L
A1
NOM
A
MAX
1.10
A1
0.00
0.05
0.15
A2
0.75
0.85
0.95
b
0.17
D
2.90
3.00
3.10
E
4.75
4.90
5.05
E1
2.90
3.00
3.10
e
L
GAUGE
PLANE
A
0.27
0.50 BSC
0.40
0.8
0°
8°
10-lead_MSOP.eps
For current Tape and Reel information, download the PDF file from:
http://www.catsemi.com/documents/tapeandreel.pdf.
Notes:
1. All dimensions are in millimeters. Angles in degrees.
2. Complies with JEDEC Specification MO-187.
3. Stand off height/coplanarity are considered as special characteristics.
Doc. No. 25092, Rev. 04
12
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT5132
EXAMPLE OF ORDERING INFORMATION
Prefix
Device #
CAT
Company ID
Suffix
5132
I
Z
Product Number
5132
-10
Temperature Range
I = Industrial (-40°C to 85°C)
–G
T3
T: Tape & Reel
3: 3000/Reel
Resistance
-10: 10k ohms
-50: 50k ohms
-00: 100k ohms
Package
Z: MSOP
Lead Finish
G: NiPdAu (PPF)
Notes:
(1) All packages are RoHS-compliant (Lead-free, Halogen-free).
(2) The standard lead finish is NiPdAu.
(3) The device used in the above example is a CAT5132ZI-10-GT3 (MSOP, Industrial Temperature range, 10k ohms, NiPdAu, Tape & Reel).
(4) For additional package and temperature options, please contact your nearest Catalyst Semiconductor Sales office.
Ordering Part Number
CAT5132ZI-10-GT3
CAT5132ZI-50-GT3
CAT5132ZI-00-GT3
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
13
Doc No. 25092, Rev. 04
REVISION HISTORY
Date
Rev.
Reason
09/12/2005
00
Initial Issue
01/18/2006
01
Update Ordering Information
03/24/2006
02
Update Features
Update Description
Update Pin Drescription
Update Absolute Maximum Ratings
Update Recommended Operating Condictions
Update Ordering Information
Update Absolute Maximum Ratings
Update Reliability Characteristics
Update Potentiometer Operation
08/11/06
03
Update Title
Update Potentiometer Characteristics
Update D. C. Electrical Characteristics
Update Typical Performance Characteristics
Update Package Outline
Update Example of Ordering Information
11/01/06
04
Update Potentiometer Operation
Update Example of Ordering Information
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DPP ™
AE2 ™
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Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets
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Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate
typical semiconductor applications and may not be complete.
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Publication #:
Revison:
Issue date:
25092
04
11/01/06