Quad Buck Regulator Integrated Power Solution ADP5054 Data Sheet FEATURES TYPICAL APPLICATION CIRCUIT ADP5054 VREG INTERNAL VREG 100mA VDD C1 C0 SYNC/MODE OSCILLATOR RT FB1 PVIN1 4.5V TO 15.5V BST1 SW1 C2 CHANNEL 1 BUCK (2A/4A/6A) COMP1 C3 VREG L1 VOUT1 C4 Q1 EN1 CFG12 PGND DL2 SW2 C5 CHANNEL 2 BUCK (2A/4A/6A) PVIN2 COMP2 PWRGD PVIN3 EN3 VOUT2 C7 FB2 BST3 SW3 CHANNEL 3 BUCK (2A) C9 L3 VOUT3 FB3 PGND3 C10 CFG34 (SS, 1/2 × fSW, PARALLEL, SCLKSET) PVIN4 C11 L2 C6 BST2 C8 COMP3 Q2 VREG EN2 VREG ILIM2 VREG (SS, 1/2 × fSW, PARALLEL) ILIM1 DL1 SELECTIVE COMP4 BST4 SW4 CHANNEL 4 BUCK (2A) FB4 PGND4 C12 L4 VOUT4 C13 EN4 12617-001 Wide input voltage range: 4.5 V to 15.5 V ±1.5% output accuracy over full temperature range 250 kHz to 2 MHz adjustable switching frequency with individual ½× frequency option Power regulation Channel 1 and Channel 2 Programmable 2 A/4 A/6 A sync buck regulators with low-side FET drivers Channel 3 and Channel 4: 2.5 A sync buck regulators Flexible parallel operation Single 12 A output (Channel 1 and Channel 2 in parallel) Single 5 A output (Channel 3 and Channel 4 in parallel) Low 1/f noise density 40 µV rms at 0.8 VREF for 10 Hz to 100 kHz Precision enable with 0.811 V accurate threshold Active output discharge switch FPWM/PSM mode selection Frequency synchronization input or output Power-good flag for Channel 1 output UVLO, OCP, and TSD protection 48-lead, 7 mm × 7 mm LFCSP −40°C to +125°C operational junctional temperature range EXPOSED PAD APPLICATIONS Figure 1. FPGA and processor applications Small cell base stations Security and surveillance Medical applications GENERAL DESCRIPTION The ADP5054 combines four high performance buck regulators in a 48-lead LFCSP package that meets demanding performance and board space requirements. The device enables direct connection to high input voltages of up to 15.5 V with no preregulators. The switching frequency of the ADP5054 can be programmed or synchronized to an external clock from 250 kHz to 2 MHz, and an individual ½× frequency configuration is available for each channel. Channel 1 and Channel 2 integrate high-side power MOSFETs and low-side MOSFET drivers. External NFETs can be used in low-side power devices to achieve an efficiency optimized solution and to deliver a programmable output current of 2 A, 4 A, or 6 A. Combining Channel 1 and Channel 2 in a parallel configuration provides a single output with up to 12 A of current. The ADP5054 contains an individual precision enable pin on each channel for easy power-up sequencing. The internal low 1/f noise reference is implemented in the ADP5054 for noise sensitive applications. Channel 3 and Channel 4 integrate both high-side and low-side MOSFETs to deliver an output current of 2.5 A. Combining Channel 3 and Channel 4 in a parallel configuration can provide a single output with up to 5 A of current. Rev. B Table 1. Related Products Model ADP5050 ADP5051 ADP5052 ADP5053 ADP5054 Channels Four bucks, one LDO Four bucks, supervisory Four bucks, one LDO Four bucks, supervisory Four high current bucks I2C Yes Yes No No No Package 48-Lead LFCSP 48-Lead LFCSP 48-Lead LFCSP 48-Lead LFCSP 48-Lead LFCSP Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2015 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADP5054 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Power-Good Function ............................................................... 19 Applications ....................................................................................... 1 Thermal Shutdown .................................................................... 19 Typical Application Circuit ............................................................. 1 Applications Information .............................................................. 20 General Description ......................................................................... 1 ADIsimPower Design Tool ....................................................... 20 Revision History ............................................................................... 2 Programming the Output Voltage ........................................... 20 Detailed Functional Block Diagram .............................................. 3 Voltage Conversion Limitations ............................................... 20 Specifications..................................................................................... 4 Current-Limit Setting ................................................................ 20 Buck Regulator Specifications .................................................... 5 Soft Start Setting ......................................................................... 21 Absolute Maximum Ratings ............................................................ 7 Inductor Selection ...................................................................... 21 Thermal Resistance ...................................................................... 7 Output Capacitor Selection....................................................... 21 ESD Caution .................................................................................. 7 Input Capacitor Selection .......................................................... 22 Pin Configuration and Function Descriptions ............................. 8 Low-Side Power Device Selection ............................................ 22 Typical Performance Characteristics ........................................... 10 Programming the UVLO Input ................................................ 22 Theory of Operation ...................................................................... 14 Compensation Components Design ....................................... 23 Buck Regulator Operational Modes......................................... 14 Power Dissipation....................................................................... 23 Adjustable and Fixed Output Voltage ...................................... 14 Junction Temperature ................................................................ 24 Internal Regulators (VREG and VDD) ................................... 14 Design Examples ............................................................................ 25 Separate Supply Applications .................................................... 15 Setting the Switching Frequency .............................................. 25 Low-Side Device Selection ........................................................ 15 Setting the Output Voltage ........................................................ 25 Bootstrap Circuitry .................................................................... 15 Setting the Current Limit .......................................................... 25 Active Output Discharge Switch .............................................. 15 Selecting the Inductor ................................................................ 25 Precision Enabling ...................................................................... 15 Selecting the Output Capacitor ................................................ 26 Oscillator ..................................................................................... 15 Selecting the Low-Side MOSFET ............................................. 26 Synchronization Input/Output ................................................. 16 Designing the Compensation Network ................................... 26 Soft Start ...................................................................................... 17 Selecting the Soft Start Time..................................................... 26 Parallel Operation....................................................................... 17 Selecting the Input Capacitor ................................................... 26 Startup with Precharged Output .............................................. 18 Printed Circuit Board Layout Recommendations ..................... 27 Current-Limit Protection .......................................................... 18 Typical Application Circuit ........................................................... 28 Frequency Foldback ................................................................... 18 Factory Programmable Options ................................................... 29 Pulse Skip in Maximum Duty................................................... 18 Factory Default Options ............................................................ 30 Short-Circuit Protection (SCP) ................................................ 18 Outline Dimensions ....................................................................... 31 Latch-Off Protection .................................................................. 19 Ordering Guide .......................................................................... 31 Undervoltage Lockout (UVLO) ............................................... 19 REVISION HISTORY 9/15—Rev. A to Rev. B Changes to Figure 1 and Table 1 ..................................................... 1 Changes to Figure 2 .......................................................................... 3 Changes to Table 3 ............................................................................ 5 Changes to Figure 44 ...................................................................... 28 4/15—Rev. 0 to Rev. A Changes to Figure 3 ...........................................................................8 3/15—Revision 0: Initial Version Rev. B | Page 2 of 31 Data Sheet ADP5054 DETAILED FUNCTIONAL BLOCK DIAGRAM CHANNEL 1—BUCK 0.8V PVIN1 UVLO1 – + ACS1 – + EN1 1MΩ VREG HICCUP AND LATCH-UP OCP CLK1 BST1 Q1 DRIVER SW1 + CMP1 CONTROL LOGIC AND MOSFET DRIVER WITH ANTICROSS PROTECTION – COMP1 0.8V FB1 + EA1 – CLK1 VREG DL1 DRIVER PGND FREQ FOLDBACK ZERO CROSS VID1 0.72V DISCHARGE SWITCH SLOPE COMP CURRENT LIMIT SELECTION + – PWRGD1 CURRENT BALANCE EN2 CHANNEL 2—BUCK PVIN2 BST2 DUPLICATE CHANNEL 1 COMP2 DL2 FB2 RT SW2 OSCILLATOR VREG SYNC/MODE CFG12 CFG34 PVIN1 FUNCTION DECODER VREG INTERNAL POWER-ON REGULATOR RESET HOUSE-KEEPING LOGIC VDD PWRGD CHANNEL 3—BUCK 0.8V PVIN3 UVLO3 – + ACS3 – + EN3 1MΩ VREG HICCUP AND LATCH-UP OCP CLK3 Q3 BST3 DRIVER SLOPE COMP SW3 + – COMP3 0.8V FB3 + EA3 – CLK3 VREG CONTROL LOGIC AND MOSFET DRIVER WITH ANTICROSS PROTECTION FREQ FOLDBACK Q4 DRIVER PGND3 ZERO CROSS DISCHARGE SWITCH CMP3 VID3 0.72V + – PWRGD3 CURRENT BALANCE COMP4 CHANNEL 4—BUCK PVIN4 DUPLICATE CHANNEL 3 FB4 Figure 2. Rev. B | Page 3 of 31 BST4 SW4 PGND4 12617-002 EN4 ADP5054 Data Sheet SPECIFICATIONS VIN = 12 V, VVREG = 5.0 V, TJ = −40°C to +125°C for minimum and maximum specifications, and TA = 25°C for typical specifications, unless otherwise noted. Table 2. Parameter INPUT SUPPLY VOLTAGE RANGE QUIESCENT CURRENT Operating Quiescent Current Shutdown Current UNDERVOLTAGE LOCKOUT Threshold, Rising Threshold, Falling Hysteresis OSCILLATOR CIRCUIT Switching Frequency Switching Frequency Range SYNC Input Input Clock Range Input Clock Pulse Width Minimum On Time Minimum Off Time Input Clock High Voltage Input Clock Low Voltage SYNC Output Clock Frequency Positive Pulse Duty Cycle Rise or Fall Time High Level Voltage PRECISION ENABLING High Level Threshold Low Level Threshold Pull-Down Resistor POWER GOOD Internal Power-Good Rising Threshold Internal Power-Good Hysteresis Internal Power-Good Falling Delay Rising Delay for PWRGD Pin Leakage Current for PWRGD Pin Output Low Voltage for PWRGD Pin INTERNAL REGULATOR VDD Output Voltage VDD Current Limit VREG Output Voltage Dropout Voltage VREG Current Limit THERMAL SHUTDOWN Thermal Shutdown Threshold Thermal Shutdown Hysteresis Symbol VIN IQ ISHDN UVLO VUVLO_RISING VUVLO_FALLING VHYS Min 4.5 3.65 fSW 570 250 fSYNC 250 tSYNC_MIN_ON tSYNC_MIN_OFF VH(SYNC) VL(SYNC) 100 100 1.3 Typ Max 15.5 Unit V 4.7 20 5.3 35 mA µA 4.22 3.79 0.43 4.34 V V V 600 630 2000 kHz kHz 2000 kHz 0.4 ns ns V V fCLK tCLK_PULSE_DUTY tCLK_RISE_FALL VH(SYNC_OUT) fSW 50 10 VVREG VTH_H(EN) VTH_L(EN) RPULL-DOWN(EN) 0.811 0.72 2.0 0.835 V V MΩ 91 3.5 50 1 0.1 50 96 % % µs ms µA mV Test Conditions/Comments PVIN1, PVIN2, PVIN3, PVIN4 pins PVIN1, PVIN2, PVIN3, PVIN4 pins No switching, all ENx pins high All ENx pins low PVIN1, PVIN2, PVIN3, PVIN4 pins RT = 32.4 kΩ kHz % ns V EN1, EN2, EN3, EN4 pins 0.69 VPWRGD(RISE) VPWRGD(HYS) tPWRGD_FALL tPWRGD_PIN_RISE IPWRGD_LEAKAGE VPWRGD_LOW 86 VVDD ILIM_VDD VVREG VDROPOUT ILIM_VREG 3.2 30 4.85 TSHDN THYS 85 3.3 50 5.0 225 160 150 15 Rev. B | Page 4 of 31 1 100 3.4 70 5.15 225 V mA V mV mA °C °C IPWRGD = 1 mA IVDD = 10 mA IVREG = 50 mA IVREG = 50 mA Data Sheet ADP5054 BUCK REGULATOR SPECIFICATIONS VIN = 12 V, VVREG = 5.0 V, fSW = 600 kHz for all channels, TJ = −40°C to +125°C for minimum and maximum specifications, and TA = 25°C for typical specifications, unless otherwise noted. Table 3. Parameter CHANNEL 1 SYNC BUCK REGULATOR FB1 Pin Adjustable Feedback Voltage Feedback Voltage Accuracy Feedback Bias Current SW1 Pin High-Side Power FET On Resistance Current-Limit Threshold Minimum On Time Minimum Off Time Low-Side Driver, DL1 Pin Rising Time Falling Time Sourcing Resistor Sinking Resistor Error Amplifier (EA), COMP1 Pin EA Transconductance Soft Start Soft Start Time Programmable Soft Start Range Hiccup Time COUT Discharge Switch On Resistance CHANNEL 2 SYNC BUCK REGULATOR FB2 Pin Adjustable Feedback Voltage Feedback Voltage Accuracy Symbol VFB1 VFB1(DEFAULT) Min Typ tMIN_ON1 tMIN_OFF1 50 6.9 3.8 10.4 115 1/9 × tSW tRISING1 tFALLING1 tSOURCING1 tSINKING1 20 3.4 8 1.2 gm1 5.2 2.6 7.8 310 465 tSS1 V % % % µA TJ = 25°C 0°C ≤ TJ ≤ 85°C −40°C ≤ TJ ≤ +125°C Adjustable voltage mΩ A A A ns ns Pin-to-pin measurement RILIM1 floating RILIM1 = 47 kΩ RILIM1 = 22 kΩ fSW = 250 kHz to 2.0 MHz fSW = 250 kHz to 2.0 MHz ns ns Ω Ω CISS = 1.2 nF CISS = 1.2 nF 8.6 5.0 12.4 150 620 7 × tSS1 250 0.800 −0.55 −1.25 −1.5 +0.55 +1.0 +1.5 0.1 Feedback Bias Current SW2 Pin High-Side Power FET On Resistance Current-Limit Threshold IFB2 Minimum On Time Minimum Off Time Low-Side Driver, DL2 Pin Rising Time Falling Time Sourcing Resistor Sinking Resistor Error Amplifier (EA), COMP2 Pin EA Transconductance tMIN_ON2 tMIN_OFF2 50 6.9 3.8 10.4 115 1/9 × tSW tRISING2 tFALLING2 tSOURCING2 tSINKING2 20 3.4 8 1.2 gm2 +0.55 +1.0 +1.5 0.1 16.0 tHICCUP1 RDIS1 RDS(ON)_2H ITH(ILIM2) Test Conditions/Comments 2.0 2.0 VFB2 VFB2(DEFAULT) Unit 0.800 −0.55 −1.25 −1.5 IFB1 RDS(ON)_1H ITH(ILIM1) Max 5.2 2.6 7.8 310 465 Rev. B | Page 5 of 31 8.6 5.0 12.4 150 620 µS ms ms ms Ω CFG12 connected to ground V % % % µA TJ = 25°C 0°C ≤ TJ ≤ +85°C −40°C ≤ TJ ≤ +125°C Adjustable voltage mΩ A A A ns ns Pin-to-pin measurement RILIM2 = floating RILIM2 = 47 kΩ RILIM2 = 22 kΩ fSW = 250 kHz to 2.0 MHz fSW = 250 kHz to 2.0 MHz ns ns Ω Ω CISS = 1.2 nF CISS = 1.2 nF µS ADP5054 Parameter Soft Start Soft Start Time Programmable Soft Start Range Hiccup Time COUT Discharge Switch On Resistance CHANNEL 3 SYNC BUCK REGULATOR FB3 Pin Adjustable Feedback Voltage Feedback Voltage Accuracy Data Sheet Symbol Min Typ tSS2 2.0 2.0 16.0 tHICCUP2 RDIS2 VFB3 VFB3(DEFAULT) Feedback Bias Current SW3 Pin High-Side Power FET On Resistance Low-Side Power FET On Resistance Current-Limit Threshold Minimum On Time Minimum Off Time Error Amplifier (EA), COMP3 Pin EA Transconductance Soft Start Soft Start Time Programmable Soft Start Range Hiccup Time COUT Discharge Switch On Resistance CHANNEL 4 SYNC BUCK REGULATOR FB4 Pin Adjustable Feedback Voltage Feedback Voltage Accuracy IFB3 Feedback Bias Current SW4 Pin High-Side Power FET On Resistance Low-Side Power FET On Resistance Current-Limit Threshold Minimum On Time Minimum Off Time Error Amplifier (EA), COMP4 Pin EA Transconductance Soft Start Soft Start Time Programmable Soft Start Range Hiccup Time COUT Discharge Switch On Resistance IFB4 7 × tSS1 250 0.800 −0.55 −1.25 −1.5 RDS(ON)_3H RDS(ON)_3L ITH(ILIM3) tMIN_ON3 tMIN_OFF3 3.5 gm3 310 +0.55 +1.0 +1.5 0.1 125 80 4.66 95 1/9 × tSW 465 tSS3 620 16.0 tHICCUP3 RDIS3 7 × tSS3 250 0.800 −0.55 −1.25 −1.5 RDS(ON)_4H RDS(ON)_4L ITH(ILIM4) tMIN_ON4 tMIN_OFF4 3.5 gm4 310 tSS4 +0.55 +1.0 +1.5 0.1 125 80 4.66 95 1/9 × tSW 465 5.5 125 620 2.0 2.0 tHICCUP4 RDIS4 5.5 125 2.0 2.0 VFB4 VFB4(DEFAULT) Max 16.0 7 × tSS3 250 Rev. B | Page 6 of 31 Unit Test Conditions/Comments ms ms ms Ω CFG12 connected to ground V % % % µA mΩ mΩ A ns ns TJ = 25°C 0°C ≤ TJ ≤ 85°C −40°C ≤ TJ ≤ +125°C Adjustable voltage Pin-to-pin measurement Pin-to-pin measurement fSW = 250 kHz to 2.0 MHz fSW = 250 kHz to 2.0 MHz µS ms ms ms Ω V % % % µA mΩ mΩ A ns ns CFG34 connected to ground TJ = 25°C 0°C ≤ TJ ≤ 85°C −40°C ≤ TJ ≤ +125°C Pin-to-pin measurement Pin-to-pin measurement fSW = 250 kHz to 2.0 MHz fSW = 250 kHz to 2.0 MHz µS ms ms ms Ω CFG34 connected to ground Data Sheet ADP5054 ABSOLUTE MAXIMUM RATINGS Table 4. Parameter1 PVIN1 to PGND PVIN2 to PGND PVIN3 to PGND3 PVIN4 to PGND4 SW1 to PGND SW2 to PGND SW3 to PGND3 SW4 to PGND4 PGND to Ground PGND3 to Ground PGND4 to Ground BST1 to SW1 BST2 to SW2 BST3 to SW3 BST4 to SW4 DL1 to PGND DL2 to PGND CFG12, CFG34 to Ground EN1, EN2, EN3, EN4 to Ground VREG to Ground SYNC/MODE to Ground RT to Ground PWRGD to Ground FB1, FB2, FB3, FB4 to Ground 2 COMP1, COMP2, COMP3, COMP4 to Ground Storage Temperate Range Operational Junction Temperature Range 1 2 Rating −0.3 V to +18 V −0.3 V to +18 V −0.3 V to +18 V −0.3 V to +18 V −0.3 V to +18 V −0.3 V to +18 V −0.3 V to +18 V −0.3 V to +18 V −0.3 V to +0.3 V −0.3 V to +0.3 V −0.3 V to +0.3 V −0.3 V to +6.5 V −0.3 V to +6.5 V −0.3 V to +6.5 V −0.3 V to +6.5 V −0.3 V to +6.5 V −0.3 V to +6.5 V −0.3 V to +6.5 V −0.3 V to +6.5 V −0.3 V to +6.5 V −0.3 V to +6.5 V −0.3 V to +3.6 V −0.3 V to +6.5 V −0.3 V to +3.6 V −0.3 V to +3.6 V −65°C to +150°C −40°C to +125°C Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. THERMAL RESISTANCE θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 5. Thermal Resistance Package Type 48-Lead LFCSP ESD CAUTION The exposed pad is the analog ground for the ADP5054. See Table 6. The rating for the FB1, FB2, FB3, and FB4 pins applies to the adjustable output voltage models of the ADP5054. Rev. B | Page 7 of 31 θJA 28.4 θJC 10.1 Unit °C/W ADP5054 Data Sheet 48 47 46 45 44 43 42 41 40 39 38 37 EN3 COMP3 FB3 VREG SYNC/MODE VDD RT FB1 COMP1 EN1 PVIN1 PVIN1 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS ADP5054 TOP VIEW (Not to Scale) 36 35 34 33 32 31 30 29 28 27 26 25 PVIN1 SW1 SW1 SW1 BST1 DL1 PGND DL2 BST2 SW2 SW2 SW2 NOTES 1. THE EXPOSED PAD MUST BE CONNECTED AND SOLDERED TO AN EXTERNAL GROUND PLANE. 12617-003 CFG34 EN4 COMP4 FB4 PWRGD CFG12 FB2 COMP2 EN2 PVIN2 PVIN2 PVIN2 13 14 15 16 17 18 19 20 21 22 23 24 BST3 1 PGND3 2 PGND3 3 SW3 4 SW3 5 PVIN3 6 PVIN4 7 SW4 8 SW4 9 PGND4 10 PGND4 11 BST4 12 Figure 3. Pin Configuration Table 6. Pin Function Descriptions Pin No. 1 2, 3 4, 5 6 7 8, 9 10, 11 12 13 Mnemonic BST3 PGND3 SW3 PVIN3 PVIN4 SW4 PGND4 BST4 CFG34 14 15 16 17 18 EN4 COMP4 FB4 PWRGD CFG12 19 20 21 22, 23, 24 25, 26, 27 28 29 FB2 COMP2 EN2 PVIN2 SW2 BST2 DL2 30 31 PGND DL1 32 33, 34, 35 36, 37, 38 BST1 SW1 PVIN1 Description High-Side FET Driver Power Supply for Channel 3. Power Ground for Channel 3. Switching Node Output for Channel 3. Power Input for Channel 3. Connect a bypass capacitor between this pin and ground. Power Input for Channel 4. Connect a bypass capacitor between this pin and ground. Switching Node Output for Channel 4. Power Ground for Channel 4. High-Side FET Driver Power Supply for Channel 4. Connect a resistor divider from this pin to VREG and ground to configure the different functionalities for Channel 3 and Channel 4, including the soft start timer, ½× frequency, parallel operation, and SYNC clock output features. Enable Input for Channel 4. Use an external resistor divider to set the turn-on threshold. Error Amplifier Output for Channel 4. Connect an RC network from this pin to ground. Feedback Sensing Input for Channel 4. Power-Good Signal Output. This open-drain output is the power-good signal for the selected channels. Connect a resistor divider from this pin to VREG and ground to configure the different functionalities for Channel 1 and Channel 2, including the soft start timer, ½× frequency, and parallel operation features. Feedback Sensing Input for Channel 2. Error Amplifier Output for Channel 2. Connect an RC network from this pin to ground. Enable Input for Channel 2. Use an external resistor divider to set the turn-on threshold. Power Input for Channel 2. Connect a bypass capacitor between this pin and ground. Switching Node Output for Channel 2. High-Side FET Driver Power Supply for Channel 2. Low-Side FET Gate Driver for Channel 2. Connect a resistor from this pin to ground to program the current-limit threshold for Channel 2. Power Ground for Channel 1 and Channel 2. Low-Side FET Gate Driver for Channel 1. Connect a resistor from this pin to ground to program the current-limit threshold for Channel 1. High-Side FET Driver Power Supply for Channel 1. Switching Node Output for Channel 1. Power Input for the Internal Linear Regulator and the Channel 1 Buck Regulator. Connect a bypass capacitor between this pin and ground. Rev. B | Page 8 of 31 Data Sheet Pin No. 39 40 41 42 43 44 Mnemonic EN1 COMP1 FB1 RT VDD SYNC/MODE 45 46 47 48 49 VREG FB3 COMP3 EN3 EPAD ADP5054 Description Enable Input for Channel 1. Use an external resistor divider to set the turn-on threshold. Error Amplifier Output for Channel 1. Connect an RC network from this pin to ground. Feedback Sensing Input for Channel 1. Connect a resistor from RT to ground to program the switching frequency from 250 kHz to 2 MHz. Output of the Internal 3.3 V Linear Regulator. Connect a 1.0 µF ceramic capacitor between this pin and ground. Synchronization Input/Output (SYNC). To synchronize the switching frequency of the device to an external clock, connect this pin to an external clock with a frequency from 250 kHz to 2.0 MHz. This pin can also be configured as a synchronization output via the CFG34 pin configuration. Forced PWM or Automatic PWM/PSM Selection Pin (MODE). When this pin is logic high, each channel works in forced PWM or automatic PWM/PSM mode. When this pin is logic low, all channels operate in automatic PWM/PSM mode. Output of the Internal 5.0 V Linear Regulator. Connect a 1.0 µF ceramic capacitor between this pin and ground. Feedback Sensing Input for Channel 3. Error Amplifier Output for Channel 3. Connect an RC network from this pin to ground. Enable Input for Channel 3. Use an external resistor divider to set the turn-on threshold. Exposed Pad (Analog Ground). The exposed pad must be connected and soldered to an external ground plane. Rev. B | Page 9 of 31 ADP5054 Data Sheet 100 100 90 90 80 80 70 70 EFFICIENCY (%) 60 50 40 30 1.0 2.0 3.0 4.0 5.0 6.0 10 Figure 4. Channel 1/Channel 2 Efficiency Curve, VIN = 12 V, fSW = 600 kHz, MOSFET = SI4204DY, FPWM Mode 0 01 90 80 80 70 70 EFFICIENCY (%) 90 50 40 60 50 40 30 VOUT = 1.2V VOUT = 1.5V VOUT = 1.8V VOUT = 2.5V VOUT = 3.3V 10 0 1.0 2.0 3.0 4.0 5.0 6.0 IOUT (A) VOUT = 1.2V VOUT = 1.5V VOUT = 1.8V VOUT = 2.5V VOUT = 3.3V 20 10 0 12617-005 20 Figure 5. Channel 1/Channel 2 Efficiency Curve, VIN = 5 V, fSW = 600 kHz, MOSFET = SI4204DY, FPWM Mode 0 90 80 80 70 70 EFFICIENCY (%) 100 40 1.5 2.0 2.5 Figure 8. Channel 3/Channel 4 Efficiency Curve, VIN = 12 V, fSW = 600 kHz, FPWM Mode 90 50 1.0 IOUT (A) 100 60 0.5 12617-008 30 30 60 50 40 30 20 VOUT = 1.2V VOUT = 1.5V VOUT = 1.8V VOUT = 2.5V VOUT = 3.3V 20 fSW = 250kHz fSW = 600kHz fSW = 1MHz 0 1.0 2.0 3.0 IOUT (A) 4.0 5.0 6.0 10 0 12617-006 10 0 10 Figure 7. Channel 1/Channel 2 Efficiency Curve, VIN = 12 V, fSW = 600 kHz, FPWM and Automatic PWM/PSM Modes 100 60 1 0.1 IOUT (A) 100 0 VOUT = 1.2V FPWM VOUT = 1.8V FPWM VOUT = 3.3V FPWM VOUT = 1.2V PWM/PSM VOUT = 1.8V PWM/PSM VOUT = 3.3V PWM/PSM 12617-007 0 IOUT (A) EFFICIENCY (%) 40 20 12617-004 10 EFFICIENCY (%) 50 30 VOUT = 1.2V VOUT = 1.5V VOUT = 1.8V VOUT = 2.5V VOUT = 3.3V 20 0 60 Figure 6. Channel 1/Channel 2 Efficiency Curve, VIN = 12 V, VOUT = 3.3 V, MOSFET = SI4204DY, FPWM Mode 0 0.5 1.0 1.5 IOUT (A) 2.0 2.5 12617-109 EFFICIENCY (%) TYPICAL PERFORMANCE CHARACTERISTICS Figure 9. Channel 3/Channel 4 Efficiency Curve, VIN = 5.0 V, fSW = 600 kHz, FPWM Mode Rev. B | Page 10 of 31 Data Sheet ADP5054 100 750 90 700 80 FREQUENCY (kHz) EFFICIENCY (%) 70 60 50 40 650 600 550 30 20 0 0.5 1.0 1.5 2.5 2.0 IOUT (A) 450 –50 12617-110 0 –20 10 40 70 100 12617-113 500 fSW = 250kHz fSW = 600kHz fSW = 1MHz 10 130 TEMPERATURE (°C) Figure 10. Channel 3/Channel 4 Efficiency Curve, VIN = 12 V, VOUT = 1.8 V, FPWM Mode Figure 13. Frequency vs. Temperature, VIN = 12 V, fSW = 600 kHz 6.0 100 90 5.5 QUIESCENT CURRENT (mA) 80 60 50 40 30 VOUT = 1.2V FPWM VOUT = 1.8V FPWM VOUT = 3.3V FPWM VOUT = 1.2V PWM/PSM VOUT = 1.8V PWM/PSM VOUT = 3.3V PWM/PSM 10 0 01 10 1 0.1 4.5 4.0 3.5 IOUT (A) 3.0 –50 12617-111 20 5.0 50 0 12617-114 EFFICIENCY (%) 70 100 TEMPERATURE (°C) Figure 11. Channel 3/Channel 4 Efficiency Curve, VIN = 12 V, fSW = 600 kHz, FPWM and Automatic PWM/PSM Modes Figure 14. Quiescent Current vs. Temperature (Includes PVIN1, PVIN2, PVIN3, and PVIN4) 50 0.810 0.800 0.795 40 35 30 25 20 VIN = 4.5V VIN = 12V VIN = 15V 15 0.790 –50 –20 10 40 70 100 130 TEMPERATURE (°C) Figure 12. 0.8 V Feedback Voltage Accuracy vs. Temperature for Channel 1, Adjustable Output Model 10 –50 –20 10 40 70 TEMPERATURE (°C) 100 130 12617-115 SHUTDOWN CURRENT (µA) 0.805 12617-112 FEEDBACK VOLTAGE (V) 45 Figure 15. Shutdown Current vs. Temperature (EN1, EN2, EN3, and EN4 Low) Rev. B | Page 11 of 31 ADP5054 Data Sheet 4.5 4.4 RISING FALLING UVLO THRESHOLD (V) 4.3 4.2 4.1 4.0 3.9 3.8 3.7 –20 10 40 70 100 12617-116 3.5 –50 12617-119 3.6 130 TEMPERATURE (°C) Figure 19. Steady State Waveform at Heavy Load, VIN = 12 V, VOUT = 3.3 V, IOUT = 3 A, fSW = 600 kHz, L = 4.7 µH, COUT = 47 µF × 2, FPWM Mode, Channel 1 = VOUTX, Channel 2 = SWx Figure 16. UVLO Threshold vs. Temperature 12 11 CURRENT LIMIT (A) 10 9 8 7 6 5 4 –20 10 40 70 100 130 TEMPERATURE (°C) 12617-120 2 –50 RLIM = 22kΩ RLIM = OPEN RLIM = 47kΩ 12617-017 3 Figure 17. Channel 1/Channel 2 Current Limit vs. Temperature 200 180 Figure 20. Steady State Waveform at Light Load, VIN = 12 V, VOUT = 3.3 V, IOUT = 30 mA, fSW = 600 kHz, L = 4.7 µH, COUT = 47 µF × 2, Automatic PWM/PSM Mode, Channel 1 = VOUTX, Channel 2 = SWx CHANNEL 1/CHANNEL 2 CHANNEL 3/CHANNEL 4 140 120 100 80 60 40 0 –50 –20 10 40 70 100 TEMPERATURE (°C) Figure 18. Minimum On Time vs. Temperature 130 12617-121 20 12617-118 MINIMUM ON TIME (ns) 160 Figure 21. Channel 1/Channel 2 Load Transient, 1 A to 4 A, VIN = 12 V, VOUT = 3.3 V, fSW = 600 kHz, L = 2.2 µH, COUT = 47 µF × 2, Channel 1 = VOUTX, Channel 4 = IOUTX Rev. B | Page 12 of 31 ADP5054 12617-122 12617-125 Data Sheet Figure 25. Channel 1 Shutdown with Active Output Discharge, VIN = 12 V, VOUT = 1.2 V, fSW = 600 kHz, L = 1 µH, COUT = 47 µF × 2, Channel 1 = VOUT1, Channel 2 = EN1, Channel 3 = PWRGD, Channel 4 = IOUT1 12617-123 12617-126 Figure 22. Load Transient, Channel 1/Channel 2 Parallel Output, 0 A to 6 A, VIN = 12 V, VOUT = 3.3 V, fSW = 600 kHz, L = 4.7 µH, COUT = 47 µF × 4, Channel 1 = VOUT, Channel 3 = IL1, Channel 4 = IL2 Figure 26. Short-Circuit Protection Entry, VIN = 12 V, VOUT = 1.2 V, fSW = 600 kHz, L = 1 µH, COUT = 47 µF × 2, Channel 1 = VOUTX, Channel 2 = SWx, Channel 4 = ILX 12617-127 12617-124 Figure 23. Channel 1 Soft Start with 4 A Resistance Load, VIN = 12 V, VOUT = 1.2 V, fSW = 600 kHz, L = 1 µH, COUT = 47 µF × 2, Channel 1 = VOUT1, Channel 2 = PWRGD, Channel 3 = EN1, Channel 4 = IOUT1 Figure 24. Channel 1 Startup with Precharged Output, VIN = 12 V, VOUT = 3.3 V, Channel 1 = VIN, Channel 2 = VOUT1, Channel 3 = EN1, Channel 4 = IL1 Figure 27. Short-Circuit Protection Recovery, VIN = 12 V, VOUT = 1.2 V, fSW = 600 kHz, L = 1 µH, COUT = 47 µF × 2, Channel 1 = VOUTX, Channel 2 = SWx, Channel 4 = ILX Rev. B | Page 13 of 31 ADP5054 Data Sheet THEORY OF OPERATION The ADP5054 is a micropower management unit that combines four high performance buck regulators in a 48-lead LFCSP package to meet demanding performance and board space requirements. The device enables direct connection to high input voltages of up to 15.5 V with no preregulators to make applications simpler and more efficient. BUCK REGULATOR OPERATIONAL MODES PWM Mode In pulse width modulation (PWM) mode, the buck regulators in the ADP5054 operate at a fixed frequency; this frequency is set by an internal oscillator that is programmed by the RT pin. At the start of each oscillator cycle, the high-side MOSFET switch turns on and sends a positive voltage across the inductor. The inductor current increases until the current-sense signal exceeds the peak inductor current threshold that turns off the high-side MOSFET switch; this threshold is set by the error amplifier output. During the high-side MOSFET off time, the inductor current decreases through the low-side MOSFET switch until the next oscillator clock pulse starts a new cycle. The buck regulators in the ADP5054 regulate the output voltage by adjusting the peak inductor current threshold. PSM Mode The buck regulators can be configured to operate in automatic PWM/PSM mode using the SYNC/MODE pin. In automatic PWM/PSM mode, the buck regulators operate in either PWM mode or PSM mode, depending on the output current. When the average output current falls below the PWM/PSM threshold, the buck regulator enters PSM mode; in PSM mode, the regulator operates with a reduced switching frequency to maintain high efficiency. The low-side MOSFET turns off when the output current reaches 0 A, causing the regulator to operate in discontinuous mode (DCM). The user can alternate between FPWM mode and automatic PWM/PSM mode during operation. The flexible configuration capability during device operation enables efficient power management. When a logic high level is applied to the SYNC/MODE pin (or when SYNC/MODE is configured as a clock input or output), the operational mode of all four buck regulators is set for forced PWM mode. When a logic low level is applied to the SYNC/MODE pin, the operational mode of all four buck regulators is automatic PWM/PSM mode. Table 7 describes the function of the SYNC/MODE pin in setting the operational mode of the device. To achieve higher efficiency, the buck regulators in the ADP5054 smoothly transition to variable frequency, power savings mode (PSM) operation when the output load falls below the PSM current threshold. When the output voltage falls below regulation, the buck regulator enters PWM mode for a few oscillator cycles until the voltage increases to within regulation. During the idle time between bursts, the MOSFET switch turns off, and the output capacitor supplies all the output current. Table 7. Configuring the Mode of Operation Using the SYNC/MODE Pin The PSM mode comparator monitors the internal compensation node, which represents the peak inductor current information. The average PSM mode current threshold depends on the input voltage (VIN), the output voltage (VOUT), the inductor, and the output capacitor. Because the output voltage occasionally falls below regulation and then recovers, the output voltage ripple in PSM mode is larger than the ripple in forced PWM (FPWM) mode under light load conditions. The ADP5054 provides adjustable and fixed output voltage settings via the factory fuse. For the adjustable output settings, use an external resistor divider to set the desired output voltage via the feedback reference voltage (0.8 V for Channel 1 to Channel 4). Forced PWM and Automatic PWM/PSM Modes The buck regulators can be configured to always operate in forced PWM (FPWM) mode using the SYNC/MODE pin and the I2C register. In FPWM mode, the regulator continues to operate at a fixed frequency even when the output current is below the PWM/PSM threshold. In PWM mode, efficiency is lower compared to PSM mode under light load conditions. The low-side MOSFET remains on when the inductor current falls to less than 0 A, causing the ADP5054 to enter continuous conduction mode (CCM). SYNC/MODE Pin High Clock In/Out Low Mode of Operation for All Channels Forced PWM mode Forced PWM mode Automatic PWM/PSM mode ADJUSTABLE AND FIXED OUTPUT VOLTAGE For the fixed output settings, the feedback resistor divider is built into the ADP5054, and the feedback pin (FBx) must be tied directly to the output. Each buck regulator channel can be programmed for a specific output voltage. Table 14 lists the fixed output ranges configured by the factory fuse. If a different output voltage range is required, contact your local Analog Devices, Inc., sales or distribution representative. INTERNAL REGULATORS (VREG AND VDD) The internal VREG regulator in the ADP5054 provides a stable 5.0 V power supply for the bias voltage of the MOSFET drivers. The internal VDD regulator in the ADP5054 provides a stable 3.3 V power supply for the internal control circuits. One 1.0 µF ceramic capacitor must be connected between VREG and ground, and another 1.0 µF ceramic capacitor must be connected between VDD and ground. Rev. B | Page 14 of 31 Data Sheet ADP5054 Note that the VDD regulator is for internal circuit use and is not recommended for other purposes. SEPARATE SUPPLY APPLICATIONS The ADP5054 supports separate input voltages for the four buck regulators, meaning the input voltages for the four buck regulators can be connected to different supply voltages. The PVIN1 voltage provides the power supply for the internal regulators and the control circuitry. Therefore, if the user plans to use separate supply voltages for the buck regulators, the PVIN1 voltage must be above the UVLO threshold before the other channels begin to operate. Note that precision enabling can be used to monitor the PVIN1 voltage and to delay the startup of the outputs to ensure that PVIN1 is high enough to support the outputs in regulation (see the Precision Enabling section). ACTIVE OUTPUT DISCHARGE SWITCH Each buck regulator in the ADP5054 integrates a discharge switch from the switching node to ground. This switch is turned on when its associated regulator is disabled, which helps to discharge the output capacitor quickly. The typical value of the discharge switch is 120 Ω for Channel 1 to Channel 4. PRECISION ENABLING The ADP5054 has an enable control pin for each regulator, including the LDO regulator. Each enable control pin (ENx) features a precision enable circuit with a 0.811 V reference voltage. When the voltage at the ENx pin is greater than 0.811 V, the regulator is enabled. When the ENx pin voltage falls below 0.72 V, the regulator is disabled. An internal 1 MΩ pull-down resistor prevents errors if the ENx pin is left floating. The precision enable threshold voltage allows easy sequencing of channels within the device, as well as sequencing between the ADP5054 and other input/output supplies. The ENx pin can also be used as a programmable UVLO input using a resistor divider (see Figure 29). The ADP5054 supports cascading supply operations for the four buck regulators. As shown in Figure 28, PVIN2, PVIN3, and PVIN4 are powered from the Channel 1 output. In this configuration, the Channel 1 output voltage must be higher than the UVLO threshold for PVIN2, PVIN3, and PVIN4. INPUT/OUTPUT VOLTAGE INTERNAL ENABLE DEGLITCH TIMER 0.811V R1 ENx 1MΩ R2 12617-010 The internal VREG and VDD regulators are active as long as PVIN1 is available. The internal VREG regulator can provide a total load of 150 mA, including the MOSFET driving current. The current-limit circuit is included in the VREG regulator to protect the circuit when the device is heavily loaded. Figure 29. Precision Enable Diagram for One Channel PVIN1 The switching frequency (fSW) of the ADP5054 can be set to a value from 250 kHz to 2.0 MHz by connecting a resistor from the RT pin to ground. The value of the RT resistor can be calculated as follows: VOUT2 TO VOUT4 BUCK 2 12617-009 PVIN2 TO PVIN4 OSCILLATOR BUCK 1 RRT (kΩ) = [14,822/fSW (kHz)]1.081 Figure 28. Cascading Supply Application The buck regulators in Channel 1 and Channel 2 integrate 6 A high-side power MOSFETs and low-side MOSFET drivers. The N-channel MOSFETs selected for use with the ADP5054 must be able to work with the synchronized buck regulators. In general, use a low RDS(ON) N-channel MOSFET to achieve higher efficiency; dual MOSFETs in one package (for both Channel 1 and Channel 2) are recommended to save space on the printed circuit board (PCB). For more information, see the Low-Side Power Device Selection section. BOOTSTRAP CIRCUITRY Each buck regulator in the ADP5054 has an integrated boot regulator. The boot regulator requires a 0.1 µF ceramic capacitor (X5R or X7R) between the BSTx and SWx pins to provide the gate drive voltage for the high-side MOSFET. Figure 30 shows the typical relationship between fSW and the RT resistor. The adjustable frequency allows users to make decisions based on the trade-off between efficiency and the size of the solution. 2200 2000 1800 FREQUENCY (kHz) LOW-SIDE DEVICE SELECTION 1600 1400 1200 1000 800 600 400 200 0 30 60 RT RESISTOR (kΩ) Figure 30. Switching Frequency vs. RT Resistor Rev. B | Page 15 of 31 90 12617-130 VIN VOUT1 ADP5054 Data Sheet The frequency in each channel can be set to half the master switching frequency set by the RT pin. This setting is configured using the CFG12 and CFG34 pins (see Table 8 and Table 9). This halving of the frequency is not recommended if the switching frequency is less than 250 kHz. with a 50% duty cycle is generated at the SYNC/MODE pin with a frequency equal to the internal switching frequency set by the RT pin. There is a short delay time (approximately 15% of tSW) from the generated synchronization clock to the Channel 1 switching node. Phase Shift Figure 32 shows two ADP5054 devices configured for frequency synchronization mode: one ADP5054 device is configured as the clock output to synchronize another ADP5054 device. It is recommended that a 100 kΩ pull-up resistor be used to prevent logic errors when the SYNC/MODE pin is left floating. By default, the phase shift between Channel 1 and Channel 2 and between Channel 3 and Channel 4 is 180° (see Figure 31). This value provides the benefits of out-of-phase operation by reducing the input ripple current and lowering the grounding noise. VREG 0° REFERENCE 100kΩ CHANNEL 1 (½ fSW OPTIONAL) SYNC/MODE 180° PHASE SHIFT SYNC/MODE 12617-013 CHANNEL 2 (½ fSW OPTIONAL) 0° REFERENCE CHANNEL 4 (½ fSW OPTIONAL) Figure 32. Two ADP5054 Devices Configured for Synchronization Mode 12617-012 180° PHASE SHIFT CHANNEL 3 (½ fSW OPTIONAL) Figure 31. Phase Shift Diagram, Four Buck Regulators In the configuration shown in Figure 32, the phase shift between Channel 1 of the first ADP5054 device and Channel 1 of the second ADP5054 device is 0° (see Figure 33). SYNCHRONIZATION INPUT/OUTPUT The switching frequency of the ADP5054 can be synchronized to an external clock with a frequency range from 250 kHz to 2.0 MHz. The ADP5054 automatically detects the presence of an external clock applied to the SYNC/MODE pin, and the switching frequency transitions smoothly to the frequency of the external clock. When the external clock signal stops, the device automatically switches back to the internal clock and continues to operate. SYNC OUTPUT AT FIRST ADP5054 1 SW1 AT FIRST ADP5054 2 SW1 AT SECOND ADP5054 Note that the internal switching frequency set by the RT pin must be programmed to a value that is close to the external clock value for successful synchronization; the suggested frequency difference is less than ±15% in typical applications. CH1 2.00V BW CH3 5.00V BW CH2 5.00V BW M400ns A CH1 560mV 12617-014 3 Figure 33. Waveforms of Two ADP5054 Devices Operating in Synchronization Mode The SYNC/MODE pin can be configured as a synchronization clock output using CFG34 (see Table 9). A positive clock pulse Table 8. CFG12 Configuration (Channel 1 and Channel 2)1 RTOP (kΩ) 0 100 200 300 400 500 600 N/A 1 RBOT (kΩ) N/A 600 500 400 300 200 100 0 Channel 1 Soft Start (ms) Frequency (kHz) 16 1 × fSW 16 ½ × fSW 2 1 × fSW 2 ½ × fSW 16 ½ × fSW 16 1 × fSW 2 1 × fSW 2 1 × fSW Channel 2 Soft Start (ms) Frequency (kHz) 16 1 × fSW 16 ½ × fSW 2 ½ × fSW 2 1 × fSW N/A N/A N/A N/A N/A N/A 2 1 × fSW N/A means not applicable. Rev. B | Page 16 of 31 Parallel or Individual Operation Individual Individual Individual Individual Parallel Parallel Parallel Individual Data Sheet ADP5054 Table 9. CFG34 Configuration (Channel 3, Channel 4, and SYNC/MODE)1 RTOP (kΩ) 0 100 200 300 400 500 RBOT (kΩ) N/A 600 500 400 300 200 Channel 3 Soft Start (ms) Frequency (kHz) 16 1 × fSW 16 ½ × fSW 2 ½ × fSW 16 ½ × fSW 2 1 × fSW 16 1 × fSW Channel 4 Soft Start (ms) Frequency (kHz) 16 1 × fSW 16 ½ × fSW 2 1 × fSW N/A N/A N/A N/A N/A N/A Parallel or Individual Operation Individual Individual Individual Parallel Parallel Parallel 600 100 2 1 × fSW 2 1 × fSW Individual N/A 0 2 1 × fSW 2 1 × fSW Individual 1 SYNC/MODE or Clock Out SYNC/MODE SYNC/MODE SYNC/MODE SYNC/MODE SYNC/MODE Clock out (FPWM) Clock out (FPWM) SYNC/MODE N/A means not applicable. SOFT START The buck regulators in the ADP5054 include soft start circuitry that ramps the output voltage in a controlled manner during startup, thereby limiting the inrush current. The soft start time is typically fixed at 2 ms for each buck regulator when the CFG12 and CFG34 pins are tied to ground. To set the soft start time to a value of 2 ms or 16 ms, connect a resistor divider from the CFG12 pin or the CFG34 pin to the VREG pin and ground (see Figure 34). This configuration may be required to accommodate a specific start-up sequence or an application with a large output capacitor. To configure a two-phase single output in parallel operation, take the following steps (see Figure 35): • • • • • Use the CFG12 pin (or CFG34 pin) to select parallel operation as specified in Table 8 and Table 9. Leave the COMP2 pin (or COMP4 pin) open. Use the FB1 pin (or FB3 pin) to set the output voltage. Connect the FB2 pin (or FB4 pin) to ground (FB2 or FB4 is ignored). Connect the EN2 pin (or EN4 pin) to ground (EN2 or EN4 is ignored). VIN PVIN1 VREG PVIN2 TOP RESISTOR VREG CFG12 OR CFG34 CFG12 SW1 CHANNEL 1 BUCK (4A) L1 VOUT (UP TO 12A) FB1 LEVEL DETECTOR AND DECODER COMP1 BOTTOM RESISTOR 12617-015 SW2 COMP2 EN1 CHANNEL 2 BUCK (4A) L2 FB2 Figure 34. Level Detector Circuit for Soft Start PARALLEL OPERATION The ADP5054 supports two-phase parallel operation of Channel 1 and Channel 2 to provide a single output with up to 12 A of current, and two-phase parallel operation of Channel 3 and Channel 4 to provide a single output with up to 5 A of current. 12617-016 EN2 The CFG12 pin can be used to program the soft start time, ½× frequency setting, and parallel operation for Channel 1 and Channel 2. The CFG34 pin can be used to program the soft start time, ½× frequency setting, parallel operation, and clock output feature for Channel 3 and Channel 4. Table 8 and Table 9 provide the values of the resistors needed to set the soft start time. Figure 35. Parallel Operation for Channel 1 and Channel 2 The following considerations apply when two channels are operated in parallel configuration. • • The input voltages and current-limit settings for both channels must be the same. Both channels must be operated in FPWM mode. Current balance in parallel configuration is well regulated by the internal control loop. Figure 36 shows the Channel 1 and Channel 2 typical current balance matching in parallel output configuration. Figure 37 shows the Channel 3 and Channel 4 current balance matching in parallel output configuration. Rev. B | Page 17 of 31 ADP5054 8 Data Sheet Table 10. Peak Current-Limit Threshold Settings for Channel 1 and Channel 2 CHANNEL 1 CURRENT CHANNEL 2 CURRENT RILIM1 or RILIM2 Floating 47 kΩ 22 kΩ 6 5 4 2 1 FREQUENCY FOLDBACK 0 0 2 4 6 8 10 12 TOTAL OUPTUT LOAD (A) Figure 36. Channel 1 and Channel 2 Current Balance in Parallel Output Configuration, VIN = 12 V, VOUT = 1.2 V, fSW = 600 kHz, FPWM Mode The buck regulators in the ADP5054 include frequency foldback to prevent output current runaway when a hard short occurs on the output. Frequency foldback is implemented as follows: • 3.0 CHANNEL 3 CURRENT CHANNEL 4 CURRENT • 2.5 CHANNEL CURRENT (A) Typical Peak Current-Limit Threshold (A) 6.9 3.8 10.4 The buck regulators in the ADP5054 include negative currentlimit protection circuitry to limit certain amounts of negative current flowing through the low-side MOSFET switch. 3 12617-136 CHANNEL CURRENT (A) 7 2.0 The reduced switching frequency allows more time for the inductor current to decrease but also increases the ripple current during peak current regulation. This results in a reduction in average current and prevents output current runaway. 1.5 1.0 PULSE SKIP IN MAXIMUM DUTY 0 1 2 3 4 TOTAL OUPTUT LOAD (A) 5 12617-137 0.5 0 If the voltage at the FBx pin falls below half of the target output voltage, the switching frequency is reduced by half. If the voltage at the FBx pin falls again to below one-fourth of the target output voltage, the switching frequency is reduced by half of its current value again, as one-fourth of fSW. Figure 37. Channel 3 and Channel 4 Current Balance in Parallel Output Configuration, VIN = 12 V, VOUT = 1.2 V, fSW = 600 kHz, FPWM Mode STARTUP WITH PRECHARGED OUTPUT The buck regulators in the ADP5054 include a precharged start-up feature to protect the low-side FETs from damage during startup. If the output voltage is precharged before the regulator is turned on, the regulator prevents reverse inductor current—which would discharge the output capacitor—until the internal soft start reference voltage exceeds the precharged voltage on the feedback (FBx) pin. CURRENT-LIMIT PROTECTION The buck regulators in the ADP5054 include peak current-limit protection circuitry to limit the amount of positive current flowing through the high-side MOSFET switch. The peak current limit on the power switch limits the amount of current that can flow from the input to the output. The programmable current-limit threshold feature allows the use of small size inductors for low current applications. To configure the current-limit threshold for Channel 1, connect a resistor from the DL1 pin to ground; to configure the currentlimit threshold for Channel 2, connect another resistor from the DL2 pin to ground. Table 10 lists the peak current-limit threshold settings for Channel 1 and Channel 2. Under maximum duty cycle conditions, frequency foldback maintains the output in regulation. If the maximum duty cycle is reached—for example, when the input voltage decreases—the PWM modulator skips every other PWM pulse, resulting in a switching frequency foldback of one-half of the switching frequency. If the maximum duty cycle increases further, the PWM modulator skips two of every three PWM pulses, resulting in a switching frequency foldback that is one-third of the switching frequency. Frequency foldback increases the effective maximum duty cycle, thereby decreasing the dropout voltage between the input and output voltages. SHORT-CIRCUIT PROTECTION (SCP) The buck regulators in the ADP5054 include a hiccup mode for overcurrent protection (OCP). When the peak inductor current reaches the current-limit threshold, the high-side MOSFET turns off, and the low-side MOSFET turns on until the next cycle. When hiccup mode is active, the overcurrent fault counter is incremented. If the overcurrent fault counter reaches 15 and overflows (indicating a short-circuit condition), both the highside and low-side MOSFETs are turned off. The buck regulator remains in hiccup mode for a period equal to seven soft start cycles and then attempts to restart from soft start. If the shortcircuit fault clears, the regulator resumes normal operation; otherwise, it reenters hiccup mode after the soft start. Hiccup detection is masked during the initial soft start cycle to enable startup of the buck regulator under heavy load conditions. Rev. B | Page 18 of 31 Data Sheet ADP5054 Note that careful design and proper component selection are required to ensure that the buck regulator recovers from hiccup mode under heavy loads. The hiccup detection can be disabled by the factory fuse for each buck regulator. When hiccup detection is disabled, the frequency foldback feature is still used for overcurrent protection. UNDERVOLTAGE LOCKOUT (UVLO) LATCH-OFF PROTECTION Undervoltage lockout circuitry monitors the input voltage level of each buck regulator in the ADP5054. If any input voltage (PVINx pin) falls below 3.79 V (typical), the corresponding channel is turned off. After the input voltage rises above 4.22 V (typical), the soft start period is initiated, and the corresponding channel is enabled when the ENx pin is high. The buck regulators in the ADP5054 have an optional latch-off mode to protect the device from serious problems such as short-circuit conditions. Latch-off mode can be enabled via the factory fuse. Note that a UVLO condition on Channel 1 (PVIN1 pin) has a higher priority than a UVLO condition on other channels, which means that the PVIN1 supply must be available before other channels can be operated. Short-Circuit Latch-Off Mode POWER-GOOD FUNCTION Short-circuit latch-off mode is enabled by the factory fuse. When short-circuit latch-off mode is enabled and the protection circuit detects an overcurrent status after a soft start, the buck regulator enters hiccup mode and attempts to start up again. If seven continuous retry attempts are made and the regulator remains in the fault condition, the regulator is shut down. This shutdown (latch-off) condition is cleared only by reenabling the channel or by resetting the channel power supply. The ADP5054 includes an open-drain power-good output (PWRGD pin) that becomes active high when the Channel 1 buck regulators are operating normally. The operation of short-circuit latch-off protection is shown in Figure 38. OUTPUT VOLTAGE A high status on the PWRGD pin indicates that the regulated output voltage of the buck regulator is above 90.5% (typical) of its nominal output. When the regulated output voltage of the buck regulator falls below 87.2% (typical) of its nominal output for a delay time greater than approximately 50 µs, the status of the PWRGD pin is set low. The PWRGD pin can be programmed by the factory fuse to indicate the outputs of other specific channels. SHORT CIRCUIT DETECTED BY COUNTER OVERFLOW THERMAL SHUTDOWN ATTEMPT TO RESTART SCP LATCH-OFF FUNCTION ENABLED AFTER 7 RETRY ATTEMPTS TIME 7 × tSS LATCH OFF THIS REGULATOR LATCH-OFF Figure 38. Short-Circuit Latch-Off Detection 12617-018 PWRGD If the ADP5054 junction temperature exceeds 150°C, the thermal shutdown (TSD) circuit turns off the IC except for the internal linear regulator. Extreme junction temperatures can be the result of high current operation, poor circuit board design, or high ambient temperature. A 15°C hysteresis is included so that the ADP5054 does not return to operation after thermal shutdown until the on-chip temperature falls below 135°C. When the device exits thermal shutdown, a soft start is initiated for each enabled channel. Note that short-circuit latch-off mode does not work if hiccup detection is disabled. Rev. B | Page 19 of 31 ADP5054 Data Sheet APPLICATIONS INFORMATION ADIsimPOWER DESIGN TOOL The ADP5054 is supported by the ADIsimPower™ design tool set. ADIsimPower is a collection of tools that produces complete power designs optimized for a specific design goal. The tools enable the user to generate a full schematic and bill of materials and to calculate performance in minutes. ADIsimPower can optimize designs for cost, area, efficiency, and part count while taking into consideration the operating conditions and limitations of the IC and all real external components. The ADIsimPower tool can be found at www.analog.com/ADIsimPower; the user can request an unpopulated board through the tool. PROGRAMMING THE OUTPUT VOLTAGE The output voltage of the ADP5054 is externally set by a resistive voltage divider from the output voltage to the FBx pin. To limit the degradation of the output voltage accuracy due to FBx bias current, ensure that the bottom resistor in the divider is not too large; a value of less than 200 kΩ is recommended. The equation for the output voltage setting is VOUT = VREF × (1 + (RTOP/RBOT)) where: VOUT is the output voltage. VREF is the 0.8 V feedback reference voltage. RTOP is the feedback resistor from VOUT to FBx. RBOT is the feedback resistor from FBx to ground. The minimum output voltage in FPWM mode for a given input voltage and switching frequency can be calculated using the following equation: VOUT_MIN = VIN × tMIN_ON × fSW − (RDSON1 − RDSON2) × IOUT_MIN × tMIN_ON × fSW − (RDSON2 + RL) × IOUT_MIN (1) where: VOUT_MIN is the minimum output voltage. tMIN_ON is the minimum on time. fSW is the switching frequency. RDSON1 is the high-side MOSFET on resistance. RDSON2 is the low-side MOSFET on resistance. IOUT_MIN is the minimum output current. RL is the resistance of the output inductor. The maximum output voltage for a given input voltage and switching frequency is limited by the minimum off time and the maximum duty cycle. Note that the frequency foldback feature helps to increase the effective maximum duty cycle by lowering the switching frequency, thereby decreasing the dropout voltage between the input and output voltages (see the Frequency Foldback section). The maximum output voltage for a given input voltage and switching frequency can be calculated using the following equation: VOUT_MAX = VIN × (1 − tMIN_OFF × fSW) − (RDSON1 − RDSON2) × IOUT_MAX × (1 − tMIN_OFF × fSW) − (RDSON2 + RL) × IOUT_MAX (2) No resistor divider is required in the fixed output options. Each channel can be programmed to have a specific output voltage over a specific range (see Table 14). If a different fixed output voltage is required, contact your local Analog Devices sales or distribution representative. VOLTAGE CONVERSION LIMITATIONS For a given input voltage, upper and lower limitations on the output voltage exist due to the minimum on time and the minimum off time. The minimum output voltage for a given input voltage and switching frequency is limited by the minimum on time. The minimum on time for Channel 1 and Channel 2 is 115 ns (typical); the minimum on time for Channel 3 and Channel 4 is 95 ns (typical). The minimum on time increases at higher junction temperatures. Note that in forced PWM mode, Channel 1 and Channel 2 can potentially exceed the nominal output voltage when the minimum on time limit is exceeded. Careful switching frequency selection is required to avoid this problem. where: VOUT_MAX is the maximum output voltage. tMIN_OFF is the minimum off time. fSW is the switching frequency. RDSON1 is the high-side MOSFET on resistance. RDSON2 is the low-side MOSFET on resistance. IOUT_MAX is the maximum output current. RL is the resistance of the output inductor. As shown in Equation 1 and Equation 2, reducing the switching frequency eases the minimum on time and minimum off time limitations. CURRENT-LIMIT SETTING The ADP5054 has three selectable current-limit thresholds for Channel 1 and Channel 2. Ensure that the selected current-limit value is larger than the peak current of the inductor, IPEAK. See Table 10 for the current-limit configurations for Channel 1 and Channel 2. Rev. B | Page 20 of 31 Data Sheet ADP5054 SOFT START SETTING Table 11. Recommended Inductors The buck regulators in the ADP5054 include soft start circuitry that ramps the output voltage in a controlled manner during startup, thereby limiting the inrush current. To set the soft start time to a value of 2 ms or 16 ms, connect a resistor divider from the CFG12 pin or the CFG34 pin to the VREG pin and ground (see the Soft Start section). Vendor Coilcraft INDUCTOR SELECTION The inductor value is determined by the operating frequency, input voltage, output voltage, and inductor ripple current. Using a small inductor yields faster transient response but degrades efficiency due to the larger inductor ripple current. Using a large inductor value yields a smaller ripple current and better efficiency but results in slower transient response. Thus, a trade-off must be made between transient response and efficiency. As a guideline, the inductor ripple current, ΔIL, is typically set to a value from 30% to 40% of the maximum load current. The inductor value can be calculated using the following equation: L = ((VIN − VOUT) × D)/(ΔIL × fSW) WE-HCI Value (µH) 3.3 4.7 6.8 0.8 1.2 2.2 3.3 4.7 1.0 2.2 3.3 4.7 0.76 1.1 2.0 3.3 ISAT (A) 5.5 4.5 3.6 18.5 12.5 9.2 8.7 6.7 11.2 7.1 5.5 4.6 15 13 9 8 IRMS (A) 6.6 5.1 3.9 13 11.1 9.7 8.1 5.9 9.1 7.0 5.3 4.2 15.5 15 11.5 9.0 DCR (mΩ) 26 40.1 67.4 5.14 8.5 13.2 21.2 36 9.4 17.3 29.6 46.6 2.25 3.15 5.85 9.0 Size (mm) 4×4 4×4 4×4 5×5 5 ×5 5× 5 5×5 5×5 6.2 × 5.8 6.2 × 5.8 6.2 × 5.8 6.2 × 5.8 7×7 7×7 7×7 7×7 OUTPUT CAPACITOR SELECTION The selected output capacitor affects both the output voltage ripple and the loop dynamics of the regulator. For example, during load step transients on the output, when the load is suddenly increased, the output capacitor supplies the load until the control loop can ramp up the inductor current, causing an undershoot of the output voltage. where: VIN is the input voltage. VOUT is the output voltage. D is the duty cycle (D = VOUT/VIN). ΔIL is the inductor ripple current. fSW is the switching frequency. The ADP5054 has internal slope compensation in the current loop to prevent subharmonic oscillations when the duty cycle is greater than 50%. The inductor peak current is calculated using the following equation: IPEAK = IOUT + (ΔIL/2) The saturation current of the inductor must be larger than the peak inductor current. For ferrite core inductors with a fast saturation characteristic, the saturation current rating of the inductor must be higher than the current-limit threshold of the buck regulator to prevent the inductor from becoming saturated. The rms current of the inductor can be calculated using the following equation: I RMS = I OUT 2 + TOKO Part No. XFL4030-332 XFL4030-472 XFL4030-682 XFL5030-801 XAL5030-122 XAL5030-222 XAL5030-332 XAL5030-472 FDV0530-1R0 FDV0530-2R2 FDV0530-3R3 FDV0530-4R7 744314076 744314110 744314200 744311330 The output capacitance required to meet the voltage drop. requirement can be calculated using the following equation: COUT _ UV = K UV × ∆I STEP 2 × L 2 × (VIN − VOUT ) × ∆VOUT _ UV where: KUV is a factor (typically set to 2). ΔISTEP is the load step. L is the output inductor. ΔVOUT_UV is the allowable undershoot on the output voltage. Another example of the effect of the output capacitor on the loop dynamics of the regulator is when the load is suddenly removed from the output and the energy stored in the inductor rushes into the output capacitor, causing an overshoot of the output voltage. The output capacitance required to meet the overshoot requirement can be calculated using the following equation: ∆I L 2 12 Shielded ferrite core materials are recommended for low core loss and low electromagnetic interference (EMI). Table 11 lists the recommended inductors. COUT _ OV = (V OUT K OV × ∆I STEP 2 × L + ∆VOUT_OV ) 2 − VOUT 2 where: KOV is a factor (typically set to 2). ΔISTEP is the load step. ΔVOUT_OV is the allowable overshoot on the output voltage. Rev. B | Page 21 of 31 ADP5054 Data Sheet The output voltage ripple is determined by the effective series resistance (ESR) of the output capacitor and its capacitance value. Use the following equations to select a capacitor that can meet the output ripple requirements: COUT _ RIPPLE = R ESR = ∆I L 8 × f SW × ∆VOUT _ RIPPLE When the high-side MOSFET is turned off, the low-side MOSFET supplies the inductor current. For low duty cycle applications, the low-side MOSFET supplies the current for most of the period. To achieve higher efficiency, it is important to select a MOSFET with low on resistance. The power conduction loss for the low-side MOSFET can be calculated using the following equation: ∆VOUT _ RIPPLE PFET_LOW = IOUT2 × RDSON × (1 − D) ∆I L where: ΔVOUT_RIPPLE is the allowable output voltage ripple. RESR is the equivalent series resistance of the output capacitor. Select the largest output capacitance given by COUT_UV, COUT_OV, and COUT_RIPPLE to meet both load transient and output ripple requirements. The selected output capacitor voltage rating must be greater than the output voltage. The minimum rms current rating of the output capacitor is determined by the following equation: I COUT _ RMS = ∆I L 12 where: RDSON is the on resistance of the low-side MOSFET. D is the duty cycle (D = VOUT/VIN). Table 12 lists recommended dual MOSFETs for various currentlimit settings. Ensure that the MOSFET can handle thermal dissipation due to power loss. Table 12. Recommended Dual MOSFETs Vendor Infineon Vishay INPUT CAPACITOR SELECTION The input decoupling capacitor attenuates high frequency noise on the input and acts as an energy reservoir. This capacitor must be a ceramic capacitor and must be placed close to the PVINx pins. The loop composed of the input capacitor, the high-side NFET, and the low-side NFET must be kept as small as possible. The voltage rating of the input capacitor must be greater than the maximum input voltage. The rms current rating of the input capacitor must be larger than the following equation: IC IN _ RMS = IOUT × D × (1 − D ) where D is the duty cycle (D = VOUT/VIN). LOW-SIDE POWER DEVICE SELECTION Channel 1 and Channel 2 have integrated low-side MOSFET drivers, which can drive the low-side N-channel MOSFETs (NFETs). The selection of the low-side N-channel MOSFET affects the buck regulator performance. The selected MOSFET must meet the following requirements: • • • • Fairchild Part No. BSC072N03LD BSO220N03MD Si4204DY Si7232DN SiA906EDJ FDMA1024 FDMB3900 VDS (V) 30 30 20 20 20 20 25 ID (A) 20 7.7 20 25 4.5 5.0 7.0 RDSON (mΩ) 7.2 27 6 16.4 46 54 33 QG (nC) 15 3.8 14.5 12 3.5 5.2 11 Size (mm) 5×6 5×6 5×6 3×3 2×2 2×2 3×2 PROGRAMMING THE UVLO INPUT The precision enable input can be used to program the UVLO threshold of the input voltage, as shown in Figure 29. To limit the degradation of the input voltage accuracy due to the internal 1 MΩ pull-down resistor tolerance, ensure that the bottom resistor in the divider is not too large; a value of less than 50 kΩ is recommended. The precision turn-on threshold is 0.811 V. The resistive voltage divider for the programmable VIN start-up voltage is calculated as follows: VIN_STARTUP = (0.8 nA + (0.811 V/RBOT_EN)) × (RTOP_EN + RBOT_EN) where: RTOP_EN is the resistor from VIN to ENx. RBOT_EN is the resistor from ENx to ground. The drain source voltage (VDS) must be higher than 1.2 × VIN. The drain current (ID) must be greater than 1.2 × ILIMIT_MAX, where ILIMIT_MAX is the selected maximum current-limit threshold. The selected MOSFET can be fully turned on at VGS = 4.5 V. Total gate charge (QG at VGS = 4.5 V) must be less than 35 nC. Lower QG characteristics provide higher efficiency. Rev. B | Page 22 of 31 Data Sheet ADP5054 COMPENSATION COMPONENTS DESIGN For the peak current-mode control architecture, the power stage can be simplified as a voltage controlled current source that supplies current to the output capacitor and load resistor. The simplified loop is composed of one domain pole and a zero contributed by the output capacitor ESR. The control-to-output transfer function is shown in the following equations: fp = 1 4. 2 × π × RESR × COUT 1 2 × π × (R + R ESR ) × COUT AVI CCP – CCP is optional. It can be used to cancel the zero caused by the ESR of the output capacitor. Use the following equation to estimate the power dissipation of the buck regulator: PLOSS = PCOND + PSW + PTRAN RESR Power Switch Conduction Loss (PCOND) 12617-019 Figure 39. Simplified, Peak Current-Mode Control, Small Signal Circuit The compensation components, RC and CC, contribute a zero, and the optional CCP and RC contribute an optional pole. The closed-loop transfer equation is as follows: R × C C × C CP × s s × 1 + C + C C C CP RC The power dissipation (PLOSS) for each buck regulator includes power switch conductive losses (PCOND), switching losses (PSW), and transition losses (PTRAN). Other sources of power dissipation exist, but these sources are generally less significant at the high output currents of the application thermal limit. COUT 1 + RC × C C × s R ESR × C OUT Buck Regulator Power Dissipation CC R BOT −g m × × R BOT + RTOP C C + C CP RC PD = PBUCK1 + PBUCK2 + PBUCK3 + PBUCK4 R RC (R + R ESR ) × COUT The total power dissipation in the ADP5054 simplifies to RTOP + Place the compensation zero at the domain pole (fP). CC can be determined as follows: POWER DISSIPATION VOUT VCOMP 2 × π × VOUT × COUT × fC 0.8 V × g m × AVI C CP = VOUT – gm + Determine the cross frequency (fC). Generally, fC is between fSW/12 and fSW/6. RC can be calculated using the following equation: CC = The ADP5054 uses a transconductance amplifier as the error amplifier to compensate the system. Figure 39 shows the simplified, peak current-mode control, small signal circuit. TV (s) = 2. 3. where: AVI = 20 A/V for Channel 1 or Channel 2, and 6.66 A/V for Channel 3 or Channel 4. R is the load resistance. RESR is the equivalent series resistance of the output capacitor. COUT is the output capacitance. RBOT 1. RC = s 1 + 2 f × π × VOUT (s) z Gvd (s) = = AVI × R × VCOMP (s) s 1 + 2 f × π × p fz = The following guidelines show how to select the compensation components (RC, CC, and CCP) for ceramic output capacitor applications. × G vd (s) Power switch conduction losses are caused by the flow of output current through both the high-side and low-side power switches, each of which has its own internal on resistance (RDS(ON)). Use the following equation to estimate the power switch conduction loss: PCOND = (RDS(ON)_HS × D + RDS(ON)_LS × (1 − D)) × IOUT2 where: RDS(ON)_HS is the high-side MOSFET on resistance. RDS(ON)_LS is the low-side MOSFET on resistance. D is the duty cycle (D = VOUT/VIN). Rev. B | Page 23 of 31 ADP5054 Data Sheet Switching Loss (PSW) JUNCTION TEMPERATURE Switching losses are associated with the current drawn by the driver to turn the power devices on and off at the switching frequency. Each time a power device gate is turned on or off, the driver transfers a charge from the input supply to the gate, and then from the gate to ground. Use the following equation to estimate the switching loss: The junction temperature of the die is the sum of the ambient temperature of the environment and the temperature rise of the package due to power dissipation, as shown in the following equation: PSW = (CGATE_HS + CGATE_LS) × VIN2 × fSW where: CGATE_HS is the gate capacitance of the high-side switch. CGATE_LS is the gate capacitance of the low-side switch. fSW is the switching frequency. Transition Loss (PTRAN) Transition losses occur because the high-side switch cannot turn on or off instantaneously. During a switch node transition, the power switch provides all the inductor current. The sourceto-drain voltage of the power switch is half the input voltage, resulting in power loss. Transition losses increase with both load and input voltage and occur twice for each switching cycle. Use the following equation to estimate the transition loss: PTRAN = 0.5 × VIN × IOUT × (tR + tF) × fSW where: tR is the rise time of the switch node. tF is the fall time of the switch node. Thermal Shutdown Channel 1 and Channel 2 store the value of the inductor current only during the on time of the internal high-side MOSFET. Therefore, a small amount of power (as well as a small amount of input rms current) is dissipated inside the ADP5054, which reduces thermal constraints. TJ = TA + TR where: TJ is the junction temperature. TA is the ambient temperature. TR is the rise in temperature of the package due to power dissipation. The rise in temperature of the package is directly proportional to the power dissipation in the package. The proportionality constant for this relationship is the thermal resistance from the junction of the die to the ambient temperature, as shown in the following equation: TR = θJA × PD where: θJA is the thermal resistance from the junction of the die to the ambient temperature of the package (see Table 5). PD is the power dissipation in the package. An important factor to consider is that the thermal resistance value is based on a 4-layer, 4 inch × 3 inch PCB with 2.5 oz of copper, as specified in the JEDEC standard, whereas real-world applications may use PCBs with different dimensions and a different number of layers. It is important to maximize the amount of copper used to remove heat from the device. Copper exposed to air dissipates heat better than copper used in the inner layers. The exposed pad must be connected to the ground plane with several vias. However, when Channel 1 and Channel 2 are operating under maximum load with high ambient temperature and high duty cycle, the input rms current can become very large and cause the junction temperature to exceed the absolute maximum rating of 125°C. If the junction temperature exceeds 150°C, the regulator enters thermal shutdown and recovers when the junction temperature falls below 135°C. Rev. B | Page 24 of 31 Data Sheet ADP5054 DESIGN EXAMPLES This section provides an example of the step-by-step design procedures and the external components required for Channel 1. Table 13 lists the design requirements for this example. Table 13. Example Design Requirements for Channel 1 Parameter Input Voltage Output Voltage Output Current Output Ripple Load Transient Specification VPVIN1 = 12 V ± 5% VOUT1 = 1.2 V IOUT1 = 4 A ΔVOUT1_RIPPLE = 12 mV in CCM mode ±5%, at 20% to 80% load transient, 1 A/µs Although this example shows step-by-step design procedures for Channel 1, the procedures also apply to all other buck regulator channels (Channel 2 to Channel 4). SETTING THE SWITCHING FREQUENCY The first step is to determine the switching frequency for the ADP5054 design. In general, higher switching frequencies produce a smaller solution size due to the lower component values required, whereas lower switching frequencies result in higher conversion efficiency due to lower switching losses. The switching frequency of the ADP5054 can be set to a value from 250 kHz to 2 MHz by connecting a resistor from the RT pin to ground. The selected resistor allows users to make decisions based on the trade-off between efficiency and solution size. (For more information, see the Oscillator section.) However, the highest supported switching frequency must be assessed by checking the voltage conversion limitations enforced by the minimum on time and the minimum off time (see the Voltage Conversion Limitations section). In this design example, a switching frequency of 600 kHz is used to achieve a good combination of small solution size and high conversion efficiency. To set the switching frequency to 600 kHz, use the following equation to calculate the resistor value, RRT: RRT (kΩ) = [14,822/fSW (kHz)]1.081 Therefore, select standard resistor RRT = 31.6 kΩ. SETTING THE OUTPUT VOLTAGE Select a 10 kΩ bottom resistor (RBOT) and then calculate the top feedback resistor using the following equation: RBOT = RTOP × (VREF/(VOUT − VREF)) where: VOUT is the output voltage. VREF is 0.8 V for Channel 1 to Channel 4, and 0.5 V for Channel 5. SETTING THE CURRENT LIMIT For 4 A output current operation, the typical peak current limit is 6.9 A. For this example, choose RILIM1 = floating (see Table 10). For more information, see the Current-Limit Protection section. SELECTING THE INDUCTOR The peak-to-peak inductor ripple current, ΔIL, is set to 35% of the maximum output current. Use the following equation to estimate the value of the inductor: L= (VIN − VOUT ) × D ∆I L × f SW where: VIN = 12 V. VOUT = 1.2 V. D is the duty cycle (D = VOUT/VIN = 0.1). ΔIL = 35% × 4 A = 1.4 A. fSW = 600 kHz. The resulting value for L1 is 1.28 µH. The closest standard inductor value is 1.5 µH; therefore, the inductor ripple current, ΔIL1, is 1.2 A. The inductor peak current is calculated using the following equation: IPEAK = IOUT + (ΔIL/2) The calculated peak current for the inductor is 4.6 A. The rms current of the inductor can be calculated using the following equation: I RMS = I OUT 2 + ∆I L 2 12 The rms current of the inductor is approximately 4.02 A. Therefore, an inductor with a minimum rms current rating of 4.02 A and a minimum saturation current rating of 4.6 A is required. However, to prevent the inductor from reaching its saturation point in current-limit conditions, it is recommended that the inductor saturation current be higher than the maximum peak current limit, typically 6 A, for reliable operation. Based on these requirements and recommendations, the Coilcraft XAL5030-122, with a DCR of 8.5 mΩ, is selected for this design. To set the output voltage to 1.2 V, choose the following resistor values: RTOP1 = 4.99 kΩ, RBOT1 = 10 kΩ. Rev. B | Page 25 of 31 ADP5054 Data Sheet SELECTING THE OUTPUT CAPACITOR The output capacitor must meet the output voltage ripple and load transient requirements. To meet the output voltage ripple requirement, use the following equations to calculate the ESR and capacitance: Choose standard components: RC = 5.6 kΩ and CC = 4.7 nF. CCP is optional. Figure 40 shows the bode plot for the 1.2 V output rail. The cross frequency is 64 kHz, and the phase margin is 65°. ∆I L MAGNITUDE (dB) The calculated capacitance, COUT_RIPPLE, is 20.8 µF, and the calculated ESR, RESR, is 10 mΩ. To meet the ±5% overshoot and undershoot requirements, use the following equations to calculate the capacitance: COUT _ OV = K UV × ∆I STEP 2 × L 2 × (VIN − VOUT ) × ∆VOUT _ UV (V K OV × ∆I STEP 2 × L OUT = 16.6 pF Figure 41 shows the load transient waveform. ∆VOUT_RIPPLE COUT _ UV = 5.77 kΩ + ∆VOUT_OV ) 2 − VOUT 2 120 120 100 100 80 80 60 60 40 40 20 20 0 0 –20 –20 –40 –40 –60 –60 –80 –80 –100 –120 For estimation purposes, use KOV = KUV = 2; therefore, COUT_OV = 117 µF and COUT_UV = 13.3 µF. –100 CROSS FREQUENCY: 64kHz PHASE MARGIN: 65° 1k 10k PHASE (Degrees) R ESR = 8 × f SW ∆I L × ∆VOUT_RIPPLE 0.001 Ω × 3 × 32 μF –120 100k 1M FREQUENCY (Hz) 12617-140 C OUT_RIPPLE = CCP = Figure 40. Bode Plot for 1.2 V Output The ESR of the output capacitor must be less than 13.3 mΩ, and the output capacitance must be greater than 117 µF. It is recommended that three ceramic capacitors be used (47 µF, X5R, 6.3 V), such as the GRM21BR60J476ME15 from Murata with an ESR of 2 mΩ. SELECTING THE LOW-SIDE MOSFET It is recommended that a 20 V, dual N-channel MOSFET (such as the Si4204DY from Vishay) be used for both Channel 1 and Channel 2. The RDS(ON) of the Si4204DY at a 4.5 V driver voltage is 6 mΩ, and the total gate charge is 14.5 nC. DESIGNING THE COMPENSATION NETWORK For better load transient and stability performance, set the cross frequency, fC, to fSW/10. In this example, fSW is set to 600 kHz; therefore, fC is set to 60 kHz. For the 1.2 V output rail, the 47 µF ceramic output capacitor has a derated value of 32 µF. RC = CC = 2 × π × 1.2 V × 3 × 32 μF × 60 kHz 0.8 V × 470 μs × 20 A/V (0.3 Ω + 0.001 Ω)× 3 × 32 μF 5.77 kΩ = 5.77 kΩ = 5.01 nF 12617-141 A low RDS(ON) N-channel MOSFET must be selected for high efficiency solutions. The MOSFET breakdown voltage must be greater than 1.2 × VIN, and the drain current must be greater than 1.2 × ILIMIT. Figure 41. 0.8 A to 3.2 A Load Transient Waveform for 1.2 V Output SELECTING THE SOFT START TIME The soft start feature allows the output voltage to ramp up in a controlled manner, eliminating output voltage overshoot during soft start and limiting the inrush current. The CFG12 pin can be used to program a soft start time of 2 ms or 16 ms and can also be used to configure parallel operation of Channel 1 and Channel 2. For more information, see the Soft Start section and Table 8. SELECTING THE INPUT CAPACITOR For the input capacitor, select a ceramic capacitor with a minimum value of 10 µF; place the input capacitor close to the PVINx pin. In this example, one ceramic capacitor of 10 µF, X5R, 25 V is recommended. Rev. B | Page 26 of 31 Data Sheet ADP5054 PRINTED CIRCUIT BOARD LAYOUT RECOMMENDATIONS Good circuit board layout is essential to obtain the best performance from the ADP5054 (see Figure 43). Poor layout can affect the regulation and stability of the device, as well as the EMI and electromagnetic compatibility (EMC) performance. Refer to the following guidelines for a good PCB layout. • • • • BSTx VOUT SWx DLx FBx 12617-022 ENx GND Figure 42. Typical Circuit with High Current Traces Shown in Blue VOUT1 100µF 00µF 6.3V/XR5 3V/XR5 1206 R0402 C0402 R0402 1 µF 0402 6 .3 V /X R 5 1 µF 0402 CINx - 10µF 25V/XR 5 0805 0402 0 . 1 µF 6 .3 V /X R 5 VOUT3 6 .3 V /X R 5 R 0402 R0402 C0402 CO UTx - 47µF 6.3V/X5R 0805 R 0402 L1 CO UTx - 47µF 6.3V/X5R 0805 R0402 100µF 00µF 6.3V/XR5 3V/XR5 1206 R0402 EN1 PVIN1 PVIN1 PVIN 1 P 36 2 PG ND D3 SW 1 35 3 PG ND 3 SW 1 34 4 SW 3 SW 1 33 5 SW 3 BST1 B 32 6 PVIN 3 N3 DL1 31 7 PVIN4 4 PG ND 30 8 SW 4 DL2 29 R0402 CO M P1 0402 38 PG ND 4 D4 SW 2 26 12 BST4 SW 2 25 R0402 27 11 0402 28 SW 2 0 . 1 µF BST2 B PG ND4 6 .3 V /X R 5 SW 4 S1 9 10 Dual D l FET D1 CINx - 10µF 25V/X5R 0805 ADP5054 PVIN2 PVIN 2 PVIN2 100µF 10 6.3V/XR5 6.3V 1206 1 19 EN2 23 18 CO M P2 24 FB2 21 CFG 12 22 PW RG D 20 FB 4 17 14 CO M P4 C 0402 R 0402 R 0402 C 0402 0402 0 . 1 µF CO UTx UT - 47µF 47 F 6.3V/X5R 0805 6 .3 V /X R 5 13 EN4 16 CFG 34 15 D1 L4 CO UTx - 47µF 6.3V/X5R 0805 R0402 R 0402 R0402 VOUT2 12617-043 CO UTx - 47µF 6.3V/X5R 6 3V/X / 5R 0805 R 0402 L2 CINx - 10µF 25V/XR5 0805 VOUT4 100µF 10 6.3V/XR5 6.3V 1206 1 FB 1 37 RT 40 VDD 39 SYNC/ M O DE 42 43 VREG 41 45 46 FB 3 44 47 CO M P3 BST3 3 0 . 1 µF CINx - 10µF 25V/X5R 25V/ V / X 5R 0805 EN3 1 6 .3 V /X R 5 L3 48 CO UTx - 47µF 6.3V/X5R 0805 G1 • PVINx D2 • VIN S2 • • D2 • Place the input capacitor, inductor, MOSFET, output capacitor, and bootstrap capacitor close to the IC. Use short, thick traces to connect the input capacitors to the PVINx pins, and use a dedicated power ground to connect the input and output capacitor grounds to minimize the connection length. Use several high current vias, if required, to connect PVINx, PGNDx, or SWx to other power planes. Use short, thick traces to connect the inductors to the SWx pins and the output capacitors. Ensure that the high current loop traces are as short and wide as possible. The high current path is shown in Figure 42. Maximize the amount of ground metal for the exposed pad, and use as many vias as possible on the component side to improve thermal dissipation. G2 • • Use a ground plane with several vias connecting to the component side ground to further reduce noise interference on sensitive circuit nodes. Place the decoupling capacitors close to the VREG and VDD pins. Place the frequency setting resistor close to the RT pin. Place the feedback resistor divider close to the FBx pin. In addition, keep the FBx traces away from the high current traces and the switch node to avoid noise pickup. Use 0402 or 0603 size resistors and capacitors to achieve the smallest possible footprint solution on boards where space is limited. Figure 43. Typical PCB Layout for the ADP5054 Rev. B | Page 27 of 31 ADP5054 Data Sheet TYPICAL APPLICATION CIRCUIT ADP5054 5.0V VREG INTERNAL VREG 100mA VDD C0 1µF C1 1µF VREG SYNC/MODE OSCILLATOR 10Ω RT 31.6kΩ FB1 COMP1 10kΩ EN1 VREG DL2 SW2 C8 10µF PVIN2 COMP2 PWRGD PVIN3 C12 10µF COMP3 2.2nF 10kΩ EN3 Q2 L2 VREG BST2 SELECTIVE 10kΩ EN2 CHANNEL 2 BUCK (2A/4A/6A) VOUT1 1.2V/6A FPGA Q1 PGND FPGA L1 1.0µH DL1 CFG12 2.2nF C3 0.1µF 22kΩ 2.2nF 4.99Ω SW1 CHANNEL 1 BUCK (2A/4A/6A) C4 47µF C5 47µF C6 47µF C7 47µF 47kΩ C2 10µF BST1 S17232DN (16.4mΩ) PVIN1 12V C9 0.1µF 4.7µF 10.2kΩ 21.5kΩ 2.5V/2A VOUT2 C10 47µF BANK 0 FPGA BANK 1 BANK 2 C11 47µF FB2 BST3 SW3 CHANNEL 3 BUCK (2A) FB3 PGND3 C14 0.1µF L3 3.3µF 10.2kΩ 8.87kΩ VOUT3 C13 47µF CFG34 AUXILIARY VOLTAGE 1.5V/2.5A DDR TERM. LDO I/O BANK 3 DDR3 MEMORY BST4 SW4 C15 2.2nF COMP4 10kΩ EN4 CHANNEL 4 BUCK (2A) FB4 PGND4 C16 0.1µF L4 4.7µF 10.2kΩ 31.6kΩ VOUT4 3.3V/2.5A FLASH MEMORY C17 47µF 12617-044 PVIN4 C15 10µF EXPOSED PAD Figure 44. Typical Field Programmable Gate Array (FPGA) Application, 600 kHz Switching Frequency, Adjustable Output Model Rev. B | Page 28 of 31 Data Sheet ADP5054 FACTORY PROGRAMMABLE OPTIONS Table 14 list the options that can be programmed into the ADP5054 when it is ordered from Analog Devices. For a list of the default options, see Table 19. To order a device with options other than the default options, contact your local Analog Devices sales or distribution representative. Table 14. Output Voltage Options for Channel 1 to Channel 4 Options Option 0 Option 1 Option 2 Option 3 Option 4 Option 5 Option 6 Option 7 Option 8 Option 9 Option 10 Option 11 Option 12 Option 13 Option 14 Option 15 Description 0.8 V adjustable output (default) 0.90 V fixed output 0.95 V fixed output 1.00 V fixed output 1.05 V fixed output 1.10 V fixed output 1.15 V fixed output 1.20 V fixed output 1.25 V fixed output 1.30 V fixed output 1.50 V fixed output 1.80 V fixed output 2.50 V fixed output 2.85 V fixed output 3.3 V fixed output 5.0 V fixed output Table 15. PWRGD Output Options Options Option 0 Option 1 Option 2 Option 3 Option 4 Option 5 Option 6 Option 7 Option 8 Option 9 Option 10 Option 11 Option 12 Option 13 Option 14 Option 15 Description No monitoring of any channel Monitor Channel 1 output (default) Monitor Channel 2 output Monitor Channel 1 and Channel 2 outputs Monitor Channel 3 output Monitor Channel 1 and Channel 3 outputs Monitor Channel 2 and Channel 3 outputs Monitor Channel 1, Channel 2, and Channel 3 outputs Monitor Channel 4 output Monitor Channel 1 and Channel 4 outputs Monitor Channel 2 and Channel 4 outputs Monitor Channel 1, Channel 2, and Channel 4 outputs Monitor Channel 3 and Channel 4 outputs Monitor Channel 1, Channel 3, and Channel 4 outputs Monitor Channel 2, Channel 3, and Channel 4 outputs Monitor Channel 1, Channel 2, Channel 3, and Channel 4 outputs Table 16. Output Discharge Functionality Options Options Option 0 Option 1 Description Output discharge function disabled for all four buck regulators Output discharge function enabled for all four buck regulators (default) Table 17. Hiccup Detection Options for the Four Buck Regulators Options Option 0 Option 1 Description Hiccup protection enabled for overcurrent events (default) Hiccup protection disabled; frequency foldback protection only for overcurrent events Rev. B | Page 29 of 31 ADP5054 Data Sheet Table 18. Short-Circuit Latch-Off Options for the Four Buck Regulators Options Option 0 Option 1 Description Latch-off function disabled for output short-circuit events (default) Latch-off function enabled for output short-circuit events FACTORY DEFAULT OPTIONS Table 19 lists the factory default options programmed into the ADP5054 when the device is ordered (see the Ordering Guide). To order the device with options other than the default options, contact your local Analog Devices sales or distribution representative. Table 14 through Table 18 list all available options for the device. Table 19. Factory Default Options Option Channel 1 Output Voltage Channel 2 Output Voltage Channel 3 Output Voltage Channel 4 Output Voltage PWRGD Pin (Pin 17) Output Output Discharge Function Hiccup Detection Short-Circuit Latch-Off Default Value 0.8 V adjustable output 0.8 V adjustable output 0.8 V adjustable output 0.8 V adjustable output Monitor Channel 1 output Enabled for all four buck regulators Hiccup protection enabled for overcurrent events Disabled for all four buck regulators Rev. B | Page 30 of 31 Data Sheet ADP5054 OUTLINE DIMENSIONS 7.10 7.00 SQ 6.90 0.30 0.25 0.20 PIN 1 INDICATOR 37 36 48 1 0.50 BSC EXPOSED PAD PIN 1 INDICATOR 5.70 5.60 SQ 5.50 25 12 0.80 0.75 0.70 13 24 BOTTOM VIEW 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.203 REF PKG-004361 SEATING PLANE 0.20 MIN 5.50 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220 12-03-2013-A TOP VIEW 0.50 0.40 0.30 Figure 45. 48-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 7 mm × 7 mm Body, Very Very Thin Quad with Fused Leads (CP-48-16) Dimensions shown in millimeters ORDERING GUIDE Model1 ADP5054ACPZ-R7 ADP5054-EVALZ 1 2 Temperature Range −40°C to +125°C Package Description 48-Lead Lead Frame Chip Scale Package [LFCSP_WQ] Evaluation Board Package Option2 CP-48-16 Z = RoHS Compliant Part. Table 19 lists the factory default options for the device. For a list of factory programmable options, see the Factory Programmable Options section. To order a device with options other than the default values, contact your local Analog Devices sales or distribution representative. ©2015 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D12617-0-9/15(B) Rev. B | Page 31 of 31