ACPL-064L, ACPL-M61L, ACPL-W61L, ACPL-K64L Low-Power 10-MBd Digital CMOS Optocouplers Data Sheet Description Features The low-power ACPL-x6xL digital optocouplers combine an AlGaAs light emitting diode (LED) and an integrated high gain photodetector. The optocoupler consumes low power, at maximum 1.3 mA IDD current per channel across temperature. With a forward LED current as low as 1.6 mA, most microprocessors can directly drive the LED. An internal Faraday shield provides a guaranteed common-mode transient immunity specification of 20 kV/μs. Maximum AC and DC circuit isolation is achieved while maintaining TTL/CMOS compatibility. The optocouplers' CMOS outputs are slew-rate controlled and designed to allow the rise and fall time to be controlled over a wide load-capacitance range. The ACPL-x6xL series operates from both 3.3V and 5V supply voltages with guaranteed AC and DC performance from –40°C to +105°C. Low IDD current: 1.3 mA/channel maximum Low input current: 1.6 mA Built-in slew-rate controlled outputs 20 kV/μs minimum Common-Mode Rejection (CMR) at VCM = 1000V High speed: 10 MBd minimum Guaranteed AC and DC performance over wide temperature: –40°C to +105°C Wide package selection: SO-5, SO-8, stretched SO-6, and stretched SO-8 Safety approval — UL 1577 recognized: 3750Vrms for 1 minute for ACPL-064L/M61L and 5000Vrms for 1 minute for ACPL-W61L/K64L — CSA approval — IEC/EN/DIN EN 60747-5-5 approval for Reinforced Insulation RoHS-compliant These low-power optocouplers are suitable for high speed logic interface applications. Functional Diagrams Applications 6 Anode Cathode ACPL-064L/K64L ACPL-M61L VDD Anode1 1 8 VDD Cathode1 2 7 Vo1 Cathode2 3 6 Vo2 Anode2 4 5 GND 1 5 Vo 4 GND 3 CAUTION ACPL-W61L Anode 1 6 VDD NC* 2 5 Vo Cathode 3 4 GND SHIELD SHIELD Communication interfaces: RS485, CANBus, and I2C Microprocessor system interfaces Digital isolation for A/D and D/A converters TRUTH TABLE (POSITIVE LOGIC) LED OUTPUT ON L OFF H A 0.1 μF bypass capacitor must be connected between pins VDD and GND. Broadcom -1- It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD. The components featured in this data sheet are not to be used in military or aerospace applications or environments. ACPL-064L, ACPL-M61L, ACPL-W61L, ACPL-K64L Data Sheet Ordering Information The ACPL-064L and ACPL-M61L are UL recognized with an isolation voltage of 3750Vrms for 1 minute per UL1577. The ACPL-W61L and ACPL-K64L are UL recognized with an isolation voltage of 5000Vrms for 1 minute per UL1577. All devices are RoHS-compliant. Part Number ACPL-M61L Option RoHS-Compliant Package -000E SO-5 -500E X X X X -000E SO-8 X X X X -500E -560E -000E -060E Stretched S08 X 1500 per reel 100 per tube -500E Stretched S06 100 per tube 1500 per reel X X -060E ACPL-K64L X -060E -000E Quantity 100 per tube X -560E ACPL-W61L X -060E -560E ACPL-064L UL1577 5000 IEC/EN/DIN EN Surface Mount Tape and Reel Vrms /1 Minute 60747-5-5 Rating X 1500 per reel X X X X X X X X X 100 per tube 100 per tube X X X X X X X -500E X X X -560E X X X 1500 per reel 100 per tube 1000 per reel X 1000 per reel 80 per tube X 80 per tube 1000 per reel X 1000 per reel To form an ordering part number, choose a part number from the part number column and combine it with the desired option from the RoHS option column. Example: Part number ACPL-M61L-560E describes an optocoupler with a surface mount SO-5 package; delivered in Tape and Reel with 1500 parts-per-reel; with IEC/EN/DIN EN 60747-5-5 Safety Approval; and full RoHS compliance. Option data sheets are available. Contact your Broadcom sales representative or authorized distributor for information. Broadcom -2- ACPL-064L, ACPL-M61L, ACPL-W61L, ACPL-K64L Data Sheet Package Outline Drawings ACPL-064L SO-8 Package LAND PATTERN RECOMMENDATION 1.91 (0.075) 0.64 (0.025) 3.937 ± 0.127 (0.155 ± 0.005) 8 7 6 5 NNNN Z YYWW EEE DEVICE PART NUMBER LEAD-FREE • PIN 1 1 2 3 TEST RATING CODE LOT ID 4 0.406 ± 0.076 (0.016 ± 0.003) 3.95 (0.156) DATE CODE 5.994 ± 0.203 (0.236 ± 0.008) 1.270 BSC (0.050) 1.27 (0.5) * 5.080 ± 0.127 (0.200 ± 0.005) 3.175 ± 0.127 (0.125 ± 0.005) 7.49 (0.295) 0.432 45° X (0.017) 7° 0 ~ 7° 1.524 (0.060) 0.228 ± 0.025 (0.009 ± 0.001) 0.203 ± 0.102 (0.008 ± 0.004) 0.305 MIN. (0.012) * Total package length (inclusive of mold flash) 5.207 ± 0.254 (0.205 ± 0.010) Dimensions in Millimeters (Inches). Note: Floating lead protrusion is 0.15 mm (6 mils) max. Lead coplanarity = 0.10 mm (0.004 inches) max. Option number 500 not marked. ACPL-M61L SO-5 Package LAND PATTERN RECOMMENDATION 0.33 (0.013) DEVICE PART NUMBER 4.4 ± 0.1 (0.173 ± 0.004) LEAD FREE NNNN Z • YYWW EEE 0.64 (0.025) 1.27 (0.05) TEST RATING CODE 7.0 ± 0.2 (0.276 ± 0.008) DATE CODE 4.39 (0.17) 8.26 (0.325) LOT ID PIN 1 DOT 1.80 (0.071) 0.4 ± 0.05 (0.016 ± 0.002) 2.54 (0.10) 3.6 ± 0.1* (0.142 ± 0.004) 2.5 ± 0.1 (0.098 ± 0.004) 0.102 ± 0.102 (0.004 ± 0.004) 1.27 BSC (0.050) Dimensions in millimeters (inches). Note: Foating Lead Protrusion is 0.15 mm (6 mils) max. * Maximum Mold flash on each side is 0.15 mm (0.006). 0.15 ± 0.025 (0.006 ± 0.001) 7° MAX. 0.71 MIN (0.028) MAX. LEAD COPLANARITY = 0.102 (0.004) Broadcom -3- ACPL-064L, ACPL-M61L, ACPL-W61L, ACPL-K64L Data Sheet ACPL-W61L Stretched SO-6 Package 4.580±0.254 (0.180±0.010) LAND PATTERN RECOMMENDATION 1.27 (0.050) BSG 12.65 (0.498) 6 5 4 RoHS-COMPLIANCE INDICATOR 0.76 (0.030) PART NUMBER NNNN DATE CODE YYWW EEE Lot ID 1.91 (0.075) 1 2 3 +0.127 0 +0.005 0.268 - 0.000 6.807 0.381±0.127 (0.015±0.005) ( 7° 7° 0.45 (0.018) ) 1.590±0.127 (0.063±0.005) 45° 3.180±0.127 (0.125±0.005) 0.20±0.10 (0.008±0.004) Dimensions in Millimeters (Inches). Lead coplanarity = 0.1 mm (0.004 inches). 0.750±0.250 (0.0295±0.010) 11.50±0.250 (0.453±0.010) ACPL-K64L Stretched SO-8 Package 5.850±0.254 (0.230±0.010) 8 7 6 LAND PATTERN RECOMMENDATION 5 PART NUMBER RoHS-COMPLIANCE INDICATOR DATE CODE NNNN Lot ID YYWW EEE 6.807±0.127 (0.268±0.005) 1.905 (0.1) 12.650 (0.5) 1 2 3 4 0.450 (0.018) 7° 7° 1.590±0.127 (0.063±0.005) 45° 3.180±0.127 (0.125±0.005) 1.270 (0.050) BSG 0.381±0.13 (0.015±0.005) Dimensions in Millimeters (Inches). Lead coplanarity = 0.1 mm (0.004 inches). 0.254±0.100 (0.010±0.004) 0.750±0.250 (0.0295±0.010) 11.5±0.250 (0.453±0.010) Broadcom -4- ACPL-064L, ACPL-M61L, ACPL-W61L, ACPL-K64L Data Sheet Reflow Soldering Profile The recommended reflow soldering conditions are per JEDEC Standard J-STD-020 (latest revision). Non-halide flux should be used. Regulatory Information The ACPL-064L, ACPL-M61L, ACPL-W61L, and ACPL-K64L are approved by the following organizations: IEC/EN/DIN EN 60747-5-5 (Option 060 only) UL — Approval under UL 1577 component recognition program up to VISO = 3750Vrms for the ACPL-M61L/064L and VISO = 5000Vrms for the ACPL-W61L/K64L File E55361. CSA — Approval under CSA Component Acceptance Notice #5, File CA 88324. Insulation and Safety Related Specifications Symbol ACPL-064L ACPL-M61L ACPL-W61L ACPL-K64L Unit Minimum External Air Gap (External Clearance) L(101) 4.9 5 8 mm Measured from input terminals to output terminals, shortest distance through air. Minimum External Tracking (External Creepage) L(102) 4.8 5 8 mm Measured from input terminals to output terminals, shortest distance path along body. 0.08 0.08 0.08 mm Through insulation distance conductor to conductor, usually the straight line distance thickness between the emitter and detector. 175 175 175 V IIIa IIIa IIIa Parameter Minimum Internal Plastic Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) Isolation Group CTI Broadcom -5- Conditions DIN IEC 112/VDE 0303 Part 1. Material Group (DIN VDE 0110, 1/89, Table 1) ACPL-064L, ACPL-M61L, ACPL-W61L, ACPL-K64L Data Sheet IEC/EN/DIN EN 60747-5-5 Insulation Characteristicsa (Option 060) Characteristic Description Symbol Unit ACPL-064L/ ACPL-M61L ACPL-W61L/ ACPL-K64L I – IV I – IV I – III I – IV I – IV I – IV I – III 55/105/21 55/105/21 2 2 VIORM 567 1140 Vpeak Input to Output Test Voltage, Method ba VIORM x 1.875 = VPR, 100% Production Test with tm = 1 sec, Partial discharge < 5 pC VPR 1063 2137 Vpeak Input to Output Test Voltage, Method aa VIORM x 1.6 = VPR, Type and Sample Test, tm = 10 sec, Partial discharge < 5 pC VPR 907 1824 Vpeak VIOTM 6000 8000 Vpeak TS IS, INPUT PS, OUTPUT 150 150 600 175 230 600 °C mA mW RS >109 >109 Ω Installation classification per DIN VDE 0110/39, Table 1 for rated mains voltage ≤ 150Vrms for rated mains voltage ≤ 300Vrms for rated mains voltage ≤ 600Vrms for rated mains voltage ≤ 1000Vrms Climatic Classification Pollution Degree (DIN VDE 0110/39) Maximum Working Insulation Voltage Highest Allowable Overvoltage (Transient Overvoltage tini = 60 sec) Safety-Limiting Values – maximum values allowed in the event of a failure Case Temperature Input Current b Output Powerb Insulation Resistance at TS, VIO = 500V a. Refer to the optocoupler section of the Isolation and Control Components Designer’s Catalog, under Product Safety Regulations section, (IEC/EN/DIN EN 60747-5-5) for a detailed description of Method a and Method b partial discharge test profiles. b. Refer to the following figures for dependence of PS and IS on ambient temperature: Surface Mount SO-8 Product Surface Mount SSO-6/SSO-8 Product 700 PS (mW) IS (mA) POWER OUTPUT – PS, INPUT CURRENT – IS POWER OUTPUT – PS, INPUT CURRENT – IS 1000 800 600 400 200 0 PS (mW) IS (mA) 600 500 400 300 200 100 0 0 NOTE 25 50 75 100 125 150 TS – CASE TEMPERATURE (°C) 175 0 25 50 75 100 125 150 TS – CASE TEMPERATURE (°C) 175 200 These optocouplers are suitable for safe electrical isolation only within the safety limit data. Maintenance of the safety data shall be ensured by means of protective circuits. Broadcom -6- ACPL-064L, ACPL-M61L, ACPL-W61L, ACPL-K64L Data Sheet Absolute Maximum Ratings Parameter Symbol Min Max Unit Storage Temperature TS –55 +125 °C Operating Temperature TA –40 +105 °C Reverse Input Voltage VR — 5 V VDD — 6.5 V IF — 8 mA IF(TRAN) — 1 A 80 mA Supply Voltage Average Forward Input Current Peak Forward Input Current (IF at 1 μs pulse width, <10% duty cycle) Output Current IO — 10 mA Output Voltage VO –0.5 VDD + 0.5 V Input Power Dissipation PI — 14 mW Output Power Dissipation PO — 20 mW Lead Solder Temperature TLS — Condition ≤1-μs Pulse Width, <300 pulses/second ≤1-μs Pulse Width, <10% Duty Cycle 260°C for 10 sec., 1.6 mm below seating plane Solder Reflow Temperature Profile See Package Outline Drawings section. Recommended Operating Conditions Parameter Symbol Min Max Unit Operating Temperature TA –40 +105 °C Input Current, Low Level IFL 0 250 μA Input Current, High Level IFH 1.6 6.0 mA Power Supply Voltage VDD 2.7 5.5 V Forward Input Voltage VF (OFF) — 0.8 V Broadcom -7- ACPL-064L, ACPL-M61L, ACPL-W61L, ACPL-K64L Data Sheet Electrical Specifications (DC) Over the recommended temperature (TA = –40°C to +105°C) and supply voltage (2.7V ≤ VDD ≤ 5.5V). All typical specifications are at VDD = 5V and TA = 25°C. Parameter Symbol Channel Min Typ Max Unit Test Conditions Input Forward Voltage VF 0.95 1.3 1.7 V IF = 2 mA; Figure 1 and Figure 2 Input Reverse Breakdown Voltage BVR 3 5 — V IR = 10 μA Logic High Output Voltage VOH VDD – 0.1 VDD — V IF = 0 mA, VI = 0V (RT = 1.68 kΩ) or (RT = 870Ω), IO = –20 μA VDD – 1.0 VDD — V IF = 0 mA, VI = 0V (RT = 1.68 kΩ) or (RT = 870Ω), IO = –3.2 mA — 0.03 0.1 V IF = 2 mA, VI = 5V (RT = 1.68 kΩ) or VI = 3.3V (RT = 870Ω), IO = 20 μA — 0.18 0.4 V IF = 2 mA, VI = 5V (RT = 1.68 kΩ) or VI = 3.3V (RT = 870Ω), IO = 3.2 mA — 0.7 1.3 mA Figure 3 Single — 0.8 1.3 mA Figure 4 Dual — 1.6 2.6 Single — 0.8 1.3 mA Figure 5 Dual — 1.6 2.6 CIN — 60 — pF f = 1 MHz, VF = 0V ΔVF/ΔTA — –1.6 — mV/°C Logic Low Output Voltage VOL Input Threshold Current ITH Logic Low Output Supply Current IDDL Logic High Output Supply Current Input Capacitance Input Diode Temperature Coefficient IDDH IF = 2 mA Switching Specifications (AC) Over the recommended temperature (TA = –40°C to +105°C) and supply voltage (2.7V ≤ VDD ≤ 5.5V). All typical specifications are at VDD = 5V and TA = 25°C. Parameter Symbol Min Typ Max Unit Propagation Delay Time to Logic Low Outputa tPHL — 46 80 ns Propagation Delay Time to Logic High Outputa tPLH — 40 80 ns Pulse Width tPW 100 — — ns IF = 2 mA, VI = 3.3V, RT = 870Ω, CL = 15 pF, CMOS Signal Levels. Pulse Width Distortionb PWD — 6 30 ns Figure 6 and Figure 7 Propagation Delay Skewc tPSK — 30 ns tR — 12 — ns IF = 2 mA, VI = 5V, RT = 1.68 kΩ, CL = 15 pF, CMOS Signal Levels. — 10 — ns IF = 2 mA, VI = 3.3V, RT = 870Ω, CL = 15 pF, CMOS Signal Levels. — 12 — ns IF = 2 mA, VI = 5V, RT = 1.68 kΩ, CL = 15 pF, CMOS Signal Levels. — 10 — ns IF = 2 mA, VI = 3.3V, RT = 870Ω, CL = 15 pF, CMOS Signal Levels. Output Rise Time (10% to 90%) Output Fall Time (90% to 10%) tF Broadcom -8- Test Conditions IF = 2 mA, VI = 5V, RT = 1.68 kΩ, CL = 15 pF, CMOS Signal Levels. ACPL-064L, ACPL-M61L, ACPL-W61L, ACPL-K64L Data Sheet Parameter Static Common-Mode Transient Immunity at Logic High Outputd Symbol Min Typ Max Unit | CMH | 20 35 — kV/μs Test Conditions VCM = 1000V, TA = 25°C, IF = 0 mA, VI = 0V (RT =1.68 kΩ) or (RT = 870Ω), CL = 15 pF, CMOS Signal Levels. Figure 8 Static Common-Mode Transient Immunity at Logic Low Outpute | CML | 20 35 — kV/μs VCM = 1000V, TA = 25°C, VI = 5 V (RT = 1.68 kΩ) or VI = 3.3V (RT = 870Ω), IF = 2 mA, CL= 15 pF, CMOS Signal Levels. Figure 8 Dynamic Common-Mode Transient Immunityf CMRD — 35 — kV/μs VCM = 1000 V, TA = 25°C, IF = 2 mA, VI = 5V (RT = 1.68 kΩ) or VI = 3.3 V (RT = 870Ω), 10 MBd datarate, the absolute increase of PWD < 10 ns Figure 8 a. tPHL propagation delay is measured from the 50% (Vin or IF) on the rising edge of the input pulse to the 50% VDD of the falling edge of the VO signal. tPLH propagation delay is measured from the 50% (Vin or IF) on the falling edge of the input pulse to the 50% level of the rising edge of the VO signal. b. PWD is defined as |tPHL – tPLH|. c. tPSK is equal to the magnitude of the worst-case difference in tPHL and/or tPLH that is seen between units at any given temperature within the recommended operating conditions. d. CMH is the maximum tolerable rate of rise of the common-mode voltage to assure that the output remains in a high logic state. e. CML is the maximum tolerable rate of fall of the common-mode voltage to assure that the output remains in a low logic state. f. CMD is the maximum tolerable rate of the common-mode voltage during data transmission to assure that the absolute increase of the PWD is less than 10 ns. Package Characteristics All typicals are at TA = 25°C. Parameter Input-Output Insulation Symbol Part Number Min Typ Max Unit VISO ACPL-064L ACPL-M61L 3750 — — Vrms ACPL-W61L ACPL-K64L 5000 — — Test Conditions RH < 50% for 1 min. TA = 25°C Input-Output Resistance RI-O — 1012 — Ω VI-O = 500V Input-Output Capacitance CI-O — 0.6 — pF f = 1 MHz, TA = 25°C Broadcom -9- ACPL-064L, ACPL-M61L, ACPL-W61L, ACPL-K64L Data Sheet Figure 1 Typical Input Diode Forward Current Characteristic Figure 2 Typical VF versus Temperature VF - FORWARD VOLTAGE (V) IF - FORWARD CURRENT (mA) 10 TA = 25°C 1 IF 0.1 VF 0.01 1.1 1.2 1.3 1.4 VF - FORWARD VOLTAGE (V) 1.5 -40 Figure 3 Typical Input Threshold Current versus Temperature -20 0 20 40 60 TA - TEMPERATURE (°C) 80 100 Figure 4 Typical Logic Low Output Supply Current (Per Channel) versus Temperature 1 0.8 IDDL - LOGIC LOW OUTPUT SUPPLY CURRENT (mA) Ith - INPUT THRESHOLD CURRENT (mA) 1.50 1.45 1.40 1.35 1.30 1.25 1.20 1.15 1.10 1.05 1.00 0.6 0.4 0.2 3.3V 5V 0 -40 -20 0 20 40 60 TA - TEMPERATURE (°C) 80 100 120 IDDH - LOGIC HIGH OUTPUT SUPPLY CURRENT (mA) Figure 5 Typical Logic High Output Supply Current (Per Channel) versus Temperature 1 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 3.3V 5V -40 0 40 TA - TEMPERATURE (°C) 80 120 Broadcom - 10 - 1 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 3.3V 5V -40 0 40 TA - TEMPERATURE (°C) 80 120 ACPL-064L, ACPL-M61L, ACPL-W61L, ACPL-K64L Data Sheet Figure 6 Typical Switching Speed versus Pulse Input with a 5V Supply Voltage Figure 7 Typical Switching Speed versus Pulse Input Current with a 3.3V Supply Voltage 60 tp - PROPAGATION DELAY; PWD-PULSE WIDTH DISTORTION (ns) tp - PROPAGATION DELAY; PWD-PULSE WIDTH DISTORTION (ns) 60 50 40 30 20 TPHL_5.0V TPLH_5.0V PWD_5.0V 10 0 -10 1.5 2 2.5 3 3.5 4 4.5 5 IF - PULSE INPUT CURRENT (mA) 5.5 50 40 30 20 0 -10 6 Broadcom - 11 - TPHL_3.3V TPLH_3.3V PWD_3.3V 10 1.5 2 2.5 3 3.5 4 4.5 5 IF - PULSE INPUT CURRENT (mA) 5.5 6 ACPL-064L, ACPL-M61L, ACPL-W61L, ACPL-K64L Data Sheet Supply Bypassing, LED Bias Resistors, and PC Board Layout The ACPL-x6xL optocouplers are extremely easy to use and feature high-speed, push-pull CMOS outputs. Pull-up resistors are not required. The external components required for proper operation are the input limiting resistors and the output bypass capacitor. Capacitor values should be 0.1 μF. For each capacitor, the total lead length connecting the capacitor to the VDD and GND pins should not exceed 20 mm. For ACPL-M61L/W61L: For ACPL-064L/K64L: VI = 3.3V: R1 = 510Ω ± 1%, R2 = 360Ω ± 1% VI = 5.0V: R1 = 1000Ω ± 1%, R2 = 680Ω ± 1% RT = R1 + R2 R1/R2 = 1.5 VI = 3.3V: R1 = 430Ω ± 1%, R2 = 430Ω ± 1% VI = 5.0V: R1 = 845Ω ± 1%, R2 = 845Ω ± 1% RT = R1 + R2 R1/R2 = 1 Figure 8 Recommended PCB Layout and Input Current-Limiting Resistor Selection VI R1 IF 1 VI VDD 6 R1 I F 1 6 C = 0.1 μF 5 Vo 2 5 3 4 3 GND2 4 GND1 R1 IF 1 8 VDD 2 7 C = 0.1 μF Vo1 3 6 Vo2 4 5 R2 GND1 R2 VI R1 IF GND2 ACPL-W61L ACPL-M61L GND2 Vo R2 R2 GND1 VI VDD C = 0.1 μF GND2 ACPL-064L/K64L 3.3V/5V VDD IF C = 0.1 μF A B Anode 0V Vo Shield Cathode GND V CM (PEAK) V CM Output Monitoring node VO V DD + CM H V O (min.) SWITCH AT B: I F = 2 mA VO V O (max.) GND VCM Pulse Gen SWITCH AT A: I F = 0 mA Broadcom - 12 - CM L ACPL-064L, ACPL-M61L, ACPL-W61L, ACPL-K64L Data Sheet Propagation Delay, Pulse-Width Distortion, and Propagation Delay Skew under the same conditions (i.e., the same supply voltage, output load, and operating temperature). As shown in Figure 10, if the inputs of a group of optocouplers are switched either ON or OFF at the same time, tPSK is the difference between the shortest propagation delay, either tPLH or tPHL, and the longest propagation delay, either tPLH or tPHL. As mentioned earlier, tPSK can determine the maximum parallel data transmission rate. Propagation delay is a figure of merit that describes how quickly a logic signal propagates through a system. The propagation delay from low-to-high (tPLH) is the amount of time required for an input signal to propagate to the output, causing the output to change from low to high. Similarly, the propagation delay from high-to-low (tPHL) is the amount of time required for the input signal to propagate to the output, causing the output to change from high-to-low (see Figure 9). Pulse-width distortion (PWD) results when tPLH and tPHL differ in value. PWD is defined as the difference between tPLH and tPHL. PWD determines the maximum data rate of a transmission system. PWD can be expressed in percent by dividing the PWD (in ns) by the minimum pulse width (in ns) being transmitted. Typically, a PWD of 20% to 30% of the minimum pulse width is tolerable; the exact figure depends on the particular application (RS232, RS422, T-1, etc.). Propagation delay skew, tPSK, is an important parameter to consider in parallel data applications where synchronization of signals on parallel data lines is a concern. If the parallel data is being sent through a group of optocouplers, differences in propagation delays cause the data to arrive at the outputs of the optocouplers at different times. If this difference in propagation delays is large enough, it determines the maximum rate at which parallel data can be sent through the optocouplers. Figure 10 is the timing diagram of a typical parallel data application with both the clock and the data lines being sent through optocouplers. The figure shows data and clock signals at the inputs and outputs of the optocouplers. To obtain the maximum data transmission rate, both edges of the clock signal are being used to clock the data; if only one edge were used, the clock signal would need to be twice as fast. Propagation delay skew represents the uncertainty of where an edge might be after being sent through an optocoupler. Figure 10 shows that there will be uncertainty in both the data and the clock lines. It is important that these two areas of uncertainty not overlap. Otherwise the clock signal might arrive before all of the data outputs have settled, or some of the data outputs might start to change before the clock signal has arrived. From these considerations, the absolute minimum pulse width that can be sent through optocouplers in a parallel application is twice tPSK. A cautious design should use a slightly longer pulse width to ensure that any additional uncertainty in the rest of the circuit does not cause a problem. Propagation delay skew is defined as the difference between the minimum and maximum propagation delays, either tPLH or tPHL, for any given group of optocouplers which are operating The tPSK specified optocouplers offer the advantages of guaranteed specifications for propagation delays, pulse-width distortion, and propagation delay skew over the recommended temperature and power supply ranges. Figure 9 Propagation Delay Skew Waveform Figure 10 Parallel Data Transmission Example VI DATA 50% INPUTS 2.5V, CMOS VO CLOCK tPSK VI 50% DATA OUTPUTS VO tPSK CLOCK 2.5V, CMOS tPSK Broadcom - 13 - ACPL-064L, ACPL-M61L, ACPL-W61L, ACPL-K64L Data Sheet Optocoupler CMR Performance indicates the typical achievable CMR performance as the input is toggled on or off during a CMR transient. The principal protection against common-mode noise comes from the fundamental isolation properties of the optocoupler, and this in turn is directly related to the Input-Output leakage capacitance of the optocoupler. To provide maximum protection to circuitry connected to the input or output of the optocoupler, the leakage capacitance is minimized by having large separation distances at all points in the optocoupler construction, including the LED/photodiode interface. The logic output of the ACPL-x6xL optocouplers is mainly controlled by LED current level, and since the LED current features very fast rise and fall times, dynamic noise immunity is essentially the same as static noise immunity. In addition to the optocouplers' basic physical construction, additional circuit design steps mitigate the effects of common-mode noise. The most important of these is the Faraday shield on the photodetector stage. Despite their immunity to input latch-up and the excellent dynamic CMR immunity, ACPL-x6xL optocoupler devices are still potentially vulnerable to misoperation caused by turning the LED either on or off during a CMR disturbance. If the LED status could be ensured by design, the overall application level CMR performance would be that of the photodetector. To benefit from the inherently high CMR capabilities of the ACPL-x6xL family, take the following precautions when operating the LED at the application level. A Faraday shield is effective in optocouplers because the internal modulation frequency (light) is many orders of magnitude higher than the common-mode noise frequency. In particular, ensure that the LED stays either on or off during a CMR transient. Some common design techniques to accomplish this include the following: Keep the LED On: Improving CMR Performance at the Application Level 1. In an end application, it is desirable that the optocouplers' common-mode isolation be as close as possible to that indicated in the data sheet specifications. The first step in meeting this goal is to ensure maximum separation between PCB interconnects on either side of the optocoupler is maintained and that PCB tracks beneath the optocoupler are avoided. Overdrive the LED with a higher-than-required forward current. Keep the LED Off: It is inevitable that a certain amount of CMR noise will be coupled into the inputs and this can potentially result in false-triggering of the input. This problem is frequently observed in devices with high input impedance. In some cases, this can cause momentary missing pulses and can even cause input circuitry to latch-up in some alternate technologies. 1. Reverse bias the LED during the off state. 2. Minimize the off-state impedance across the anode and cathode of the LED during the off state. All of these methods allow the full CMR capability of the ACPL-x6xL family to be achieved, but they do have practical implementation issues or require a compromise on power consumption. There is, however, an effective method to meet the goal of maintaining the LED status during a CMR event with no other design compromises other than a single added resistor. This CMR optimization takes advantage of the differential connection to the LED. By ensuring the common-mode impedances at both the cathode and anode of the LED are equal, the CMR transient on the LED is effectively canceled. As shown in Figure 11, this is easily achieved by using two, instead of one, input bias resistors. The ACPL-x6xL optocoupler family does not have an input latch-up issue. Even at very high CMR levels, such as those experienced in end equipment level tests (for example IEC61000-4-4), the ACPL-x6xL series is immune to latch-up because of the simple diode structure of the LED. In some cases, achieving the rated data sheet CMR performance level is not possible in an application. This is often because of the practical requirement to actually connect the isolator input to the output of a dynamically changing signal rather than statically tying the input to VDD or GND. To address achievable end application performance on data sheets, the ACPL-x6xL optocouplers include an additional typical performance specification for dynamic CMR in the electrical parameter table. The dynamic CMR specification Broadcom - 14 - ACPL-064L, ACPL-M61L, ACPL-W61L, ACPL-K64L Data Sheet Split LED Bias Resistor for Optimum CMR Figure 11 shows the recommended drive circuit for the ACPL-x6xL that gives optimum common-mode rejection. The two current-setting resistors balance the common-mode impedances at the LED’s anode and cathode. Common-mode transients can capacitively couple from the LED anode (or cathode) to the output-side ground causing current to be shunted away from the LED (which is not wanted when the LED should be on) or conversely causing current to be injected into the LED (which is not wanted when the LED should be off). Figure 12 shows the parasitic capacitances (CLA and CLC) between the LED’s anode and cathode, and output ground. Also shown in Figure 12 on the input side is an AC-equivalent circuit. Table 1 shows that the directions of ILP and ILN depend on the polarity of the common-mode transient. For transients occurring when the LED is on, common-mode rejection (CML, since the output is at low state) depends on LED current (IF). For conditions where IF is close to the switching threshold (ITH), CML also depends on the extent to which ILP and ILN balance each other. In other words, any condition where a common-mode transient causes a momentary decrease in IF (meaning when dVCM/dt > 0 and |IFP| > |IFN|, referring to Table 1) also causes a common-mode failure for transients that are fast enough. Likewise, for a common-mode transient that occurs when the LED is off (meaning CMH, since the output is at high state), if an imbalance between ILP and ILN results in a transient IF equal to or greater than the switching threshold of the optocoupler, the transient signal can cause the output to spike below 2V, which constitutes a CMH failure. The resistors recommended in Figure 11 include both the output impedance of the logic driver circuit and the external limiting resistor. The balanced ILED-setting resistors help equalize the common-mode voltage change at the anode and cathode. This reduces ILED changes caused by transient coupling through the parasitic capacitors CLA and CLC shown in Figure 12. For ACPL-M61L/W61L: For ACPL-064L/K64L: VDD = 3.3V: R1 = 510Ω ± 1%, R2 = 360Ω ± 1% VDD = 5.0V: R1 = 1000Ω ± 1%, R2 = 680Ω ± 1% RT = R1 + R2 R1/R2 = 1.5 VDD = 3.3V: R1 = 430Ω ± 1%, R2 = 430Ω ± 1% VDD = 5.0V: R1 = 845Ω ± 1%, R2 = 845Ω ± 1% RT = R1 + R2 R1/R2 = 1 Figure 11 Recommended High-CMR Drive Circuit for the ACPL-x6xL R1 VDD2 VDD VO 0.1μF R2 74LS04 or any totem-pole output logic gate GND2 Shield GND1 Broadcom - 15 - ACPL-064L, ACPL-M61L, ACPL-W61L, ACPL-K64L Data Sheet For ACPL-M61L/W61L: For ACPL-064L/K64L: VDD = 3.3V: R1 = 510Ω ± 1%, R2 = 360Ω ± 1% VDD = 5.0V: R1 = 1000Ω ± 1%, R2 = 680Ω ± 1% RT = R1 + R2 R1/R2 = 1.5 VDD = 3.3V: R1 = 430Ω ± 1%, R2 = 430Ω ± 1% VDD = 5.0V: R1 = 845Ω ± 1%, R2 = 845Ω ± 1% RT = R1 + R2 R1/R2 = 1 Figure 12 AC Equivalent Circuit of ACPL-x6xL VDD2 R1 ILP VO CLA 0.1μF R2 ILN CLC GND2 Shield Table 1 Common-Mode Pulse Polarity and LED Current Transient dVCM/dt Value Resultant ILP Flow Direction Resultant ILN Flow Direction If |ILP| < |ILN|, LED current IF is momentarily: If |ILP| > |ILN|, LED current IF is momentarily: Positive (> 0) Away from the LED anode through CLA Away from the LED cathode through CLC Increased Decreased Negative (< 0) Toward the LED anode through CLA Toward the LED cathode through CLC Decreased Increased Broadcom - 16 - ACPL-064L, ACPL-M61L, ACPL-W61L, ACPL-K64L Data Sheet Slew-Rate Controlled Outputs Feature Figure 13 Rise and Fall Time of ACPL-x6xL across Wide-Load Capacitance Rise Time (VDD = 5.0V) 30 25 Rise Time (nS) Typically, the output slew rate (rise and fall time) varies with the output load, as more time is required to charge up the higher load. The propagation delay and the PWD both increase with the load capacitance. This will be an issue especially in parallel communication because different communication lines will have different load capacitances. However, optocoupler ACPL-x6xL has a built-in slew-rate controlled feature to ensure that the output slew rate remains stable across wide load capacitance. Figure 13 shows the rise time and fall time for ACPL-x6xL at 3.3V and 5V. 20 15 10 5 0 –40 10 pF 33 pF –20 15 pF 47 pF 0 22 pF 100 pF 20 40 Temperature (°C) 60 80 100 60 80 100 60 80 100 60 80 100 Fall Time (VDD = 5.0V) 25 Fall Time (nS) 20 15 10 5 0 –40 10 pF 33 pF –20 15 pF 47 pF 0 22 pF 100 pF 20 40 Temperature (°C) Rise Time (VDD = 3.3V) 25 Rise Time (nS) 20 15 10 5 0 –40 10 pF 33 pF –20 15 pF 47 pF 0 22 pF 100 pF 20 40 Temperature (°C) Fall Time (VDD = 3.3V) 25 Rise Time (nS) 20 15 10 5 0 –40 Broadcom - 17 - 10 pF 33 pF –20 15 pF 47 pF 0 22 pF 100 pF 20 40 Temperature (°C) ACPL-064L, ACPL-M61L, ACPL-W61L, ACPL-K64L Data Sheet Speed Improvement Figure 15 Improvement of tp and PWD with an Added 100-pF Peaking Capacitor in Parallel of Input Limiting Resistor Figure 14 Connection of Peaking Capacitor (Cpeak) in Parallel with the Input Limiting Resistor (R1) to Improve Speed Performance a. VDD2 = 5V, IF = 2 mA TPHL 50 TPLH 40 TPHL 30 TPLH No Peaking With Peaking PWD 20 10 Cpeak 0 –40 VDD2 + VDD = 5V, Cpeak = 47 pF, R1 = 845Ω 60 tP or PWD (ns) A peaking capacitor can be placed across the input current-limit resistor (Figure 14) to achieve enhanced speed performance. The value of the peaking capacitor is dependent on the rise and fall time of the input signal, supply voltages, and LED input driving current (IF). Figure 15 shows significant improvement of propagation delay and pulse with distortion with an added peak capacitor at a driving current of 2 mA and 3.3V/5V power supply. R1 –20 0 V0 Vin 20 40 Temp (°C) 60 80 100 0.1 μF − b. VDD = 3.3V, Cpeak = 47 pF, R1 = 430Ω R2 SHIELD GND2 VDD2 = 3.3V, IF = 2 mA 60 TPHL 50 tP or PWD (ns) GND1 40 TPLH 30 No Peaking With Peaking TPHL 20 10 0 –40 Broadcom - 18 - TPLH PWD –20 0 20 40 Temp (°C) 60 80 100 For product information and a complete list of distributors, please go to our web site: www.broadcom.com. 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