AD ADF4117BCP Rf pll frequency synthesizer Datasheet

a
RF PLL Frequency Synthesizers
ADF4116/ADF4117/ADF4118
GENERAL DESCRIPTION
FEATURES
ADF4116: 550 MHz
ADF4117: 1.2 GHz
ADF4118: 3.0 GHz
2.7 V to 5.5 V Power Supply
Separate V P Allows Extended Tuning Voltage in 3 V
Systems
Selected Charge Pump Currents
Dual Modulus Prescaler
ADF4116: 8/9
ADF4117/ADF4118: 32/33
3-Wire Serial Interface
Digital Lock Detect
Power-Down Mode
Fast Lock Mode
The ADF4116 family of frequency synthesizers can be used
to implement local oscillators in the up-conversion and downconversion sections of wireless receivers and transmitters. They
consist of a low-noise digital PFD (Phase Frequency Detector),
a precision charge pump, a programmable reference divider,
programmable A and B counters and a dual-modulus prescaler
(P/P+1). The A (5-bit) and B (13-bit) counters, in conjunction
with the dual modulus prescaler (P/P+1), implement an N
divider (N = BP+A). In addition, the 14-bit reference counter
(R Counter), allows selectable REFIN frequencies at the PFD
input. A complete PLL (Phase-Locked Loop) can be implemented if the synthesizer is used with an external loop filter and
VCO (Voltage Controlled Oscillator).
Control of all the on-chip registers is via a simple 3-wire interface.
The devices operate with a power supply ranging from 2.7 V to
5.5 V and can be powered down when not in use.
APPLICATIONS
Base Stations for Wireless Radio (GSM, PCS, DCS,
CDMA, WCDMA)
Wireless Handsets (GSM, PCS, DCS, CDMA, WCDMA)
Wireless LANS
Communications Test Equipment
CATV Equipment
FUNCTIONAL BLOCK DIAGRAM
AVDD
DVDD
VP
CPGND
REFERENCE
ADF4116/ADF4117/ADF4118
14-BIT
R COUNTER
REFIN
PHASE
FREQUENCY
DETECTOR
14
CHARGE
PUMP
CP
R COUNTER
LATCH
CLK
21-BIT
INPUT REGISTER
DATA
FUNCTION
LATCH
19
LOCK
DETECT
LE
SDOUT
A, B COUNTER
LATCH
18
FROM
FUNCTION LATCH
HIGH Z
AVDD
13
MUX
N = BP + A
RFINA
PRESCALER
P/P +1
RFINB
13-BIT
B COUNTER
MUXOUT
SDOUT
LOAD
LOAD
5-BIT
A COUNTER
M3
M2
M1
FLO
SWITCH
FLO
5
CE
AGND
DGND
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000
ADF4116/ADF4117/ADF4118–SPECIFICATIONS1
(AVDD = DVDD = 3 V ⴞ 10%, 5 V ⴞ 10%; AVDD ≤ VP ≤ 6.0 V; AGND = DGND = CPGND = 0 V; TA = TMIN to TMAX unless otherwise noted)
Parameter
B Version
B Chips2
Unit
RF CHARACTERISTICS
RF Input Frequency
ADF4116
ADF4117
ADF4118
ADF4118
Maximum Allowable
Prescaler Output Frequency3
45/550
0.045/1.2
0.1/3.0
0.2/3.0
45/550
0.045/1.2
0.1/3.0
0.2/3.0
MHz min/max
GHz min/max
GHz min/max
GHz min/max
165
200
–15/0
–10/0
165
200
–15/0
–10/0
MHz max
MHz max
dBm min/max
dBm min/max
REFIN CHARACTERISTICS
Reference Input Frequency
Reference Input Sensitivity4
0/100
–5/0
0/100
–5/0
MHz min/max
dBm min/max
REFIN Input Capacitance
REFIN Input Current
10
± 100
10
± 100
pF max
µA max
PHASE DETECTOR FREQUENCY5
55
55
MHz max
CHARGE PUMP
ICP Sink/Source
High Value
Low Value
Absolute Accuracy
ICP Three-State Leakage Current
Sink and Source Current Matching
ICP vs. VCP
ICP vs. Temperature
1
250
2.5
1
3
2
2
1
250
2.5
1
3
2
2
mA typ
µA typ
% typ
nA max
% typ
% typ
% typ
LOGIC INPUTS
VINH, Input High Voltage
VINL, Input Low Voltage
IINH/IINL, Input Current
CIN, Input Capacitance
Reference Input Current
0.8 × DVDD
0.2 × DVDD
±1
10
± 100
0.8 × DVDD
0.2 × DVDD
±1
10
± 100
V min
V max
µA max
pF max
µA max
LOGIC OUTPUTS
VOH, Output High Voltage
VOL, Output Low Voltage
DVDD – 0.4
0.4
DVDD – 0.4
0.4
V min
V max
2.7/5.5
AVDD
AVDD/6.0
2.7/5.5
AVDD
AVDD/6.0
V min/V max
5.5
5.5
7.5
0.4
1
4.5
4.5
6.5
0.4
1
mA max
mA max
mA max
mA max
µA typ
RF Input Sensitivity
POWER SUPPLIES
AVDD
DVDD
VP
IDD6 (AIDD + DIDD)
ADF4116
ADF4117
ADF4118
IP
Low-Power Sleep Mode
Test Conditions/Comments
See Figure 22 for Input Circuit
–2–
V min/V max
Input Level = –10 dBm
AVDD, DVDD = 3 V
AVDD, DVDD = 5 V
AVDD = 3 V
AVDD = 5 V
AC-Coupled. When DC-Coupled:
0 to VDD Max (CMOS Compatible)
0.5 V ≤ VCP ≤ VP – 0.5
0.5 V ≤ VCP ≤ VP – 0.5
VCP = VP/2
IOH = 500 µA
IOL = 500 µA
AVDD ≤ VP ≤ 6.0 V
See Figure 20
4.5 mA Typical
4.5 mA Typical
6.5 mA Typical
TA = 25°C
REV. 0
ADF4116/ADF4117/ADF4118
B Version
B Chips2
Unit
Test Conditions/Comments
–170
–162
–170
–162
dBc/Hz typ
dBc/Hz typ
Phase Noise Performance8
ADF41169 540 MHz Output
ADF411710 900 MHz Output
ADF411810 900 MHz Output
ADF411711 836 MHz Output
ADF411812 1750 MHz Output
ADF411813 1750 MHz Output
ADF411814 1960 MHz Output
–89
–87
–90
–78
–85
–65
–84
–89
–87
–90
–78
–85
–65
–84
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
@ 25 kHz PFD Frequency
@ 200 kHz PFD Frequency
@ VCO Output
@ 1 kHz Offset and 200 kHz PFD Frequency
Note 15
Note 15
@ 300 Hz Offset and 30 kHz PFD Frequency
@ 1 kHz Offset and 200 kHz PFD Frequency
@ 200 Hz Offset and 10 kHz PFD Frequency
@ 1 kHz Offset and 200 kHz PFD Frequency
Spurious Signals
ADF41169 540 MHz Output
ADF411710 900 MHz Output
ADF411810 900 MHz Output
ADF411711 836 MHz Output
ADF411812 1750 MHz Output
ADF411813 1750 MHz Output
ADF411814 1960 MHz Output
–88/–99
–90/–104
–91/–100
–80/–84
–88/–90
–65/–73
–80/–86
–88/–99
–90/–104
–91/–100
–80/–84
–88/–90
–65/–73
–80/–86
dBc typ
dBc typ
dBc typ
dBc typ
dBc typ
dBc typ
dBc typ
@ 200 kHz/400 kHz and 200 kHz PFD Frequency
Note 15
Note 15
@ 30 kHz/60 kHz and 30 kHz PFD Frequency
@ 200 kHz/400 kHz and 200 kHz PFD Frequency
@ 10 kHz/20 kHz and 10 kHz PFD Frequency
@ 200 kHz/400 kHz and 200 kHz PFD Frequency
Parameter
NOISE CHARACTERISTICS
ADF4118 Phase Noise Floor7
NOTES
1
Operating temperature range is as follows: B Version: –40°C to +85°C.
2
The B Chip specifications are given as typical values.
3
This is the maximum operating frequency of the CMOS counters.
4
AVDD = DVDD = 3 V; for AVDD = DVDD = 5 V, use CMOS-compatible levels.
5
Guaranteed by design. Sample tested to ensure compliance.
6
AVDD = DVDD = 3 V; RFIN for ADF4116 = 540 MHz; RF IN for ADF4117, ADF4118 = 900 MHz.
7
The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log N (where N is the N divider
value).
8
The phase noise is measured with the EVAL-ADF411xEB Evaluation Board and the HP8562E Spectrum Analyzer. The spectrum analyzer provides the REFIN for
the synthesizer (f REFOUT = 10 MHz @ 0 dBm).
9
fREFIN = 10 MHz; fPFD = 200 kHz; Offset frequency = 1 kHz; f RF = 540 MHz; N = 2700; Loop B/W = 20 kHz.
10
fREFIN = 10 MHz; fPFD = 200 kHz; Offset frequency = 1 kHz; f RF = 900 MHz; N = 4500; Loop B/W = 20 kHz.
11
fREFIN = 10 MHz; fPFD = 30 kHz; Offset frequency = 300 Hz; f RF = 836 MHz; N = 27867; Loop B/W = 3 kHz.
12
fREFIN = 10 MHz; fPFD = 200 kHz; Offset frequency = 1 kHz; f RF = 1750 MHz; N = 8750; Loop B/W = 20 kHz.
13
fREFIN = 10 MHz; fPFD = 10 kHz; Offset frequency = 200 Hz; f RF = 1750 MHz; N = 175000; Loop B/W = 1 kHz.
14
fREFIN = 10 MHz; fPFD = 200 kHz; Offset frequency = 1 kHz; f RF = 1960 MHz; N = 9800; Loop B/W = 20 kHz.
15
Same conditions as above.
Specifications subject to change without notice.
1 (AVDD = DVDD = 3 V ⴞ 10%, 5 V ⴞ 10%; AVDD ≤ VP < 6.0 V; AGND = DGND = CPGND = 0 V;
TIMING CHARACTERISTICS
TA = TMIN to TMAX unless otherwise noted)
Parameter
Limit at TMIN to TMAX
(B Version)
Unit
Test Conditions/Comments
t1
t2
t3
t4
t5
t6
10
10
25
25
10
20
ns min
ns min
ns min
ns min
ns min
ns min
DATA to CLOCK Setup Time
DATA to CLOCK Hold Time
CLOCK High Duration
CLOCK Low Duration
CLOCK to LE Setup Time
LE Pulsewidth
NOTE
1
Guaranteed by design but not production tested.
Specifications subject to change without notice.
REV. 0
–3–
ADF4116/ADF4117/ADF4118
ABSOLUTE MAXIMUM RATINGS 1, 2
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
(TA = 25°C unless otherwise noted)
AVDD to GND3 . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
AVDD to DVDD . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
VP to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
VP to AVDD . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +5.5 V
Digital I/O Voltage to GND . . . . . . . . –0.3 V to VDD + 0.3 V
Analog I/O Voltage to GND . . . . . . . . . –0.3 V to VP + 0.3 V
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Maximum Junction Temperature . . . . . . . . . . . . . . . . 150°C
TSSOP θJA Thermal Impedance . . . . . . . . . . . . . 150.4°C/W
CSP θJA Thermal Impedance
(Paddle Soldered) . . . . . . . . . . . . . . . . . . . . . . . . . 122°C/W
(Paddle Not Soldered) . . . . . . . . . . . . . . . . . . . . . . 216°C/W
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2
This device is a high-performance RF integrated circuit with an ESD rating of
< 2 kV and it is ESD sensitive. Proper precautions should be taken for handling
and assembly.
3
GND = AGND = DGND = 0 V.
TRANSISTOR COUNT
6425 (CMOS) and 303 (Bipolar).
t3
t4
CLOCK
t1
DATA
DB20 (MSB)
t2
DB19
DB2
DB1
(CONTROL BIT C2)
DB0 (LSB)
(CONTROL BIT C1)
t6
LE
t5
LE
Figure 1. Timing Diagram
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the
ADF4116/ADF4117/ADF4118 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions
are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option*
ADF4116BRU
ADF4116BCP
ADF4117BRU
ADF4117BCP
ADF4118BRU
ADF4118BCP
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
Thin Shrink Small Outline Package (TSSOP)
Chip Scale Package
Thin Shrink Small Outline Package (TSSOP)
Chip Scale Package
Thin Shrink Small Outline Package (TSSOP)
Chip Scale Package
RU-16
CP-20
RU-16
CP-20
RU-16
CP-20
*Contact the factory for chip availability.
–4–
REV. 0
ADF4116/ADF4117/ADF4118
PIN FUNCTION DESCRIPTIONS
Pin No.
Mnemonic
Function
1
FLO
2
CP
3
4
5
CPGND
AGND
RFINB
6
7
RFINA
AVDD
8
REFIN
9
10
DGND
CE
11
CLK
12
DATA
13
LE
14
MUXOUT
15
DVDD
16
VP
Fast Lock Switch Output. This can be used to switch an external resistor to change the loop filter bandwidth. This will speed up locking of the PLL.
Charge Pump Output. When enabled, this provides the ±ICP to the external loop filter, which in turn drives
the external VCO.
Charge Pump Ground. This is the ground return path for the charge pump.
Analog Ground. This is the ground return path for the prescaler.
Complementary Input to the RF Prescaler. This point should be decoupled to the ground plane with a
small bypass capacitor, typically 100 pF. See Figure 22.
Input to the RF Prescaler. This small signal input is normally ac-coupled from the VCO.
Analog Power Supply. This may range from 2.7 V to 5.5 V. Decoupling capacitors to the analog ground
plane should be placed as close as possible to this pin. AVDD must be the same value as DVDD.
Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and an equivalent input
resistance of 100 kΩ. See Figure 21. The oscillator input can be driven from a TTL or CMOS crystal
oscillator or it can be ac-coupled.
Digital Ground.
Chip Enable. A logic low on this pin powers down the device and puts the charge pump output into threestate mode. Taking the pin high will power up the device depending on the status of the power-down bit F2.
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into
the 21-bit shift register on the CLK rising edge. This input is a high impedance CMOS input.
Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This
input is a high impedance CMOS input.
Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one
of the four latches, the latch being selected using the control bits.
This multiplexer output allows either the Lock Detect, the scaled RF or the scaled Reference Frequency
to be accessed externally.
Digital Power Supply. This may range from 2.7 V to 5.5 V. Decoupling capacitors to the digital ground
plane should be placed as close as possible to this pin. DVDD must be the same value as AVDD.
Charge Pump Power Supply. This should be greater than or equal to VDD. In systems where VDD is 3 V,
it can be set to 5 V and used to drive a VCO with a tuning range of up to 6 V.
PIN CONFIGURATIONS
2
TOP VIEW
RFINB 5 (Not to Scale) 12 DATA
AGND
3
RFINA 6
11
CLK
RFINB
4
AVDD 7
10
CE
RFINA
5
REFIN 8
9
DGND
–5–
16 DVDD
15 MUXOUT
ADF4116
ADF4117
ADF4118
14 LE
13 DATA
TOP VIEW
(Not to Scale)
12 CLK
11 CE
DGND 10
1
AGND
AVDD 6
CPGND
18 VP
LE
17 DVDD
MUXOUT
13
AGND 4
REFIN 8
DVDD
14
ADF4116
ADF4117
ADF4118
DGND 9
VP
15
20 CP
16
CP 2
19 FLO
FLO 1
CPGND 3
REV. 0
Chip Scale Package
AVDD 7
TSSOP
ADF4116/ADF4117/ADF4118–Typical Performance Characteristics
Table I. S-Parameter Data for the ADF4118 RF Input
(Up to 1.8 GHz)
10dB/DIVISION
–40
PARAMTYPE
S
DATAFORMAT
MA
FREQ MagS11
AngS11
FREQ MagS11 AngS11
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
0.50
0.55
0.60
0.65
0.70
0.75
0.80
0.85
0.90
–2.0571
–4.4427
–6.3212
–2.1393
–12.13
–13.52
–15.746
–18.056
–19.693
–22.246
–24.336
–25.948
–28.457
–29.735
–31.879
–32.681
–31.522
–34.222
0.95
1.00
1.05
1.10
1.15
1.20
1.25
1.30
1.35
1.40
1.45
1.50
1.55
1.60
1.65
1.70
1.75
1.80
0.89207
0.8886
0.89022
0.96323
0.90566
0.90307
0.89318
0.89806
0.89565
0.88538
0.89699
0.89927
0.87797
0.90765
0.88526
0.81267
0.90357
0.92954
0.92087
0.93788
0.9512
0.93458
0.94782
0.96875
0.92216
0.93755
0.96178
0.94354
0.95189
0.97647
0.98619
0.95459
0.97945
0.98864
0.97399
0.97216
0.64ⴗ rms
–36.961
–39.343
–40.134
–43.747
–44.393
–46.937
–49.6
–51.884
–51.21
–53.55
–56.786
–58.781
–60.545
–61.43
–61.241
–64.051
–66.19
–63.775
–70
–80
–90
–100
–110
–120
–130
–140
100Hz
FREQUENCY OFFSET FROM 900 MHz CARRIER
1MHz
Figure 4. ADF4118 Integrated Phase Noise (900 MHz,
200 kHz, 35 kHz, Typical Lock Time: 200 µ s)
10dB/DIVISION
–40
–5
RMS NOISE = 0.64ⴗ
–60
0
VDD = 3V
VP = 3V
RL = –40dBc/Hz
RMS NOISE = 0.575ⴗ
–50
0.575ⴗ rms
–60
PHASE NOISE – dBc/Hz
–10
RF INPUT POWER – dBm
RL = –40dBc/Hz
–50
PHASE NOISE – dBc/Hz
FREQUNIT
GHZ
KEYWORD
IMPEDANCEOHMS
R
50
–15
–20
–25
TA = –40ⴗC
–30
–70
–80
–90
–100
–110
–35
TA = ⴙ85ⴗC
–40
–45
–120
TA = ⴙ25ⴗC
0
0.5
–130
1.0
1.5
2.0
2.5
3.0
RF INPUT FREQUENCY – GHz
3.5
–140
100Hz
4.0
Figure 2. Input Sensitivity (ADF4118)
0
REFERENCE
LEVEL = –4.2dBm
–10
–20
VDD = 3V, VP = 5V
–20
PFD FREQUENCY = 200kHz
–30
LOOP BANDWIDTH = 20kHz
RES. BANDWIDTH = 10Hz
–40
VIDEO BANDWIDTH = 10Hz
SWEEP = 1.9 SECONDS
–50
VDD = 3V, VP = 5V
PFD FREQUENCY = 200kHz
LOOP BANDWIDTH = 20kHz
–30
REFERENCE
LEVEL = –3.8dBm
ICP = 1mA
–10
OUTPUT POWER – dB
OUTPUT POWER – dB
1MHz
Figure 5. ADF4118 Integrated Phase Noise (900 MHz,
200 kHz, 20 kHz, Typical Lock Time: 400 µ s)
0
AVERAGES = 22
–60
–90.2dBc/Hz
–70
–80
ICP = 1mA
RES. BANDWIDTH = 1kHz
–40
VIDEO BANDWIDTH = 1kHz
–50
SWEEP = 2.5 SECONDS
AVERAGES = 4
–60
–70
–91.5dBc
–80
–90
–100
FREQUENCY OFFSET FROM 900 MHz CARRIER
–90
–2kHz
–1kHz
900MHz
+1kHz
–100
+2kHz
Figure 3. ADF4118 Phase Noise (900 MHz, 200 kHz, 20 kHz)
–400kHz
–200kHz
900MHz
+200kHz
+400kHz
Figure 6. ADF4118 Reference Spurs (900 MHz, 200 kHz,
20 kHz)
–6–
REV. 0
ADF4116/ADF4117/ADF4118
0
REFERENCE
LEVEL = –4.2dBm
–10
–20
0
VDD = 3V, VP = 5V
ICP = 1mA
–10
PFD FREQUENCY = 200kHz
–20
–40
VIDEO BANDWIDTH = 1kHz
OUTPUT POWER – dB
OUTPUT POWER – dB
RES. BANDWIDTH = 1kHz
SWEEP = 2.5 SECONDS
–50
VDD = 3V, Vp = 5V
ICP = 5mA
PFD FREQUENCY = 30kHz
LOOP BANDWIDTH = 5kHz
LOOP BANDWIDTH = 35kHz
–30
REFERENCE
LEVEL = –7.0dBm
AVERAGES = 10
–60
–70
–30
RES. BANDWIDTH = 300Hz
–40
VIDEO BANDWIDTH = 300Hz
SWEEP = 4.2ms
–50
AVERAGES = 20
–60
–72.3dBc
–70
–90.67dBc
–80
–80
–90
–90
–100
–400kHz
–200kHz
900MHz
+200kHz
–100
+400kHz
Figure 7. ADF4118 Reference Spurs (900 MHz, 200 kHz,
35 kHz)
–60kHz
–30kHz
+30kHz
+60kHz
Figure 10. ADF4118 Reference Spurs (1750 MHz,
30 kHz, 3 kHz)
0
0
REFERENCE
LEVEL = –7.0dBm
–10
VDD = 3V, Vp = 5V
REFERENCE
LEVEL = –10.3dBm
–10
ICP = 1mA
PFD FREQUENCY = 30kHz
–20
ICP = 1mA
RES. BANDWIDTH = 10kHz
–40
VIDEO BANDWIDTH = 10kHz
OUTPUT POWER – dB
LOOP BANDWIDTH = 100kHz
–30
SWEEP = 477ms
–50
VDD = 3V, Vp = 5V
PFD FREQUENCY = 1MHz
–20
LOOP BANDWIDTH = 5kHz
OUTPUT POWER – dB
1750MHz
AVERAGES = 25
–60
–70
–30
RES. BANDWIDTH = 10Hz
VIDEO BANDWIDTH = 10Hz
–40
SWEEP = 1.9 SECONDS
–50
AVERAGES = 26
–60
–85.2dBc/Hz
–70
–71.5dBc/Hz
–80
–80
–90
–90
–100
–400kHz
–200kHz
1750MHz
+200kHz
–100
+400kHz
Figure 8. ADF4118 Phase Noise (1750 MHz, 30 kHz,
3 kHz)
10dB/DIVISION
–40
RL = –40dBc/Hz
–2kHz
RMS NOISE = 2.0ⴗ
10dB/DIVISION
–40
+2kHz
RL = –40dBc/Hz
RMS NOISE = 1.552ⴗ
1.55ⴗ rms
–60
PHASE NOISE – dBc/Hz
–60
PHASE NOISE – dBc/Hz
+1kHz
–50
2.0ⴗ rms
–70
–80
–90
–100
–110
–70
–80
–90
–100
–110
–120
–120
–130
–130
FREQUENCY OFFSET FROM 1.75GHz CARRIER
–140
100Hz
1MHz
Figure 9. ADF4118 Integrated Phase Noise (1750 MHz,
30 kHz, 3 kHz)
REV. 0
2800MHz
Figure 11. ADF4118 Phase Noise (2800 MHz, 1 MHz,
100 kHz)
–50
–140
100Hz
–1kHz
FREQUENCY OFFSET FROM 2.8 GHz CARRIER
1MHz
Figure 12. ADF4118 Integrated Phase Noise (2800 MHz,
1 MHz, 100 kHz)
–7–
ADF4116/ADF4117/ADF4118
–60
0
REFERENCE
LEVEL = –9.3dBm
–10
VDD = 3V, VP = 5V
–20
FIRST REFERENCE SPUR – dBc
PFD FREQUENCY = 1MHz
OUTPUT POWER – dB
LOOP BANDWIDTH = 100kHz
–30
RES. BANDWIDTH = 3kHz
VIDEO BANDWIDTH = 3kHz
–40
SWEEP = 1.4 SECONDS
–50
VDD = 3V
VP = 5V
ICP = 1mA
AVERAGES = 4
–60
–77.3dBc
–70
–80
–70
–80
–90
–90
–100
–2MHz
–1MHz
2800MHz
+1MHz
–100
–40
+2MHz
–20
0
20
40
60
80
100
TEMPERATURE – ⴗC
Figure 16. ADF4118 Reference Spurs vs. Temperature
(900 MHz, 200 kHz, 20 kHz)
Figure 13. ADF4118 Reference Spurs (2800 MHz, 1 MHz,
100 kHz)
5
–130
FIRST REFERENCE SPUR – dBc
–135
PHASE NOISE – dBc/Hz
–140
–145
–150
–155
–160
–165
–170
–175
VDD = 3V
VP = 5V
–5
VDD = 3V
VP = 5V
–15
–25
–35
–45
–55
–65
–75
–85
–95
–105
1
100
1000
10
PHASE DETECTOR FREQUENCY – kHz
10000
0
1
2
3
4
Figure 17. ADF4118 Reference Spurs (200 kHz) vs.
VTUNE (900 MHz, 200 kHz, 20 kHz)
Figure 14. ADF4118 Phase Noise (Referred to CP Output) vs. PFD Frequency
–60
–60
VDD = 3V
VP = 5V
VDD = 3V
VP = 5V
–70
PHASE NOISE – dBc/Hz
PHASE NOISE – dBc/Hz
5
TURNING VOLTAGE
–80
–70
–80
–90
–100
–40
–20
0
20
40
60
80
–90
100
0
20
40
60
80
100
TEMPERATURE – ⴗC
TEMPERATURE – ⴗC
Figure 18. ADF4118 Phase Noise vs. Temperature
(836 MHz, 30 kHz, 3 kHz)
Figure 15. ADF4118 Phase Noise vs. Temperature
(900 MHz, 200 kHz, 20 kHz)
–8–
REV. 0
ADF4116/ADF4117/ADF4118
3.0
VDD = 3V
VP = 5V
2.5
–70
2.0
DIDD – mA
FIRST REFERENCE SPUR – dBc
–60
–80
1.5
1.0
–90
–100
0.5
0
20
40
60
80
0.0
100
0
50
TEMPERATURE – ⴗC
Figure 19. ADF4118 Reference Spurs vs. Temperature
(836 MHz, 30 kHz, 3 kHz)
CIRCUIT DESCRIPTION
The reference input stage is shown below in Figure 21. SW1
and SW2 are normally-closed switches. SW3 is normally-open.
When power-down is initiated, SW3 is closed and SW1 and SW2
are opened. This ensures that there is no loading of the REFIN
pin on power-down.
100k⍀
SW2
Figure 20. DIDD vs. Prescaler Output Frequency
(ADF4116, ADF4117, ADF4118)
The A and B CMOS counters combine with the dual modulus
prescaler to allow a wide ranging division ratio in the PLL
feedback counter. The counters are specified to work when the
prescaler output is 200 MHz or less.
Pulse Swallow Function
fVCO = [(P × B) + A] × fREFIN/R
TO R COUNTER
BUFFER
SW1
fVCO
Output Frequency of external voltage controlled oscillator (VCO).
P
Preset modulus of dual modulus prescaler.
B
Preset Divide Ratio of binary 13-bit counter (3 to 8191).
A
Preset Divide Ratio of binary 5-bit swallow counter
(0 to 31).
SW3
NO
Figure 21. Reference Input Stage
RF INPUT STAGE
The RF input stage is shown in Figure 22. It is followed by a 2stage limiting amplifier to generate the CML clock levels needed
for the prescaler.
BIAS
GENERATOR
500⍀
200
The A and B counters, in conjunction with the dual modulus
prescaler make it possible to generate output frequencies which
are spaced only by the Reference Frequency divided by R. The
equation for the VCO frequency is as follows:
POWER-DOWN
CONTROL
REFIN NC
150
A AND B COUNTERS
REFERENCE INPUT SECTION
NC
100
PRESCALER OUTPUT FREQUENCY – MHz
fREFIN Output frequency of the external reference frequency
oscillator.
R
1.6V
AVDD
500⍀
Preset divide ratio of binary 14-bit programmable reference counter (1 to 16383).
R COUNTER
The 14-bit R counter allows the input reference frequency to be
divided down to produce the input clock to the phase frequency
detector (PFD). Division ratios from 1 to 16,383 are allowed.
RFINA
RFINB
N = BP + A
AGND
13-BIT B
COUNTER
Figure 22. RF Input Stage
FROM RF
INPUT STAGE
PRESCALER (P/P + 1)
The dual modulus prescale (P/P + 1), along with the A and B
counters, enables the large division ratio, N, to be realized, (N =
PB + A). The dual-modulus prescaler takes the CML clock
from the RF input stage and divides it down to a manageable
frequency for the CMOS A and B counters. The prescaler is
programmable. It can be set in software to 8/9 for the
ADF4116, and set to 32/33 for the ADF4117 and ADF4118.
It is based on a synchronous 4/5 core.
REV. 0
PRESCALER
P/P + 1
MODULUS
CONTROL
LOAD
LOAD
5-BIT A
COUNTER
Figure 23. A and B Counters
–9–
TO PFD
ADF4116/ADF4117/ADF4118
PHASE FREQUENCY DETECTOR (PFD) AND CHARGE
PUMP
DVDD
The PFD takes inputs from the R counter and N counter and
produces an output proportional to the phase and frequency
difference between them. Figure 24 is a simplified schematic.
The PFD includes a fixed delay element which sets the width of
the antibacklash pulse. This is typically 3 ns. This pulse ensures
that there is no dead zone in the PFD transfer function and
gives a consistent reference spur level.
VP
HI
D1
Q1
ANALOG LOCK DETECT
DIGITAL LOCK DETECT
R COUNTER OUTPUT
N COUNTER OUTPUT
SDOUT
MUX
MUXOUT
CONTROL
DGND
CHARGE
PUMP
Figure 25. MUXOUT Circuit
UP
Lock Detect
U1
MUXOUT can be programmed for two types of lock detect:
Digital Lock Detect and Analog Lock Detect.
CLR1
Digital Lock Detect is active high. It is set high when the phase
error on three consecutive phase detector cycles is less than 15 ns.
It will stay set high until a phase error of greater than 25 ns is
detected on any subsequent PD cycle.
R DIVIDER
CP
DELAY
U3
The N-channel open-drain analog lock detect should be operated with an external pull-up resistor of 10 kΩ nominal. When
lock has been detected it is high with narrow low-going pulses.
CLR2
HI
D2
Q2
DOWN
INPUT SHIFT REGISTER
The ADF4116 family digital section includes a 21-bit input shift
register, a 14-bit R counter and a˙`-bit N counter, comprising
a 5-bit A counter and a 13-bit B counter. Data is clocked into
the 21-bit shift register on each rising edge of CLK. The data is
clocked in MSB first. Data is transferred from the shift register
to one of four latches on the rising edge of LE. The destination
latch is determined by the state of the two control bits (C2, C1)
in the shift register. These are the two LSBs DB1, DB0 as
shown in the timing diagram of Figure 1. The truth table for
these bits is shown in Table VII. Table II shows a summary
of how the latches are programmed.
U2
N DIVIDER
CP GND
R DIVIDER
N DIVIDER
CP OUTPUT
Figure 24. PFD Simplified Schematic and Timing (In Lock)
Table II. C2, C1 Truth Table
MUXOUT AND LOCK DETECT
The output multiplexer on the ADF4116 family allows the
user to access various internal points on the chip. The state of
MUXOUT is controlled by M3, M2 and M1 in the function
latch. Table VI shows the full truth table. Figure 25 shows the
MUXOUT section in block diagram form.
–10–
Control Bits
C2
C1
Data Latch
0
0
1
1
R Counter
N Counter (A and B)
Function Latch
Initialization Latch
0
1
0
1
REV. 0
ADF4116/ADF4117/ADF4118
Table III. ADF4116 Family Latch Summary
LOCK
DETECT
PRECISION
REFERENCE COUNTER LATCH
TEST
MODE BITS
CONTROL
BITS
14-BIT REFERENCE COUNTER, R
DB20
DB19
DB18
DB17
DB16
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
LDP
T4
T3
T2
T1
R14
R13
R12
R11
R10
R9
R8
R7
R6
R5
R4
R3
R2
R1
C2 (0)
C1 (0)
CP GAIN
AB COUNTER LATCH
13-BIT B COUNTER
CONTROL
BITS
5-BIT A COUNTER
DB20
DB19
DB18
DB17
DB16
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
G1
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
A5
A4
A3
A2
A1
C2 (0)
C1 (1)
PD
POLARITY
POWERDOWN 1
COUNT
RESETER
DB20
DB19
DB18
DB17
DB16
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
X
PD2
X
X
X
TC4
TC3
TC2
TC1
F6
X
F4
F3
F2
M3
M2
M1
PD1
F1
C2 (1)
C1 (0)
POWERDOWN 1
COUNT
RESETER
POWERDOWN 2
CP
THREESTATE
FASTLOCK
ENABLE
RESERVED
FASTLOCK
MODE
RESERVED
FUNCTION LATCH
TIMER COUNTER
CONTROL
RESERVED
MUXOUT
CONTROL
CONTROL
BITS
REV. 0
CP
THREESTATE
PD
POLARITY
DB19
DB18
DB17
DB16
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
PD2
X
X
X
TC4
TC3
TC2
TC1
F6
X
F4
F3
F2
M3
M2
M1
PD1
F1
C2 (1)
C1 (1)
FASTLOCK
MODE
FASTLOCK
ENABLE
X
RESERVED
DB20
POWERDOWN 2
RESERVED
INITIALIZATION LATCH
TIMER COUNTER
CONTROL
RESERVED
–11–
MUXOUT
CONTROL
CONTROL
BITS
ADF4116/ADF4117/ADF4118
LOCK
DETECT
PRECISION
Table IV. Reference Counter Latch Map
TEST
MODE BITS
CONTROL
BITS
14-BIT REFERENCE COUNTER, R
DB20
DB19
DB18
DB17
DB16
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
LDP
T4
T3
T2
T1
R14
R13
R12
R11
R10
R9
R8
R7
R6
R5
R4
R3
R2
R1
C2 (0)
C1 (0)
R14
R13
R12
••••••••••
R3
R2
R1
DIVIDE RATIO
0
0
0
••••••••••
0
0
1
1
0
0
0
••••••••••
0
1
0
2
0
0
0
••••••••••
0
1
1
3
0
0
0
••••••••••
1
0
0
4
•
•
•
••••••••••
•
•
•
•
•
•
•
••••••••••
•
•
•
•
•
•
•
••••••••••
•
•
•
•
1
1
1
••••••••••
1
0
0
163 80
1
1
1
••••••••••
1
0
1
163 81
1
1
1
••••••••••
1
1
0
163 82
1
1
1
••••••••••
1
1
1
163 83
TEST MODE BITS SHOULD
BE SET TO 0000 FOR
NORMAL OPERATION
LDP
0
1
OPERATION
3 CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN
15ns MUST OCCUR BEFORE LOCK DETECT IS SET.
5 CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN
15ns MUST OCCUR BEFORE LOCK DETECT IS SET.
–12–
REV. 0
ADF4116/ADF4117/ADF4118
CP GAIN
Table V. AB Counter Latch Map
13-BIT B COUNTER
CONTROL
BITS
5-BIT A COUNTER
DB20
DB19
DB18
DB17
DB16
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
G1
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
A5
A4
A3
A2
A1
C2 (0)
C1 (1)
ADF4116
ADF4117/ADF4118
LDP
A4
A3
A2
A1
A COUNTER
DIVIDE RATIO
X
X
0
0
0
0
X
X
0
0
1
1
•
•
•
•
•
•
•
•
•
•
•
•
X
X
1
1
0
6
X
X
1
1
1
7
A5
A4
A3
A2
A1
A COUNTER
DIVIDE RATIO
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
1
0
2
•
•
•
•
•
•
•
•
•
•
•
•
1
1
1
0
1
29
1
1
1
1
0
30
1
1
1
1
1
31
B13
B12
B11
••••••••••
B3
B2
B1
B COUNTER DIVIDE RATIO
0
0
0
••••••••••
0
0
1
NOT ALLOWED
0
0
0
••••••••••
0
1
0
NOT ALLOWED
0
0
0
••••••••••
0
1
1
3
0
0
0
••••••••••
1
0
0
4
•
•
•
••••••••••
•
•
•
•
•
•
•
••••••••••
•
•
•
•
•
•
•
••••••••••
•
•
•
•
1
1
1
••••••••••
1
0
0
8188
1
1
1
••••••••••
1
0
1
8189
1
1
1
••••••••••
1
1
0
8190
1
1
1
••••••••••
1
1
1
8191
CURRENT SETTINGS
0
250␮A
1
1mA
REV. 0
A5
N = BP + A, P IS PRESCALER VALUE. B MUST BE GREATER
THAN OR EQUAL TO A. FOR CONTINUOUSLY ADJACENT
VALUES OF NX FREF, NMIN IS (P2-P).
–13–
ADF4116/ADF4117/ADF4118
CP
THREESTATE
PD
POLARITY
POWERDOWN 1
COUNT
RESETER
DB18
DB17
DB16
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
X
PD2
X
X
X
TC4
TC3
TC2
TC1
F6
X
F4
F3
F2
M3
M2
M1
PD1
F1
C2 (1)
C1 (0)
FASTLOCK
ENABLE
DB19
TIMER COUNTER
CONTROL
RESERVED
RESERVED
POWERDOWN 2
DB20
FASTLOCK
MODE
RESERVED
Table VI. Function Latch Map
MUXOUT
CONTROL
COUNTER
OPERATION
F1
CE PIN PD2 PD1
0
X
X
CONTROL
BITS
0
NORMAL
1
R, A, B COUNTERS
HELD IN RESET
MODE
ASYNCHRONOUS POWER-DOWN
M3
M2
M1
0
0
0
THREE-STATE OUTPUT
OUTPUT
1
X
0
NORMAL OPERATION
1
0
1
ASYNCHRONOUS POWER-DOWN
0
0
1
DIGITAL LOCK DETECT
(ACTIVE HIGH)
1
1
1
SYNCHRONOUS POWER-DOWN
0
1
0
N DIVIDER OUTPUT
0
1
1
AVDD
1
0
0
R DIVIDER OUTPUT
1
0
1
ANALOG LOCK DETECT
(N CHANNEL OPEN DRAIN)
1
1
0
SERIAL DATA OUTPUT
(INVERSE POLARITY OF
SERIAL DATA INPUT)
1
1
1
DGND
PD POLARITY
0
NEGATIVE
1
POSITIVE
F3
CHARGE PUMP
OUTPUT
0
NORMAL
1
3-STATE
F4
F6
0
X
FASTLOCK DISABLED
1
0
FASTLOCK MODE 1
1
1
TC1
F2
FASTLOCK MODE
FASTLOCK MODE 2
TIMEOUT
(PFD CYCLES)
TC4
TC3
TC2
0
0
0
0
0
0
0
1
7
0
0
1
0
11
0
0
1
1
15
0
1
0
0
19
0
1
0
1
23
0
1
1
0
27
0
1
1
1
31
1
0
0
0
35
1
0
0
1
39
1
0
1
0
43
1
0
1
1
47
1
1
0
0
51
1
1
0
1
55
1
1
1
0
59
1
1
1
1
63
3
–14–
REV. 0
ADF4116/ADF4117/ADF4118
RESERVED
POWERDOWN 2
FASTLOCK
MODE
RESERVED
FASTLOCK
ENABLE
CP
THREESTATE
PD
POLARITY
POWERDOWN 1
COUNT
RESETER
Table VII. Initialization Latch Map
DB20
DB19
DB18
DB17
DB16
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
X
PD2
X
X
X
TC4
TC3
TC2
TC1
F6
X
F4
F3
F2
M3
M2
M1
PD1
F1
C2 (1)
C1 (1)
RESERVED
TIMER COUNTER
CONTROL
MUXOUT
CONTROL
COUNTER
OPERATION
F1
CE PIN PD2 PD1
CONTROL
BITS
0
NORMAL
1
R, A, B COUNTERS
HELD IN RESET
M3
M2
M1
0
0
0
THREE-STATE OUTPUT
0
0
1
DIGITAL LOCK DETECT
(ACTIVE HIGH)
OUTPUT
MODE
0
X
X
ASYNCHRONOUS POWER-DOWN
1
X
0
NORMAL OPERATION
1
0
1
ASYNCHRONOUS POWER-DOWN
0
1
0
N DIVIDER OUTPUT
1
1
1
SYNCHRONOUS POWER-DOWN
0
1
1
AVDD
1
0
0
R DIVIDER OUTPUT
1
0
1
ANALOG LOCK DETECT
(N CHANNEL OPEN DRAIN)
1
1
0
SERIAL DATA OUTPUT
(INVERSE POLARITY OF
SERIAL DATA INPUT)
1
1
1
DGND
F3
REV. 0
FASTLOCK MODE
FASTLOCK DISABLED
1
0
FASTLOCK MODE 1
1
1
FASTLOCK MODE 2
TIMEOUT
(PFD CYCLES)
0
0
0
0
0
0
0
1
7
0
0
1
0
11
0
0
1
1
15
0
1
0
0
19
0
1
0
1
23
0
1
1
0
27
0
1
1
1
31
1
0
0
0
35
1
0
0
1
39
1
0
1
0
43
1
0
1
1
47
1
1
0
0
51
1
1
0
1
55
1
1
1
0
59
1
1
1
1
63
3
–15–
CHARGE PUMP
OUTPUT
THREE-STATE
X
TC1
POSITIVE
NORMAL
F6
TC2
NEGATIVE
1
1
0
TC3
PD POLARITY
0
0
F4
TC4
F2
ADF4116/ADF4117/ADF4118
THE FUNCTION LATCH
Fastlock Mode Bit
With C2, C1 set to 1, 0, the on-chip function latch will be programmed. Table VI shows the input data format for programming
the Function Latch.
DB11 of the Function Latch is the Fastlock Mode bit. When
Fastlock is enabled, this bit determines which Fastlock Mode is
used. If the Fastlock Mode bit is “0” then Fastlock Mode 1 is
selected and if the Fastlock Mode bit is “1,” then Fastlock
Mode 2 is selected.
Counter Reset
DB2 (F1) is the counter reset bit. When this is “1,” the R counter
and the A, B counters are reset. For normal operation this bit
should be “0.” Upon powering up, the F1 bit needs to be disabled,
the N counter resumes counting in “close” alignment with the R counter.
(The maximum error is one prescaler cycle.)
DB3 (PD1) and DB19 (PD2) on the ADF4116 family, provide
programmable power-down modes. They are enabled by the
CE pin.
When the CE pin is low, the device is immediately disabled
regardless of the states of PD2, PD1.
In the programmed asynchronous power-down, the device powers down immediately after latching a “1” into bit PD1, with the
condition that PD2 has been loaded with a “0.”
In the programmed synchronous power-down, the device power
down is gated by the charge pump to prevent unwanted frequency jumps. Once the power-down is enabled by writing a
“1” into bit PD1 (on condition that a “1” has also been loaded
to PD2), then the device will go into power-down after the first
successive charge pump event.
When a power down is activated (either synchronous or asynchronous mode including CE-pin-activated power down), the
following events occur:
All active dc current paths are removed.
The charge pump is forced into three-state mode.
The RFIN input is debiased.
In the ADF4116 family, the output level of FLO is programmed
to a low state and the charge pump current is switched to the high
value (1 mA). FLO is used to switch a resistor in the loop filter and
ensure stability while in Fastlock by altering the loop bandwidth.
The device enters Fastlock by having a “1” written to the CP
Gain bit in the N register. The device exits Fastlock under the
control of the Timer Counter. After the timeout period determined by the value in TC4–TC1, the CP Gain bit in the N
register is automatically reset to “0” and the device reverts to
normal mode instead of Fastlock.
The user must make sure that Fastlock is enabled. Set DB9 of the
ADF4116 family to “1.” The user must also choose which Fastlock
Mode to use. As discussed in the previous section, Fastlock
Mode 2 uses the values in the Timer Counter to determine the
timeout period before reverting to normal mode operation after
Fastlock. Fastlock Mode 2 is chosen by setting DB11 of the
ADF4116 family to “1.”
The oscillator input buffer circuitry is disabled.
The input register remains active and capable of loading and
latching data.
MUXOUT Control
The on-chip multiplexer is controlled by M3, M2, M1 on the
ADF4116 family. Table VI shows the truth table.
Phase Detector Polarity
DB7 (F2) of the function latch sets the Phase Detector Polarity.
When the VCO characteristics are positive this should be set to
“1.” When they are negative it should be set to “0.”
DB9 of the Function Latch is the Fastlock Enable Bit. Only
when this is “1” is Fastlock enabled.
Fastlock Mode 2
When using the Fastlock feature with the ADF4116 family, the
normal sequence of events is as follows:
The digital clock detect circuitry is reset.
Fastlock Enable Bit
The device enters Fastlock by having a “1” written to the CP
Gain bit in the N register. The device exits Fastlock by having a
“0” written to the CP Gain bit in the N register.
Timer Counter Control
In the ADF4116 family, the user has the option of switching
between two charge pump current values to speed up locking to
a new frequency.
The R, N and timeout counters are forced to their load state
conditions.
This bit puts the charge pump into three-state mode when programmed to a “1.” It should be set to “0” for normal operation.
Fastlock Mode 1
In the ADF4116 family, the output level of FLO is programmed
to a low state and the charge pump current is switched to the
high value (1 mA). FLO is used to switch a resistor in the loop
filter and ensure stability while in Fastlock by altering the loop
bandwidth.
Power-Down
Charge Pump Three-State
If Fastlock is not enabled (DB9 = “0”), then DB11 (ADF4116)
determines the state of the FLO output. FLO state will be the
same as that programmed to DB11.
The user must also decide how long they want the high current
(1 mA) to stay active before reverting to low current (250 µA).
This is controlled by the Timer Counter Control Bits DB14 to
DB11 (TC4–TC1) in the Function Latch. The truth table is
given in Table VI.
Now, when the user wishes to program a new output frequency,
they can simply program the A, B counter latch with new values
for A and B. At the same time they can set the CP Gain bit to a
“1,” which sets the charge pump 1 mA for a period of time determined by TC4–TC1. When this time is up, the charge pump
current reverts to 250 µA. At the same time the CP Gain Bit in
the A, B Counter latch is reset to 0 and is now ready for the
next time that the user wishes to change the frequency again.
–16–
REV. 0
ADF4116/ADF4117/ADF4118
The Initialization Latch
The CE Pin Method
When C2, C1 = 1, 1 then the Initialization Latch is programmed.
This is essentially the same as the Function Latch (programmed
when C2, C1 = 1, 0).
Apply VDD.
However, when the Initialization Latch is programmed there is a
additional internal reset pulse applied to the R and N counters.
This pulse ensures that the N counter is at load point when the
N counter data is latched and the device will begin counting in
close phase alignment.
If the Latch is programmed for synchronous power-down (CE
pin is High; PD1 bit is High; PD2 bit is Low), the internal pulse
also triggers this power-down. The prescaler reference and the
oscillator input buffer are unaffected by the internal reset pulse and
so close phase alignment is maintained when counting resumes.
When the first N counter data is latched after initialization, the
internal reset pulse is again activated. However, successive N
counter loads after this will not trigger the internal reset pulse.
Bring CE low to put the device into power-down. This is an
asynchronous power-down in that it happens immediately.
Program the Function Latch (10). Program the R Counter
Latch (00). Program the N Counter Latch (01). Bring CE high
to take the device out of power-down. The R and N counter will
now resume counting in close alignment.
Note that after CE goes high, a duration of 1 µs may be required
for the prescaler bandgap voltage and oscillator input buffer bias
to reach steady state.
CE can be used to power the device up and down in order to
check for channel activity. The input register does not need to
be reprogrammed each time the device is disabled and enabled
as long as it has been programmed at least once after VCC was
initially applied.
The Counter Reset Method
Device Programming After Initial Power-Up
Apply VDD.
After initially powering up the device, there are three ways to
program the device.
Do a Function Latch Load (“10” in 2 LSBs). As part of this,
load “1” to the F1 bit. This enables the counter reset. Do an R
Counter Load (“00” in 2 LSBs). Do an N Counter Load (“01”
in 2 LSBs). Do a Function Latch Load (“10” in 2 LSBs). As
part of this, load “0” to the F1 bit. This disables the counter reset.
Initialization Latch Method
Apply VDD.
Program the Initialization Latch (“11” in 2 LSBs of input word).
Make sure that F1 bit is programmed to “0.” Then do an R load
(“00” in 2 LSBs). Then do an N load (“01” in 2 LSBs). When the
Initialization Latch is loaded, the following occurs:
1. The function latch contents are loaded.
2. An internal pulse resets the R, N and timeout counters to
load state conditions and also three-states the charge pump.
Note that the prescaler bandgap reference and the oscillator
input buffer are unaffected by the internal reset pulse,
allowing close phase alignment when counting resumes.
This sequence provides the same close alignment as the initialization method. It offers direct control over the internal reset.
Note that counter reset holds the counters at load point and
three-states the charge pump, but does not trigger synchronous
power-down. The counter reset method requires an extra function latch load compared to the initialization latch method.
3. Latching the first N counter data after the initialization word
will activate the same internal reset pulse. Successive N loads
will not trigger the internal reset pulse unless there is another
initialization.
REV. 0
–17–
ADF4116/ADF4117/ADF4118
APPLICATIONS SECTION
Local Oscillator for GSM Base Station Transmitter
SHUTDOWN CIRCUIT
The attached circuit in Figure 27 shows how to shut down both
the ADF4116 family and the accompanying VCO. The ADG702
switch goes open circuit when a Logic 1 is applied to the IN
input. The low-cost switch is available in both SOT-23 and
micro SOIC packages.
Figure 26 shows the ADF4117/ADF4118 being used with a
VCO to produce the LO for a GSM base station transmitter.
The reference input signal is applied to the circuit at FREFIN
and, in this case, is terminated in 50 Ω. Typical GSM system
would have a 13 MHz TCXO driving the Reference Input
without any 50 Ω termination. In order to have a channel
spacing of 200 kHz (the GSM standard), the reference input
must be divided by 65, using the on-chip reference divider of
the ADF4117/ADF1118.
DIRECT CONVERSION MODULATOR
In some applications a direct conversion architecture can be used
in base station transmitters. Figure 28 shows the combination
available from ADI to implement this solution.
The circuit diagram shows the AD9761 being used with the
AD8346. The use of dual integrated DACs such as the AD9761
with specified ± 0.02 dB and ± 0.004 dB gain and offset matching characteristics ensures minimum error contribution (over
temperature) from this portion of the signal chain.
The charge pump output of the ADF4117/ADF1118 (Pin 2)
drives the loop filter. In calculating the loop filter component
values, a number of items need to be considered. In this example,
the loop filter was designed so that the overall phase margin for
the system would be 45 degrees. Other PLL system specifications are given below:
The Local Oscillator (LO) is implemented using the ADF4117/
ADF4118. In this case, the OSC 3B1-13M0 provides the
stable 13 MHz reference frequency. The system is designed
for a 200 kHz channel spacing and an output center frequency
of 1960 MHz. The target application is a WCDMA base station transmitter. Typical phase noise performance from this LO
is –85 dBc/Hz at a 1 kHz offset. The LO port of the AD8346 is
driven in single-ended fashion. LOIN is ac-coupled to ground
with the 100 pF capacitor and LOIP is driven through the accoupling capacitor from a 50 Ω source. An LO drive level of
between –6 dBm and –12 dBm is required. The circuit of Figure
28 gives a typical level of –8 dBm.
KD = 1 mA
KV = 12 MHz/V
Loop Bandwidth = 20 kHz
FREF = 200 kHz
N = 4500
Extra Reference Spur Attenuation = 10 dB
All of these specifications are needed and used to come up with
the loop filter components values shown in Figure 27.
The loop filter output drives the VCO, which, in turn, is fed
back to the RF input of the PLL synthesizer and also drives
the RF Output terminal. A T-circuit configuration provides
50 Ω matching between the VCO output, the RF output and
the RFIN terminal of the synthesizer.
The RF output is designed to drive a 50 Ω load but must be
ac-coupled as shown in Figure 28. If the I and Q inputs are driven
in quadrature by 2 V p-p signals, the resulting output power will
be around –10 dBm.
In a PLL system, it is important to know when the system is in
lock. In Figure 26, this is accomplished by using the MUXOUT
signal from the synthesizer. The MUXOUT pin can be programmed to monitor various internal signals in the synthesizer.
One of these is the LD or lock-detect signal.
VDD
RFOUT
VP
100pF
7
15 16
AVDD DVDD VP
2
1000pF 1000pF
CP
REFIN
8
51⍀
FREFIN
VCC
3.3k⍀
27k⍀
0.15nF
620pF
VCO190-902T
100pF 18⍀
18⍀
18⍀
FLO
10k⍀
1.5nF
14
CE
LOCK
MUXOUT
CLK
DETECT
DATA
100pF
LE
6
RFINA
3
4
DGND
AGND
RFINB 5
CPGND
SPI-COMPATIBLE SERIAL BUS
ADF4117/
ADF4118
9
51⍀
100pF
DECOUPLING CAPACITORS (10␮F/10pF) ON AVDD, DVDD, VP OF THE
ADF4117/ADF4118 AND ON VCC OF THE VCO190-902T HAVE BEEN
OMITTED FROM THE DIAGRAM TO AID CLARITY.
Figure 26. Local Oscillator for GSM Base Station
–18–
REV. 0
ADF4116/ADF4117/ADF4118
VP
POWER-DOWN CONTROL
VDD
S
GND
D
7
15 16
AVDD DVDD VP CE
CP
8 REF
IN
FREFIN
DGND
AGND
100pF
18⍀
VCO
18⍀
18⍀
10k⍀
RFINA
CPGND
LOOP
FILTER
GND
ADF4116/
ADF4117/
ADF4118
4
100pF
VCC
2
1
FLO
3
RFOUT
IN ADG702
VDD
RFINB
6
100pF
5
51⍀
100pF
9
DECOUPLING CAPACITORS AND INTERFACE SIGNALS HAVE
BEEN OMITTED FROM THE DIAGRAM TO AID CLARITY.
Figure 27. Local Oscillator Shutdown Circuit
0.1␮F
REFIO
IOUTA
IOUTB
MODULATED
DIGITAL
DATA
IBBP
LOW-PASS
FILTER
AD9761
TXDAC
QBBP
LOW-PASS
FILTER
QOUTB
QBBP
2k⍀
LOIN
LOIP
100pF
OSC 3B1-13M0
REFIN
SERIAL
DIGITAL
NTERFACE
100pF
10k⍀
CP
1k⍀
ADF4118
680pF
VCO190-1960T
18pF
100pF 18⍀
6.8nF
RFINB
100pF
18⍀
RSET
TCXO
RFOUT
AD8346
QOUTA
FS ADJ
100pF
VOUT
IBBP
18⍀
RFINA
100pF
51⍀
POWER SUPPLY CONNECTIONS AND DECOUPLING CAPACITORS
ARE OMITTED FROM DIAGRAM FOR CLARITY.
Figure 28. Direct Conversion Transmitter Solution
INTERFACING
The ADF4116 family has a simple SPI-compatible serial interface for writing to the device. SCLK, SDATA and LE control
the data transfer. When LE (Latch Enable) goes high, the 24 bits
which have been clocked into the input register on each rising
edge of SCLK will get transferred to the appropriate latch. See
Figure 1 for the Timing Diagram and Table II for the Latch
Truth Table.
REV. 0
The maximum allowable serial clock rate is 20 MHz. This means
that the maximum update rate possible for the device is 833 kHz or
one update every 1.2 microseconds. This is certainly more than
adequate for systems which will have typical lock times in hundreds of microseconds.
–19–
ADF4116/ADF4117/ADF4118
Figure 29 shows the interface between the ADF4116 family and
the ADuC812 microconverter. Since the ADuC812 is based on
an 8051 core, this interface can be used with any 8051-based
microcontroller. The microconverter is set up for SPI Master
Mode with CPHA = 0. To initiate the operation, the I/O port
driving LE is brought low. Each latch of the ADF4116 family
needs a 24-bit word. This is accomplished by writing three 8-bit
bytes from the microconverter to the device. When the third
byte has been written the LE input should be brought high to
complete the transfer.
ADSP-2181 Interface
Figure 30 shows the interface between the ADF4116 family and
the ADSP-21xx Digital Signal Processor. The ADF4116 family
needs a 21-bit serial word for each latch write. The easiest way
to accomplish this using the ADSP-21xx family is to use the
Autobuffered Transmit Mode of operation with Alternate Framing. This provides a means for transmitting an entire block of
serial data before an interrupt is generated.
SCLK
SCLOCK
LE
I/O PORTS
SCLK
SCLK
SDATA
MOSI
ADuC812
When operating in the mode described, the maximum SCLOCK
rate of the ADuC812 is 4 MHz. This means that the maximum
rate at which the output frequency can be changed will be 166 kHz.
SDATA
DT
ADSP-21xx
ADF4116/
ADF4117/
ADF4118
C3767–5–4/00 (rev. 0)
ADuC812 Interface
TFS
ADF4116/
ADF4117/
ADF4118
LE
CE
CE
I/O FLAGS
MUXOUT
(LOCK DETECT)
MUXOUT
(LOCK DETECT)
Figure 29. ADuC812 to ADF4116 Family Interface
Figure 30. ADSP-21xx to ADF4116 Family Interface
On first applying power to the ADF4116 family, it needs three
writes (one each to the R counter latch, the N counter latch and
the initialization latch) for the output to become active.
Set up the word length for 8 bits and use three memory locations for each 24-bit word. To program each 21-bit latch, store
the three 8-bit bytes, enable the Autobuffered mode and then
write to the transmit register of the DSP. This last operation
initiates the autobuffer transfer.
I/O port lines on the ADuC812 are also used to control powerdown (CE input) and to detect lock (MUXOUT configured as
lock detect and polled by the port input).
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
Chip Scale
(CP-20)
0.159 (4.05)
0.157 (4.00)
0.156 (3.95)
TOP VIEW
0.039 (1.00)
0.035 (0.90)
0.031 (0.80)
SEATING 0.0079 (0.20)
PLANE
REF
0.201 (5.10)
0.193 (4.90)
0.079 (2.0) REF
0.014 (0.35) ⴛ 45°
0.018 (0.45)
0.016 (0.40)
0.014 (0.35)
16
15
20
16
1
11
10
0.0083 (0.211)
0.0079 (0.200)
0.0077 (0.195)
0.177 (4.50)
0.169 (4.30)
0.256 (6.50)
0.246 (6.25)
5
6
1
8
PIN 1
BOTTOM VIEW
(ROTATED 180ⴗ)
0.006 (0.15)
0.002 (0.05)
LEAD OPTION
DETAIL E
SEATING
PLANE
0.011 (0.275)
0.010 (0.250)
0.009 (0.225)
0.018 (0.45)
0.016 (0.40)
0.014 (0.35)
9
0.079
(2.0)
REF
DETAIL E
0.020 (0.5) REF
LEAD PITCH
0.0433 (1.10)
MAX
0.0256 (0.65) 0.0118 (0.30)
BSC
0.0075 (0.19)
0.0079 (0.20)
0.0035 (0.090)
8ⴗ
0ⴗ
0.028 (0.70)
0.020 (0.50)
0.0059
(0.15)
REF
0.0059 (0.15)
REF
CONTROLLING DIMENSIONS ARE IN MILLIMETERS
–20–
REV. 0
PRINTED IN U.S.A.
0.159 (4.05)
0.157 (4.00)
0.156 (3.95)
Thin Shrink Small Outline
(RU-16)