Fairchild CD4724BCN 8-bit addressable latch Datasheet

Revised January 1999
CD4724BC
8-Bit Addressable Latch
General Description
The CD4724BC is an 8-bit addressable latch with three
address inputs (A0–A2), an active low enable input (E),
active high clear input (CL), a data input (D) and eight outputs (Q0–Q7).
Data is entered into a particular bit in the latch when that is
addressed by the address inputs and the enable (E) is
LOW. Data entry is inhibited when enable (E) is HIGH.
When clear (CL) and enable (E) are HIGH, all outputs are
LOW. When clear (CL) is HIGH and enable (E) is LOW, the
channel demultiplexing occurs. The bit that is addressed
has an active output which follows the data input while all
unaddressed bits are held LOW. When operating in the
addressable latch mode (E = CL = LOW), changing more
than one bit of the address could impose a transient wrong
address. Therefore, this should only be done while in the
memory mode (E = HIGH, CL = LOW).
Features
■ Wide supply voltage range:
■ High noise immunity:
3.0V to 15V
0.45 VDD (typ.)
■ Low power TTL compatibility:
fan out of 2 driving 74L or 1 driving 74LS
■ Serial to parallel capability
■ Storage register capability
■ Random (addressable) data entry
■ Active high demultiplexing capability
■ Common active high clear
Ordering Code:
Package Number
Package Description
CD4724BCM
Order Number
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body
CD4724BCN
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Truth Table
Pin Assignments for DIP and SOIC
Mode Selection
E
CL
Addressed
Unaddressed
Latch
Latch
L
L
Follows Data
Holds Previous
Data
H
L
Hold Previous Holds Previous
Data
Data
Mode
Addressable
Latch
Memory
L
H Follows Data
Reset to “0”
Demultiplexer
H
H Reset to “0”
Reset to “0”
Clear
Top View
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DS006003.prf
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CD4724BC 8-Bit Addressable Latch
October 1987
CD4724BC
Logic Diagram
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2
Recommended Operating
Conditions (Note 2)
(Note 2)
−0.5V to +18 VDC
DC Supply Voltage (VDD )
Input Voltage (VIN)
DC Supply Voltage (VDD)
−0.5V to VDD +0.5 VDC
−65°C to +150°C
Storage Temperature (TS)
700 mW
Small Outline
500 mW
Symbol
IDD
VOL
Parameter
VIH
IOL
IOH
IIN
−40°C
Conditions
Min
Max
+25°C
Min
+85°C
Typ
Max
Min
Max
Units
Quiescent Device
VDD = 5V
20
0.02
20
150
µA
VDD = 10V
40
0.02
40
300
µA
VDD = 15V
80
0.02
80
600
µA
LOW Level
HIGH Level
Output Voltage
VIL
(Note 2)
Current
Output Voltage
VOH
Note 2: VSS = 0V unless otherwise specified.
260°C
DC Electrical Characteristics
−40°C to +85°C
Note 1: “Absolute Maximum Ratings” are those values beyond which the
safety of the device cannot be guaranteed; they are not meant to imply that
the devices should be operated at these limits. The tables of “Recommended Operating Conditions” and Electrical Characteristics” provide conditions for actual device operation.
Lead Temperature (TL)
(Soldering, 10 seconds)
0V to VDD VDC
Operating Temperature Range (TA)
Power Dissipation (PD)
Dual-In-Line
3.0V to 15 VDC
Input Voltage (VIN)
|IO| ≤ 1 µA
VDD = 5V
0.05
0
0.05
0.05
V
VDD = 10V
0.05
0
0.05
0.05
V
VDD = 15V
0.05
0
0.05
0.05
V
|IO| ≤ 1 µA
VDD = 5V
4.95
4.95
5.0
4.95
V
VDD = 10V
9.95
9.95
10
9.95
V
VDD = 15V
14.95
14.95
15
14.95
V
LOW Level
VDD = 5V, VO = 0.5V or 4.5V
Input Voltage
VDD = 10V, VO = 1V or 9V
3.0
4.5
3.0
3.0
V
VDD = 15V, VO = 1.5V or 13.5V
4.0
6.75
4.0
4.0
V
1.5
2.25
1.5
1.5
V
HIGH Level
VDD = 5V, VO = 0.5V or 4.5V
3.5
3.5
2.75
3.5
V
Input Voltage
VDD = 10V, VO = 1V or 9V
7.0
7.0
5.5
7.0
V
VDD = 15V, VO = 1.5V or 13.5V
11.0
11.0
8.25
11.0
V
LOW Level Output
VDD = 5V, VO = 0.4V
0.52
0.44
0.88
0.36
mA
Current
VDD = 10V, VO = 0.5V
1.3
1.1
2.25
0.9
mA
(Note 3)
VDD = 15V, VO = 1.5V
3.6
3.0
8.8
2.4
mA
HIGH Level Output
VDD = 5V, VO = 4.6V
−0.52
−0.44
−0.88
−0.36
mA
Current
VDD = 10V, VO = 9.5V
−1.3
−1.1
−2.25
−0.9
mA
(Note 3)
VDD = 15V, VO = 13.5V
−3.6
Input Current
VDD = 15V, VIN = 0V
−0.30
−10−5
−0.30
−1.0
µA
VDD = 15V, VIN = 15V
0.30
10−5
0.30
1.0
µA
−3.0
−8.8
−2.4
mA
Note 3: IOL and IOH are tested one output at a time.
3
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CD4724BC
Absolute Maximum Ratings(Note 1)
CD4724BC
AC Electrical Characteristics
(Note 4)
TA = 25°C, CL = 50 pF, RL = 200k, Input tr = tf = 20 ns, unless otherwise noted
Symbol
tPHL, tPLH
tPLH, tPHL
tPHL
tPLH, tPHL
tTHL, tTLH
TWH, TWL
tWH, tWL
tWH
tSU
tH
tSU
tH
CPD
CIN
Typ
Max
Units
Propagation Delay
Parameter
VDD = 5V
Conditions
Min
200
400
ns
Data to Output
VDD = 10V
75
150
ns
VDD = 15V
50
100
ns
Propagation Delay
VDD = 5V
200
400
ns
Enable to Output
VDD = 10V
80
160
ns
VDD = 15V
60
120
ns
Propagation Delay
VDD = 5V
175
350
ns
Clear to Output
VDD = 10V
80
160
ns
VDD = 15V
65
130
ns
Propagation Delay
VDD = 5V
225
450
ns
Address to Output
VDD = 10V
100
200
ns
VDD = 15V
75
150
ns
Transition Time
VDD = 5V
100
200
ns
(Any Output)
VDD = 10V
50
100
ns
VDD = 15V
40
80
ns
Minimum Data
VDD = 5V
100
200
ns
Pulse Width
VDD = 10V
50
100
ns
VDD = 15V
40
80
ns
Minimum Address
VDD = 5V
200
400
ns
Pulse Width
VDD = 10V
100
200
ns
VDD = 15V
65
125
ns
Minimum Clear
VDD = 5V
75
150
ns
Pulse Width
VDD = 10V
40
75
ns
VDD = 15V
25
50
ns
Minimum Setup Time
VDD = 5V
40
80
ns
Data to E
VDD = 10V
20
40
ns
VDD = 15V
15
30
ns
Minimum Hold Time
VDD = 5V
60
120
ns
Data to E
VDD = 10V
30
60
ns
VDD = 15V
25
50
ns
Minimum Setup Time
VDD = 5V
−15
50
ns
Address to E
VDD = 10V
0
30
ns
VDD = 15V
0
20
ns
Minimum Hold Time
VDD = 5V
−50
15
ns
Address to E
VDD = 10V
−20
10
ns
VDD = 15V
−15
5
ns
Power Dissipation
Per Package
100
Capacitance
(Note 5)
Input Capacitance
Any Input
5.0
pF
7.5
pF
Note 4: AC Parameters are guaranteed by DC correlated testing.
Note 5: Dynamic power dissipation (PD) is given by: PD = (CPD + CL) VCC2f + PQ; where CL = load capacitance; f = frequency of operation; for further details,
see Application Note AN-90, “Family Characteristics”.
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4
CD4724BC
Switching Time Waveforms
5
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CD4724BC
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body
Package Number M16A
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6
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Package Number N16E
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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
1. Life support devices or systems are devices or systems
device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the
sonably expected to cause the failure of the life support
body, or (b) support or sustain life, and (c) whose failure
device or system, or to affect its safety or effectiveness.
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
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user.
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
CD4724BC 8-Bit Addressable Latch
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
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