2.5 V to 5.5 V Octal Voltage Output 8-/10-/12-Bit DACs in 16-Lead TSSOP AD5308/AD5318/AD5328 FEATURES APPLICATIONS AD5308: 8 buffered 8-bit DACs in 16-lead TSSOP A version: ±1 LSB INL, B version: ±0.75 LSB INL AD5318: 8 buffered 10-bit DACs in 16-lead TSSOP A version: ±4 LSB INL, B version: ±3 LSB INL AD5328: 8 buffered 12-bit DACs in 16-lead TSSOP A version: ±16 LSB INL, B version: ±12 LSB INL Low power operation: 0.7 mA @ 3 V Guaranteed monotonic by design over all codes Power-down to 120 nA @ 3 V, 400 nA @ 5 V Double-buffered input logic Buffered/unbuffered/VDD reference input options Output range: 0 V to VREF or 0 V to 2 VREF Power-on reset to 0 V Programmability Individual channel power-down Simultaneous update of outputs (LDAC) Low power, SPI-®, QSPI-™, MICROWIRE-™, and DSPcompatible 3-wire serial interface On-chip rail-to-rail output buffer amplifiers Temperature range: −40°C to +125°C Qualified for automotive applications Portable battery-powered instruments Digital gain and offset adjustment Programmable voltage and current sources Optical networking Automatic test equipment Mobile communications Programmable attenuators Industrial process control GENERAL DESCRIPTION The AD5308/AD5318/AD5328 are octal 8-, 10-, and 12-bit buffered voltage output DACs in a 16-lead TSSOP. They operate from a single 2.5 V to 5.5 V supply, consuming 0.7 mA typical at 3 V. Their on-chip output amplifiers allow the outputs to swing rail-to-rail with a slew rate of 0.7 V/μs. The AD5308/ AD5318/AD5328 use a versatile 3-wire serial interface that operates at clock rates up to 30 MHz and is compatible with standard SPI, QSPI, MICROWIRE, and DSP interface standards. The references for the eight DACs are derived from two reference pins (one per DAC quad). These reference inputs can be configured as buffered, unbuffered, or VDD inputs. The parts incorporate a power-on reset circuit, which ensures that the DAC outputs power up to 0 V and remain there until a valid write to the device takes place. The outputs of all DACs may be updated simultaneously using the asynchronous LDAC input. The parts contain a power-down feature that reduces the current consumption of the devices to 400 nA at 5 V (120 nA at 3 V). The eight channels of the DAC may be powered down individually. All three parts are offered in the same pinout, which allows users to select the resolution appropriate for their application without redesigning their circuit board. Rev. F Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2002–2011 Analog Devices, Inc. All rights reserved. AD5308/AD5318/AD5328 TABLE OF CONTENTS Features .............................................................................................. 1 Low Power Serial Interface ....................................................... 18 Applications....................................................................................... 1 Load DAC Input (LDAC) Function......................................... 18 General Description ......................................................................... 1 Double-Buffered Interface ........................................................ 18 Revision History ............................................................................... 2 Microprocessor Interface............................................................... 19 Functional Block Diagram .............................................................. 3 Specifications..................................................................................... 4 ADSP-2101/ADSP-2103-to-AD5308/AD5318/AD5328 Interface ....................................................................................... 19 Absolute Maximum Ratings............................................................ 7 68HC11/68L11-to-AD5308/AD5318/AD5328 Interface ..... 19 ESD Caution.................................................................................. 7 80C51/80L51-to-AD5308/AD5318/AD5328 Interface......... 19 Pin Configuration and Function Descriptions............................. 8 Microwire-to-AD5308/AD5318/AD5328 Interface.............. 20 Typical Performance Characteristics ............................................. 9 Applications Information .............................................................. 21 Terminology .................................................................................... 13 Typical Application Circuit....................................................... 21 Theory of Operation ...................................................................... 15 Driving VDD from the Reference Voltage ................................ 21 Digital-to-Analog Converter .................................................... 15 Bipolar Operation Using the AD5308/AD5318/AD5328..... 21 Resistor String ............................................................................. 15 Opto-Isolated Interface for Process Control Applications ... 21 Output Amplifier........................................................................ 15 Decoding Multiple AD5308/AD5318/AD5328s.................... 22 Power-On Reset .......................................................................... 16 Outline Dimensions ....................................................................... 24 Power-Down Mode .................................................................... 16 Ordering Guide .......................................................................... 24 Serial Interface ............................................................................ 16 REVISION HISTORY 4/11—Rev. E to Rev. F Added Automotive Products Information ................. Throughout 2/11—Rev. D to Rev. E Change to Temperature Range .................................... Throughout Changes to Table 3, t4 Timing Characteristics .............................. 6 3/07—Rev. C to Rev. D Updated Format..................................................................Universal Changes to Absolute Maximum Ratings Section......................... 7 9/05—Rev. B to Rev. C Updated Format..................................................................Universal Change to Equation........................................................................ 21 11/03—Rev. A to Rev. B Changes to Ordering Guide ............................................................ 4 Changes to Y axis on TPCs 12, 13, and 15 .................................... 9 8/03—Rev. 0 to Rev. A Added A Version.................................................................Universal Changes to Features.......................................................................... 1 Changes to Specifications ................................................................ 2 Edits to Absolute Maximum Ratings ............................................. 4 Edits to Ordering Guide .................................................................. 4 Updated Outline Dimensions ....................................................... 18 Rev. F | Page 2 of 28 AD5308/AD5318/AD5328 FUNCTIONAL BLOCK DIAGRAM VREFABCD VDD VDD GAIN-SELECT LOGIC LDAC INPUT REGISTER DAC REGISTER STRING BUFFER DAC A BUFFER VOUTA INPUT REGISTER STRING DAC REGISTER STRING DAC B BUFFER VOUTB INPUT REGISTER DAC REGISTER STRING DAC C BUFFER VOUTC INPUT REGISTER DAC REGISTER STRING DAC D BUFFER VOUTD INPUT REGISTER DAC REGISTER STRING DAC E BUFFER VOUTE INPUT REGISTER DAC REGISTER STRING DAC F BUFFER VOUTF INPUT REGISTER DAC REGISTER STRING DAC G BUFFER VOUTG RESET INPUT REGISTER DAC REGISTER STRING DD DAC H BUFFER GND VOUTH SYNC INTERFACE LOGIC DIN POWER-ON RESET GAIN-SELECT LOGIC POWER-DOWN LOGIC VDD VREFEFGH LDAC Figure 1. Rev. F | Page 3 of 28 GND 02812-001 SCLK AD5308/AD5318/AD5328 SPECIFICATIONS VDD = 2.5 V to 5.5 V; VREF = 2 V; RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications TMIN to TMAX, unless otherwise specified. Table 1. 2 Parameter DC PERFORMANCE3, 4 AD5308 Resolution Relative Accuracy Differential Nonlinearity Min A Version1 Typ Max 8 Min B Version1 Typ Max Unit ±0.15 ±0.02 ±0.75 ±0.25 Bits LSB LSB ±0.5 ±0.05 ±3 ±0.50 Bits LSB LSB 8 ±0.15 ±0.02 ±1 ±0.25 ±0.5 ±0.05 ±4 ±0.50 ±2 ±0.2 ±16 ±1.0 ±2 ±0.2 ±12 ±1.0 Bits LSB LSB Offset Error ±5 ±60 ±5 ±60 mV Gain Error ±0.30 ±1.25 ±0.30 ±1.25 % of FSR Lower Deadband5 10 60 10 60 mV Upper Deadband5 10 60 10 60 mV Offset Error Drift6 −12 −12 Gain Error Drift6 −5 −5 −60 200 −60 200 AD5318 Resolution Relative Accuracy Differential Nonlinearity AD5328 Resolution Relative Accuracy Differential Nonlinearity 10 10 12 12 Conditions/Comments Guaranteed monotonic by design over all codes Guaranteed monotonic by design over all codes Guaranteed monotonic by design over all codes VDD = 4.5 V, gain = 2, see Figure 27 and Figure 28 VDD = 4.5 V, gain = 2, see Figure 27 and Figure 28 Lower deadband exists only if offset error is negative, see Figure 27 Upper deadband exists only if VREF = VDD and offset plus gain error is positive, see Figure 28 DC Power Supply Rejection Ratio6 DC Crosstalk6 DAC REFERENCE INPUTS6 VREF Input Range 1.0 0.25 VREF Input Impedance (RDAC) Reference Feedthrough Channel-to-Channel Isolation OUTPUT CHARACTERISTICS6 Minimum Output Voltage7 Maximum Output Voltage7 DC Output Impedance VDD VDD 1.0 0.25 >10.0 ppm of FSR/°C ppm of FSR/°C dB μV VDD VDD >10.0 V V MΩ 37.0 45.0 37.0 45.0 kΩ 18.0 22.0 18.0 22.0 kΩ −70.0 −75.0 −70.0 −75.0 dB dB 0.001 0.001 V VDD − 0.001 0.5 VDD − 0.001 V 0.5 Ω Rev. F | Page 4 of 28 VDD = ±10% RL = 2 kΩ to GND or VDD Buffered reference mode Unbuffered reference mode Buffered reference mode and power-down mode Unbuffered reference mode, 0 V to VREF output range Unbuffered reference mode, 0 V to 2 VREF output range Frequency = 10 kHz Frequency = 10 kHz This is a measure of the minimum and maximum Drive capability of the output amplifier AD5308/AD5318/AD5328 2 Parameter Short Circuit Current Min Power-Up Time A Version1 Typ Max 25.0 16.0 2.5 Min 5.0 Pin Capacitance POWER REQUIREMENTS VDD IDD (Normal Mode)8 VDD = 4.5 V to 5.5 V Max 5.0 LOGIC INPUTS6 Input Current VIL, Input Low Voltage VIH, Input High Voltage B Version1 Typ 25.0 16.0 2.5 ±1 0.8 0.8 0.7 μs ±1 0.8 0.8 0.7 1.7 1.7 3.0 3.0 2.5 5.5 2.5 Unit mA mA μs μA V V V V Conditions/Comments VDD = 5 V VDD = 3 V Coming out of power-down mode, VDD = 5 V Coming out of power-down mode, VDD = 3 V VDD = 5 V ± 10% VDD = 3 V ± 10% VDD = 2.5 V VDD = 2.5 V to 5.5 V, TTL and CMOS compatible pF 5.5 V 1.0 1.8 1.0 1.8 mA VDD = 2.5 V to 3.6 V 0.7 1.5 0.7 1.5 mA IDD (Power-Down Mode)9 VDD = 4.5 V to 5.5 V VDD = 2.5 V to 3.6 V 0.4 0.12 1 1 0.4 0.12 1 1 μA μA VIH = VDD and VIL = GND All DACs in unbuffered mode, in buffered mode Extra current is typically x μA per DAC; x = (5 μA + VREF/RDAC)/4 VIH = VDD and VIL = GND 1 Temperature range (A, B version): −40°C to +125°C; typical at 25°C. See the Terminology section. 3 DC specifications tested with the outputs unloaded unless stated otherwise. 4 Linearity is tested using a reduced code range: AD5308 (Code 8 to Code 255), AD5318 (Code 28 to Code 1023), and AD5328 (Code 115 to Code 4095). 5 This corresponds to x codes. x = deadband voltage/LSB size. 6 Guaranteed by design and characterization; not production tested. 7 For the amplifier output to reach its minimum voltage, offset error must be negative. For the amplifier output to reach its maximum voltage, VREF = VDD and offset plus gain error must be positive. 8 Interface inactive. All DACs active. DAC outputs unloaded. 9 All eight DACs powered down. 2 VDD = 2.5 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications TMIN to TMAX, unless otherwise noted. Table 2. AC Characteristics1 Parameter3 Output Voltage Settling Time AD5308 AD5318 AD5328 Slew Rate Major-Code Change Glitch Energy Digital Feedthrough Digital Crosstalk Analog Crosstalk DAC-to-DAC Crosstalk Multiplying Bandwidth Total Harmonic Distortion Min A, B Version2 Typ Max 6 7 8 0.7 12 0.5 0.5 1 3 200 −70 8 9 10 Unit μs μs μs V/μs nV-sec nV-sec nV-sec nV-sec nV-sec kHz dB 1 Guaranteed by design and characterization; not production tested. Temperature range (A, B version): –40°C to +125°C; typical at 25°C. 3 See the Terminology section. 2 Rev. F | Page 5 of 28 Conditions/Comments VREF = VDD = 5 V 1/4 scale to 3/4 scale change (0x40 to 0xC0) 1/4 scale to 3/4 scale change (0x100 To 0x300) 1/4 scale to 3/4 scale change (0x400 to 0xC00) 1 LSB change around major carry VREF = 2 V ± 0.1 V p-p, unbuffered mode VREF = 2.5 V ± 0.1 V p-p, frequency = 10 kHz AD5308/AD5318/AD5328 Table 3. Timing Characteristics 1, 2, 3 Parameter t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 A, B Version Limit at TMIN, TMAX 33 13 13 13 Unit ns min ns min ns min ns min 15 ns min 5 4.5 0 50 20 20 0 ns min ns min ns min ns min ns min ns min ns min Conditions/Comments SCLK cycle time SCLK high time SCLK low time SYNC to SCLK falling edge setup time; temperature range (A, B verstion): −40°C to +105°C SYNC to SCLK falling edge setup time; temperature range (A, B verstion): −40°C to +125°C Data set up time Data hold time SCLK falling edge to SYNC rising edge Minimum SYNC high time LDAC pulse width SCLK falling edge to LDAC rising edge SCLK falling edge to LDAC falling edge 1 Guaranteed by design and characterization; not production tested. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. 3 See Figure 2. 2 t1 SCLK t8 t3 t4 t2 t7 SYNC t6 t5 DIN DB0 DB15 t9 t11 t10 LDAC2 NOTES 1ASYNCHRONOUS LDAC UPDATE MODE. 2SYNCHRONOUS LDAC UPDATE MODE. Figure 2. Serial Interface Timing Diagram Rev. F | Page 6 of 28 02812-002 LDAC1 AD5308/AD5318/AD5328 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise specified. Table 4. Parameter VDD to GND Digital Input Voltage to GND Reference Input Voltage to GND VOUTA–VOUTD to GND Operating Temperature Range Industrial (A, B Version) Storage Temperature Range Junction Temperature (TJ MAX) 16-Lead TSSOP Power Dissipation θJA Thermal Impedance Lead Temperature Soldering 1 Rating1 −0.3 V to +7 V −0.3 V to VDD + 0.3 V −0.3 V to VDD + 0.3 V −0.3 V to VDD + 0.3 V −40°C to +125°C −65°C to +150°C 150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION (TJ MAX − TA)/θJA 150.4°C/W JEDEC industry-standard J-STD-020 Transient currents of up to 100 mA do not cause SCR latch-up. Rev. F | Page 7 of 28 AD5308/AD5318/AD5328 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS LDAC 1 16 SCLK SYNC 2 15 DIN 3 4 VOUTB 5 VOUTC 6 VOUTD 7 VREFABCD 8 AD5308/ AD5318/ AD5328 TOP VIEW (Not to Scale) 14 GND 13 VOUTH 12 VOUTG 11 VOUTF 10 VOUTE 9 VREFEFGH 02812-003 VDD VOUTA Figure 3. Pin Configuration Table 5. Pin Function Descriptions Pin No. 1 Mnemonic LDAC 2 SYNC 3 VDD 4 5 6 7 8 VOUTA VOUTB VOUTC VOUTD VREFABCD 9 VREFEFGH 10 11 12 13 14 15 VOUTE VOUTF VOUTG VOUTH GND DIN 16 SCLK Description This active low control input transfers the contents of the input registers to their respective DAC registers. Pulsing this pin low allows any or all DAC registers to be updated if the input registers have new data. This allows simultaneous updates of all DAC outputs. Alternatively, this pin can be tied permanently low. Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, it powers on the SCLK and DIN buffers and enables the input shift register. Data is transferred in on the falling edges of the following 16 clocks. If SYNC is taken high before the 16th falling edge, the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the device. Power Supply Input. These parts can be operated from 2.5 V to 5.5 V, and the supply should be decoupled with a 10 μF capacitor in parallel with a 0.1 μF capacitor to GND. Buffered Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation. Buffered Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation. Buffered Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation. Buffered Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation. Reference Input Pin for DACs A, B, C, and D. It can be configured as a buffered, unbuffered, or VDD input to the four DACs, depending on the state of the BUF and VDD control bits. It has an input range from 0.25 V to VDD in unbuffered mode and from 1 V to VDD in buffered mode. Reference Input Pin for DACs E, F, G, and H. It can be configured as a buffered, unbuffered, or VDD input to the four DACs, depending on the state of the BUF and VDD control bits. It has an input range from 0.25 V to VDD in unbuffered mode and from 1 V to VDD in buffered mode. Buffered Analog Output Voltage from DAC E. The output amplifier has rail-to-rail operation. Buffered Analog Output Voltage from DAC F. The output amplifier has rail-to-rail operation. Buffered Analog Output Voltage from DAC G. The output amplifier has rail-to-rail operation. Buffered Analog Output Voltage from DAC H. The output amplifier has rail-to-rail operation. Ground Reference Point for All Circuitry on the Part. Serial Data Input. This device has a 16-bit shift register. Data is clocked into the register on the falling edge of the serial clock input. The DIN input buffer is powered down after each write cycle. Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be transferred at rates up to 30 MHz. The SCLK input buffer is powered down after each write cycle. Rev. F | Page 8 of 28 AD5308/AD5318/AD5328 TYPICAL PERFORMANCE CHARACTERISTICS 0.3 1.0 TA = 25°C VDD = 5V TA = 25°C VDD = 5V 0.2 DNL ERROR (LSB) INL ERROR (LSB) 0.5 0 0.1 0 –0.1 –0.5 0 50 100 150 200 250 CODE –0.3 02812-006 –1.0 02812-009 –0.2 0 100 150 200 250 800 1000 CODE Figure 7. AD5308 Typical DNL Plot Figure 4. AD5308 Typical INL Plot 0.6 3 TA = 25°C VDD = 5V TA = 25°C VDD = 5V 0.4 DNL ERROR (LSB) 2 1 0 –1 0.2 0 –0.2 –0.4 02812-007 –2 –3 0 200 400 600 800 02812-010 INL ERROR (LSB) 50 –0.6 0 1000 200 400 600 CODE CODE Figure 5. AD5318 Typical INL Plot Figure 8. AD5318 Typical DNL Plot 12 1.0 TA = 25°C VDD = 5V 8 TA = 25°C VDD = 5V DNL ERROR (LSB) 0 –4 0 –0.5 –12 0 500 1000 1500 2000 2500 3000 3500 02812-011 –8 02812-008 INL ERROR (LSB) 0.5 4 –1.0 4000 0 CODE 500 1000 1500 2000 2500 3000 CODE Figure 6. AD5328 Typical INL Plot Figure 9. AD5328 Typical DNL Plot Rev. F | Page 9 of 28 3500 4000 AD5308/AD5318/AD5328 0.50 0.2 TA = 25°C VDD = 5V TA = 25°C VREF = 2V 0.1 MAX INL 0.25 0 ERROR (% FSR) ERROR (LSB) GAIN ERROR MAX DNL 0 MIN DNL –0.1 –0.2 –0.3 OFFSET ERROR –0.25 –0.4 MIN INL –0.50 0 1 2 3 4 02812-015 02812-012 –0.5 –0.6 0 5 1 2 VREF (V) Figure 10. AD5308 INL and DNL Error vs. VREF 4 5 6 Figure 13. Offset Error and Gain Error vs. VDD 0.5 5 VREF = 3V VDD = 5V 0.4 MAX INL 0.3 5V SOURCE 4 0.2 3V SOURCE MAX DNL 0.1 VOUT (V) ERROR (LSB) 3 VDD (V) 0 –0.1 3 2 MIN DNL –0.2 –0.3 1 –0.4 –0.5 – 40 0 40 80 3V SINK 5V SINK 02812-016 02812-013 MIN INL 0 0 120 1 2 3 4 5 6 SINK/SOURCE CURRENT (mA) TEMPERATURE (°C) Figure 14. VOUT Source and Sink Current Capability Figure 11. AD5308 INL Error and DNL Error vs. Temperature 1.0 1.0 VDD = 5V VREF = 2V 0.9 TA = 25°C VDD = 5V 0.8 0.5 IDD (mA) 0 OFFSET ERROR 0.6 0.5 0.4 0.3 –0.5 –1.0 –40 0 40 80 02812-017 0.2 02812-014 ERROR (% FSR) 0.7 GAIN ERROR 0.1 0 120 ZERO SCALE HALF SCALE DAC CODE FULL SCALE TEMPERATURE (°C) Figure 15. Supply Current vs. DAC Code Figure 12. AD5308 Offset Error and Gain Error vs. Temperature Rev. F | Page 10 of 28 AD5308/AD5318/AD5328 1.3 TA = 25°C TA = 25°C VDD = 5V VREF = 5V VREF = 2V, GAIN = +1, BUFFERED 1.2 1.1 VREF = VDD IDD (mA) VOUTA 1.0 CH1 0.9 SCLK CH2 02812-018 VREF = 2V, GAIN = +1, UNBUFFERED VREF = VDD, GAIN = +1, UNBUFFERED 0.7 0.6 2.5 2.0 3.0 3.5 4.0 SUPPLY VOLTAGE (V) 02812-021 0.8 4.5 CH1 1V, CH2 5V, TIME BASE = 1μs/DIV 5.0 Figure 16. Supply Current vs. Supply Voltage Figure 19. Half-Scale Settling (1/4 to 3/4 Scale Code Change) 1.0 IDD POWER-DOWN (μA) TA = 25°C VDD = 5V VREF = 2V TA = 25°C 0.9 0.8 0.7 0.6 VDD CH1 0.5 0.4 0.3 VOUTA 0.2 0.1 0 2.0 2.5 3.0 3.5 4.0 VDD (V) 4.5 5.0 02812-022 02812-019 CH2 CH1 2.00V, CH2 200mV, TIME BASE = 200μs/DIV 5.5 Figure 17. Power-Down Current vs. Supply Voltage Figure 20. Power-On Reset to 0 V 1.4 DECREASING TA = 25°C VDD = 5V VREF = 2V TA = 25°C VDD = 5V 1.3 INCREASING IDD (mA) 1.2 1.1 VOUTA CH1 1.0 0.9 0.8 PD VDD = 3V 0.6 0 0.5 1.0 1.5 2.0 3.0 2.5 VLOGIC (V) 3.5 4.0 4.5 02812-023 CH2 02812-020 0.7 CH1 500V, CH2 5.00mV, TIME BASE = 1μs/DIV 5.0 Figure 18. Supply Current vs. Logic Input Voltage for SCLK and DIN Increasing and Decreasing Rev. F | Page 11 of 28 Figure 21. Exiting Power-Down to Midscale AD5308/AD5318/AD5328 35 0.02 SS = 300 VDD = 3V VDD = 5V TA = 25°C VDD = 5V FULL-SCALE ERROR (V) FREQUENCY 30 25 MEAN: 0.693798 MEAN: 1.02055 20 15 0.01 0 10 02812-024 0 0.6 0.7 0.8 0.9 IDD (mA) 1.0 02812-027 –0.01 5 –0.02 1.1 0 Figure 22. IDD Histogram with VDD = 3 V and VDD = 5 V 1 2 3 VREF (V) 4 5 6 Figure 25. Full-Scale Error vs. VREF 2.50 VOUT (V) 1mV/DIV 2.49 02812-025 02812-028 2.48 2.47 100ns/DIV 1μs/DIV Figure 26. DAC-to-DAC Crosstalk Figure 23. AD5328 Major-Code Transition Glitch Energy 10 0 (dB) –10 –20 –30 –40 –60 10 02812-026 –50 100 1k 10k 100k FREQUENCY (Hz) 1M 10M Figure 24. Multiplying Bandwidth (Small-Signal Frequency Response) Rev. F | Page 12 of 28 AD5308/AD5318/AD5328 TERMINOLOGY Relative Accuracy For the DAC, relative accuracy or integral nonlinearity (INL) is a measure of the maximum deviation, in LSB, from a straight line passing through the endpoints of the DAC transfer function. Typical INL vs. code plots can be seen in Figure 4, Figure 5, and Figure 6. Differential Nonlinearity Differential nonlinearity (DNL) is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of ±1 LSB maximum ensures monotonicity. This DAC is guaranteed monotonic by design. Typical DNL vs. code plots can be seen in Figure 7, Figure 8, and Figure 9. Offset Error This is a measure of the offset error of the DAC and the output amplifier (see Figure 27 and Figure 28). It can be negative or positive, and is expressed in millivolts. Gain Error This is a measure of the span error of the DAC. It is the deviation in slope of the actual DAC transfer characteristic from the ideal expressed as a percentage of the full-scale range. Offset Error Drift This is a measure of the change in offset error with changes in temperature. It is expressed in (ppm of full-scale range)/°C. Gain Error Drift This is a measure of the change in gain error with changes in temperature. It is expressed in (ppm of full-scale range)/°C. DC Power Supply Rejection Ratio (PSRR) This indicates how the output of the DAC is affected by changes in the supply voltage. PSRR is the ratio of the change in VOUT to a change in VDD for full-scale output of the DAC. It is measured in decibels. VREF is held at 2 V and VDD is varied ±10%. DC Crosstalk This is the dc change in the output level of one DAC in response to a change in the output of another DAC. It is measured with a full-scale output change on one DAC while monitoring another DAC. It is expressed in microvolts. Reference Feedthrough This is the ratio of the amplitude of the signal at the DAC output to the reference input when the DAC output is not being updated (that is, LDAC is high). It is expressed in decibels. Channel-to-Channel Isolation This is the ratio of the amplitude of the signal at the output of one DAC to a sine wave on the reference input of another DAC. It is measured in decibels. Major-Code Transition Glitch Energy Major-code transition glitch energy is the energy of the impulse injected into the analog output when the code in the DAC register changes state. It is normally specified as the area of the glitch in nV-sec and is measured when the digital code is changed by 1 LSB at the major carry transition (011 ... 11 to 100 ... 00 or 100 ... 00 to 011 ... 11). Digital Feedthrough Digital feedthrough is a measure of the impulse injected into the analog output of a DAC from the digital input pins of the device, but is measured when the DAC is not being written to (SYNC held high). It is specified in nV-sec and is measured with a full-scale change on the digital input pins, that is, from all 0s to all 1s and vice versa. Digital Crosstalk This is the glitch impulse transferred to the output of one DAC at midscale in response to a full-scale code change (all 0s to all 1s and vice versa) in the input register of another DAC. It is measured in standalone mode and is expressed in nV-sec. Analog Crosstalk This is the glitch impulse transferred to the output of one DAC due to a change in the output of another DAC. It is measured by loading one of the input registers with a full-scale code change (all 0s to all 1s and vice versa) while keeping LDAC high. Then pulse LDAC low and monitor the output of the DAC whose digital code is not changed. The area of the glitch is expressed in nV-sec. DAC-to-DAC Crosstalk This is the glitch impulse transferred to the output of one DAC due to a digital code change and subsequent output change of another DAC. This includes both digital and analog crosstalk. It is measured by loading one of the DACs with a full-scale code change (all 0s to all 1s and vice versa) with LDAC low and monitoring the output of another DAC. The energy of the glitch is expressed in nV-sec. Multiplying Bandwidth The amplifiers within the DAC have a finite bandwidth. The multiplying bandwidth is a measure of this. A sine wave on the reference (with full-scale code loaded to the DAC) appears on the output. The multiplying bandwidth is the frequency at which the output amplitude falls to 3 dB below the input. Total Harmonic Distortion (THD) This is the difference between an ideal sine wave and its attenuated version using the DAC. The sine wave is used as the reference for the DAC and the THD is a measure of the harmonics present on the DAC output. It is measured in decibels. Rev. F | Page 13 of 28 AD5308/AD5318/AD5328 GAIN ERROR PLUS OFFSET ERROR GAIN ERROR PLUS OFFSET ERROR OUTPUT VOLTAGE OUTPUT VOLTAGE UPPER DEADBAND CODES ACTUAL DAC CODE POSITIVE OFFSET ERROR ACTUAL IDEAL FULL SCALE DAC CODE Figure 28. Transfer Function with Positive Offset LOWER DEADBAND CODES NEGATIVE OFFSET ERROR 02812-004 AMPLIFIER FOOTROOM Figure 27. Transfer Function with Negative Offset (VREF = VDD) Rev. F | Page 14 of 28 02812-005 IDEAL NEGATIVE OFFSET ERROR AD5308/AD5318/AD5328 THEORY OF OPERATION The AD5308/AD5318/AD5328 are octal resistor-string DACs fabricated on a CMOS process with resolutions of 8, 10, and 12 bits, respectively. Each contains eight output buffer amplifiers and is written to via a 3-wire serial interface. They operate from single supplies of 2.5 V to 5.5 V and the output buffer amplifiers provide rail-to-rail output swing with a slew rate of 0.7 V/μs. DAC A, DAC B, DAC C, and DAC D share a common reference input, VREFABCD. DAC E, DAC F, DAC G, and DAC H share a common reference input, VREFEFGH. Each reference input can be buffered to draw virtually no current from the reference source, can be unbuffered to give a reference input range from 0.25 V to VDD, or can come from VDD. The devices have a power-down mode in which all DACs can be turned off individually with a high impedance output. If there is a buffered reference in the circuit (for example, the REF192), there is no need to use the on-chip buffers of the AD5308/AD5318/AD5328. In unbuffered mode, the input impedance is still large at typically 45 kΩ per reference input for 0 V to VREF mode and 22 kΩ for 0 V to 2 VREF mode. RESISTOR STRING The resistor-string section is shown in Figure 30. It is simply a string of resistors, each of value R. The digital code loaded to the DAC register determines at which node on the string the voltage is tapped off to be fed into the output amplifier. The voltage is tapped off by closing one of the switches connecting the string to the amplifier. Because it is a string of resistors, it is guaranteed monotonic. R DIGITAL-TO-ANALOG CONVERTER The architecture of one DAC channel consists of a resistor string DAC followed by an output buffer amplifier. The voltage at the VREF pin provides the reference voltage for the corresponding DAC. Figure 29 shows a block diagram of the DAC architecture. Since the input coding to the DAC is straight binary, the ideal output voltage is given by TO OUTPUT AMPLIFIER R R VREF × D 2N R 02812-030 VOUT = R where: Figure 30. Resistor String D is the decimal equivalent of the binary code that is loaded to the DAC register: 0 to 255 for AD5308 (8 bits) 0 to 1023 for AD5318 (10 bits) 0 to 4095 for AD5328 (12 bits) N is the DAC resolution. BUF DAC REGISTER If a gain of 1 is selected (gain bit = 0), the output range is 0.001 V to VREF. REFERENCE GAIN MODE BUFFER (GAIN = +1 OR +2) RESISTOR STRING VOUTA OUTPUT BUFFER AMPLIFIER 02812-029 INPUT REGISTER The output buffer amplifier is capable of generating output voltages to within 1 mV of either rail. Its actual range depends on the value of VREF, the gain of the output amplifier, the offset error, and the gain error. VREFABCD VDD VDD OUTPUT AMPLIFIER Figure 29. Single DAC Channel Architecture DAC Reference Inputs There is a reference pin for each quad of DACs. The reference inputs can be buffered from VDD, or unbuffered. The advantage with the buffered input is the high impedance it presents to the voltage source driving it. However, if the unbuffered mode is used, the user can have a reference voltage as low as 0.25 V and as high as VDD since there is no restriction due to the headroom and footroom of the reference amplifier. If a gain of 2 is selected (gain bit = 1), the output range is 0.001 V to 2 VREF. Because of clamping, however, the maximum output is limited to VDD − 0.001 V. The output amplifier is capable of driving a load of 2 kΩ to GND or VDD, in parallel with 500 pF to GND or VDD. The source and sink capabilities of the output amplifier can be seen in the plot in Figure 14. The slew rate is 0.7 V/μs with a half-scale settling time to ±0.5 LSB (at 8 bits) of 6 μs. Rev. F | Page 15 of 28 AD5308/AD5318/AD5328 POWER-ON RESET SERIAL INTERFACE The AD5308/AD5318/AD5328 are provided with a power-on reset function so that they power up in a defined state. The power-on state is The AD5308/AD5318/AD5328 are controlled over a versatile 3-wire serial interface that operates at clock rates up to 30 MHz and is compatible with SPI, QSPI, MICROWIRE, and DSP interface standards. • Normal operation • Reference inputs unbuffered • 0 V to VREF output range • Output voltage set to 0 V • LDAC bits set to LDAC high Input Shift Register The input shift register is 16 bits wide. Data is loaded into the device as a 16-bit word under the control of a serial clock input, SCLK. The timing diagram for this operation is shown in Figure 2. Both input and DAC registers are filled with 0s and remain so until a valid write sequence is made to the device. This is particularly useful in applications where it is important to know the state of the DAC outputs while the device is powering up. POWER-DOWN MODE The AD5308/AD5318/AD5328 have low power consumption, typically dissipating 2.4 mW with a 3 V supply and 5 mW with a 5 V supply. Power consumption can be further reduced when the DACs are not in use by putting them into power-down mode, which is described in the Serial Interface section. When in default mode, all DACs work normally with a typical power consumption of 1 mA at 5 V (800 μA at 3 V). However, when all DACs are powered down, that is, in power-down mode, the supply current falls to 400 nA at 5 V (120 nA at 3 V). Not only does the supply current drop, but the output stage is also internally switched from the output of the amplifier, making it open-circuit. This has the advantage that the output is three-state while the part is in power-down mode, and provides a defined input condition for whatever is connected to the output of the DAC amplifier. The output stage is illustrated in Figure 31. The bias generator, the output amplifiers, the resistor string, and all other associated linear circuitry are shut down when the power-down mode is activated. However, the contents of the registers are unaffected when in power-down. In fact, it is possible to load new data to the input registers and DAC registers during power-down. The DAC outputs update as soon as the device comes out of power-down mode. The time to exit power-down is typically 2.5 μs when VDD = 5 V and 5 μs when VDD = 3 V. AMPLIFIER RESISTORSTRING DAC POWER-DOWN CIRCUITRY 02812-035 VOUT Figure 31. Output Stage During Power-Down The SYNC input is a level-triggered input that acts as a frame synchronization signal and chip enable. Data can be transferred into the device only while SYNC is low. To start the serial data transfer, SYNC should be taken low, observing the minimum SYNC to SCLK falling edge set-up time, t4. After SYNC goes low, serial data is shifted into the device’s input shift register on the falling edges of SCLK for 16 clock pulses. To end the transfer, SYNC must be taken high after the falling edge of the 16th SCLK pulse, observing the minimum SCLK falling edge to SYNC rising edge time, t7. After the end of the serial data transfer, data is automatically transferred from the input shift register to the input register of the selected DAC. If SYNC is taken high before the 16th falling edge of SCLK, the data transfer is aborted and the DAC input registers are not updated. Data is loaded MSB first (Bit 15). The first bit determines whether it is a DAC write or a control function. DAC Write The 16-bit word consists of 1 control bit and 3 address bits followed by 8, 10, or 12 bits of DAC data, depending on the device type. In the case of a DAC write, the MSB is a 0. The next 3 address bits determine whether the data is for DAC A, DAC B, DAC C, DAC D, DAC E, DAC F, DAC G, or DAC H. The AD5328 uses all 12 bits of DAC data. The AD5318 uses 10 bits and ignores the 2 LSBs. The AD5308 uses 8 bits and ignores the last 4 bits. These ignored LSBs should be set to 0. The data format is straight binary, with all 0s corresponding to 0 V output and all 1s corresponding to full-scale output. Table 6. Address Bits for the AD5308/AD5318/AD5328 A2 (Bit 14) 0 0 0 0 1 1 1 1 Rev. F | Page 16 of 28 A1 (Bit 13) 0 0 1 1 0 0 1 1 A0 (Bit 12) 0 1 0 1 0 1 0 1 DAC Addressed DAC A DAC B DAC C DAC D DAC E DAC F DAC G DAC H AD5308/AD5318/AD5328 Control Functions BUF In the case of a control function, the MSB (Bit 15) is a 1. This is followed by two control bits, which determine the mode. There are four different control modes: reference and gain mode, LDAC mode, power-down mode, and reset mode. The write sequences for these modes are shown in Table 7. This controls whether the reference of a group of DACs is buffered or unbuffered. The reference of the first group of DACs (A, B, C, and D) is controlled by setting Bit 2, and the second group of DACs (E, F, G, and H) is controlled by setting Bit 3. 0: unbuffered reference. 1: buffered reference. Reference and Gain Mode GAIN This mode determines whether the reference for each group of DACs is buffered, unbuffered, or from VDD. It also determines the gain of the output amplifier. To set up the reference of both groups, set the control bits to (00), set the GAIN bits, the BUF bits, and the VDD bits. The gain of the DACs is controlled by setting Bit 4 for the first group of DACs (A, B, C, and D) and Bit 5 for the second group of DACs (E, F, G, and H). 0: output range of 0 V to VREF. 1: output range of 0 V to 2 VREF. Table 7. Control Words for the AD53x8 D/C 15 Control Bits 14 13 12 11 10 9 8 7 6 1 0 0 x x x x x x 1 0 1 x x x x x 1 1 x x x x 1 1 0 Reset 1 1/0 x x x x 5 4 GAIN Bits E...H A...D 2 BUF Bits E...H A...D x x x x x x H G F E x x x x x BIT 0 (LSB) D/C A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 DATA BITS Figure 32. AD5308 Input Shift Register Contents D/C BIT 0 (LSB) A2 A1 A0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 DATA BITS 02812-032 BIT 15 (MSB) Figure 33. AD5318 Input Shift Register Contents D/C A2 BIT 0 (LSB) A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DATA BITS 02812-033 BIT 15 (MSB) x Channels D C x x 1 0 VDD Bits E...H A...D LDAC Bits 1/0 1/0 Mode Gain of output amplifier and reference selection B A Power-down x x Reset LDAC LDAC Mode 02812-031 BIT 15 (MSB) 3 Figure 34. AD5328 Input Shift Register Contents LDAC mode controls LDAC, which determines when data is transferred from the input registers to the DAC registers. There are three options when updating the DAC registers, as shown in Table 8. Table 8. LDAC Mode Bit 15 Bit 14 Bit 13 Bits 12:2 Bit 1 Bit 0 Description 1 1 1 0 0 0 1 1 1 x ... x x ... x x ... x 0 0 1 0 1 0 1 0 1 x ... x 1 1 LDAC low LDAC high LDAC single update Reserved VDD LDAC Low (00): This option sets LDAC permanently low, allowing the DAC registers to be updated continuously. These bits are set when VDD is to be used as a reference. The first group of DACs (A, B, C, and D) can be set up to use VDD by setting Bit 0, and the second group of DACs (E, F, G, and H) by setting Bit 1. The VDD bits have priority over the BUF bits. LDAC High (01): This option sets LDAC permanently high. The DAC registers are latched and the input registers can change without affecting the contents of the DAC registers. This is the default option for this mode. When VDD is used as the reference, it is always unbuffered and has an output range of 0 V to VREF regardless of the state of the GAIN and BUF bits. LDAC Single Update (10): This option causes a single pulse on LDAC, updating the DAC registers once. Reserved (11): reserved. Rev. F | Page 17 of 28 AD5308/AD5318/AD5328 Power-Down Mode The individual channels of the AD5308/AD5318/AD5328 can be powered down separately. The control mode for this is (10). On completion of this write sequence, the channels that have been set to 1 are powered down. Reset Mode This mode consists of two possible reset functions, as outlined in Table 9. Table 9. Reset Mode Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 ... 0 Description 1 1 1 1 1 1 0 1 x ... x x ... x DAC data reset Data and control reset DAC Data Reset: On completion of this write sequence, all DAC registers and input registers are filled with 0s. Data and Control Reset: This function carries out a DAC data reset and resets all the control bits (GAIN, BUF, VDD, LDAC, and power-down channels) to their power-on conditions. LOW POWER SERIAL INTERFACE To minimize the power consumption of the device, the interface powers up fully only when the device is being written to, that is, on the falling edge of SYNC. The SCLK and DIN input buffers are powered down on the rising edge of SYNC. LOAD DAC INPUT (LDAC) FUNCTION Access to the DAC registers is controlled by both the LDAC pin and the LDAC mode bits. The operation of the LDAC function can be likened to the configuration shown in Figure 35. LDAC FUNCTION 02812-034 EXTERNAL LDAC PIN INTERNAL LDAC MODE Figure 35. LDAC Function If the user wishes to update the DAC through software, the LDAC pin should be tied high and the LDAC mode bits set as required. Alternatively, if the user wishes to control the DAC through hardware, that is, the LDAC pin, the LDAC mode bits should be set to LDAC high (default mode). Use of the LDAC function enables double-buffering of the DAC data, and the GAIN, BUF and VDD bits. There are two ways in which the LDAC function can operate: Synchronous LDAC: The DAC registers are updated after new data is read in on the falling edge of the 16th SCLK pulse. LDAC can be permanently low or pulsed as in Figure 2. Asynchronous LDAC: The outputs are not updated at the same time that the input registers are written to. When LDAC goes low, the DAC registers are updated with the contents of the input register. DOUBLE-BUFFERED INTERFACE The AD5308/AD5318/AD5328 DACs all have double-buffered interfaces consisting of two banks of registers: input and DAC. The input registers are connected directly to the input shift register and the digital code is transferred to the relevant input register on completion of a valid write sequence. The DAC registers contain the digital code used by the resistor strings. When the LDAC pin is high and the LDAC bits are set to (01), the DAC registers are latched and the input registers can change state without affecting the contents of the DAC registers. However, when the LDAC bits are set to (00) or when the LDAC pin is brought low, the DAC registers become transparent and the contents of the input registers are transferred to them. The double-buffered interface is useful if the user requires simultaneous updating of all DAC outputs. The user can write up to seven of the input registers individually and then, by bringing LDAC low when writing to the remaining DAC input register, all outputs will update simultaneously. These parts contain an extra feature whereby a DAC register is not updated unless its input register has been updated since the last time LDAC was low. Normally, when LDAC is brought low, the DAC registers are filled with the contents of the input registers. In the case of the AD5308/AD5318/AD5328, the part updates the DAC register only if the input register has been changed since the last time the DAC register was updated, thereby removing unnecessary digital crosstalk. Rev. F | Page 18 of 28 AD5308/AD5318/AD5328 MICROPROCESSOR INTERFACE AD5308/ AD5318/ AD5328* DT SCLK SYNC DIN SCLK *ADDITIONAL PINS OMITTED FOR CLARITY 02812-036 TFS Figure 36. ADSP-2101/ADSP-2103-to-AD5308/AD5318/AD5328 Interface 68HC11/68L11-to-AD5308/AD5318/AD5328 INTERFACE Figure 37 shows a serial interface between the AD5308/AD5318/ AD5328 and the 68HC11/68L11 microcontroller. SCK of the 68HC11/68L11 drives the SCLK of the AD5308/AD5318/AD5328, and the MOSI output drives the serial data line (DIN) of the DAC. The sync signal is derived from a port line (PC7). The set up conditions for the correct operation of this interface are as follows: the 68HC11/68L11 should be configured so that its CPOL bit is a 0 and its CPHA bit is a 1. When data is being transmitted to the DAC, the sync line is taken low (PC7). When the 68HC11/ 68L11 is configured as just described, data appearing on the MOSI output is valid on the falling edge of SCK. Serial data from the 68HC11/ 68L11 is transmitted in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. Data is transmitted MSB first. To load data to the AD5308/AD5318/AD5328, PC7 is left low after the first eight bits are transferred, and a second serial write operation is performed to the DAC. PC7 is taken high at the end of this procedure. PC7 SYNC SCK SCLK MOSI DIN *ADDITIONAL PINS OMITTED FOR CLARITY Figure 37. 68HC11/68L11-to-AD5308/AD5318/ AD5328 Interface 80C51/80L51-to-AD5308/AD5318/AD5328 INTERFACE Figure 38 shows a serial interface between the AD5308/AD5318/ AD5328 and the 80C51/80L51 microcontroller. The setup for the interface is as follows: TxD of the 80C51/80L51 drives SCLK of the AD5308/AD5318/AD5328, while RxD drives the serial data line of the part. The SYNC signal is again derived from a bit programmable pin on the port. In this case, port line P3.3 is used. When data is transmitted to the AD5308/AD5318/AD5328, P3.3 is taken low. The 80C51/80L51 transmits data only in 8-bit bytes; thus, only eight falling clock edges occur in the transmit cycle. To load data to the DAC, P3.3 is left low after the first eight bits are transmitted, and a second write cycle is initiated to transmit the second byte of data. P3.3 is taken high following the completion of this cycle. The 80C51/80L51 outputs the serial data in a format that has the LSB first. The AD5308/AD5318/AD5328 requires its data with the MSB as the first bit received. The 80C51/80L51 transmit routine should take this into account. Rev. F | Page 19 of 28 AD5308/ AD5318/ AD5328* 80C51/80L51* P3.3 SYNC TxD SCLK RxD DIN *ADDITIONAL PINS OMITTED FOR CLARITY Figure 38. 80C51/80L51-to-AD5308/AD5318/AD5328 Interface 02812-038 Figure 36 shows a serial interface between the AD5308/AD5318/ AD5328 and the ADSP-2101/ADSP-2103. The ADSP-2101/ ADSP-2103 should be set up to operate in the SPORT transmit alternate framing mode. The ADSP-2101/ADSP-2103 SPORT is programmed through the SPORT control register and should be configured as follows: internal clock operation, active low framing, and 16-bit word length. Transmission is initiated by writing a word to the Tx register after the SPORT has been enabled. The data is clocked out on each rising edge of the DSP’s serial clock and clocked into the AD5308/AD5318/ AD5328 on the falling edge of the DAC’s SCLK. ADSP-2101/ ADSP-2103* AD5308/ AD5318/ AD5328* 68HC11/68L11 02812-037 ADSP-2101/ADSP-2103-toAD5308/AD5318/AD5328 INTERFACE AD5308/AD5318/AD5328 AD5308/ AD5318/ AD5328* MICROWIRE* Figure 39 shows an interface between the AD5308/AD5318/ AD5328 and any MICROWIRE-compatible device. Serial data is shifted out on the falling edge of the serial clock, SK, and is clocked into the AD5308/AD5318/AD5328 on the rising edge of SK, which corresponds to the falling edge of the DAC’s SCLK. SK SYNC SCLK SO DIN CS *ADDITIONAL PINS OMITTED FOR CLARITY Figure 39. MICROWIRE-to-AD5308/AD5318/AD5328 Interface Rev. F | Page 20 of 28 02812-039 MICROWIRE-to-AD5308/AD5318/AD5328 INTERFACE AD5308/AD5318/AD5328 APPLICATIONS INFORMATION TYPICAL APPLICATION CIRCUIT The AD5308/AD5318/AD5328 can be used with a wide range of reference voltages where the devices offer full, one-quadrant multiplying capability over a reference range of 0.25 V to VDD. More typically, these devices are used with a fixed, precision reference voltage. Suitable references for 5 V operation are the AD780, ADR381, and REF192 (2.5 V references). For 2.5 V operation, a suitable external reference is the AD589 or the AD1580 (1.2 V band gap references). Figure 40 shows a typical setup for the AD5308/AD5318/AD5328 when using an external reference. output is achievable using an AD820, the AD8519, or an OP196 as the output amplifier. R2 10kΩ +5V +6V TO +16V 10μF +5V 0.1μF ±5V VDD VOUTA AD5308/ AD5318/ AD5328 VIN REF192 VOUT GND R1 10kΩ VREFABCD 1μF VREFB VOUTB VOUTC GND VOUTH –5V AD820/ AD8519/ OP196 VDD = 2.5V TO 5.5V 10μF DIN SCLK SYNC VOUTA VIN VOUT 1μF EXT REF SERIAL INTERFACE VOUTB VREFABCD VREFEFGH Figure 41. Bipolar Operation with the AD5308/AD5318/AD5328 AD5308/AD5318/ AD5328 AD780/ADR3811/REF192 WITH VDD = 5V OR AD589/AD1580 WITH VDD = 2.5V 02812-041 0.1μF The output voltage for any input code can be calculated as follows: SCL GND VOUTG VOUTH ⎡ (REFIN × D / 2 N )× (R1 + R2 )⎤ VOUT = ⎢ ⎥ − REFIN × (R2 / R1) R1 ⎣⎢ ⎦⎥ 02812-040 DIN SYNC SERIAL INTERFACE where: Figure 40. AD5308/AD5318/AD5328 Using a 2.5 V or 5 V External Reference DRIVING VDD FROM THE REFERENCE VOLTAGE If an output range of 0 V to VDD is required when the reference inputs are configured as unbuffered, the simplest solution is to connect the reference input to VDD. As this supply can be noisy and not very accurate, the AD5308/AD5318/AD5328 can be powered from a voltage reference. For example, using a 5 V reference, such as the REF195, works because the REF195 outputs a steady supply voltage for the AD5308/AD5318/ AD5328. The typical current required from the REF195 is a 1 μA supply current and ≈ 112 μA into the reference inputs (if unbuffered); this is with no load on the DAC outputs. When the DAC outputs are loaded, the REF195 also needs to supply the current to the loads. The total current required (with a10 kΩ load on each output) is 1.22 mA + 8(5 V/10 kΩ) = 5.22 mA The load regulation of the REF195 is typically 2.0 ppm/mA, which results in an error of 10.4 ppm (52 μV) for the 5.22 mA current drawn from it. This corresponds to a 0.003 LSB error at 8 bits and 0.043 LSB error at 12 bits. BIPOLAR OPERATION USING THE AD5308/AD5318/AD5328 The AD5308/AD5318/AD5328 have been designed for singlesupply operation, but a bipolar output range is also possible using the circuit in Figure 41. This circuit gives an output voltage range of ±5 V. Rail-to-rail operation at the amplifier D is the decimal equivalent of the code loaded to the DAC. N is the DAC resolution. REFIN is the reference voltage input. with REFIN = 5 V , R1 = R2 = 10 kΩ VOUT = (10 × D / 2 N ) − 5 V OPTO-ISOLATED INTERFACE FOR PROCESS CONTROL APPLICATIONS The AD5308/AD5318/AD5328 have a versatile 3-wire serial interface, making them ideal for generating accurate voltages in process control and industrial applications. Due to noise and safety requirements, or distance, it may be necessary to isolate the AD5308/AD5318/AD5328 from the controller. This can easily be achieved by using opto-isolators that provide isolation in excess of 3 kV. The actual data rate achieved may be limited by the type of optocouplers chosen. The serial loading structure of the AD5308/AD5318/AD5328 makes them ideally suited for use in opto-isolated applications. Figure 42 shows an optoisolated interface to the AD5308/AD5318/AD5328 where DIN, SCLK, and SYNC are driven from optocouplers. The power supply to the part also needs to be isolated. This is done by using a transformer. On the DAC side of the transformer, a 5 V regulator provides the 5 V supply required for the AD5308/ AD5318/AD5328. Rev. F | Page 21 of 28 AD5308/AD5318/AD5328 5V REGULATOR VOUTA 10μF POWER 0.1μF VOUTB SCLK SYNC VDD 10kΩ SCLK VDD SCLK SCLK DIN DIN VREFABCD VDD AD5308 VOUTG VOUTH VREFEFGH VCC VDD AD5308/AD5318/ AD5328 CODED ADDRESS VOUTB SYNC VOUTC 1A 1B 1Y0 1Y1 1Y2 1Y3 VOUTB SYNC DIN SCLK DGND VOUTD VOUTE VDD SYNC VOUTH DIN 02812-042 GND VOUTG VOUTH VOUTB VOUTG DIN AD5308 VOUTA VOUTF 10kΩ DIN 1G 74HC139 VOUTA 10kΩ SYNC ENABLE VOUTA SCLK AD5308 VOUTG VOUTH Figure 42. AD5308/AD5318/AD5328 in an Opto-Isolated Interface VOUTA DECODING MULTIPLE AD5308/AD5318/AD5328s Rev. F | Page 22 of 28 VOUTB SYNC DIN SCLK AD5308 VOUTG VOUTH Figure 43. Decoding Multiple AD5308 Devices in a System 02812-043 The SYNC pin on the AD5308/AD5318/AD5328 can be used in applications to decode a number of DACs. In this application, the DACs in the system receive the same serial clock and serial data but only the SYNC to one of the devices is active at any one time, allowing access to four channels in this 16-channel system. The 74HC139 is used as a 2-to-4 line decoder to address any of the DACs in the system. To prevent timing errors from occurring, the enable input should be brought to its inactive state while the coded-address inputs are changing state. Figure 43 shows a diagram of a typical setup for decoding multiple AD5308 devices in a system. AD5308/AD5318/AD5328 Table 10. Overview of AD53xx Serial Devices Part No. SINGLES AD5300 AD5310 AD5320 AD5301 AD5311 AD5321 DUALS AD5302 AD5312 AD5322 AD5303 AD5313 AD5323 QUADS AD5304 AD5314 AD5324 AD5305 AD5315 AD5325 AD5306 AD5316 AD5326 AD5307 AD5317 AD5327 OCTALS AD5308 AD5318 AD5328 Resolution DNL VREF Pins Settling Time (μs) Interface Package Pins 8 10 12 8 10 12 ±0.25 ±0.50 ±1.00 ±0.25 ±0.50 ±1.00 0 (VREF = VDD) 0 (VREF = VDD) 0 (VREF = VDD) 0 (VREF = VDD) 0 (VREF = VDD) 0 (VREF = VDD) 4 6 8 6 7 8 SPI SPI SPI 2-Wire 2-Wire 2-Wire SOT-23, MSOP SOT-23, MSOP SOT-23, MSOP SOT-23, MSOP SOT-23, MSOP SOT-23, MSOP 6, 8 6, 8 6, 8 6, 8 6, 8 6, 8 8 10 12 8 10 12 ±0.25 ±0.50 ±1.00 ±0.25 ±0.50 ±1.00 2 2 2 2 2 2 6 7 8 6 7 8 SPI SPI SPI SPI SPI SPI MSOP MSOP MSOP TSSOP TSSOP TSSOP 10 10 10 16 16 16 8 10 12 8 10 12 8 10 12 8 10 12 ±0.25 ±0.50 ±1.00 ±0.25 ±0.50 ±1.00 ±0.25 ±0.50 ±1.00 ±0.25 ±0.50 ±1.00 1 1 1 1 1 1 4 4 4 2 2 2 6 7 8 6 7 8 6 7 8 6 7 8 SPI SPI SPI 2-Wire 2-Wire 2-Wire 2-Wire 2-Wire 2-Wire SPI SPI SPI MSOP MSOP MSOP MSOP MSOP MSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP 10 10 10 10 10 10 16 16 16 16 16 16 8 10 12 ±0.25 ±0.50 ±1.00 2 2 2 6 7 8 SPI SPI SPI TSSOP TSSOP TSSOP 16 16 16 Table 11. Overview of AD53xx Parallel Devices Part No. SINGLES Resolution DNL VREF Pins Settling Time (μs) Additional Pin Functions BUF GAIN Package Pins AD5330 8 ±0.25 1 6 ✓ ✓ ✓ TSSOP 20 AD5331 10 ±0.50 1 7 AD5340 12 ±1.00 1 8 ✓ ✓ ✓ TSSOP 20 ✓ ✓ TSSOP AD5341 12 ±1.00 1 8 24 ✓ TSSOP ✓ ✓ 20 DUALS AD5332 8 ±0.25 2 6 ✓ TSSOP 20 AD5333 10 ±0.50 2 7 ✓ AD5342 12 ±1.00 2 8 ✓ ✓ ✓ TSSOP 24 ✓ ✓ TSSOP AD5343 12 ±1.00 1 8 28 ✓ TSSOP 20 QUADS AD5334 8 ±0.25 2 6 ✓ TSSOP 24 AD5335 10 ±0.50 2 7 AD5336 10 ±0.50 4 7 ✓ TSSOP 24 ✓ TSSOP AD5344 12 ±1.00 4 8 28 TSSOP 28 HBEN ✓ ✓ ✓ ✓ ✓ Rev. F | Page 23 of 28 CLR AD5308/AD5318/AD5328 OUTLINE DIMENSIONS 5.10 5.00 4.90 16 9 4.50 4.40 4.30 6.40 BSC 1 8 PIN 1 1.20 MAX 0.15 0.05 0.20 0.09 0.30 0.19 0.65 BSC COPLANARITY 0.10 SEATING PLANE 8° 0° 0.75 0.60 0.45 COMPLIANT TO JEDEC STANDARDS MO-153-AB Figure 44. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters ORDERING GUIDE Model 1 , 2 AD5308ARU AD5308ARU-REEL7 AD5308ARUZ AD5308ARUZ-REEL7 AD5308BRU AD5308BRU-REEL AD5308BRU-REEL7 AD5308BRUZ AD5308BRUZ-REEL AD5308BRUZ-REEL7 AD5318ARU AD5318ARU-REEL7 AD5318ARUZ AD5318ARUZ-REEL7 AD5318BRU AD5318BRU-REEL AD5318BRU-REEL7 AD5318BRUZ AD5318BRUZ-REEL AD5318BRUZ-REEL7 AD5328ARU AD5328ARU-REEL7 AD5328ARUZ AD5328ARUZ-REEL7 AD5328BRU AD5328BRU-REEL AD5328BRU-REEL7 AD5328BRUZ AD5328BRUZ-REEL AD5328BRUZ-REEL7 AD5308WARUZ-REEL7 1 2 Temperature Range −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C Package Description 16-Lead Thin Shrink Small Outline Package (TSSOP) 16-Lead Thin Shrink Small Outline Package (TSSOP) 16-Lead Thin Shrink Small Outline Package (TSSOP) 16-Lead Thin Shrink Small Outline Package (TSSOP) 16-Lead Thin Shrink Small Outline Package (TSSOP) 16-Lead Thin Shrink Small Outline Package (TSSOP) 16-Lead Thin Shrink Small Outline Package (TSSOP) 16-Lead Thin Shrink Small Outline Package (TSSOP) 16-Lead Thin Shrink Small Outline Package (TSSOP) 16-Lead Thin Shrink Small Outline Package (TSSOP) 16-Lead Thin Shrink Small Outline Package (TSSOP) 16-Lead Thin Shrink Small Outline Package (TSSOP) 16-Lead Thin Shrink Small Outline Package (TSSOP) 16-Lead Thin Shrink Small Outline Package (TSSOP) 16-Lead Thin Shrink Small Outline Package (TSSOP) 16-Lead Thin Shrink Small Outline Package (TSSOP) 16-Lead Thin Shrink Small Outline Package (TSSOP) 16-Lead Thin Shrink Small Outline Package (TSSOP) 16-Lead Thin Shrink Small Outline Package (TSSOP) 16-Lead Thin Shrink Small Outline Package (TSSOP) 16-Lead Thin Shrink Small Outline Package (TSSOP) 16-Lead Thin Shrink Small Outline Package (TSSOP) 16-Lead Thin Shrink Small Outline Package (TSSOP) 16-Lead Thin Shrink Small Outline Package (TSSOP) 16-Lead Thin Shrink Small Outline Package (TSSOP) 16-Lead Thin Shrink Small Outline Package (TSSOP) 16-Lead Thin Shrink Small Outline Package (TSSOP) 16-Lead Thin Shrink Small Outline Package (TSSOP) 16-Lead Thin Shrink Small Outline Package (TSSOP) 16-Lead Thin Shrink Small Outline Package (TSSOP) 16-Lead Thin Shrink Small Outline Package (TSSOP) Z = RoHS Compliant Part. W = Qualified for Automotive Applications. Rev. F | Page 24 of 28 Package Option RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 AD5308/AD5318/AD5328 AUTOMOTIVE PRODUCTS The AD5308WARUZ-REEL7 model is available with controlled manufacturing to support the quality and reliability requirement s of automotive applications. Note that this automotive model may have specifications that differ from the commercial models; therefore, designers should review the Specifications section of this data sheet carefully. Only the automotive grade product shown is available for use in automotive applications. Contact your local Analog Devices, Inc., account representative for specific product ordering information and to obtain the specific Automotive Reliability report for this model. Rev. F | Page 25 of 28 AD5308/AD5318/AD5328 NOTES Rev. F | Page 26 of 28 AD5308/AD5318/AD5328 NOTES Rev. F | Page 27 of 28 AD5308/AD5318/AD5328 NOTES ©2002–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D02812-0-4/11(F) Rev. F | Page 28 of 28