AD AD9601BCPZ-250 1.8 v analog-to-digital converter Datasheet

10-Bit, 200 MSPS/250 MSPS
1.8 V Analog-to-Digital Converter
AD9601
FEATURES
APPLICATIONS
SNR = 59.4 dBFS @ fIN up to 70 MHz @ 250 MSPS
ENOB of 9.7 @ fIN up to 70 MHz @ 250 MSPS (−1.0 dBFS)
SFDR = 81 dBc @ fIN up to 70 MHz @ 250 MSPS (−1.0 dBFS)
Excellent linearity
DNL = 0.2 LSB typical
INL = 0.2 LSB typical
CMOS outputs
Single data port at up to 250 MHz
Demultiplexed dual port at up to 2 × 125 MHz
700 MHz full power analog bandwidth
On-chip reference, no external decoupling required
Integrated input buffer and track-and-hold
Low power dissipation
274 mW @ 200 MSPS
322 mW @ 250 MSPS
Programmable input voltage range
1.0 V to 1.5 V, 1.25 V nominal
1.8 V analog and digital supply operation
Selectable output data format (offset binary, twos
complement, Gray code)
Clock duty cycle stabilizer
Integrated data capture clock
Wireless and wired broadband communications
Cable reverse path
Communications test equipment
Radar and satellite subsystems
Power amplifier linearization
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The AD9601 is a 10-bit monolithic sampling analog-to-digital
converter optimized for high performance, low power, and ease
of use. The product operates at up to a 250 MSPS conversion
rate and is optimized for outstanding dynamic performance in
wideband carrier and broadband systems. All necessary functions, including a track-and-hold (T/H) and voltage reference,
are included on the chip to provide a complete signal
conversion solution.
1.
High Performance—Maintains 59.4 dBFS SNR @ 250 MSPS
with a 70 MHz input.
2.
Low Power—Consumes only 322 mW @ 250 MSPS.
3.
Ease of Use—CMOS output data and output clock signal
allow interface to current FPGA technology. The on-chip
reference and sample-and-hold provide flexibility in
system design. Use of a single 1.8 V supply simplifies
system power supply design.
4.
Serial Port Control—Standard serial port interface supports
various product functions, such as data formatting, powerdown, gain adjust, and output test pattern generation.
5.
Pin-Compatible Family—12-bit pin-compatible family
offered as the AD9626.
The ADC requires a 1.8 V analog voltage supply and a differential clock for full performance operation. The digital outputs are
CMOS compatible and support either twos complement, offset
binary format, or Gray code. A data clock output is available for
proper output data timing.
Fabricated on an advanced CMOS process, the AD9601 is
available in a 56-lead LFCSP, specified over the industrial
temperature range (−40°C to +85°C).
FUNCTIONAL BLOCK DIAGRAM
RBIAS
PWDN
AGND
AVDD (1.8V)
AD9601
REFERENCE
CML
VIN+
VIN–
DRVDD
DRGND
TRACK-AND-HOLD
ADC
10-BIT
CORE
CLK+
CLK–
10
OUTPUT 10
STAGING
LVDS
CLOCK
MANAGEMENT
Dx9 TO Dx0
OVRA
OVRB
SERIAL PORT
DCO–
RESET SCLK SDIO
CSB
07100-001
DCO+
Figure 1.
Rev. 0
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
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Fax: 781.461.3113
©2007 Analog Devices, Inc. All rights reserved.
AD9601* PRODUCT PAGE QUICK LINKS
Last Content Update: 02/23/2017
COMPARABLE PARTS
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• AD9601 IBIS Models
EVALUATION KITS
REFERENCE MATERIALS
• AD9601 Evaluation Board
Technical Articles
• MS-2210: Designing Power Supplies for High Speed ADC
DOCUMENTATION
Application Notes
DESIGN RESOURCES
• AN-1142: Techniques for High Speed ADC PCB Layout
• AD9601 Material Declaration
• AN-282: Fundamentals of Sampled Data Systems
• PCN-PDN Information
• AN-501: Aperture Uncertainty and ADC System
Performance
• Quality And Reliability
• Symbols and Footprints
• AN-586: LVDS Outputs for High Speed A/D Converters
• AN-715: A First Approach to IBIS Models: What They Are
and How They Are Generated
DISCUSSIONS
View all AD9601 EngineerZone Discussions.
• AN-737: How ADIsimADC Models an ADC
• AN-741: Little Known Characteristics of Phase Noise
SAMPLE AND BUY
• AN-742: Frequency Domain Response of SwitchedCapacitor ADCs
Visit the product page to see pricing options.
• AN-756: Sampled Systems and the Effects of Clock Phase
Noise and Jitter
TECHNICAL SUPPORT
• AN-807: Multicarrier WCDMA Feasibility
• AN-808: Multicarrier CDMA2000 Feasibility
• AN-812: MicroController-Based Serial Port Interface (SPI)
Boot Circuit
• AN-827: A Resonant Approach to Interfacing Amplifiers to
Switched-Capacitor ADCs
Submit a technical question or find your regional support
number.
DOCUMENT FEEDBACK
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• AN-835: Understanding High Speed ADC Testing and
Evaluation
• AN-878: High Speed ADC SPI Control Software
• AN-905: Visual Analog Converter Evaluation Tool Version
1.0 User Manual
Data Sheet
• AD9601: 10-Bit, 200 MSPS/250 MSPS 1.8 V Analog-toDigital Converter Data Sheet
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AD9601
TABLE OF CONTENTS
Features .............................................................................................. 1
Clock Input Considerations...................................................... 17
Applications....................................................................................... 1
Power Dissipation and Power-Down Mode ........................... 18
Functional Block Diagram .............................................................. 1
Digital Outputs ........................................................................... 18
General Description ......................................................................... 1
Timing—Single Port Mode ....................................................... 19
Product Highlights ........................................................................... 1
Timing—Interleaved Mode....................................................... 19
Revision History ............................................................................... 2
Layout Considerations................................................................... 20
Specifications..................................................................................... 3
Power and Ground Recommendations ................................... 20
DC Specifications ......................................................................... 3
CML ............................................................................................. 20
AC Specifications.......................................................................... 4
RBIAS........................................................................................... 20
Digital Specifications ................................................................... 5
AD9601 Configuration Using the SPI ..................................... 20
Switching Specifications .............................................................. 6
Hardware Interface..................................................................... 21
Timing Diagrams.......................................................................... 7
Configuration Without the SPI ................................................ 21
Absolute Maximum Ratings............................................................ 8
Memory Map .................................................................................. 23
Thermal Resistance ...................................................................... 8
Reading the Memory Map Table.............................................. 23
ESD Caution.................................................................................. 8
Reserved Locations .................................................................... 23
Pin Configurations and Function Descriptions ........................... 9
Default Values ............................................................................. 23
Equivalent Circuits ......................................................................... 11
Logic Levels................................................................................. 23
Typical Performance Characteristics ........................................... 12
Evaluation Board ............................................................................ 25
Theory of Operation ...................................................................... 16
Outline Dimensions ....................................................................... 31
Analog Input and Voltage Reference ....................................... 16
Ordering Guide .......................................................................... 31
REVISION HISTORY
11/07—Revision 0: Initial Version
Rev. 0 | Page 2 of 32
AD9601
SPECIFICATIONS
DC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, TMIN = −40°C, TMAX = +85°C, fIN = −1.0 dBFS, full scale = 1.25 V, single port output mode, DCS enabled,
unless otherwise noted.
Table 1.
Parameter 1
RESOLUTION
ACCURACY
No Missing Codes
Offset Error
Temp
Gain Error
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL)
TEMPERATURE DRIFT
Offset Error
Gain Error
ANALOG INPUTS (VIN+, VIN−)
Differential Input Voltage Range 2
Input Common-Mode Voltage
Input Resistance (Differential)
Input Capacitance
POWER SUPPLY
AVDD
DRVDD
Supply Currents
IAVDD 3
IDRVDD3/Single Port Mode 4
IDRVDD3/Interleaved Mode 5
Power Dissipation3
Single Port Mode4
5
Interleaved Mode
Power-Down Mode Supply Currents
IAVDD
IDRVDD
Standby Mode Supply Currents
IAVDD
IDRVDD
Full
25°C
Full
25°C
Full
25°C
Full
25°C
Full
Min
AD9601-200
Typ
Max
10
Min
Guaranteed
4.0
−12
Guaranteed
4.0
+12
−12
+4.5
−2.1
1.4
−2.1
Full
Full
+4.5
0.2
+0.5
−0.5
0.2
−0.5
+12
1.4
0.2
−0.5
AD9601-250
Typ
Max
10
+0.5
0.2
+0.5
−0.5
8
0.021
+0.5
8
0.021
Unit
Bits
mV
mV
% FS
% FS
LSB
LSB
LSB
LSB
μV/°C
%/°C
Full
Full
Full
25°C
0.98
1.25
1.4
4.3
2
1.5
0.98
1.25
1.4
4.3
2
1.5
V p-p
V
kΩ
pF
Full
Full
1.7
1.7
1.8
1.8
1.9
1.9
1.7
1.7
1.8
1.8
1.9
1.9
V
V
Full
Full
Full
Full
Full
133
19
16
142
20
157
22
18
167
24
274
291
322
344
mA
mA
mA
mW
mW
Full
268
315
Full
Full
40
170
40
170
22
μA
μA
Full
Full
19
170
19
170
22
mA
μA
1
mW
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.
The input range is programmable through the SPI, and the range specified reflects the nominal values of each setting. See the Memory Map section.
IAVDD and IDRVDD are measured with a −1 dBFS, 10.3 MHz sine input at rated sample rate.
4
Single data rate mode; this is the default mode of the AD9601.
5
Interleaved mode; user-programmable feature. See the Memory Map section.
2
3
Rev. 0 | Page 3 of 32
AD9601
AC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, TMIN = −40°C, TMAX = +85°C, fIN = −1.0 dBFS, full scale = 1.25 V, DCS enabled, unless otherwise noted. 1
Table 2.
Parameter 2
SNR
fIN = 10 MHz
fIN = 70 MHz
SINAD
fIN = 10 MHz
fIN = 70 MHz
EFFECTIVE NUMBER OF BITS (ENOB)
fIN = 10 MHz
fIN = 70 MHz
WORST HARMONIC (SECOND OR THIRD)
fIN = 10 MHz
fIN = 70 MHz
WORST OTHER (SFDR EXCLUDING SECOND AND THIRD)
fIN = 10 MHz
fIN = 70 MHz
TWO-TONE IMD
170.2 MHz/171.3 MHz @ −7 dBFS
ANALOG INPUT BANDWIDTH
1
2
Temp
Min
AD9601-200
Typ
Max
25°C
Full
25°C
59.5
25°C
Full
25°C
59.5
59.3
25°C
25°C
9.6
9.6
25°C
Full
25°C
84
25°C
Full
25°C
88
87
25°C
25°C
81
700
Min
AD9601-250
Typ
Max
59.4
57.8
dB
dB
dB
57.7
59.4
dB
dB
dB
9.7
9.7
Bits
Bits
58.5
59.3
59.4
59.4
58.5
84
72
dBc
dBc
dBc
75
85
dBc
dBc
dBc
81
700
dBFS
MHz
77
78
Unit
81
86
80
All ac specifications tested by driving CLK+ and CLK− differentially.
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.
Rev. 0 | Page 4 of 32
AD9601
DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, TMIN = −40°C, TMAX = +85°C, fIN = −1.0 dBFS, full scale = 1.25 V, DCS enabled, unless otherwise noted.
Table 3.
Parameter 1
CLOCK INPUTS
Logic Compliance
Internal Common-Mode Bias
Differential Input Voltage
Input Voltage Range
Input Common-Mode Range
High Level Input Voltage (VIH)
Low Level Input Voltage (VIL)
Input Resistance (Differential)
Input Capacitance
LOGIC INPUTS
Logic 1 Voltage
Logic 0 Voltage
Logic 1 Input Current (SDIO)
Logic 0 Input Current (SDIO)
Logic 1 Input Current
(SCLK, PDWN, CSB, RESET)
Logic 0 Input Current
(SCLK, PDWN, CSB, RESET)
Input Capacitance
LOGIC OUTPUTS
High Level Output Voltage
Low Level Output Voltage
Output Coding
1
AD9601-200
Typ
Max
Min
AD9601-250
Typ
Max
Temp
Min
Full
Full
Full
Full
Full
Full
Full
Full
Full
CMOS/LVDS/LVPECL
1.2
0.2
6
AVDD − 0.3
AVDD + 1.6
1.1
AVDD
1.2
3.6
0
0.8
16
20
24
4
CMOS/LVDS/LVPECL
1.2
0.2
6
AVDD − 0.3
AVDD + 1.6
1.1
AVDD
1.2
3.6
0
0.8
16
20
24
4
Full
Full
Full
Full
Full
0.8 × VDD
0.8 × VDD
Unit
V
V p-p
V
V
V
V
kΩ
pF
0
−60
55
0
−60
50
V
V
μA
μA
μA
Full
0
0
μA
25°C
4
4
pF
Full
Full
0.2 × AVDD
0.2 × AVDD
DRVDD − 0.05
DRVDD − 0.05
GND + 0.05
GND + 0.05
Twos complement, Gray code, or offset binary (default)
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.
Rev. 0 | Page 5 of 32
V
V
AD9601
SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, TMIN = −40°C, TMAX = +85°C, fIN = −1.0 dBFS, full scale = 1.25 V, DCS enabled, unless otherwise noted.
Table 4.
Parameter (Conditions)
Maximum Conversion Rate
Minimum Conversion Rate
CLK+ Pulse Width High (tCH)
CLK+ Pulse Width Low (tCL)
Output, Single Data Port Mode 1
Data Propagation Delay (tPD)
DCO Propagation Delay (tCPD)
Data to DCO Skew (tSKEW)
Latency
Output, Interleaved Mode 2
Data Propagation Delay (tPDA, tPDB)
DCO Propagation Delay (tCPDA, tCPDB)
Data to DCO Skew (tSKEWA, tSKEWB )
Latency
Standby Recovery
Power-Down Recovery
Aperture Delay (tA)
Aperture Uncertainty (Jitter, tJ)
1
2
Temp
Full
Full
Full
Full
25°C
25°C
Full
Full
25°C
25°C
Full
Full
25°C
25°C
25°C
Min
200
AD9601-200
Typ
Max
Min
250
AD9601-250
Typ
Max
2.0
2.0
Unit
MSPS
MSPS
ns
ns
3.7
3.4
0.3
6
ns
ns
ns
Cycles
40
2.15
2.15
0
0
2.4
2.4
3.7
3.4
0.3
6
3.5
3.0
0.5
6
250
50
0.1
0.2
See Figure 2.
See Figure 3.
Rev. 0 | Page 6 of 32
40
1.8
1.8
0.55
1.1
0
0
3.5
3.0
0.5
6
250
50
0.1
0.2
0.55
1.1
ns
ns
ns
Cycles
ns
μs
ns
ps rms
AD9601
TIMING DIAGRAMS
N+1
N+2
N+3
N
N+4
tA
N+8
N+5
N+7
N+6
tCLK = 1/fCLK
CLK+
CLK–
tCPD
DCO–
DCO+
DAX
N–7
N–6
N–5
N–4
N–3
N–2
N–1
N
N+1
N+2
07100-042
tSKEW
tPD
Figure 2. Single Port Mode
N+1
N+2
N+3
N
N+4
tA
N+8
N+5
N+6
N+7
tCLK = 1/fCLK
CLK+
CLK–
tCPDA
DCO+
DCO–
tCPDB
tSKEWA
tPDA
DAX
N–6
N–4
N–2
N
N+2
tSKEWB
DBX
N–7
N–5
N–3
Figure 3. Interleaved Mode
Rev. 0 | Page 7 of 32
N–1
N+1
07100-043
tPDB
AD9601
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter
ELECTRICAL
AVDD to AGND
DRVDD to DRGND
AGND to DRGND
AVDD to DRVDD
Dx0 Through Dx9 to DRGND
DCO+/DCO− to DRGND
OVRA/OVRB to DGND
CLK+ to AGND
CLK− to AGND
VIN+ to AGND
VIN− to AGND
SDIO/DCS to DGND
PDWN to AGND
CSB to AGND
SCLK/DFS to AGND
ENVIRONMENTAL
Storage Temperature Range
Operating Temperature Range
Lead Temperature
(Soldering, 10 sec)
Junction Temperature
Rating
−0.3 V to +2.0 V
−0.3 V to +2.0 V
−0.3 V to +0.3 V
−2.0 V to +2.0 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to +3.6 V
−0.3 V to +3.6 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to +3.6 V
−0.3 V to +3.6 V
−0.3 V to +3.6 V
−65°C to +125°C
−40°C to +85°C
300°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
The exposed paddle must be soldered to the ground plane for
the LFCSP package. Soldering the exposed paddle to the
customer board increases the reliability of the solder joints,
maximizing the thermal capability of the package.
Table 6.
Package Type
56-Lead LFCSP (CP-56-2)
θJA
30.4
θJC
2.9
Unit
°C/W
Typical θJA and θJC are specified for a 4-layer board in still air.
Airflow increases heat dissipation, effectively reducing θJA. In
addition, metal in direct contact with the package leads from
metal traces, and through holes, ground, and power planes
reduces the θJA.
150°C
ESD CAUTION
Rev. 0 | Page 8 of 32
AD9601
56
55
54
53
52
51
50
49
48
47
46
45
44
43
DA3
DA2
DA1
DA0 (LSB)
NIC
NIC
DCO+
DCO–
DRGND
DRVDD
AVDD
CLK–
CLK+
AVDD
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
PIN 1
INDICATOR
AD9601
TOP VIEW
(Not to Scale)
PIN 0 (EXPOSED PADDLE) = AGND
42
41
40
39
38
37
36
35
34
33
32
31
30
29
AVDD
AVDD
CML
AVDD
AVDD
AVDD
VIN–
VIN+
AVDD
AVDD
AVDD
RBIAS
AVDD
PWDN
07100-002
DB3
DB4
DB5
DB6
DB7
DB8
(MSB) DB9
OVRB
DRGND
DRVDD
SDIO/DCS
SCLK/DFS
CSB
RESET
15
16
17
18
19
20
21
22
23
24
25
26
27
28
DA4
DA5
DA6
DA7
DA8
(MSB) DA9
DRVDD
DRGND
OVRA
NIC
NIC
(LSB) DB0
DB1
DB2
Figure 4. Pin Configuration
Table 7. Single Data Rate Mode Pin Function Descriptions
Pin No.
30, 32, 33, 34, 37, 38, 39,
41, 42, 43, 46
7, 24, 47
0
8, 23, 48
35
36
40
Mnemonic
AVDD
Description
1.8 V Analog Supply.
DRVDD
AGND 1
DRGND1
VIN+
VIN−
CML
44
45
31
CLK+
CLK−
RBIAS
28
25
RESET
SDIO/DCS
26
27
29
49
50
53
54
55
56
1
2
3
SCLK/DFS
CSB
PWDN
DCO−
DCO+
DA0 (LSB)
DA1
DA2
DA3
DA4
DA5
DA6
1.8 V Digital Output Supply.
Analog Ground.
Digital Output Ground.
Analog Input—True.
Analog Input—Complement.
Common-Mode Output Pin. Enabled through the SPI, this pin provides a reference for the
optimized internal bias voltage for VIN+/VIN−.
Clock Input—True.
Clock Input—Complement.
Set Pin for Chip Bias Current. (Place 1% 10 kΩ resistor terminated to ground.)
Nominally 0.5 V.
CMOS-Compatible Chip Reset (Active Low).
Serial Port Interface (SPI) Data Input/Output (Serial Port Mode); Duty Cycle Stabilizer
Select (External Pin Mode).
Serial Port Interface Clock (Serial Port Mode); Data Format Select Pin (External Pin Mode).
Serial Port Chip Select (Active Low).
Chip Power-Down.
Data Clock Output—Complement.
Data Clock Output—True.
Output Port A Output Bit 0 (LSB).
Output Port A Output Bit 1.
Output Port A Output Bit 2.
Output Port A Output Bit 3.
Output Port A Output Bit 4.
Output Port A Output Bit 5.
Output Port A Output Bit 6.
Rev. 0 | Page 9 of 32
AD9601
Pin No.
4
5
6
10, 11, 51, 52
9
12
13
14
15
16
17
18
19
20
21
22
1
Mnemonic
DA7
DA8
DA9 (MSB)
NIC
OVRA
DB0 (LSB)
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB8
DB9 (MSB)
OVRB
Description
Output Port A Output Bit 7.
Output Port A Output Bit 8.
Output Port A Output Bit 9 (MSB).
Not internally connected.
Output Port A Overrange Output Bit.
Output Port B Output Bit 0 (LSB).
Output Port B Output Bit 1.
Output Port B Output Bit 2.
Output Port B Output Bit 3.
Output Port B Output Bit 4.
Output Port B Output Bit 5.
Output Port B Output Bit 6.
Output Port B Output Bit 7.
Output Port B Output Bit 8.
Output Port B Output Bit 9 (MSB).
Output Port B Overrange Output Bit.
AGND and DRGND should be tied to a common quiet ground plane.
Rev. 0 | Page 10 of 32
AD9601
EQUIVALENT CIRCUITS
AVDD
AVDD
26kΩ
CSB
1kΩ
1.2V
10kΩ
CLK–
07100-003
07100-006
10kΩ
CLK+
Figure 8. Equivalent CSB Input Circuit
Figure 5. Clock Inputs
AVDD
DRVDD
VIN+
BUF
AVDD
2kΩ
AVDD
VIN–
BUF
VCML
~1.4V
2kΩ
07100-004
DRGND
Figure 6. Analog Inputs (VCML = ~1.4 V)
SCLK/DFS
RESET
PDWN
07100-044
BUF
Figure 9. CMOS Outputs (Dx, OVRA, OVRB, DCO+, DCO−)
1kΩ
DRVDD
30kΩ
1kΩ
07100-007
07100-005
SDIO/DCS
Figure 7. Equivalent SCLK/DFS, RESET, PDWN Input Circuit
Figure 10. Equivalent SDIO/DCS Input Circuit
Rev. 0 | Page 11 of 32
AD9601
TYPICAL PERFORMANCE CHARACTERISTICS
AVDD = 1.8 V, DRVDD = 1.8 V, rated sample rate, DCS enabled, TA = 25°C, 1.25 V p-p differential input, AIN = −1 dBFS, unless
otherwise noted.
0
50k
NUMBER OF HITS
–40
60k
–60
–80
20k
–120
10k
10
20
30
40
50
60
70
80
90
100
0
07100-020
0
FREQUENCY (MHz)
SFDR (–40°C)
SNR/SFDR (dB)
80
–80
SFDR (+25°C)
75
70
65
SNR (+25°C)
60
–120
SNR (–40°C)
SNR (+85°C)
55
10
20
30
40
50
60
70
80
90
100
FREQUENCY (MHz)
50
07100-021
0
Figure 12. AD9601-200 64k Point Single-Tone FFT; 200 MSPS, 70.3 MHz
100
150
200
250
300
350
400
450
500
Figure 15. AD9601-200 Single-Tone SNR/SFDR vs. Input Frequency (fIN) and
Temperature with 1.25 V p-p Full Scale; 200 MSPS
90
200MSPS
170.3MHz @ –1.0dBFS
SNR: 59.35dB
ENOB: 9.7 BITS
SFDR: 83dBc
SFDR (dBFS)
80
70
SNR/SFDR (dB)
–40
50
ANALOG INPUT FREQUENCY (MHz)
0
–20
0
07100-024
–100
–60
–80
–100
60
SNR (dBFS)
50
40
SFDR (dBc)
30
SNR (dB)
20
–120
0
10
20
30
40
50
60
FREQUENCY (MHz)
70
80
90
100
Figure 13. AD9601-200 64k Point Single-Tone FFT; 200 MSPS, 170.3 MHz
Rev. 0 | Page 12 of 32
0
90
80
70
60
50
40
30
20
10
0
AMPLITUDE (–dBFS)
Figure 16. AD9601-200 SNR/SFDR vs. Input Amplitude; 170.3 MHz
07100-025
10
07100-022
–140
N+1
SFDR (+85°C)
85
–60
–140
N
90
200MSPS
70.3MHz @ –1.0dBFS
SNR: 59.3dB
ENOB: 9.7 BITS
SFDR: 78dBc
–40
N–1
Figure 14. AD9601-200 Grounded Input Histogram; 200 MSPS
0
–20
N–2
BIN
Figure 11. AD9601-200 64k Point Single-Tone FFT; 200 MSPS, 10.3 MHz
AMPLITUDE (dBFS)
30k
–100
–140
AMPLITUDE (dBFS)
40k
07100-023
–20
AMPLITUDE (dBFS)
70k
200MSPS
10.3MHz @ –1.0dBFS
SNR: 59.48dB
ENOB: 9.58 BITS
SFDR: 83.79dBc
AD9601
1.0
90
0.8
85
SFDR (+25°C)
0.6
80
SNR/SFDR (dB)
INL (LSB)
0.4
0.2
0
–0.2
75
70
SFDR (–40°C)
SFDR (+85°C)
65
–0.4
60
–0.6
128
256
384
512
640
768
896
1024
OUTPUT CODE
50
Figure 17. AD9601-200 INL; 200 MSPS
100
150
200
250
300
350
400
450
500
Figure 20. SNR/SFDR vs. Analog Input Frequency, Interleaved Mode vs.
Temperature
0
350
250MSPS
10.3MHz @ –1.0dBFS
SNR: 59.4dB
ENOB: 9.7 BITS
SFDR: 84dBc
–20
AMPLITUDE (dBFS)
300
TOTAL POWER (mW)
200
150
IAVDD (mA)
IDVDD (mA)
0
5
25
45
65
85
–60
–80
–100
–120
105 125 145 165 185 205 225 245
SAMPLE RATE (MSPS)
–140
07100-027
50
–40
Figure 18. AD9601-200 Power Supply Current vs. Sample Rate
0
20
40
60
80
100
120
FREQUENCY (MHz)
07100-030
250
100
Figure 21. AD9601-250 64k Point Single-Tone FFT; 250 MSPS, 10.3 MHz
1.0
0
0.8
250MSPS
70.3MHz @ –1.0dBFS
SNR: 59.4dB
ENOB: 9.7 BITS
SFDR: 81dBc
–20
0.6
AMPLITUDE (dBFS)
0.4
0.2
0
–0.2
–0.4
–40
–60
–80
–100
–0.6
–1.0
0
128
256
384
512
640
768
OUTPUT CODE
Figure 19. AD9601-200 DNL; 200 MSPS
896
1024
–140
0
20
40
60
80
FREQUENCY (MHz)
100
120
07100-031
–120
–0.8
07100-028
DNL (LSB)
50
SNR (–40°C)
ANALOG INPUT FREQUENCY (MHz)
400
CURRENT (mA)
0
SNR (+25°C)
07100-029
0
07100-026
–1.0
SNR (+85°C)
55
–0.8
Figure 22. AD9601-250 64k Point Single-Tone FFT; 250 MSPS, 70.3 MHz
Rev. 0 | Page 13 of 32
AD9601
0
–20
–40
SFDR (dBFS)
90
80
70
SNR/SFDR (dB)
AMPLITUDE (dBFS)
100
250MSPS
170.3MHz @ –1.0dBFS
SNR: 59.1dB
ENOB: 9.60 BITS
SFDR: 73dBc
–60
–80
60
SNR (dBFS)
50
40
30
–100
SFDR (dBc)
SNR (dB)
20
–120
0
20
40
60
80
100
120
FREQUENCY (MHz)
0
90
80
70
60
50
40
30
20
10
0
AMPLITUDE (–dBFS)
Figure 23. AD9601-250 64k Point Single-Tone FFT; 250 MSPS, 170.3 MHz
07100-035
10
07100-032
–140
Figure 26. AD9601-250 SNR/SFDR vs. Input Amplitude; 250 MSPS, 170.3 MHz
70k
1.0
0.8
60k
0.6
0.4
40k
INL (LSB)
NUMBER OF HITS
50k
30k
0.2
0
–0.2
–0.4
20k
–0.6
10k
N
N+1
N+2
–1.0
BIN
0
128
1024
105 125 145 165 185 205 225 245
384
512
640
768
896
OUTPUT CODE
Figure 24. AD9601-250 Grounded Input Histogram; 250 MSPS
Figure 27. AD9601-250 DNL; 250 MSPS
400
90
85
350
SFDR (+85°C)
80
300
SFDR (+25°C)
TOTAL POWER (mW)
CURRENT (mA)
SNR/SFDR (dB)
256
07100-036
N–1
07100-033
N–2
07100-037
–0.8
0
75
70
SFDR (–40°C)
65
250
200
IAVDD (mA)
150
SNR (+25°C)
100
60
SNR (+85°C)
50
0
50
100
150
200
250
IDVDD (mA)
50
SNR (–40°C)
300
350
400
ANALOG INPUT FREQUENCY (MHz)
450
500
07100-034
55
Figure 25. AD9601-250 Single-Tone SNR/SFDR vs. Input Frequency (fIN) and
Temperature with 1.25 V p-p Full Scale; 250 MSPS
Rev. 0 | Page 14 of 32
0
5
25
45
65
85
SAMPLE RATE (MSPS)
Figure 28. AD9601 Power Supply Current vs. Sample Rate
AD9601
2.5
1.0
0.8
2.0
0.6
AD9601-250
1.5
0.2
GAIN (%FS)
DNL (LSB)
0.4
0
–0.2
AD9601-210
1.0
AD9601-170
0.5
–0.4
–0.6
0
0
128
256
384
512
640
768
OUTPUT CODE
896
–0.5
–60
07100-038
–1.0
–40
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
07100-040
–0.8
Figure 31. Gain vs. Temperature
Figure 29. AD9601-250 DNL; 250 MSPS
6.0
90
SFDR
80
5.5
AD9601-250
5.0
OFFSET (mV)
60
SNR
50
40
4.5
AD9601-210
4.0
AD9601-170
3.5
30
3.0
20
0
75
125
175
225
SAMPLE RATE (MSPS)
275
2.0
–40 –30 –20 –10
0
10
20
30
40
50
60
TEMPERATURE (°C)
Figure 32. Offset vs. Temperature
Figure 30. SNR/SFDR vs. Sample Rate;
AD9626-250 , 170.3 MHz @ −1 dBFS
Rev. 0 | Page 15 of 32
70
80
90
07100-041
2.5
10
07100-039
SNR/SFDR (dB)
70
AD9601
THEORY OF OPERATION
ANALOG INPUT AND VOLTAGE REFERENCE
499Ω
An internal differential voltage reference creates positive and
negative reference voltages that define the 1.25 V p-p fixed span
of the ADC core. This internal voltage reference can be adjusted
by means of SPI control. See the AD9601 Configuration Using
the SPI section for more details.
AD8138
523Ω
VIN–
33Ω
CML
499Ω
Figure 33. Differential Input Configuration Using the AD8138
At input frequencies in the second Nyquist zone and above, the
performance of most amplifiers may not be adequate to achieve
the true performance of the AD9601. This is especially true in
IF undersampling applications where frequencies in the 70 MHz
to 100 MHz range are being sampled. For these applications,
differential transformer coupling is the recommended input
configuration. The signal characteristics must be considered
when selecting a transformer. Most RF transformers saturate at
frequencies below a few millihertz, and excessive signal power
can also cause core saturation, which leads to distortion.
In any configuration, the value of the shunt capacitor, C, is
dependent on the input frequency and may need to be reduced
or removed.
15Ω
1.25V p-p
50Ω
VIN+
AD9601
2pF
VIN–
15Ω
0.1µF
Figure 34. Differential Transformer-Coupled Configuration
As an alternative to using a transformer-coupled input at
frequencies in the second Nyquist zone, the AD8352 differential
driver can be used (see Figure 35).
VCC
0.1µF
0.1µF
0Ω 16
1
ANALOG INPUT
8, 13
11
0.1µF
R
2
VIN+
200Ω
CD
Differential Input Configurations
RD
AD8352
RG
3
Optimum performance is achieved while driving the AD9601
in a differential input configuration. For baseband applications,
the AD8138 differential driver provides excellent performance
and a flexible interface to the ADC. The output common-mode
voltage of the AD8138 is easily set to AVDD/2 + 0.5 V, and the
driver can be configured in a Sallen-Key filter topology to
provide band limiting of the input signal.
AD9601
20pF
0.1µF
The analog input to the AD9601 is a differential buffer. For best
dynamic performance, the source impedances driving VIN+
and VIN− should be matched such that common-mode settling
errors are symmetrical. The analog input is optimized to provide
superior wideband performance and requires that the analog
inputs be driven differentially.
A wideband transformer, such as Mini-Circuits® ADT1-1WT,
can provide the differential analog inputs for applications that
require a single-ended-to-differential conversion. Both analog
inputs are self-biased by an on-chip resistor divider to a
nominal 1.4 V.
AVDD
VIN+
33Ω
499Ω
0.1µF
200Ω
R
4
ANALOG INPUT
Rev. 0 | Page 16 of 32
10
C
5
0.1µF 0Ω
AD9601
VIN– CML
14
0.1µF
0.1µF
Figure 35. Differential Input Configuration Using the AD8352
07100-010
The input stage contains a differential SHA that can be ac- or
dc-coupled. The output-staging block aligns the data, carries
out the error correction, and passes the data to the output
buffers. The output buffers are powered from a separate supply,
allowing adjustment of the output voltage swing. During powerdown, the output buffers go into a high impedance state.
49.9Ω
07100-008
Each stage of the pipeline, excluding the last, consists of a low
resolution flash ADC connected to a switched capacitor DAC
and interstage residue amplifier (MDAC). The residue amplifier
magnifies the difference between the reconstructed DAC output
and the flash input for the next stage in the pipeline. One bit of
redundancy is used in each stage to facilitate digital correction
of flash errors. The last stage simply consists of a flash ADC.
1V p-p
07100-009
The AD9601 architecture consists of a front-end sample-andhold amplifier (SHA) followed by a pipelined switched capacitor
ADC. The quantized outputs from each stage are combined into
a final 10-bit result in the digital correction logic. The pipelined
architecture permits the first stage to operate on a new input
sample, while the remaining stages operate on preceding
samples. Sampling occurs on the rising edge of the clock.
AD9601
For optimum performance, the AD9601 sample clock inputs
(CLK+ and CLK−) should be clocked with a differential signal.
This signal is typically ac-coupled into the CLK+ pin and the
CLK− pin via a transformer or capacitors. These pins are biased
internally and require no additional bias.
Figure 36 shows one preferred method for clocking the AD9601.
The low jitter clock source is converted from single-ended to
differential using an RF transformer. The back-to-back Schottky
diodes across the secondary transformer limit clock excursions
into the AD9601 to approximately 0.8 V p-p differential. This
helps prevent the large voltage swings of the clock from feeding
through to other portions of the AD9601 and preserves the fast
rise and fall times of the signal, which are critical to low jitter
performance.
MINI-CIRCUITS
ADT1–1WT, 1:1Z
0.1µF
XFMR
50Ω
CLOCK
INPUT
AD9510/AD9511/
AD9512/AD9513/
AD9514/AD9515
0.1µF
CLK
50Ω*
CMOS DRIVER
0.1µF
CLK–
0.1µF
Figure 39. Single-Ended 1.8 V CMOS Sample Clock
ADC
AD9601
0.1µF
07100-011
SCHOTTKY
DIODES:
HSM2812
CLOCK
INPUT
AD9510/AD9511/
AD9512/AD9513/
AD9514/AD9515
100Ω
0.1µF
CLK
AD9601
CLK–
07100-012
240Ω
Figure 37. Differential PECL Sample Clock
AD9510/AD9511/
AD9512/AD9513/
AD9514/AD9515
0.1µF
CLK+
CLK
100Ω
0.1µF
CLK
50Ω*
ADC
AD9601
CLK–
50Ω*
*50Ω RESISTORS ARE OPTIONAL.
Figure 38. Differential LVDS Sample Clock
07100-013
CLOCK
INPUT
LVDS DRIVER
ADC
0.1µF
AD9601
CLK–
Figure 40. Single-Ended 3.3 V CMOS Sample Clock
ADC
*50Ω RESISTORS ARE OPTIONAL.
0.1µF
CLK+
*50Ω RESISTOR IS OPTIONAL.
CLK+
PECL DRIVER
0.1µF
OPTIONAL
0.1µF
100Ω
CLK
0.1µF
CLK
CLOCK
INPUT
CMOS DRIVER
Clock Duty Cycle Considerations
0.1µF
240Ω
CLK
0.1µF
AD9510/AD9511/
AD9512/AD9513/
AD9514/AD9515
50Ω*
0.1µF
50Ω*
If a low jitter clock is available, another option is to ac couple a
differential PECL signal to the sample clock input pins, as
shown in Figure 37. The AD9510/AD9511/AD9512/AD9513/
AD9514/AD9515 family of clock drivers offers excellent jitter
performance.
50Ω*
39kΩ
CLK+
Figure 36. Transformer-Coupled Differential Clock
0.1µF
ADC
*50Ω RESISTOR IS OPTIONAL.
100Ω
0.1µF
CLOCK
INPUT
CLK+
AD9601
CLK
CLK–
CLOCK
INPUT
OPTIONAL
0.1µF
100Ω
07100-015
0.1µF
CLOCK
INPUT
In some applications, it is acceptable to drive the sample clock
inputs with a single-ended CMOS signal. In such applications,
CLK+ should be directly driven from a CMOS gate, and the
CLK− pin should be bypassed to ground with a 0.1 μF capacitor
in parallel with a 39 kΩ resistor (see Figure 39). Although the
CLK+ input circuit supply is AVDD (1.8 V), this input is
designed to withstand input voltages up to 3.3 V, making the
selection of the drive logic voltage very flexible.
07100-014
CLOCK INPUT CONSIDERATIONS
Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals. As a result, these ADCs may
be sensitive to the clock duty cycle. Commonly, a 5% tolerance
is required on the clock duty cycle to maintain dynamic performance characteristics. The AD9601 contains a duty cycle
stabilizer (DCS) that retimes the nonsampling edge, providing
an internal clock signal with a nominal 50% duty cycle. This
allows a wide range of clock input duty cycles without affecting
the performance of the AD9601. When the DCS is on, noise
and distortion performance are nearly flat for a wide range of
duty cycles. However, some applications may require the DCS
function to be off. If so, keep in mind that the dynamic range
performance can be affected when operated in this mode. See the
AD9601 Configuration Using the SPI section for more details
on using this feature.
The duty cycle stabilizer uses a delay-locked loop (DLL) to
create the nonsampling edge. As a result, any changes to the
sampling frequency require approximately eight clock cycles
to allow the DLL to acquire and lock to the new rate.
Rev. 0 | Page 17 of 32
AD9601
Clock Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality of the
clock input. The degradation in SNR for a full-scale input signal
at a given input frequency (fA) due only to aperture jitter (tJ) can
be calculated by
SNR Degradation = 20 × log10[1/2 × π × fA × tJ]
In this equation, the rms aperture jitter represents the root mean
square of all jitter sources, including the clock input, analog input
signal, and ADC aperture jitter specifications. IF undersampling
applications are particularly sensitive to jitter (see Figure 41).
The clock input should be treated as an analog signal in cases
where aperture jitter may affect the dynamic range of the AD9601.
Power supplies for clock drivers should be separated from the
ADC output driver supplies to avoid modulating the clock signal
with digital noise. Low jitter, crystal controlled oscillators make
the best clock sources. If the clock is generated from another
type of source (by gating, dividing, or other methods), it should
be retimed by the original clock at the last step.
Refer to the AN-501 Application Note and the AN-756
Application Note for more in-depth information about jitter
performance as it relates to ADCs (visit www.analog.com).
130
RMS CLOCK JITTER REQUIREMENT
90
14 BITS
The off-chip drivers on the AD9601 are CMOS-compatible
output levels. The outputs are biased from a separate supply
(DRVDD), allowing isolation from the analog supply and easy
interface to external logic. The outputs are CMOS devices that
swing from ground to DRVDD (with no dc load). It is recommended to minimize the capacitive load the ADC drives by
keeping the output traces short (<1 inch, for a total CLOAD < 5 pF).
When operating in CMOS mode, it is also recommended to
place low value (20 Ω) series damping resistors on the data lines
to reduce switching transient effects on performance.
The format of the output data is offset binary by default. An
example of the output coding format can be found in Table 11.
If it is desired to change the output data format to twos complement, see the AD9601 Configuration Using the SPI section.
12 BITS
70
10 BITS
60
8 BITS
50
40
1
0.125ps
0.25ps
0.5ps
1.0ps
2.0ps
10
100
ANALOG INPUT FREQUENCY (MHz)
1000
Figure 41. Ideal SNR vs. Input Frequency and Jitter for 0 dBFS Input Signal
POWER DISSIPATION AND POWER-DOWN MODE
As shown in Figure 28, the power dissipated by the AD9601 is
proportional to its sample rate. The digital power dissipation
does not vary much because it is determined primarily by the
DRVDD supply and bias current of the LVDS output drivers.
An out-of-range condition exists when the analog input voltage
is beyond the input range of the ADC. OVRA/OVRB is a digital
output that is updated along with the data output corresponding
to the particular sampled input voltage. Thus, OVRA/OVRB
has the same pipeline latency as the digital data. OVRA/OVRB
is low when the analog input voltage is within the analog input
range and high when the analog input voltage exceeds the input
range, as shown in Figure 42. OVRA/OVRB remains high until
the analog input returns to within the input range and another
conversion is completed. By logically AND-ing OVRA/OVRB
with the MSB and its complement, overrange high or underrange low conditions can be detected.
By asserting PDWN (Pin 29) high, the AD9601 is placed in
standby mode or full power-down mode, as determined by the
contents of Serial Port Register 08. Reasserting the PDWN pin
low returns the AD9601 into its normal operational mode.
An additional standby mode is supported by means of varying
the clock input. When the clock rate falls below 20 MHz, the
AD9601 assumes a standby state. In this case, the biasing network
Rev. 0 | Page 18 of 32
OVRA/OVRB
DATA OUTPUTS
1
0
0
1111 1111 1111
1111 1111 1111
1111 1111 1110
+FS – 1 LSB
OVRA/
OVRB
–FS + 1/2 LSB
0
0
1
0000 0000 0001
0000 0000 0000
0000 0000 0000
–FS
–FS – 1/2 LSB
+FS
+FS – 1/2 LSB
07100-017
80
30
Digital Outputs and Timing
Out-of-Range
07100-016
SNR (dB)
110
16 BITS
DIGITAL OUTPUTS
An output clock signal is provided to assist in capturing data
from the AD9601. The DCO+/DCO− signal is used to clock the
output data and is equal to the sampling clock (CLK) rate in
single port mode, and one-half the clock rate in interleaved
output mode. See the timing diagrams shown in Figure 2 and
Figure 3 for more information.
120
100
and internal reference remain on, but digital circuitry is powered
down. Upon reactivating the clock, the AD9601 resumes normal
operation after allowing for the pipeline latency.
Figure 42. OVRA/OVRB Relation to Input Voltage and Output Data
AD9601
TIMING—SINGLE PORT MODE
In single port mode, the CMOS output data is available from
Data Port A (DA0 to DA9). The outputs for Port B (DB0 to
DB9) are unused, and are high impedance in this mode.
The Port A outputs and the differential output data clock
(DCO+/DCO−) switch nearly simultaneously during the rising
edge of DCO+. In this mode, it is recommended to use the
rising edge of DCO− to capture the data from Port A. The setup
and hold time depends on the input sample clock period, and is
approximately 1/fCLK ± tSKEW.
TIMING—INTERLEAVED MODE
In interleaved mode, the output data of the AD9601 is demultiplexed onto two data port buses, Port A (DA0 to DA9) and
Port B (DB0 to DB9). The output data and differential data
capture clock switch at one-half the rate of the sample clock
input (CLK+/CLK−), increasing the setup and hold time for the
external data capture circuit relative to single port mode (see
Figure 3, interleaved mode timing diagram). The two ports
switch on alternating sample clock cycles, with the data for
Port A being valid during the rising edge of DCO+, and the
data for Port B being valid during the rising edge of DCO−. The
pipeline latency for both ports is six sample clock cycles. Due to
the random nature of the ÷2 circuit that generates the timing
for the output stage in interleaved mode, the first data sample
during power-up can be assigned to either Data Port A or Port
B. The user cannot control the polarity of the output data clock
relative to the input sample clock. In this mode, it is recom-
mended to use the rising edge of DCO+ to capture the data
from Port A, and the rising edge of DCO− to capture the data
from Port B. In both cases, the setup and hold time depends on
the input sample clock period, and both are approximately
2/fS ± tSKEW.
fS/2 Spurious
Because the AD9601 output data rate is at one-half the sampling
frequency in interleaved output mode, there is significant fS/2
energy in the outputs of the part, and there is significant energy
in the ADC output spectrum at fS/2. Care must be taken to be
certain that this fS/2 energy does not couple into either the clock
circuit or the analog inputs of the AD9601. When fS/2 energy is
coupled in this fashion, it appears as a spurious tone reflected
around fS/4, 3fS/4, 5fS/4, and so on. For example, in a 125 MSPS
sampling application with a 90 MHz single-tone analog input,
this energy generates a tone at 97.5 MHz.
[(3 × 125 MSPS/4 − 90 MHz) + 3 × 125 MSPS/4]
Depending on the relationship of the IF frequency to the center
of the Nyquist zone, this spurious tone may or may not be in the
user’s band of interest. Some residual fS/2 energy is present in
the AD9601, and the level of this spur is typically below the
level of the harmonics at clock rates. Figure 20 shows a plot of
the fS/2 spur level vs. the analog input frequency for the
AD9601-250. For the specifications provided in Table 2, the fS/2
spur effect is not a factor, as the device is specified in single port
output mode.
Rev. 0 | Page 19 of 32
AD9601
LAYOUT CONSIDERATIONS
POWER AND GROUND RECOMMENDATIONS
RBIAS
When connecting power to the AD9601, it is recommended
that two separate supplies be used: one for analog (AVDD, 1.8 V
nominal) and one for digital (DRVDD, 1.8 V nominal). If only a
single 1.8 V supply is available, it is routed to AVDD first, then
tapped off and isolated with a ferrite bead or filter choke with
decoupling capacitors proceeding connection to DRVDD. The
user can employ several different decoupling capacitors to cover
both high and low frequencies. These should be located close to
the point of entry at the PC board level and close to the parts
with minimal trace length.
The AD9601 requires the user to place a 10 kΩ resistor between
the RBIAS pin and ground. This resistor sets the master current
reference of the ADC core and should have at least a 1% tolerance.
A single PC board ground plane is sufficient when using the
AD9601. With proper decoupling and smart partitioning of
analog, digital, and clock sections of the PC board, optimum
performance is easily achieved.
Exposed Paddle Thermal Heat Slug Recommendations
It is required that the exposed paddle on the underside of the
ADC be connected to analog ground (AGND) to achieve the
best electrical and thermal performance of the AD9601. An
exposed, continuous copper plane on the PCB should mate to
the AD9601 exposed paddle, Pin 0. The copper plane should
have several vias to achieve the lowest possible resistive thermal
path for heat dissipation to flow through the bottom of the PCB.
These vias should be solder-filled or plugged.
To maximize the coverage and adhesion between the ADC and
PCB, partition the continuous plane by overlaying a silkscreen
on the PCB into several uniform sections. This provides several
tie points between the two during the reflow process. Using one
continuous plane with no partitions guarantees only one tie
point between the ADC and PCB. See Figure 43 for a PCB layout
example. For detailed information on packaging and the PCB
layout of chip scale packages, see Application Note AN-772,
A Design and Manufacturing Guide for the Lead Frame Chip
Scale Package.
07100-018
SILKSCREEN PARTITION
PIN 1 INDICATOR
Figure 43. Typical PCB Layout
CML
The CML pin should be decoupled to ground with a 0.1 μF
capacitor, as shown in Figure 45.
AD9601 CONFIGURATION USING THE SPI
The AD9601 SPI allows the user to configure the converter for
specific functions or operations through a structured register
space inside the ADC. This gives the user added flexibility to
customize device operation depending on the application.
Addresses are accessed (programmed or read back) serially in
one-byte words. Each byte can be further divided down into
fields, which are documented in the Memory Map section.
There are three pins that define the serial port interface or SPI
to this particular ADC. They are the SPI SCLK/DFS, SPI
SDIO/DCS, and CSB pins. The SCLK/DFS (serial clock) is used
to synchronize the read and write data presented the ADC. The
SDIO/DCS (serial data input/output) is a dual-purpose pin that
allows data to be sent and read from the internal ADC memory
map registers. The CSB is an active low control that enables or
disables the read and write cycles (see Table 8).
Table 8. Serial Port Pins
Mnemonic
SCLK
SDIO
CSB
RESET
Function
SCLK (Serial Clock) is the serial shift clock in.
SCLK is used to synchronize serial interface
reads and writes.
SDIO (Serial Data Input/Output) is a dual-purpose
pin. The typical role for this pin is an input and
output depending on the instruction being sent
and the relative position in the timing frame.
CSB (Chip Select Bar) is an active low control that
gates the read and write cycles.
Master Device Reset. When asserted, device
assumes default settings. Active low.
The falling edge of the CSB, in conjunction with the rising edge
of the SCLK, determines the start of the framing. An example of
the serial timing and its definitions can be found in Figure 44
and Table 10.
During an instruction phase, a 16-bit instruction is transmitted.
Data then follows the instruction phase and is determined by
the W0 and W1 bits, which is 1 or more bytes of data. All data is
composed of 8-bit words. The first bit of each individual byte of
serial data indicates whether this is a read or write command.
This allows the serial data input/output (SDIO) pin to change
direction from an input to an output.
Data can be sent in MSB or in LSB first mode. MSB first is
default on power-up and can be changed by changing the
configuration register. For more information about this feature
and others, see Interfacing to High Speed ADCs via SPI at
www.analog.com.
Rev. 0 | Page 20 of 32
AD9601
HARDWARE INTERFACE
CONFIGURATION WITHOUT THE SPI
The pins described in Table 8 comprise the physical interface
between the user’s programming device and the serial port of
the AD9601. All serial pins are inputs, which is an open-drain
output and should be tied to an external pull-up or pull-down
resistor (suggested value of 10 kΩ).
In applications that do not interface to the SPI control registers,
the SPI SDIO/DCS and SPI SCLK/DFS pins can alternately
serve as standalone CMOS-compatible control pins. When the
device is powered up, it is assumed that the user intends to use
the pins as static control lines for the duty cycle stabilizer. In
this mode, the SPI CSB chip select should be connected to
ground, which disables the serial port interface.
This interface is flexible enough to be controlled by either
PROMS or PIC microcontrollers as well. This provides the user
with an alternate method to program the ADC other than a SPI
controller.
Table 9. Mode Selection
Mnemonic
SPI SDIO/DCS
If the user chooses not to use the SPI interface, some pins serve
a dual function and are associated with a specific function when
strapped externally to AVDD or ground during device poweron. The Configuration Without the SPI section describes the
strappable functions supported on the AD9601.
tDS
tS
tHI
SPI SCLK/DFS
External
Voltage
AVDD
AGND
AVDD
AGND
Configuration
Duty cycle stabilizer enabled
Duty cycle stabilizer disabled
Twos complement enabled
Offset binary enabled
tCLK
tDH
tH
tLO
CSB
SDIO DON’T CARE
DON’T CARE
R/W
W1
W0
A12
A11
A10
A9
A8
A7
D5
Figure 44. Serial Port Interface Timing Diagram
Rev. 0 | Page 21 of 32
D4
D3
D2
D1
D0
DON’T CARE
07100-019
SCLK DON’T CARE
AD9601
Table 10. Serial Timing Definitions
Parameter
tDS
tDH
tCLK
tS
tH
tHI
tLO
tEN_SDIO
Timing (minimum, ns)
5
2
40
5
2
16
16
1
tDIS_SDIO
5
Description
Setup time between the data and the rising edge of SCLK
Hold time between the data and the rising edge of SCLK
Period of the clock
Setup time between CSB and SCLK
Hold time between CSB and SCLK
Minimum period that SCLK should be in a logic high state
Minimum period that SCLK should be in a logic low state
Minimum time for the SDIO pin to switch from an input to an output relative to the SCLK
falling edge (not shown in Figure 44)
Minimum time for the SDIO pin to switch from an output to an input relative to the SCLK
rising edge (not shown in Figure 44)
Table 11. Output Data Format
Input (V)
VIN+ − VIN−
VIN+ − VIN−
VIN+ − VIN−
VIN+ − VIN−
VIN+ − VIN−
Condition (V)
< 0.62
= 0.62
=0
= 0.62
> 0.62 + 0.5 LSB
Offset Binary Output Mode
D11 to D0
0000 0000 0000
0000 0000 0000
0000 0000 0000
1111 1111 1111
1111 1111 1111
Twos Complement Mode
D11 to D0
0000 0000 0000
0000 0000 0000
0000 0000 0000
1111 1111 1111
1111 1111 1111
Rev. 0 | Page 22 of 32
Gray Code Mode
(SPI Accessible)
D11 to D0
0000 0000 0000
0000 0000 0000
0000 0000 0000
0000 0000 0000
0000 0000 0000
OR
1
0
0
0
1
AD9601
MEMORY MAP
READING THE MEMORY MAP TABLE
RESERVED LOCATIONS
Each row in the memory map table has eight address locations.
The memory map is roughly divided into three sections: chip
configuration register map (Address 0x00 to Address 0x02),
transfer register map (Address 0xFF), and program register map
(Address 0x08 to Address 0x2A).
Undefined memory locations should not be written to other
than their default values suggested in this data sheet. Addresses
that have values marked as 0 should be considered reserved and
have a 0 written into their registers during power-up.
The Addr (Hex) column of the memory map indicates the
register address in hexadecimal, and the Default Value (Hex)
column shows the default hexadecimal value that is already
written into the register. The Bit 7 (MSB) column is the start of
the default hexadecimal value given. For example, Hexadecimal
Address 0x09, clock, has a hexadecimal default value of 0x01.
This means Bit 7 = 0, Bit 6 = 0, Bit 5 = 0, Bit 4 = 0, Bit 3 = 0,
Bit 2 = 0, Bit 1 = 0, and Bit 0 = 1, or 0000 0001 in binary. The
default value enables the duty cycle stabilizer. Overwriting this
default so that Bit 0 = 0 disables the duty cycle stabilizer. For more
information on this and other functions, consult the Interfacing
to High Speed ADCs via SPI user manual at www.analog.com.
Coming out of reset, critical registers are preloaded with default
values. These values are indicated in Table 12. Other registers
do not have default values and retain the previous value when
exiting reset.
DEFAULT VALUES
LOGIC LEVELS
An explanation of various registers follows: “Bit is set” is
synonymous with “bit is set to Logic 1” or “writing Logic 1 for
the bit.” Similarly, “clear a bit” is synonymous with “bit is set to
Logic 0” or “writing Logic 0 for the bit.”
Table 12. Memory Map Register
Addr
Bit 7
(Hex) Parameter Name
(MSB)
Chip Configuration Registers
00
chip_port_config
0
01
chip_id
02
chip_grade
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
LSB
first
Soft reset
1
1
Soft reset
LSB first
0
8-bit chip ID, Bits[7:0]
AD9601 = 0x36
0
0
0
Transfer Register
FF
device_update
0
0
0
0
ADC Functions
08
modes
0
0
PDWN:
0 = full
(default)
1=
standby
0
Default
Value
(Hex)
0x18
Readonly
Default Notes/
Comments
The nibbles
should be
mirrored by the
user so that LSB
or MSB first mode
registers correctly,
regardless of shift
mode.
Default is unique
chip ID, different
for each device.
This is a readonly register.
Child ID used to
differentiate
graded devices.
X
X
X
Readonly
0
0
0
SW
transfer
0x00
Synchronously
transfers data
from the master
shift register to
the slave.
0
Internal power-down mode:
000 = normal (power-up, default)
001 = full power-down
010 = standby
011 = normal (power-up)
Note: external PDWN pin overrides
this setting
0x00
Determines
various generic
modes of chip
operation.
Speed grade:
01 = 200 MSPS
10 = 250 MSPS
Rev. 0 | Page 23 of 32
AD9601
Addr
(Hex)
09
Parameter Name
clock
OD
test_io
OF
ain_config
0
14
output_mode
16
output_phase
17
flex_output_delay
18
flex_vref
Bit 7
(MSB)
0
Bit 6
0
Bit 2
0
Bit 1
0
Bit 0
(LSB)
Duty cycle
stabilizer:
0=
disabled
1=
enabled
(default)
Bit 5
0
Bit 4
0
Bit 3
0
Reset
PN23 gen:
1 = on
0 = off
(default)
Reset
PN9 gen:
1 = on
0 = off
(default)
0
0
0
0
0
Output
enable:
0=
enable
(default)
1=
disable
Output
clock
polarity
1=
inverted
0=
normal
(default)
Output
delay
enable:
0=
enable
1=
disable
0
Interleave
output
mode:
1=
enabled
0=
disabled
(default)
0
Output test mode:
0000 = off (default)
0001 = midscale short
0010 = +FS short
0011 = −FS short
0100 = checker board output
0101 = PN 23 sequence
0110 = PN 9
0111 = one/zero word toggle
1000 = unused
1001 = unused
1010 = unused
1011 = unused
1100 = unused
(Format determined by output_mode)
CML
0
0
Analog
enable:
input
disable:
1 = on
0 = off
1 = on
(default)
0 = off
(default)
Data format select:
0
Output
00 = offset binary
invert:
(default)
1 = on
01 = twos
0 = off
complement
(default)
10 = Gray code
0
Default
Value
(Hex)
0x01
0x00
0x00
0x00
0x03
Output clock delay:
00000 = 0.1 ns
00001 = 0.2 ns
00010 = 0.3 ns
…
11101 = 3.0 ns
11110 = 3.1 ns
11111 = 3.2 ns
Input voltage range setting:
10000 = 0.98 V
10001 =1.00 V
10010 = 1.02 V
10011 =1.04 V
…
11111 = 1.23 V
00000 = 1.25 V
00001 = 1.27 V
…
01110 = 1.48 V
01111 = 1.50 V
Rev. 0 | Page 24 of 32
0x00
0x00
Default Notes/
Comments
When set, the
test data is
placed on the
output pins in
place of normal
data.
GND
L1
10NH
R4
DNP
C16
2
4
5
3
T5
4
2
5
PRI SEC
3
1
PRI SEC
6
1
Rev. 0 | Page 25 of 32
Figure 45. AD9601 Evaluation Board Schematic Page 1
GND
GND
XTALINPUT
R3
50
GND
R15
DNP
0.1UF
C23
VCLK
6
VCLK
GND
3
2
C74
0.1UF
E20
E19
GND
VCLK
GND
AVDD
TRI_STATE
45
NC
R86
10K
R85
10K
0.1UF
C61
51
E18
VOLT_CONTROL
VCLK
52
5
VOLT_CONTROL
1
AVDD
OUTPUT
CVHD_956 Crystek Crystal
U6
OPTIONAL ENCODE CIRCUITS
DNP
XTALINPUT 4
R90
00
GND
CLK
49
0
R87
4
PRI SEC
3
0
J4
PRI SEC
ETC1-1-13
nc
43
GND
44
ENCODE
CLKCT
U4
AD9601_CSP
DRVDD
ADT1-1WT
1
6
5
2
GND
GND
CLKCT
VSPI
E3
47
50
46
T2
CLK
CLK
R1
CLKB
GND
AVDD_FL
AVDD_FL1
SPSCLK/DFS
AVDD_CLK
42
41
CML
AVDD_PIPE
AVDD_PIPE1
AVDD_PIPE2
AINB
AIN
AVDD_PIPE3
AVDD_PIPE4
AVDD_PIPE5
RBIAS
AVDD_REF
SPSDIO/DCS
AVDD_CLK1
48
R89
00
CML
R17
0 DNP
AVDD
AVDD
40
39
38
37
36
35
34
33
32
31
30
DVDD2
R8
00
C18
AMPOUT-
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
29
E1
E2
DGND2
J3
5
2
4
0.1UF
GND
R9
DNP
E8
RESETB
PDN
E4
E10
DCOB
R14
DNP
C20
DNP
T6
GND
R6
36
CML
R5
36
AMPOUT+
E9
E7
E5
R10
1K
DCO
GND
C19
0.1UF
GND
VSPI
GND
VSPI
R13
1K
CSB_DUT
D0B
GND
GND
3
TOUTB
C22
0.1UF
GND
GND
1
E6
CML
TOUT
TOUT
CML
TOUTB
EVQ-Q2
2
OUT
R11
1K
AVDD
P10
P9
GND
GND
DVDD1
ETC1-1-13
GND
TINB
0.1UF
GND
CML nc
TINB
1
SW3
P1
P17
P16
VSPI
D0
CR2 TO MAKE LAYOUT AND PARASITIC LOADING SYMMETRICAL
J2
GND
Input
T3
ADT1-1WT
Alternate Options
GND
IN
L8
0
ANALOG
R12
10K
GND
R7
33
GND
GND
DGND1
L9
SPCSB
0.1UF
C21
GND
DNP
P5
P4
P3
P2
D11B
C15
0.1UF
E32
D1
C75
28
D1B
3
27
D10
2
SCLK_DTP
26
DOR
C17
CSB
SDIO_ODM
25
optional
DRVDD
24
DORB
R16
33
GND
23
D11
CMLX
22
E31
E33
D2B
0.1UF
21
CR3
20
D9
11
10
9
6
7
8
13
4
10
14
3
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
8
15
2
9
12
16
1
7
RN4
50_OHMS
RN3
50_OHMS
9
10
11
12
13
14
15
11
8
7
6
5
4
3
2
6
DRVDD
GND
12
5
5
6
7
8
9
10
11
12
13
14
13
4
16
14
3
1
15
2
RN2
16
1
50_OHMS
RN1
50_OHMS
5
D4 4
D4B
3
D3
2
D3B
1
PAD
D5B
D5
DVDD
DGND
D6B
D6
D7B
D7
D8B
D8
CSB
57
1
19
D10B
1
2
18
CR2
17
56
3
16
D9B
GND
15
DCOB
DCO
D0B
D0
D1B
D1
D2B
D2
D3B
D3
D4B
D4
D5B
D5
D6B
D6
D7B
D7
D8B
D8
D9B
D9
D10B
D10
D11B
D11
DORB
DOR
D1
D3
D5
D7
D9
D11
D0
D2
D4
D6
D8
D10
DOR
GNDAB1
GNDAB2
GNDAB3
GNDAB4
GNDAB5
GNDAB6
GNDAB7
GNDAB8
GNDAB9
GNDAB10
GNDCD1
GNDCD2
GNDCD3
GNDCD4
GNDCD5
GNDCD6
GNDCD7
GNDCD8
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
D1
D2
D3
D4
D5
D6
D7
D8
D9
11
12
13
14
15
16
17
18
19
20
41
42
43
44
45
46
47
48
49
50
GNDCD10
GNDCD6
GNDCD7
D7
D8
GNDCD1
GNDCD2
GNDCD3
GNDCD4
D2
D3
D4
D5
A1
A2
A3
A4
A5
A6
B1
GNDAB1 B2
GNDAB2 B3
GNDAB3 B4
GNDAB4 B5
GNDAB5 B6
GNDAB6
GNDAB7 B8
A8
B7
GNDAB8 B9
A9
A7
GNDAB9 B10
A10
C1 GNDAB10 D1
C2
C3
C4
C5
C6 GNDCD5 D6
C7
C8
C9 GNDCD8 D9
C10 GNDCD9 D10
11
12
13
14
15
16
17
18
19
20
41
42
43
44
45
46
47
48
49
50
SDO_CHA
SDI_CHA
SCLK_CHA
DCOB
D1B
D3B
D5B
D7B
D9B
D11B
D0B
D2B
D4B
D6B
D8B
D10B
DORB
HEADERM1469169_1
60
40
59
39
58
38
57
37
56
36
55
35
54
34
53
33
52
32
51
31
30
10
29
9
28
8
27
7
26
6
25
5
24
4
23
3
22
2
21
1
P11
CONNECTS TO J1
HEADERM1469169_1
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10 GNDCD9 D10
GNDCD10
P7
CONNECTS TO J2
60
40
59
39
58
38
57
37
56
36
55
35
54
34
53
33
52
32
51
31
30
10
29
9
28
8
27
7
26
6
25
5
24
4
23
3
22
2
21
1
CSB1_CHA
GND
DCO
GND
07100-045
GND
GND
GND
AD9601
EVALUATION BOARD
D2
55
GND
54
53
50
GND
GND
ADP3338
U10
+5V
VAMPX
4
OUT
EGND
EGND
10UF
C11
IN
3
OUT1
2
2
3
1
GND
GND
U7
ADP3338
U9
EGND
T1
AVDDX
1.8V
1
GND
2
3
GND
GND
U8
FERRITE
4
4
EGND
IN
+
GND
1UF
Figure 46. AD9601 Evaluation Board Schematic Page 2
L7
3
OUT
2
FERRITE
GND
1
VAMPX
VAMP1
1UF
GND
L4
OUT1
AVDDX
AVDD1
ADP3338
U12
DRVDDX1
499
R2
1.8V
4
PJ-102A
L5
IN
3
VIN
DRVDDX
OUT
2
DRVDDX1
GND
VIN
GND
1
OUT1
VSPI
P8
1UF
DRVDD1
C6
R88
1
GND
FERRITE
C2
L3
VIN
FERRITE
GND
GND
C9
GND
0.1UF
C36
10UF
VSPI
GND
DRVDD
GND
+
+
ADP3338
U11
C4
FERRITE
0.1UF
C26
3.3V
VSPIEXTX
0.1UF
C35
C30
0.1UF
C31
0.1UF
0.1UF
C39
0.1UF
+
GND
VSPIEXT
GND
10UF
C54
C29
0.1UF
VCLK
GND
C59
0.1UF
C28
0.1UF
0.1UF
0.1UF
P6
H1
MTHOLE6
H2
MTHOLE6
H3
MTHOLE6
H4
MTHOLE6
C12 +
10UF
C62
0.1UF
C66
0.1UF
C13
VAMP1
AVDD1
GND
GND
DRVDD1
GND
VSPIEXT1
GND
C34
0.1UF
C63
0.1UF
0.1UF
C67
C64
0.1UF
C14
0.1UF
10UF
L12
FERRITE
L13
FERRITE
L14
FERRITE
L15
FERRITE
GND
VAMP
C68
+
0.1UF
C69
C65
0.1UF
VAMP
AVDD
DRVDD
VSPIEXT
C58
C8
10UF
L2
OUT1
0.1UF
0.1UF
C32
0.1UF
C25
L6
0.1UF
C72
C70
+5.0V
1.8V
1.8V
3.3V
C57
C71
0.1UF
C73
C56
C33
0.1UF
IN
3
VIN
VSPIEXT1
4
OUT
VSPIEXTX
FERRITE
2
GND
1
GND
VCLK
C27
8
7
6
Rev. 0 | Page 26 of 32
5
C5
4
C7
3
C1
GND
2
C3
1
0.1UF
0.1UF
POWER OPTIONS
100PF
07100-046
C24
AVDD
AD9601
VSPIEXTX
1UF
1UF
0
1UF
VIN
C10
1UF
1UF
0.1UF
C60
0.1UF
P14
P15
SMBMST
SMBMST
P12
SMBMST
R34
DNP
TINB2
TINB1
GND
GND
50
R48
R49
DNP
GND
R35
DNP
2
4
3
GND
R50
DNP
00
R51
GND
5
1
T7
TINB2
TINB1
2
4
5
3
TOUTB2
TOUT2
TOUTB2
PRI SEC
6
1
GND
nc
TOUT2
T4
ADT1-1WT
R94
00
GND
25
R38
GND
25
R37
49.9
R33
00
R56
00
R53
GND
00
R52
00
R55
VCLK
R57
00
E15
5
2
3
SYNCB
CLK
CLKB
U1
.1UF
C42
R62
4.12K
R40
DNP
OUT1
OUT1B
OUT0
OUT0B
C43
DNP
R39
5
R45
5
AD9515
DNC; 27, 28
VCLK; 1, 4, 17, 20, 21, 24, 26, 29, 30
10K
R54
AD9515(Opt_Clk Circuit)
PRI SEC
ETC1-1-13
00
R36
00
R47
C48
P13
SMBMST
C40
C41
C49
DNP
GND
DNP
DNP
0.1UF
C47
.1UF
VREF
S0
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
Operational Amplifier
RSET
6
7
8
9
10
11
12
13
14
15
16
25
18
19
22
23
GND
R44
00
GND
RGP
RDP
16
100
R58
0.1UF
C52
0.1UF
240
R60
VAMP
GND
E16
9
0.1UF
C50
0.1UF
R46
00
CLK
CLK
GND
R41
00
C53
GND
10
11
12
GND
CML
E17
100
R59
GND
VON
VCC
8
GND
VOP
VCC
VAMP
C46
R91
00
.1UF
13
10K
AD8352
C51
GND
240
R61
GND
7
Z1
VCM
14
GND
6
ENB
15
5
VIP
C37
VIN
4 RDN
3 RGN
2
1
.1UF
E14
R42
L11
DNP
VCLK
VCLK
VCLK
VCLK
VCLK
VCLK
VCLK
VCLK
VCLK
VCLK
VCLK
DNP
S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
AD9515 Logic Setup
AMPOUT-
AMPOUT+
R64
00
R66
00
R68
00
R70
00
10K
00
R74
00
R72
00
R63
00
R65
00
R67
00
R69
00
R76
00
Figure 47. AD9601 Evaluation Board Schematic Page 3
GND
R78
00
32
GND_PAD
R80
00
31
S0
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
R82
00
Rev. 0 | Page 27 of 32
R71
00
R43
C45
DNP
R84
33
R73
00
E12
R75
00
E13
R77
00
C44
DNP
R79
00
GND
L10
DNP
R81
00
C76
R83
00
VAMP
AD9601
07100-047
CSB_DUT
4
Y2
SCLK_DTP
VSPI
5
A2
GND
3
GND
A1
VSPIEXT
R19
10K
R18
10K
GND
GND
SDO_CHA
SDIO_ODM
2
1
A1
A2
3
2
R26
10K
GND
1
GND
U5
NC7WZ07
U3
NC7WZ16
VCC
6
Y1
5
4
Y2
Y1
VCC
6
VSPI
R25
1K
VSPIEXT
VSPI
R27
1K
CSB1_CHA
SDI_CHA
SCLK_CHA
SPI CIRCUITRY
07100-048
R24
1K
AD9601
Figure 48. AD9601 Evaluation Board Schematic Page 4
Table 13. Bill of Materials
Qty
1
7
6
1
7
6
10
1
1
1
15
2
10
1
1
1
Reference
Designator
C1, C3, C4, C5,
C6, C7, C10
C8, C9, C11,
C12, C14, C55
C17
C27, C32, C33,
C62, C63, C64,
C71
C28, C29, C30,
C31, C65, C70
C21, C22, C23,
C24, C25, C26,
C34, C35, C36,
C39
CR4
CR2
F1
E1, E2, E3, E4,
E5, E7, E8, E9,
E10, E12, E13,
E14, E31, E32,
E33
J2, J3
L2, L3, L4, L5,
L7, L12, L13,
L14, L15, R88
P8
R1
R2
Package
PCB
603
Description
PCB, AD9230 customer evaluation board, Rev. G
Capacitor, 1 μF, 0603, X5R, ceramic, 6.3 V, 10%
Vendor
Moog
Panasonic
Part Number
AD9230revG
ECJ-1VB0J105K
6032-28
Capacitor, 10 μF, tantalum, 16 V, 10%
Kemet
T491C106K016AS
402
402
Capacitor, 2.0 pF, 50 V, ceramic, 0402, SMD
Capacitor, 0.33 μF, ceramic, X5R, 10 V, 10%
Murata
Murata
GRM1555C1H2R0GZ01D
GRM155R61A334KE15D
402
Capacitor, 120 pF, ceramic, C0G, 25 V, 5%
Murata
GRM1555C1H121JA01J
402
Capacitor, 0.1 μF, ceramic, X5R, 10 V, 10%
Murata
GRM155R71C104KA88D
603
Mini 3P
1210
LED green, SMT, 0603, SS-TYPE
Diode, 30 V, 20 mA
Fuse, 6.0 V, 2.2 A trip current resettable fuse
Connector, header, 0.1"
Panasonic
Agilent
Tyco/Raychem
Samtec
LNJ314G8TRA
HSMS2812
NANOSMDC110F-2
TSW-150-08-G-S
SMA end
launch
1206
Connector, SMA PCB coax end launch, Johnson
142
Ferrite bead, BLM, 3 A, 50 Ω @ 100 MHz
Johnson
142-0701-851
Murata
BLM31PG500SN1L
201
603
Power jack, male, 2.1 mm power jack dc
Resistor, 100 Ω, 0201, 1/20 W, 1%
Resistor, 499 Ω, 0603, 1/10 W, 1%
CUI Inc
NIC Components
NIC Components
CP-102A-ND
NRC02F1000TRF
NRC06F4990TRF
Rev. 0 | Page 28 of 32
AD9601
3
1
1
Reference
Designator
R5, R6
R7, R16
R10, R11, R13,
R24, R25, R27
R12, R18, R19,
R26,
R15, C16, C18,
C19, C20, R89,
R90
RN1, RN2, RN3,
RN4
L1, L8, L9
P9, P10
SW3
1
2
1
1
1
1
1
2
1
T1
T2,T3
U3
U5
U7
U8
U11
U9, U12
U4
603
805
EVQQ2F03W
2020
CD542
6-SC70
6-SC70
DO-214AA
DO-214AB
SOT-223
SOT-223
LFCSP56
2
P7, P11
HM-Zd PCB
Qty
2
2
6
4
7
4
Package
402
402
402
Description
Resistor, 36 Ω, 0402, 1/16 W, 1%
Resistor, 15 Ω, 0402, 1/16 W, 5%
Resistor, 1 kΩ, 0402, 1/16 W, 1%
Vendor
Panasonic
Panasonic
NIC Components
Part Number
ERJ-2GEJ360X
ERJ-2RKF15R0X
NRC04F1001TRF
402
Resistor, 10 kΩ, 0402, 1/16 W, 5%
NIC Components
NRC04J103TRF
402
Resistor, 0 Ω, 0402, 1/16 W, 5%
NIC Components
NRC04ZOTRF
0402x8
Resistor array, SMT 0402; 0 Ω, ¼ W, 5%,
RESNEXB-2HV
Resistor, 0 Ω, 0603, 1/10 W, 5%
Resistor, 0 Ω, 0805, 1/8 W, 1%
Switch, light touch SMD
Panasonic
EXB2HV050JV
NIC Components
NIC Components
Panasonic
NRC06ZOTRF
NRC10ZOTRF
P12937SCT-ND
Ferrite bead, 5 A, 50 V, 190 Ω @ 100 MHz
Transformer, 0.5 W, 30 mA
IC, buffer, inverter, UHS dual SC70-6
IC, buffer, inverter, UHS dual OD out SC70-6
Diode, 50 V, 2 A
Diode, 30 V, 3 A (SMC)
Voltage regulator, 3.3 V, 1.5 A
Voltage regulator, 1.8 V, 1.5 A
AD9230 12-bit, 170 MSPS/210 MSPS/250 MSPS,
1.8 V ADC, LFCSP-56
Connector, 2-Pr, 10-column, high speed, HM-Zd,
PCB-mounted
Murata
Mini-Circuits
Fairchild
Fairchild
Micro Commercial
Micro Commercial
Analog Devices
Analog Devices
Analog Devices
DLW5BSN191SQ2L
ADT1-1WT+
NC7WZ16P6X
NC7WZ07P6X
S2A-TPMSTR-ND
SK33-TPMSCT-ND
ADP3339AKCZ-3.3
ADP3339AKCZ-1.8
AD9230BCPZ-xxx
Tyco
6469169-1
Capacitor, tantalum, SMT 6032, 10 μF, 16 V, 10%
Capacitor, 0.1 μF, ceramic, 10%
Kemet
Murata
T491C106K016AS
GRM155R71C104KA88D
LED green, USS type 0603
Schottky diode
Connector, header, 0.1"
Panasonic
Agilent
Tyco/Raychem
Samtec
LNJ314G8TRA
HSMS2812
NANOSMDC110F-2
TSW-150-08-G-S
TSW-110-08-G-D
Samtec
TSW-110-08-G-D
Connector, PCB coax SMA end launch,
Johnson 142
Inductor, 10 nH
SMA
Johnson
142-0701-851
Murata
Amphenol RF
BLM31P500S
ARFX1231-ND
Do not install the following:
0
C2, C54
TAJD
0
402
C15, C37, C38,
C40, C41, C61,
C42, C43, C44,
C45, C46, C47,
C48, C49, C50,
C51, C52, C53,
C39, C56, C57,
C58, C59, C74,
C75, C60, C66,
C67, C68, C69,
C72
0
CR1
Led_ss
0
CR3
Diode
0
805
0
E6, E15, E16,
E17, E18, E19,
E20
0
J1
10-pin
header
0
J4
SMA
0
0
L6
P12, P13, P14,
P15
1206
Rev. 0 | Page 29 of 32
AD9601
0
0
Reference
Designator
R3, R14, R33,
R34, R35, R48,
R49
R42, R43, R54,
R85, R86
R28, R29, R30,
R31, R32
R37, R38
R39, R45
R58, R59
R60, R61
R8, R9, R17,
R36, R40, R41,
R44, R46, R47,
R87, R50, R51,
R52, R53, R55,
R56, R57, R62,
R63, R64, R65,
R66, R67, R68,
R69, R70, R71,
R72, R73, R74,
R75, R76, R77,
R78, R79, R80,
R81, R82, R83,
R84
P1, P2, P16, P17
SW1
0
T4
0
0
0
0
0
0
0
0
T5, T6
U2
U6
U10
Z1
U1
P6
P6
Qty
0
0
0
0
0
0
0
0
Package
402
Description
Resistor, 49.9 Ω
Vendor
Susumu
Part Number
RR0510R-49R9-D
402
Resistor, 10 kΩ
NIC Components
NRC04J103TRF
402
Resistor, 5 kΩ
NIC Components
NRC04F4991TRF
402
402
402
402
402
Resistor, 25 Ω
Resistor, 5 Ω
Resistor, 100 Ω
Resistor, 240 Ω
Resistor, 0 Ω
NIC Components
NIC Components
NIC Components
NIC Components
NIC Components
NRC04F24R9TRF
NRC04J5R1TRF
NRC04F1000TRF
NRC04J241TRF
NRC04ZOTRF
805
EVQQ2F03W
Resistor, 0 Ω
Switch, light touch SMD
NIC Components
Panasonic
NRC10ZOTRF
P12937SCT-ND
Transformer, RF, 0.4 MHz to 800 MHz, SMD case
style CD542
Balun
PIC12F629
Cvhd_956 crystal
Regulator
AD8352
AD9515
8-pin power connector post
8-pin power connector top
Mini-Circuits
ADT1-1WT+
M/A-Com
Microchip Tech
MABA007159-0000
PIC12F629-I/SN
CVHD_956
ADP3339AKCZ-5.0
Wieland
Wieland
Z5.530.0825.0
25.602.2853.0
sm-22
SOIC-8
Crystal
SOT-223
16CSP4X4
16CSP8X8
Rev. 0 | Page 30 of 32
AD9601
OUTLINE DIMENSIONS
8.00
BSC SQ
0.60 MAX
14
29
28
15
0.30 MIN
6.50
REF
0.80 MAX
0.65 TYP
0.50 BSC
PIN 1
INDICATOR
4.45
4.30 SQ
4.15
EXPOSED
PAD
(BOTTOM VIEW)
7.75
BSC SQ
0.50
0.40
0.30
SEATING
PLANE
1
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-VLLD-2
112805-0
TOP
VIEW
12° MAX
56
43
42
PIN 1
INDICATOR
1.00
0.85
0.80
0.30
0.23
0.18
0.60 MAX
Figure 49. 56-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
8 mm × 8 mm Body, Very Thin Quad
(CP-56-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD9601BCPZ-200 1
AD9601BCPZ-2501
AD9601-250EBZ1
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
Package Description
56-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
56-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
CMOS Evaluation Board with AD9601BCPZ-250
Z = RoHS Compliant Part.
Rev. 0 | Page 31 of 32
Package Option
CP-56-2
CP-56-2
AD9601
NOTES
©2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07100-0-11/07(0)
Rev. 0 | Page 32 of 32