TI ADS2807Y250G4 Dual, 12-bit, 50mhz sampling analog-to-digital converter Datasheet

ADS2807
ADS
280
7
SBAS169B – NOVEMBER 2000 – REVISED MAY 2002
Dual, 12-Bit, 50MHz Sampling
ANALOG-TO-DIGITAL CONVERTER
FEATURES
APPLICATIONS
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HIGH SNR: 66dB (2Vp-p), 68dB (3Vp-p)
LOW POWER: 720mW
INTERNAL OR EXTERNAL REFERENCE
LOW DLE: 0.6LSB
FLEXIBLE INPUT RANGE: 2Vp-p to 3Vp-p
TQFP-64 POWER PACKAGE
DESCRIPTION
COMMUNICATIONS IF PROCESSING
COMMUNICATIONS BASESTATIONS
TEST EQUIPMENT
MEDICAL IMAGING
VIDEO DIGITIZING
CCD DIGITIZING
The ADS2807 provides an over-range indicator flag to
indicate an input signal that exceeds the full-scale input
range of the converter. This flag can be used to reduce the
gain of front-end gain control circuitry. There is also an
output enable pin to allow for multiplexing and testability on
a PC board.
The ADS2807 is a dual, high-speed, high dynamic range,
12-bit pipelined Analog-to-Digital Converter (ADC). This
converter includes a high-bandwidth track-and-hold that
gives excellent spurious performance up to and beyond the
Nyquist rate. The differential nature of this track-and-hold
and ADC circuitry minimizes even-order harmonics and
gives excellent common-mode noise immunity. The trackand-hold can also be operated single-ended.
The ADS2807 employs digital error correction techniques to
provide excellent differential linearity for demanding imaging applications. The ADS2807 is available in a TQFP-64
power package.
The ADS2807 provides for setting the full-scale range of the
converter without any external reference circuitry. The internal reference can be disabled allowing low-drive, external
references to be used for improved tracking in multichannel
systems.
+VS
CMA
VIN
ADS2807
INA
12-Bit
Pipelined
ADC
T&H
INA
(Opt.)
INT/EXT
Internal
Reference
FSSEL
VIN
INB
T&H
INB
(Opt.)
OEA OVRA
Error
Correction
Logic
3-State
Outputs
Timing
Circuitry
12-Bit
Pipelined
ADC
Error
Correction
Logic
D12A
•
•
•
D1A
CLK
3-State
Outputs
D12B
•
•
•
D1B
CMB
Optional External
Reference
OEB OVRB
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright © 2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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ELECTROSTATIC
DISCHARGE SENSITIVITY
ABSOLUTE MAXIMUM RATINGS(1)
+VS ....................................................................................................... +6V
Analog Input ........................................................... (–0.3V) to (+VS + 0.3V)
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
Logic Input ............................................................. (–0.3V) to (+VS + 0.3V)
Case Temperature ......................................................................... +100°C
Junction Temperature .................................................................... +150°C
Storage Temperature ..................................................................... +150°C
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings”
may cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may affect device reliability.
PACKAGE/ORDERING INFORMATION
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
PRODUCT
PACKAGE-LEAD
PACKAGE
DESIGNATOR(1)
ADS2807Y
TQFP-64
PAP
–40°C to +85°C
ADS2807Y
ADS2807Y/1K5
Tape and Reel, 1500
"
"
"
"
ADS2807Y/250
Tape and Reel, 250
"
NOTE: (1) For the most current specifications and package information, refer to our web site at www.ti.com.
ELECTRICAL CHARACTERISTICS
At TA = full specified temperature range, VS = +5V, differential input range = 2V to 3V for each input, sampling rate = 50MHz, unless otherwise noted.
ADS2807Y
PARAMETER
CONDITIONS
MIN
RESOLUTION
SPECIFIED TEMPERATURE RANGE
ANALOG INPUT
2V Full-Scale Input Range
2V Full-Scale Input Range
3V Full-Scale Input Range
3V Full-Scale Input Range
Analog Input Bias Current
Analog Input Bandwidth
Input Impedance
TYP
MAX
12 Tested
(Differential)
(Single-Ended)
(Differential)
(Single-Ended)
Ambient Air
2Vp-p,
2Vp-p,
3Vp-p,
3Vp-p,
INT
INT
INT
INT
or
or
or
or
EXT
EXT
EXT
EXT
Ref
Ref
Ref
Ref
DYNAMIC CHARACTERISTICS
Differential Linearity Error (largest code error)
f = 1MHz
f = 10MHz
No Missing Codes
Integral Linearity Error, f = 1MHz
Spurious-Free Dynamic Range(1)
f = 1MHz (–1dBFS input)
f = 10MHz (–1dBFS input)
f = 20MHz (–1dBFS input)
2-Tone Intermodulation Distortion(3)
f = 12MHz and 13MHz (–7dBFS each tone)
Signal-to-Noise Ratio (SNR)
f = 1MHz (–1dBFS input)
f = 10MHz (–1dBFS input)
f = 20MHz (–1dBFS input)
f = 1MHz (–1dBFS input)
f = 10MHz (–1dBFS input)
Bits
–40
+85
°C
2
1.5
1.75
1
3
3.5
3.25
4
V
V
V
V
µA
MHz
MΩ || pF
50M
Samples/s
Clock Cycles
±1.0
±1.0
LSB
LSB
±5.0
LSBs
1
270
1.25 || 3
CONVERSION CHARACTERISTICS
Sample Rate
Data Latency
10k
6
±0.6
±0.6
Tested
Tested
±3.5
fS = 40MHz
fS = 50MHz,TA = +25°C
fS = 40MHz, Full Temp
TA = +25°C
60
60
3Vp-p
3Vp-p
UNITS
72
70
70
dBFS(2)
dBFS
dBFS
–71.8
dBc
66
65
65
68
68
dBFS
dBFS
dBFS
dBFS
dBFS
ADS2807
2
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SBAS169B
ELECTRICAL CHARACTERISTICS (Cont.)
At TA = full specified temperature range, VS = +5V, differential input range = 2V to 3V for each input, sampling rate = 50MHz, unless otherwise noted.
ADS2807Y
PARAMETER
DYNAMIC CHARACTERISTICS (Cont.)
Signal-to-(Noise + Distortion) (SINAD)(4)
f = 1MHz (–1dBFS input)
f = 10MHz (–1dBFS input)
f = 20MHz (–1dBFS input)
f = 1MHz (–1dBFS input)
f = 10MHz (–1dBFS Input)
Channel-to-Channel Crosstalk
Output Noise
Aperture Delay Time
Aperture Jitter
Overvoltage Recovery Time
DIGITAL INPUTS
Logic Family
Convert Command
High Level Input Current(5) (VIN = 5V)
Low Level Input Current (VIN = 0V)
High Level Input Voltage
Low Level Input Voltage
Input Capacitance
DIGITAL OUTPUTS
Logic Family
Logic Coding
Low Output Voltage (IOL = 50µA)
Low Output Voltage, (IOL = 1.6mA)
High Output Voltage, (IOH = 50µA)
High Output Voltage, (IOH = 0.5mA)
Low Output Voltage, (IOL = 50µA)
High Output Voltage, (IOH = 50µA)
3-State Enable Time
3-State Disable Time
Output Capacitance
ACCURACY (Internal Reference, 2Vp-p,
Unless Otherwise Noted)
Zero Error (Midscale)
Zero Error Drift (Midscale)
Gain Error(6)
Gain Error Drift(6)
Gain Error(7)
Gain Error Drift(7)
Power-Supply Rejection of Gain
REFT Tolerance
2V Full-Scale
3V Full-Scale
REFB Tolerance
2V Full-Scale
3V Full-Scale
External REFT Voltage Range
External REFB Voltage Range
Reference Input Resistance
POWER-SUPPLY REQUIREMENTS
Supply Voltage: +VS
Supply Current: +IS
Power Dissipation: VDRV = 5V
VDRV = 3V
VDRV = 5V
VDRV = 3V
Thermal Resistance, θJA
TQFP-64
CONDITIONS
MIN
TYP
MAX
65
64
64
68
68
85
0.2
2
1.2
2
57
3Vp-p
3Vp-p
2Vp-p
Input Grounded
UNITS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
LSBs rms
ns
ps rms
ns
+3V/+5V CMOS Compatible
Rising Edge of Convert Clock
Start Conversion
+50
+10
+2.4
+1.0
5
µA
µA
V
V
pF
CMOS
Straight Offset Binary
VDRV = 5V
VDRV = 5V
VDRV = 5V
VDRV = 5V
VDRV = 3V
VDRV = 3V
OE = L(5)
OE = H(5)
+0.1
+0.2
+4.9
+4.8
+0.4
+2.4
20
2
5
40
10
V
V
V
V
V
V
ns
ns
pF
∆VS = ±5%
±1.0
16
±1.5
66
±1.0
23
70
Deviation From Ideal 3.0V
Deviation From Ideal 3.25V
±10
±20
±65
mV
mV
Deviation From Ideal 2.0V
Deviation From Ideal 1.75V
±10
±20
3
2
375
±65
mV
mV
V
V
Ω
at 25°C
at 25°C
at 25°C
REFB + 0.4
1.70
Operating
Operating
External Reference
External Reference
Internal Reference
Internal Reference
+4.75
+5.0
134
720
700
740
720
21.5
%FS
ppm/°C
%FS
ppm/°C
%FS
ppm/°C
dB
VS – 1.70
REFT – 0.4
+5.25
760
V
mA
mW
mW
mW
mW
°C/W
NOTES: (1) Spurious-Free Dynamic Range refers to the magnitude of the largest harmonic. (2) dBFS means dB relative to Full-Scale. (3) 2-tone intermodulation
distortion is referred to the largest fundamental tone. This number will be 6dB higher if it is referred to the magnitude of the 2-tone fundamental envelope.
(4) Effective number of bits (ENOB) is defined by as (SINAD – 1.76)/6.02. (5) A 50kΩ pull-down resistor is inserted internally on OE pins. (6) Includes internal
reference. (7) Excludes internal reference.
ADS2807
SBAS169B
3
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TIMING DIAGRAM
N+2
N+1
Analog In
N+4
N+3
N
tD
N+5
tL
tCONV
N+6
N+7
tH
Clock
6 Clock Cycles
t2
Data Out
N–6
N–5
N–4
N–3
N–2
N–1
N
Data Invalid
N+1
t1
t3
Data Valid
t4
SYMBOL
DESCRIPTION
MIN
tCONV
tL
tH
tD
t1(1)
t2(1)
t3
t4
Convert Clock Period
Clock Pulse LOW
Clock Pulse HIGH
Aperture Delay
Data Hold Time, CL = 0pF
New Data Delay Time, CL = 15pF max
Data Valid Falling Edge Delay, CL = 15pF max
Data Valid Rising Edge Delay, CL = 15pF max
20
9.0
9.0
TYP
MAX
UNITS
100µs
ns
ns
ns
ns
ns
ns
ns
ns
tCONV/2
tCONV/2
2
2.7
8.2
7.5
5.6
12
NOTE: (1) t1 and t2 times are valid for VDRV voltages of +2.7V to +5V.
61
60
59
58
57
54
53
52
51
50
GND
INA
INA
TQFP
CMA
55
REFTA
56
REFBA
+VS
GND
REFBB
CMB
INB
62
GND
63
INT/EXT
64
INB
GND
Top View
REFTB
PIN CONFIGURATION
49
GND
1
48 GND
GND
2
47 GND
+VS
3
46 +VS
GND
4
45 SEL
+VS
5
44 GND
OEB
6
43 +VS
GND
7
42 OEA
VDRVB
8
OVRB
9
41 GND
ADS2807Y
40 VDRVA
B12 (LSB) 10
39 OVRA
24
25
26
27
28
29
30
31
32
A8
A7
23
A9
22
A10
21
A11
20
A12 (LSB)
19
DVA
18
GND
17
CLK
33 A6
GND
34 A5
B6 16
DVB
B7 15
B1(MSB)
35 A4
B2
36 A3
B8 14
B3
37 A2
B9 13
B4
38 A1 (MSB)
B10 12
B5
B11 11
ADS2807
4
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SBAS169B
PIN DESCRIPTIONS
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
I/O
DESIGNATOR
I
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
O
O
O
O
O
O
O
O
GND
GND
+VS
GND
+VS
OEB
GND
VDRVB
OVRB
B12 (LSB)
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1 (MSB)
DVB
GND
CLK
GND
DVA
A12 (LSB)
A11
A10
A9
A8
A7
A6
DESCRIPTION
PIN
Ground
Ground
+5V Supply
Ground
+5V Supply
Output Enable, Channel B
GND
Logic Driver Supply Voltage, Channel B
Over-Range Indicator, Channel B
Data Bit 12 (D0), Channel B
Data Bit 11 (D1), Channel B
Data Bit 10 (D2), Channel B
Data Bit 9 (D3), Channel B
Data Bit 8 (D4), Channel B
Data Bit 7 (D5), Channel B
Data Bit 6 (D6), Channel B
Data Bit 5 (D7), Channel B
Data Bit 4 (D8), Channel B
Data Bit 3 (D9), Channel B
Data Bit 2 (D10), Channel B
Data Bit 1 (D11), Channel B
Data Valid, Channel B
Ground
Clock
Ground
Data Valid, Channel A
Data Bit 12 (D0), Channel A
Data Bit 11 (D1), Channel A
Data Bit 10 (D2), Channel A
Data Bit 9 (D3), Channel A
Data Bit 8 (D4), Channel A
Data Bit 7 (D5), Channel A
Data Bit 6 (D6), Channel A
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
ADS2807
SBAS169B
I/O
DESIGNATOR
O
O
O
O
O
O
A5
A4
A3
A2
A1 (MSB)
OVRA
VDRVA
GND
OEA
+VS
GND
SEL
+VS
GND
GND
GND
INA
INA
CMA
REFTA
REFBA
GND
INT/EXT
I
I
I
I
O
I/O
I/O
I
I/O
I/O
O
I
I
+VS
GND
REFBB
REFTB
CMB
INB
INB
GND
DESCRIPTION
Data Bit 5 (D7), Channel A
Data Bit 4 (D8), Channel A
Data Bit 3 (D9), Channel A
Data Bit 2 (D10), Channel A
Data Bit 1 (D11), Channel A
Over-Range Indicator, Channel A
Logic Driver Supply Voltage, Channel A
Ground
Output Enable, Channel A
+5V Supply
Ground
Input Range Select: HIGH = 3V, LOW = 2V
+5V Supply
Ground
Ground
Ground
Analog Input, Channel A
Complementary Analog Input, Channel A
Common-Mode, Channel A
Top Reference/Bypass, Channel A
Bottom Reference/Bypass, Channel A
Ground
Reference Select: HIGH = External,
LOW = Internal 50kΩ Pull-Up Resistor
+5V Supply
Ground
Bottom Reference/Bypass, Channel B
Top Reference/Bypass, Channel B
Common-Mode, Channel B
Complementary Analog Input, Channel B
Analog Input, Channel B
Ground
5
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TYPICAL CHARACTERISTICS
At TA = full specified temperature range, VS = +5V, differential input range = 2V to 3V for each input, sampling rate = 50MSPS, unless otherwise noted.
SPECTRAL PERFORMANCE
(Differential, 2Vp-p)
SPECTRAL PERFORMANCE
(Differential, 2Vp-p)
0
0
fIN = 1MHz
SFDR = 72.7dBFS
SNR = 65.1dBFS
Amplitude (dBFS)
Amplitude (dBFS)
–20
–40
–60
–80
–40
–60
–80
–100
–100
–120
–120
0
5
10
15
20
0
25
5
15
20
Frequency (MHz)
SPECTRAL PERFORMANCE
(Differential, 3Vp-p)
SPECTRAL PERFORMANCE
(Differential, 3Vp-p)
25
0
fIN = 1MHz
SFDR = 71.8dBFS
SNR = 67.2dBFS
fIN = 10MHz
SFDR = 68.4dBFS
SNR = 66.4dBFS
–20
Amplitude (dBFS)
–20
–40
–60
–80
–100
–40
–60
–80
–100
–120
–120
0
5
10
15
20
25
0
5
Frequency (MHz)
10
15
20
25
Frequency (MHz)
DYNAMIC PERFORMANCE vs CLOCK
2-TONE INTERMODULATION DISTORTION
80
0
REF = 2V
fIN = 3.5MHz
f1 = 12MHz
f2 = 13MHz
IMD(3) = –71.8dBc
75
SNR, SFDR (dBFS)
–20
Amplitude (dBFS)
10
Frequency (MHz)
0
Amplitude (dBFS)
fIN = 10MHz
SFDR = 69.8dBFS
SNR = 64.9dBFS
–20
–40
–60
–80
SFDR
70
65
SNR
60
–100
55
–120
0
5
10
15
20
25
35
40
45
50
55
60
Clock (MHz)
Frequency (MHz)
ADS2807
6
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SBAS169B
TYPICAL CHARACTERISTICS (Cont.)
At TA = full specified temperature range, VS = +5V, differential input range = 2V to 3V for each input, sampling rate = 50MSPS, unless otherwise noted.
DYNAMIC PERFORMANCE vs CLOCK
DYNAMIC PERFORMANCE vs INPUT FREQUENCY
80
85
REF = 3V
fIN = 3.5MHz
Dynamic Performance (dBFS)
80
SNR, SFDR (dBFS)
75
SFDR
70
SNR
65
60
55
SFDR
75
70
THD
65
SNR
60
55
SINAD
50
45
Power = –1dBFS
40
35
40
45
50
55
60
1
10
Clock (MHz)
SWEPT POWER (SFDR)
DYNAMIC PERFORMANCE vs INPUT FREQUENCY
85
100
fIN = 10MHz
dBFS
90
80
80
SFDR
75
SFDR (dBFS, dBc)
Dynamic Performance (dBFS)
100
Frequency (MHz)
70
THD
65
60
SNR
SINAD
60
50
dBc
40
30
20
55
10
Power = –6dBFS
50
1
70
10
0
100
–60
–50
–40
–30
–20
–10
Frequency (MHz)
Input Amplitude (dBFS)
DIFFERENTIAL LINEARITY ERROR
(Differential, 2Vp-p)
INTEGRAL LINEARITY ERROR
(Differential, 2Vp-p)
0
6
2
fIN = 10MHz
fIN = 10MHz
1.5
4
2
0.5
ILE (LSB)
DLE (LSB)
1
0
–0.5
0
–2
–1
–4
–1.5
–6
–2
0
1024
2048
3072
4096
ADS2807
SBAS169B
0
1024
2048
3072
4096
Code
Code
7
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TYPICAL CHARACTERISTICS (Cont.)
At TA = full specified temperature range, VS = +5V, differential input range = 2V to 3V for each input, sampling rate = 50MSPS, unless otherwise noted.
INTEGRAL LINEARITY ERROR
(Differential, 3Vp-p)
DIFFERENTIAL LINEARITY ERROR
(Differential, 3Vp-p)
5
0.75
fIN = 10MHz
0.50
3
2
ILE (LSB)
0.25
DLE (LSB)
fIN = 10MHz
4
0
–0.25
1
0
–1
–2
–3
–0.50
–4
–5
–0.75
0
1024
2048
3072
0
4096
1024
2048
3072
CROSSTALK (Channel A)
OUTPUT NOISE HISTOGRAM (DC Input)
500k
0
3V Full Scale
fIN = 4.8MHz
–25
Amplitude (dBFS)
400k
Counts
4096
Output Codes
Code
300k
200k
–50
–75
–100
100k
–110
N-2
N-1
N
N+1
0
N+2
2.5
5
7.5
DYNAMIC PERFORMANCE vs TEMPERATURE
12.5
15
17.5
20
22.5
25
CROSSTALK (Channel B)
75
0
fIN = 10MHz
fIN = 3.5MHz
70
–25
Amplitude (dBFS)
SFDR
SNR, SFDR (dBFS)
10
Frequency (MHz)
Code
65
SNR
60
–50
–75
55
–100
50
–110
–60
–40
–20
0
20
40
60
80
100
0
Temperature (°C)
2.5
5
7.5
10
12.5
15
17.5
20
22.5
25
Frequency (MHz)
ADS2807
8
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SBAS169B
APPLICATION INFORMATION
• Even-order harmonics are minimized.
THEORY OF OPERATION
• Improves the noise immunity based on the converter’s
common-mode input rejection.
The ADS2807 integrates two high-speed CMOS ADCs and
an internal reference. The ADCs utilize a pipelined converter architecture consisting of eleven internal stages.
Each stage feeds its data into the digital error correction
logic, ensuring excellent differential linearity and no missing
codes at the 12-bit level. The output data becomes valid
after the rising clock edge (see Timing Diagram). The
pipeline architecture results in a data latency of 6 clock
cycles.
The analog input of the ADS2807 consists of a differential
track-and-hold circuit. The differential topology along with
tightly matched poly-poly capacitors produce a high level of
AC performance at high sampling rates and in some undersampling applications.
Both inputs (IN, IN) require external biasing using a common-mode voltage that is typically at the mid-supply level
(+VS/2).
DRIVING THE ANALOG INPUTS
The analog inputs of the ADS2807 are very high impedance
and should be driven through an R-C network designed to
pass the highest frequency of interest. This prevents highfrequency noise in the input from affecting SFDR and SNR.
The ADS2807 can be used in a wide variety of applications
and deciding on the best performing analog interface circuit
depends on the type of application. The circuit definition
should include considerations of input frequency spectrum
and amplitude, single-ended or differential drive, and available power supplies. For example, communication (frequency
domain) applications process frequency bands not including
DC. In imaging (time domain) applications, the input DC
component must be maintained into the ADC. Features of
the ADS2807 include full-scale select (SEL), external reference, and CM output, providing flexibility to accommodate a
wide range of applications. The ADS2807 should be configured to meet application objectives, while observing the
headroom requirements of the driving amplifiers, to yield the
best overall performance.
The ADS2807 input structure allows it to be driven either
single-ended or differentially. Differential operation of the
ADS2807 requires an in-phase input signal and a 180° outof-phase part simultaneously applied to the inputs (IN, IN).
The differential operation offers a number of advantages
that, in most applications, will be instrumental in achieving
the best dynamic performance of the ADS2807:
• The signal swing is half of that required for the singleended operation and, therefore, is less demanding to
achieve while maintaining good linearity performance from
the signal source.
• The reduced signal swing allows for more headroom in the
interface circuitry and, therefore, a wider selection of the
best suitable driver op amp.
Using the single-ended mode, the signal is applied to one of
the inputs, while the other input is biased with a DC voltage
to the required common-mode level. Both inputs are equal in
terms of their impedance and performance, except that
applying the signal to the complementary input (IN) instead
of the IN input will invert the input signal relative to the output
code. For example, in the case when the input driver operates in inverting mode, using IN as the signal input will
restore the phase of the signal to its original orientation.
Time-domain applications may benefit from a single-ended
interface configuration and its reduced circuit complexity.
Driving the ADS2807 with a single-ended signal will result in
a reduction of the distortion performance, while maintaining
good signal-to-noise ratio (SNR). Employing dual-supply
amplifiers and AC-coupling will usually yield the best results,
while DC-coupling and/or single-supply amplifiers impose
additional design constraints due to their headroom requirements, especially when selecting the 3Vp-p input range.
However, single-supply amplifiers have the advantage of
inherently limiting their output swing to within the supply rails.
Alternatively, a voltage limiting amplifier, like the OPA688,
may be considered to set fixed-signal limits and avoid any
severe overrange condition for the ADC.
The full-scale input range of the ADS2807 is defined by the
reference voltages. For example, setting the range select
pin to SEL = LOW, and using the internal references
(REFT = +3.0V and REFTB = +2.0V), the full-scale range is
defined as: FSR = 2 • (REFT – REFB) = 2Vp-p.
The trade-off of the differential input configuration versus the
single-ended is its higher complexity. In either case, the
selection of the driver amplifier should be such that the
amplifier’s performance will not degrade the ADC’s performance. The ADS2807 operates on a single power supply
that requires a level shift for ground-based bipolar input
signals to comply with its input voltage range requirements.
The input of the ADS2807 is of a capacitive nature and the
driving source needs to provide the current to charge or
discharge the input sampling capacitor while the track-andhold is in track mode. This effectively results in a dynamic
input impedance that depends on the sampling frequency.
In most applications, it is recommended to add a series
resistor, typically 20Ω to 50Ω, between the drive source and
the converter inputs. This will isolate the capacitive input
from the source, which can be crucial to avoid gain peaking
when using wideband operational amplifiers. Secondly, it will
create a first-order, low-pass filter in conjunction with the
specified input capacitance of the ADS2807. Its cutoff frequency can be adjusted even further by adding an external
shunt capacitor from each signal input to ground. The optimum values of this R-C network depend on a variety of
factors that include the ADS2807 sampling rate, the selected
op amp, the interface configuration and the particular application (time domain versus frequency domain). Generally,
ADS2807
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9
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increasing the size of the series resistor and/or capacitor will
improve the SNR performance, but depending on the signal
source, large resistor values may be detrimental to achieving
good harmonic distortion. In any case, optimizing the R-C
values for the specific application is encouraged.
Transformer Coupled, Single-Ended to Differential
Configuration
If the application requires a signal conversion from a singleended source to drive the ADS2807 differentially, an RF
transformer might be a good solution. The selected transformer must have a center tap in order to apply the commonmode DC voltage necessary to bias the converter inputs. AC
grounding the center tap will generate the differential signal
swing across the secondary winding. Consider a step-up
transformer to take advantage of a signal amplification without the introduction of another noise source. Furthermore,
the reduced signal swing from the source may lead to
improved distortion performance.
The differential input configuration provides the noticeable
advantage of achieving high SFDR over a wide range of
input frequencies. In this mode, both inputs of the ADS2807
see matched impedances. Figure 1 shows the schematic for
the suggested transformer coupled interface circuit. The
component values of the R-C low-pass may be optimized
depending on the desired roll-off frequency. The resistor
across the secondary side (RT) should be calculated using
the equation RT = n2 • RG to match the source impedance
(RG) for good power transfer and VSWR.
The circuit example of Figure 1 shows voltage feedback
amplifier OPA680 driving the RF transformer, which converts
the single-ended signal into a differential. The OPA680 can
be employed for either single- or dual-supply operation. For
details on how to optimize its frequency response, refer to
the OPA680 data sheet. With the 49.9Ω series output resistor, the amplifier emulates a 50Ω source (RG). Any DC
content of the signal can be easily blocked by a capacitor
(0.1µF) to avoid DC loading of the op amp’s output stage.
AC-Coupled, Single-Ended to Differential Interface
with Dual-Supply Op Amps
Some applications demand a very high dynamic range and
low levels of intermodulation distortion, but usually allow the
input signal to be AC-coupled into the ADC. Appropriate
driver amplifiers need to be selected to maintain the excellent
distortion performance of the ADS2807. Often, these op
amps deliver the lowest distortion with a small, groundcentered signal swing that requires dual power supplies.
Because of the AC-coupling, this requirement can be easily
accomplished, and the needed level shifting of the input
signal can be implemented without affecting the driver circuit.
RG
VIN
49.9Ω
0.1µF 1:n
24.9Ω
IN
OPA680
47pF
R1
1/2
ADS2807Y
RT
24.9Ω
R2
IN
CM
+2.5V
47pF
+
One Channel of Two
10µF
0.1µF
FIGURE 1. Converting a Single-Ended Input Signal into a Differential Signal Using an RF-Transformer.
ADS2807
10
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SBAS169B
to the ADS2807. With a minimum gain stability of +3, the gain
resistors have to be modified, as well as optimizing the series
resistor and shunt capacitance at each of the converter
inputs.
Figure 2 shows an example of such an interface circuit
specifically designed to maximize the dynamic performance.
The voltage feedback amplifier, OPA642, maintains an excellent distortion performance for input frequencies of up to
15MHz. The two amplifiers (A1, A2) are configured as an
inverting and noninverting gain stage to convert the input
signal from single-ended to differential. The nominal gain for
this stage is set to +2V/V. The outputs of the OPA642s are
AC-coupled to the converter’s differential inputs. This will
keep the distortion performance at its best since the signal
range stays within the linear region of the op amp and
sufficient headroom to the supply rails can be maintained.
Four resistors located between the top (REFT) and bottom
(REFB) reference shift the input signal to a common-mode
voltage of approximately +2.5V.
AC-Coupled, Single-Ended-to-Differential Interface
for Single-Supply Operation
The previously discussed interface circuit can be modified if
the system only allows for a single-supply operation, e.g.,
VS = +5V. Single-supply operation requires the driver amplifier to be biased as well in order to process a bipolar input
signal. Typically, single-supply amplifiers do not achieve
distortion performance as well as dual-supply op amps. The
driver amplifier’s output swing must exceed the full-scale
input range of the converter. In addition, dual op amps, such
as the current-feedback OPA2681, should be considered
since they provide the closest open-loop gain and phase
matching between the two channels. Shown in Figure 3 is a
single-supply interface circuit for an AC-coupled input signal.
With the ADS2807 set to the 2Vp-p input range, the top and
bottom references (REFT, REFB) provide an output voltage
The interface circuit of Figure 2 can be modified to extend the
bandwidth to approximately 25MHz, by replacing the OPA642
with its decompensated version, the OPA643. The OPA643
provides the necessary slew rate for a low distortion front end
402Ω
200Ω
VIN
0.1µF
16.5Ω
A1
OPA642
1.82kΩ
1.82kΩ
REFT
IN
100pF
402Ω
1/2
ADS2807Y
402Ω
0.1µF
16.5Ω
A2
OPA642
IN
100pF
1.82kΩ
REFB
1.82kΩ
One Channel of Two
FIGURE 2. AC-Coupled Differential Driver Interface with OPA642.
RF
499Ω
0.1µF
VIN
RIN
249Ω
1/2
OPA2681
RS
24.9Ω
IN
RP
499Ω
499Ω
68pF
VCM = +2.5V
1/2
ADS2807Y
CM
0.1µF
+5V
RS
24.9Ω
1/2
OPA2681
IN
68pF
RF
499Ω
RG
249Ω
RP
499Ω
One Channel of Two
0.1µF
FIGURE 3. AC-Coupled, Differential Interface for Single-Supply Operation.
ADS2807
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11
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of +3.0V and +2.0V, respectively. The CM output of the
ADS2807 is used to bias the inputs of the driving amplifiers.
Using the OPA2681 on a single +5V supply, its ideal common-mode point is +2.5V, which coincides with the recommended common-mode input level for the ADS2807, thus
eliminating the need for coupling capacitors between the
amplifiers and the converter.
The addition of a small series resistor (RS) between the
output of the op amps and the input of the ADS2807 will be
beneficial in almost all interface configurations. It will decouple the op amp’s output from the capacitive load and
avoid gain peaking that can result in increased noise. For
best spurious and distortion performance, the resistor value
should be kept below 100Ω. Furthermore, the series resistor,
in combination with the shunt capacitor, establishes a passive low-pass filter limiting the bandwidth for the wideband
noise, thus improving the SNR. The spurious free dynamic
range of this single-supply front end is limited by the second
harmonic distortion. An improvement of several dB may be
realized by adding a pull-down resistor (RP) at the output of
each amplifier. This pulls a DC bias current out of the output
stage of the amplifier. It is set to approximately 5mA, see
Figure 3, but will vary depending on the amplifier used.
Single-Ended, AC-Coupled, Dual-Supply Interface
The circuit provided in Figure 4 shows typical connections for
using the ADS2807 in a single-ended input configuration.
The bias requirements for AC-coupling are provided by a
single resistor to the CM output lead. The single-ended mode
of operation should be considered for ease of interface
complexity and applications where the dynamic performance
can be compromised. The series resistor RS, along with the
shunt capacitance, provide the means to adjust the bandwidth and optimize the performance towards good signal-tonoise ratio. In addition, the amplifier configuration can be
easily modified for an anti-aliasing filter based on a secondorder Sallen-Key or Multiple-Feedback topology.
The interface example, shown in Figure 4, operates with the
full-scale range of the ADS2807 set to 2Vp-p, leaving sufficient headroom for the output of the OPA642 to drive the
converter and maintain low signal distortion.
+5V
RS
16.5Ω
VIN
0.1µF
IN
OPA642
68pF
1/2
ADS2807Y
–5V
RF
402Ω
1.82kΩ
CM
IN
0.1µF
RG
402Ω
One Channel of Two
FIGURE 4. AC-Coupling the Dual-Supply Amplifier OPA642 to the ADS2807 for a 2Vp-p Full-Scale Input Range.
ADS2807
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SBAS169B
DC-Coupled, Differential Driver with Level Shift
Several applications will require that the bandwidth of the
signal path include DC, in which case, the signal has to be
DC-coupled to the ADC. An op amp based interface circuit
can be configured to scale and level shift the input signal to
be compatible with the selected input range of the ADC. The
circuit shown in Figure 5 employs a dual op amp, OPA2681,
to drive the input of the ADS2807 differentially. The singlesupply, general-purpose op amp OPA234 is added to buffer
the common-mode voltage of +2.5V, available at the CM pin,
and apply it to the input of the driver amplifier. This sets the
correct DC voltage to bias the inputs of the ADS2807. It
should be noted that any DC voltage differences between the
IN and IN inputs of the ADS2807 will result in an offset error.
Using the OPA2681, this circuit can be operated either with
a single or a dual ±5V supply.
down resistor at the range select pin (SEL). Therefore, this pin
can be either hardwired to ground or left unconnected, which
will default the converter to a 2Vp-p full-scale input range
(FSR). While set for the 2Vp-p range, the top and bottom
reference voltages will be REFT = +3.0V and REFB = +2.0V.
Switching to the 3Vp-p range changes those voltages to
REFT = +3.25V and REFB = +1.75V. The reference buffers
can be utilized to supply up to 1mA/channel (2mA total, sink
and source) to external circuitry. To ensure proper operation
with any reference configuration, it is necessary to provide
solid bypassing at all reference pins in order to keep the clock
feedthrough to a minimum, as shown in Figure 6. Good
performance requires using 0.1µF low inductance capacitors.
All bypassing capacitors should be located as close to their
respective pins as possible.
REFERENCE OPERATION
The internal reference consists of a bandgap voltage reference, the drivers for the top and bottom reference, and the
resistive reference ladder. References are internally connected, e.g.: REFTA is connected to REFTB, and REFBA is
connected to REFBB. The bandgap reference circuit includes
logic functions that allow setting the analog input swing of the
ADS2807 to a differential full-scale range of either 2Vp-p or
3Vp-p by simply tying the SEL pin to a LOW or HIGH
potential, respectively. While operating the ADS2807 in the
external reference mode, the buffer amplifiers for REFT and
REFB are disabled. The ADS2807 has an internal 50kΩ pull-
1/2
ADS2807
REFT
+
10µF
CM
0.1µF
+
10µF
REFB
0.1µF
+
10µF
0.1µF
FIGURE 6. Recommended Bypassing for the Reference Pins.
499Ω
249Ω
VIN
1/2
OPA2681
24.9Ω
IN
22pF
499Ω
249Ω
1/2
ADS2807Y
499Ω
IN
249Ω
24.9Ω
CM
1/2
OPA2681
22pF
499Ω
24.9Ω
OPA234
249Ω
0.1µF
0.1µF
0.1µF
1kΩ
One Channel of Two
FIGURE 5. DC-Coupled Input Driver with Level Shifting.
ADS2807
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13
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USING EXTERNAL REFERENCES
For even more design flexibility, the internal reference can be
disabled and an external reference voltage used. Driving
both channels with an external reference offers the best
performance, as it allows the channels to maintain balance.
The utilization of an external reference may be considered
for applications requiring higher accuracy, improved temperature performance, or a wide adjustment range of the
converter’s full-scale range. In multichannel applications, the
use of a common external reference has the benefit of
obtaining better matching and drift of the full-scale range
between converters. Figure 7 gives an example of an external reference circuit using a single-supply, low-power, dual
op amp (OPA2234).
The external references can vary as long as the value of the
external top reference (REFT) stays within the range of
VS – 1.70V and REFB + 0.4V, and the external bottom
reference (REFB) stays within 1.70V and REFT – 0.4V. Note
that the function of the range selector pin (SEL) is disabled
while the converter operates in external reference mode.
Setting the ADS2807 for external reference mode requires
the INT/EXT pin (pin 18) to be HIGH.
The logic level applied to the INT/EXT pin of the ADS2807
determines if the converter operates with either the built-in
reference or external reference voltages. Due to this function
pin having an internal 50kΩ pull-up resistor, the default
configuration is external reference mode. Grounding this pin
will activate the internal reference option.
IN (see Figure 3) results in 2Vp-p on the output of the trackand-hold. Likewise, 2Vp-p on the IN and 0Vp-p on the IN (see
Figure 4) results in 2Vp-p on the output of the track-and-hold.
Therefore, the reference voltages, REFT and REFB, are the
same for both differential and single-ended inputs, as shown
in Table I.
INPUT
REFERENCE IN (Pins-50, 63) IN (Pins-51, 62) REFT
REFB
2Vp-p Differential
1Vp-p Times 2 Inputs
Internal
or External
2V to 3V
3V to 2V
+3V
+2V
2Vp-p Single-Ended
2Vp-p Times 1 Input
Internal
or External
1.5V to 3.5V
2.5VDC
+3V
+2V
3Vp-p Differential
1.5Vp-p Times 2 Inputs
Internal
or External
3Vp-p Single-Ended
3Vp-p Times 1 Input
Internal
or External
1.75V to 3.35V 3.25V to 1.75V +3.25V +1.75V
1V to 4V
2.5VDC
+3.25V +1.75V
TABLE I. Reference Voltages for Input Signal Ranges.
The external references may be changed for different tasks.
The ADS2807 will follow the external references with a
latency of 8 to 10 clock cycles. If it is desired to use INT/EXT
and SEL to change the configuration of a circuit for different
tasks, a large amount of time must be allowed. This time
could be hundreds of microseconds. Refer to the Diagram on
the front page. Note that there is no disconnect for external
references. If it is desired to switch between internal and
external references, disconnect switches must be added
between the external references and the ADS2807.
The input track and hold amplifier is differential. A positive
1Vp-p on the IN and its compliment, a negative 1Vp-p, on the
+5V
+5V
OPA2234
A1
4.7kΩ
< 3.30V
Top Reference
R3
R4
R1
REF1004
+2.5V
+
10µF
R2
0.1µF
OPA2234
A2
> 1.70V
Bottom Reference
One Channel of Two
FIGURE 7. Example for an External Reference Driver Using the Dual, Single-Supply Op Amp, OPA2234.
ADS2807
14
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SBAS169B
DIGITAL INPUTS AND OUTPUTS
Clock Input Requirements
Data Outputs
Both channels of the ADS2807 are controlled by the same
clock on the rising edge. Utilizing a single clock reduces
timing uncertainty in the sampling of the two channels. Clock
jitter is critical to the SNR performance of high-speed, highresolution ADCs. Clock jitter leads to aperture jitter (tA),
which adds noise to the signal being converted. The ADS2807
samples the input signal on the rising edge of the CLK input.
Therefore, this edge should have the lowest possible jitter.
The jitter noise contribution to total SNR is given by the
following equation. If this value is near your system requirements, input clock jitter must be reduced.
Jitter SNR = 20 log
1
rms signal to rms noise
2π ƒIN t A
where: ƒIN is input signal frequency
tA is rms clock jitter
Particularly in undersampling applications, special consideration should be given to clock jitter. The clock input should be
treated as an analog input in order to achieve the highest
level of performance. Any overshoot or undershoot of the
clock signal may cause degradation of the performance.
When digitizing at high sampling rates, the clock should have
50% duty cycle (tH = tL), along with fast rise and fall times of
2ns or less. The clock input of the ADS2807 can be driven
with either 3V or 5V logic levels. Using low-voltage logic (3V)
may lead to improved AC performance of the converter.
Over Range Indicator (OVR)
If the analog input voltage exceeds the set full-scale range,
an over range condition exists. The “OVR” pin of the ADS2807
can be used to monitor any such out-of-range condition. This
“OVR” output is updated along with the data output corresponding to the particular sampled analog input voltage.
Therefore, the OVR data is subject to the same pipeline
delay as the digital data. The OVR output is LOW when the
input voltage is within the defined input range.
It will go to HIGH if the applied signal exceeds the full-scale
range.
The digital outputs of the ADS2807 can be set to a highimpedance state by driving OE (pins 6 and 42) with a logic
HIGH. Normal operation is achieved with pins 6 and 42 LOW
due to internal pull-down resistors. This function is provided
for testability purposes and is not meant to drive digital buses
directly, or be dynamically changed during the conversion
process. The output data format of the ADS2807 is in
positive Straight Offset Binary code, as shown in Tables II
and III. This format can easily be converted into the Binary
Two’s Complement code by inverting the MSB.
SINGLE-ENDED INPUT
(IN = CM, Pins 52, 61)
+FS–1LSB (IN = CMV + FSR/2)
1111 1111 1111
+1/2 FS
1100 0000 0000
Bipolar Zero (IN = VCM)
1000 0000 0000
–1/2 FS
0100 0000 0000
–FS (IN = CMV – FSR/2)
0000 0000 0000
TABLE II. Coding Table for Single-Ended Input Configuration
with IN Tied to the Common-Mode Voltage.
DIFFERENTIAL INPUT
STRAIGHT OFFSET BINARY
(SOB)
+FS–1LSB (IN = +3V, IN = +2V)
1111 1111 1111
+1/2 FS
1100 0000 0000
Bipolar Zero (IN = IN = VCM)
1000 0000 0000
–1/2 FS
0100 0000 0000
–FS (IN = +2V, IN = +3V)
0000 0000 0000
TABLE III. Coding Table for Differential Input Configuration.
Data output is in the form of two parallel words. It is recommended that the capacitive loading on the data lines be as
low as possible (< 15pF). Higher capacitive loading will
cause larger dynamic currents as the digital outputs are
changing. Those high current surges can feed back to the
analog portion of the ADS2807 and affect the performance.
If necessary, external buffers or latches close to the converter’s
output pins may be used to minimize the capacitive loading.
They also provide the added benefit of isolating the ADS2807
from high-frequency digital noise on the bus coupling back
into the converter.
ADS2807
SBAS169B
STRAIGHT OFFSET BINARY
(SOB)
15
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Digital Output Driver Supply (VDRV)
high-frequency designs. Multilayer PC boards are recommended for best performance since they offer distinct advantages, such as minimizing ground impedance, separation of
signal layers by ground layers, etc. The ADS2807 should be
treated as an analog component. Whenever possible, the
supply pins should be powered by the analog supply. This
will ensure the most consistent results, since digital supply
lines often carry high levels of noise that otherwise would be
coupled into the converter and degrade the achievable performance. The ground pins should directly connect to an
analog ground plane that covers the PC board area under
the converter. While designing the layout it is important to
keep the analog signal traces separated from any digital lines
to prevent noise coupling onto the analog signal path. Due to
its high sampling rate, the ADS2807 generates high-frequency current transients and noise (clock feedthrough) that
are fed back into the supply and reference lines. This
requires that all supply and reference pins are sufficiently
bypassed. Figure 8 shows the recommended decoupling
scheme for the ADS2807. In most cases, 0.1µF ceramic chip
capacitors at each pin are adequate to keep the impedance
low over a wide frequency range. Their effectiveness largely
depends on the proximity to the individual supply pin. Therefore, they should be located as close to the supply pins as
possible. If system supplies are not a low enough impedance, adding a small tantalum capacitor will yield the best
results.
Each channel of the ADS2807 has a separate dedicated
supply pin (8, 40) for the output logic drivers, VDRV, which
are not internally connected to the other supply pins. Setting
the voltage at VDRV to +5V or +3V, the ADS2807 produces
corresponding logic levels and can directly interface to the
selected logic family. The output stages are designed to
supply sufficient current to drive a variety of logic families.
However, it is recommended to use the ADS2807 with +3V
logic supply. This will lower the power dissipation in the
output stages due to the lower output swing and reduce
current glitches on the supply line that may affect the AC
performance of the converter. In some applications, it might
be advantageous to decouple the VDRV pin with additional
capacitors or a pi-filter.
OUTPUT ENABLE (OE )
The digital outputs of the ADS2807 can be set to high
impedance (tri-state) by driving OE A and OE B (pins 6, 42)
with a logic HIGH. Normal operation is achieved with the
same pins pulled LOW.
GROUNDING AND DECOUPLING
Proper grounding, bypassing, short trace lengths, and the
use of power and ground planes are particularly important for
ADS2807
+VS
GND
57
0.1µF
55, 58
+VS
+VS
GND
3 (46)
1, 2, 64
(47, 48, 49)
GND
5 (43)
0.1µF
0.1µF
+5V
4 (44)
GND
VDRV
7 (41)
8 (40)
GND
23, 25
0.1µF
+3V/+5V
Numbers in Parenthesis Indicate Pins for Channel A
FIGURE 8. Recommended Bypassing for the Supply Pins.
ADS2807
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SBAS169B
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
ADS2807Y/1K5
ACTIVE
HTQFP
PAP
64
1500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
ADS2807Y
ADS2807Y/1K5G4
ACTIVE
HTQFP
PAP
64
1500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
ADS2807Y
ADS2807Y/250
ACTIVE
HTQFP
PAP
64
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
ADS2807Y
ADS2807Y/250G4
ACTIVE
HTQFP
PAP
64
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
ADS2807Y
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Feb-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
ADS2807Y/1K5
HTQFP
PAP
64
1500
330.0
24.8
13.0
13.0
1.5
16.0
24.0
Q2
ADS2807Y/250
HTQFP
PAP
64
250
330.0
24.4
13.0
13.0
1.5
16.0
24.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Feb-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
ADS2807Y/1K5
HTQFP
PAP
64
1500
367.0
367.0
45.0
ADS2807Y/250
HTQFP
PAP
64
250
367.0
367.0
45.0
Pack Materials-Page 2
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