TI ADS5424IPJYR 14 bit, 105 msps analog to digital converter Datasheet

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D 52 Pin HTQFP Package With Exposed
FEATURES
D 14 Bit Resolution
D 105 MSPS Maximum Sample Rate
D SNR = 74 dBc at 105 MSPS and 50-MHz IF
D SFDR = 93 dBc at 105 MSPS and 50-MHz IF
D 2.2 Vpp Differential Input Range
D 5 V Supply Operation
D 3.3 V CMOS Compatible Outputs
D 1.9 W Total Power Dissipation
D 2s Complement Output Format
D On-Chip Input Analog Buffer, Track and Hold,
Heatsink
D Pin Compatible to the AD6644/45
D Industrial Temperature Range = −405C to 855C
APPLICATIONS
D Single and Multichannel Digital Receivers
D Base Station Infrastructure
D Instrumentation
D Video and Imaging
RELATED DEVICES
D Clocking: CDC7005
D Amplifiers: OPA695, THS4509
and Reference Circuit
DESCRIPTION
The ADS5424 is a 14 bit 105 MSPS analog-to-digital converter (ADC) that operates from a 5 V supply, while providing 3.3 V
CMOS compatible digital outputs. The ADS5424 input buffer isolates the internal switching of the on-chip Track and Hold
(T&H) from disturbing the signal source. An internal reference generator is also provided to further simplify the system
design. The ADS5424 has outstanding low noise and linearity, over input frequency. With only a 2.2 VPP input range,
simplifies the design of multicarrier applications, where the carriers are selected on the digital domain.
The ADS5424 is available in a 52 pin HTQFP with heatsink package and is pin compatible to the AD6645. The ADS5424
is built on state of the art Texas Instruments complementary bipolar process (BiCom3) and is specified over full industrial
temperature range (−40°C to 85°C).
FUNCTIONAL BLOCK DIAGRAM
AVDD
AIN
AIN
TH1
A1
+
TH2
Σ
A2
+
TH3
ADC1
DAC1
A3
ADC3
−
−
VREF
Σ
DRVDD
ADC2
DAC2
Reference
5
5
6
C1
C2
CLK+
CLK−
Digital Error Correction
Timing
DMID OVR
DRY
D[13:0]
GND
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPad is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.
Copyright  2005, Texas Instruments Incorporated
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PACKAGE/ORDERING INFORMATION
PRODUCT
PACKAGE LEAD
PACKAGE
DESIGNATOR
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
ADS5424
HTQFP-52(1)
PowerPAD
PJY
−40°C to +85°C
ADS5424I
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
ADS5424IPJY
Tray, 160
ADS5424IPJYR
Tape and Reel, 1000
(1) Thermal pad size: Octagonal 2,5 mm side
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
ADS5424
Supply voltage
AVDD to GND
DRVDD to GND
6
5
−0.3 to
AVDD + 0.3
Analog input to GND
−0.3 to
AVDD + 0.3
±2.5
Clock input to GND
CLK to CLK
Digital data output to GND
Operating temperature range
Maximum junction temperature
Storage temperature range
UNIT
This integrated circuit can be damaged by ESD. Texas
Instruments recommends that all integrated circuits be
handled with appropriate precautions. Failure to observe
proper handling and installation procedures can cause damage.
V
ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be more
susceptible to damage because small parametric changes could cause
the device not to meet its published specifications.
V
RECOMMENDED OPERATING CONDITIONS
V
V
PARAMETER
−0.3 to
DRVDD + 0.3
−40 to 85
°C
150
°C
Output driver supply voltage,
DRVDD
−65 to 150
°C
Analog Input
V
(1) Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods
may degrade device reliability. These are stress ratings only, and
functional operation of the device at these or any other conditions
beyond those specified is not implied.
MIN
TYP
MAX
UNIT
4.75
5
5.25
V
3
3.3
3.6
V
Supplies
Analog supply voltage, AVDD
Differential input range
Input common-mode voltage,
VCM
Digital Output
Maximum output load
THERMAL CHARACTERISTICS(1)
VPP
2.4
V
10
pF
Clock Input
PARAMETER
TEST
CONDITIONS
TYP
UNIT
θJA
Soldered slug, no
airflow
22.5
°C/W
θJA
Soldered slug,
200-LPFM airflow
15.8
°C/W
θJA
Unsoldered slug,
no airflow
33.3
°C/W
θJA
Unsoldered slug,
200-LPFM airflow
25.9
°C/W
θJC
Bottom of
package
(heatslug)
2
°C/W
(1) Using 25 thermal vias (5 x 5 array). See the Application Section.
2
2.2
ADCLK input sample rate (sine
wave) 1/tC
Clock amplitude, sine wave,
differential(1)
Clock duty cycle(2)
30
105
3
MSPS
VPP
50%
Open free-air temperature range −40
85
(1) See Figure 22 and Figure 23 for more information.
(2) See Figure 21 for more information.
°C
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ELECTRICAL CHARACTERISTICS
Over full temperature range (TMIN = −40°C to TMAX = 85°C), sampling rate = 105 MSPS, 50% clock duty cycle, AVDD = 5 V, DRVDD = 3.3 V,
−1 dBFS differential input, and 3 VPP differential sinusoidal clock, unless otherwise noted
TEST CONDITIONS
PARAMETER
MIN
Resolution
TYP
MAX
UNIT
14
Bits
2.2
VPP
kΩ
Analog Inputs
Differential input range
Differential input resistance
See Figure 32
Differential input capacitance
See Figure 32
1
Analog input bandwidth
1.5
pF
570
MHz
2.4
V
Internal Reference Voltages
Reference voltage, VREF
Dynamic Accuracy
No missing codes
Differential linearity error, DNL
Integral linearity error, INL
Tested
fIN = 5 MHz
fIN = 5 MHz
−0.95
±0.5
1.5
±1.5
Offset error
−5
Offset temperature coefficient
0
LSB
5
1.7
Gain error
−5
0.9
LSB
mV
ppm/°C
5
%FS
PSRR
1
mV/V
Gain temperature coefficient
77
ppm/°C
Power Supply
Analog supply current, IAVDD
VIN = full scale, fIN = 70 MHz
FS = 92.16 MSPS
FS = 105 MSPS
355
Output buffer supply current, IDRVDD
VIN = full scale, fIN = 70 MHz
FS = 92.16 MSPS
FS = 105 MSPS
38
Total power with 10-pF load
on each digital output to
ground, fIN = 70 MHz
FS = 92.16 MSPS
1.9
Power dissipation
FS = 105 MSPS
1.9
2.2
FS = 105 MSPS
20
100
Power-up time
355
40
410
47
mA
mA
W
ms
3
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SLWS157A − JANUARY 2005 − REVISED MAY 2005
ELECTRICAL CHARACTERISTICS
Over full temperature range (TMIN = −40°C to TMAX = 85°C), sampling rate = 105 MSPS, 50% clock duty cycle, AVDD = 5 V, DRVDD = 3.3 V,
−1 dBFS differential input, and 3 VPP differential sinusoidal clock, unless otherwise noted
TEST CONDITIONS
PARAMETER
MIN
TYP
MAX
UNIT
Dynamic AC Characteristics
Signal-to-noise ratio, SNR
Spurious-free dynamic range, SFDR
Signal-to-noise + distortion, SINAD
4
fIN = 10 MHz
FS = 92.16 MSPS
FS = 105 MSPS
74.5
fIN = 30 MHz
FS = 92.16 MSPS
FS = 105 MSPS
fIN = 50 MHz
FS = 92.16 MSPS
FS = 105 MSPS
fIN = 70 MHz
FS = 92.16 MSPS
FS = 105 MSPS
fIN = 100 MHz
FS = 92.16 MSPS
FS = 105 MSPS
73.5
fIN = 170 MHz
FS = 92.16 MSPS
FS = 105 MSPS
72
fIN = 230 MHz
FS = 92.16 MSPS
FS = 105 MSPS
71.5
fIN = 10 MHz
FS = 92.16 MSPS
FS = 105 MSPS
94
fIN = 30 MHz
FS = 92.16 MSPS
FS = 105 MSPS
fIN = 50 MHz
FS = 92.16 MSPS
FS = 105 MSPS
94
fIN = 70 MHz
FS = 92.16 MSPS
FS = 105 MSPS
89
fIN = 100 MHz
FS = 92.16 MSPS
FS = 105 MSPS
88
fIN = 170 MHz
FS = 92.16 MSPS
FS = 105 MSPS
73
fIN = 230 MHz
FS = 92.16 MSPS
FS = 105 MSPS
64
fIN = 10 MHz
FS = 92.16 MSPS
FS = 105 MSPS
74.4
fIN = 30 MHz
FS = 92.16 MSPS
FS = 105 MSPS
74.3
fIN = 50 MHz
FS = 92.16 MSPS
FS = 105 MSPS
fIN = 70 MHz
FS = 92.16 MSPS
FS = 105 MSPS
fIN = 100 MHz
FS = 92.16 MSPS
FS = 105 MSPS
73.3
fIN = 170 MHz
FS = 92.16 MSPS
FS = 105 MSPS
69.3
fIN = 230 MHz
FS = 92.16 MSPS
FS = 105 MSPS
63.4
74.4
73
74.4
dBc
74.3
dBc
74.2
74.2
74
72.5
74
73.5
72
71.5
93
85
dBc
dBc
dBc
dBc
dBc
dBc
95
dBc
95
dBc
93
88
87
73
64
74.3
72.8
dBc
74.3
74.1
74
74
73.9
73.3
69.1
63.4
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
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SLWS157A − JANUARY 2005 − REVISED MAY 2005
ELECTRICAL CHARACTERISTICS
Over full temperature range (TMIN = −40°C to TMAX = 85°C), sampling rate = 105 MSPS, 50% clock duty cycle, AVDD = 5 V, DRVDD = 3.3 V,
−1 dBFS differential input, and 3 VPP differential sinusoidal clock, unless otherwise noted
PARAMETER
Second harmonic, HD2
Third harmonic, HD3
Worst-harmonic / spur (other than HD2
and HD3)
RMS idle channel noise
TEST CONDITIONS
MIN
TYP
MAX
UNIT
fIN = 10 MHz
fIN = 30 MHz
100
dBc
105
dBc
fIN = 50 MHz
fIN = 70 MHz
98
dBc
98
dBc
fIN = 100 MHz
fIN = 170 MHz
98
dBc
98
dBc
fIN = 230 MHz
fIN = 10 MHz
96
dBc
93
dBc
fIN = 30 MHz
fIN = 50 MHz
95
dBc
93
dBc
fIN = 100 MHz
fIN = 170 MHz
87
dBc
73
dBc
fIN = 230 MHz
fIN = 10 MHz
64
dBc
93
dBc
fIN = 30 MHz
fIN = 50 MHz
95
dBc
93
dBc
fIN = 70 MHz
fIN = 100 MHz
88
dBc
88
dBc
fIN = 170 MHz
fIN = 230 MHz
88
dBc
88
dBc
Input pins tied together
0.9
LSB
DIGITAL CHARACTERISTICS
Over full temperature range (TMIN = −40°C to TMAX = 85°C), AVDD = 5 V, DRVDD = 3.3 V, unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
0.1
0.6
V
Digital Outputs
Low-level output voltage
High-level output voltage
CLOAD = 10 pF(1)
CLOAD = 10 pF(1)
Output capacitance
DMID
2.6
3.2
V
3
pF
DRVDD/2
V
(1) Equivalent capacitance to ground of (load + parasitics of transmission lines).
5
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TIMING CHARACTERISTICS(3)
Over full temperature range, AVDD = 5 V, DRVDD = 3.3 V, sampling rate = 105 MSPS
DESCRIPTION
PARAMETER
MIN
TYP
MAX
UNIT
Aperture Time
tA
tJ
Aperture delay
500
Clock slope independent aperture uncertainity (jitter)
150
ps
fs
kJ
Clock slope dependent jitter factor
50
µV
Clock period
9.5
ns
Clock pulsewidth high
4.75
ns
Clock pulsewidth low
4.75
ns
Clock Input
tCLK
tCLKH(1)
tCLKL(1)
Clock to DataReady (DRY)
tDR
Clock rising 50% to DRY falling 50%
2.8
3.9
7.6
tDR +
tCLKH
8.7
4.7
ns
tC_DR
Clock rising 50% to DRY rising 50%
ns
tC_DR_50%
Clock to DATA, OVR(4)
Clock rising 50% to DRY rising 50% with 50% duty cycle clock
tr
tf
Data VOL to data VOH (rise time)
2
Data VOH to data VOL (fall time)
2
ns
L
Latency
3
Cycles
tsu(C)
tH(C)
Valid DATA(2) to clock 50% with 50% duty cycle clock (setup time)
Clock 50% to invalid DATA(2) (hold time)
1.8
3.4
ns
2.6
3.6
ns
1.8
2.6
ns
3.9
4.4
ns
9.5
ns
ns
DataReady (DRY) to DATA, OVR(4)
tsu(DR)_50%
Valid DATA(2) to DRY 50% with 50% duty cycle clock (setup time)
th(DR)_50%
DRY 50% to invalid DATA(2) with 50% duty cycle clock (hold time)
(1) See Figure 21 for more information.
(2) See VOH and VOL levels.
(3) All values obtained from design and characterization.
(4) Data is updated with clock rising edge or DRY falling edge.
tA
N+3
N
AIN
N+1
N+2
tCLKH
tCLK
CLK, CLK
N+1
N
N+4
tCLKL
N+2
N+3
tC_DR
D[13:0], OVR
DRY
N−3
tr
N−2
tf
tDR
Figure 1. Timing Diagram
6
tsu(C)
N−1
tsu(DR)
N+4
th(DR)
N
th(C)
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PIN CONFIGURATION
DRY
D13 (MSB)
D12
D11
D10
D9
D8
D7
D6
DRVCC
GND
D5
D4
PJY PACKAGE
(TOP VIEW)
52 51 50 49 48 47 46 45 44 43 42 41 40
DRVDD
GND
VREF
GND
CLK
CLK
GND
AVDD
AVDD
GND
AIN
AIN
GND
1
39
2
3
38
37
4
36
5
6
35
34
7
33
GND
8
9
32
31
10
30
11
12
29
28
13
27
D3
D2
D1
D0 (LSB)
DMID
GND
DRVDD
OVR
DNC
AVDD
GND
AVDD
GND
AVDD
GND
AVDD
GND
AVDD
GND
C1
GND
AVDD
GND
C2
GND
AVDD
14 15 16 17 18 19 20 21 22 23 24 25 26
PIN ASSIGNMENTS
TERMINAL
NAME
NO.
DRVDD
1, 33, 43
DESCRIPTION
3.3 V power supply, digital output stage only
GND
2, 4, 7, 10, 13, 15,
17, 19, 21, 23, 25,
27, 29, 34, 42
VREF
3
2.4 V reference. Bypass to ground with a 0.1-µF microwave chip capacitor.
CLK
5
Clock input. Conversion initiated on rising edge.
CLK
6
Complement of CLK, differential input
AVDD
8, 9, 14, 16, 18,
22, 26, 28, 30
Ground
5 V analog power supply
AIN
11
Analog input
AIN
12
Complement of AIN, differential analog input
C1
20
Internal voltage reference. Bypass to ground with a 0.1-µF chip capacitor.
C2
24
Internal voltage reference. Bypass to ground with a 0.1-µF chip capacitor.
DNC
31
Do not connect
OVR
32
Overrange bit. A logic level high indicates the analog input exceeds full scale.
DMID
35
Output data voltage midpoint. Approximately equal to (DVCC)/2
36
Digital output bit (least significant bit); two’s complement
D0 (LSB)
D1−D5, D6−D12
37−41, 44−50
Digital output bits in two’s complement
D13 (MSB)
51
Digital output bit (most significant bit); two’s complement
DRY
52
Data ready output
7
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DEFINITION OF SPECIFICATIONS
Analog Bandwidth
The analog input frequency at which the power of the
fundamental is reduced by 3 dB with respect to the low
frequency value.
Aperture Delay
The delay between the rising edge of the input sampling
clock and the actual time at which the sampling occurs.
Aperture Uncertainty (Jitter)
The sample-to-sample variation in aperture delay.
Clock Pulse Width/Duty Cycle
The duty cycle of a clock signal is the ratio of the time
the clock signal remains at a logic high (clock pulse
width) to the period of the clock signal. Duty cycle is
typically expressed as a percentage. A perfect
differential sine wave clock results in a 50% duty cycle.
Maximum Conversion Rate
The maximum sampling rate at which certified
operation is given. All parametric testing is performed
at this sampling rate unless otherwise noted.
Offset Error
The offset error is the difference, given in number of
LSBs, between the ADC’s actual value average idle
channel output code and the ideal average idle channel
output code. This quantity is often mapped into mV.
Temperature Drift
The temperature drift coefficient (with respect to gain
error and offset error) specifies the change per degree
celcius of the paramter from TMIN or TMAX. It is
computed as the maximum variation of that parameter
over the whole temperature range divided by TMAX −
TMIN.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the power of the fundamental (PS)
to the noise floor power (PN), excluding the power at dc
and the first five harmonics.
SNR + 10Log 10
PS
PN
Minimum Conversion Rate
The minimum sampling rate at which the ADC
functions.
SNR is either given in units of dBc (dB to carrier) when
the absolute power of the fundamental is used as the
reference or dBFS (dB to full scale) when the power of
the fundamental is extrapolated to the converter’s
full-scale range.
Differential Nonlinearity (DNL)
An ideal ADC exhibits code transitions at analog input
values spaced exactly 1 LSB apart. The DNL is the
deviation of any single step from this ideal value,
measured in units of LSB.
Signal-to-Noise and Distortion (SINAD)
SINAD is the ratio of the power of the fundamental (PS)
to the power of all the other spectral components
including noise (PN) and distortion (PD), but excluding
dc.
Integral Nonlinearity (INL)
The INL is the deviation of the ADC’s transfer function
from a best fit line determined by a least squares curve
fit of that transfer function, measured in units of LSB.
Gain Error
The gain error is the deviation of the ADC’s actual input
full-scale range from its ideal value. The gain error is
given as a percentage of the ideal input full-scale range.
8
SINAD + 10Log 10
PS
PN ) PD
SINAD is either given in units of dBc (dB to carrier) when
the absolute power of the fundamental is used as the
reference or dBFS (dB to full scale) when the power of
the fundamental is extrapolated to the converter’s
full-scale range.
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Total Harmonic Distortion (THD)
THD is the ratio of the fundamental power (PS) to the
power of the first five harmonics (PD).
THD + 10Log 10
PS
PD
THD is typically given in units of dBc (dB to carrier).
Two-Tone Intermodulation Distortion
IMD3 is the ratio of the power of the fundamental (at
frequiencies f1, f2) to the power of the worst spectral
component at either frequency 2f1 − f2 or 2f2 − f1). IMD3 is
either given in units of dBc (dB to carrier) when the
absolute power of the fundamental is used as the
reference or dBFS (dB to full scale) when it is referred to
the full-scale range.
Spurious-Free Dynamic Range (SFDR)
The ratio of the power of the fundamental to the highest
other spectral component (either spur or harmonic). SFDR
is typically given in units of dBc (dB to carrier).
9
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TYPICAL CHARACTERISTICS
Typical values are at TA = 25°C, AVDD = 5 V, DRVDD = 3.3 V, differential input amplitude = −1 dBFS, sampling rate = 105 MSPS, 3 VPP
sinusoidal clock, 50% duty cycle, 16k FFT points, unless otherwise noted
SPECTRAL PERFORMANCE
1
0
fS = 105 MSPS
fIN = 2 MHz
SNR = 74.4 dBc
SINAD = 74.4 dBc
SFDR = 93 dBc
THD = 95 dBc
−40
−60
−80
−40
−60
−80
X
5
−100
6
2
2
6
4
−120
−120
0
10
20
30
40
50
0
10
Figure 3
SPECTRAL PERFORMANCE
fS = 105 MSPS
fIN = 100 MHz
SNR = 73.5 dBc
SINAD = 73.3 dBc
SFDR = 87 dBc
THD = 86 dBc
Amplitude − dBFS
−20
−60
−80
3
X
4
−40
−60
−80
3
X
5
2
−100
5
6
50
1
0
fS = 105 MSPS
fIN = 70 MHz
SNR = 74 dBc
SINAD = 73.9 dBc
SFDR = 92 dBc
THD = 91 dBc
−100
40
Figure 2
1
−40
30
f − Frequency − MHz
SPECTRAL PERFORMANCE
−20
20
f − Frequency − MHz
0
Amplitude − dBFS
X 5
3
3
−100
fS = 105 MSPS
fIN = 30 MHz
SNR = 74.4 dBc
SINAD = 74.3 dBc
SFDR = 94 dBc
THD = 93 dBc
−20
Amplitude − dBFS
−20
Amplitude − dBFS
SPECTRAL PERFORMANCE
1
0
4
2
6
−120
−120
0
10
20
30
40
50
0
10
Figure 5
Amplitude − dBFS
Amplitude − dBFS
fS = 105 MSPS
fIN = 230 MHz
SNR = 71 dBc
SINAD = 64.2 dBc
SFDR = 65 dBc
THD = 65 dBc
−20
−60
3
X
5
2
−40
−60
3
−80
5
4
6
X
4
−100
−120
2
6
−120
0
10
1
0
fS = 105 MSPS
fIN = 170 MHz
SNR = 71.9 dBc
SINAD = 69.1 dBc
SFDR = 72 dBc
THD = 72 dBc
−80
50
SPECTRAL PERFORMANCE
1
−100
40
Figure 4
SPECTRAL PERFORMANCE
−40
30
f − Frequency − MHz
0
−20
20
f − Frequency − MHz
10
20
30
40
50
0
10
20
30
f − Frequency − MHz
f − Frequency − MHz
Figure 6
Figure 7
40
50
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SLWS157A − JANUARY 2005 − REVISED MAY 2005
Typical values are at TA = 25°C, AVDD = 5 V, DRVDD = 3.3 V, differential input amplitude = −1 dBFS, sampling rate = 105 MSPS, 3 VPP
sinusoidal clock, 50% duty cycle, 16k FFT points, unless otherwise noted
SPECTRAL PERFORMANCE
−60
−80
−100
−40
−60
3
−80
X
−100
2
6
−120
10
20
30
40
0
10
20
30
f − Frequency − MHz
f − Frequency − MHz
Figure 8
Figure 9
SPECTRAL PERFORMANCE
40
SPECTRAL PERFORMANCE
0
0
fS = 92.16 MSPS
fIN 1 = 69.2 MHz, −7 dBFS
fIN 2 = 70.7 MHz, −7 dBFS
IMD3 = −93 dBFS
−40
fS = 92.16 MSPS
fIN 1 = 169.6 MHz, −7 dBFS
fIN 2 = 170.4 MHz, −7 dBFS
IMD3 = −82 dBFS
−20
Amplitude − dBFS
−20
Amplitude − dBFS
5
6
−120
0
−60
−80
−100
−120
−40
−60
−80
−100
−120
−140
−140
0
10
20
30
40
0
10
20
30
f − Frequency − MHz
f − Frequency − MHz
Figure 10
Figure 11
WCDMA CARRIER
40
WCDMA CARRIER
0
0
fS = 92.16 MSPS
fIN = 70 MHz
PAR = 5 dB
ACPR Adj Top = 79.2 dB
ACPR Adj Low = 79.7 dB
−40
fS = 92.16 MSPS
fIN = 170 MHz
PAR = 5 dB
ACPR Adj Top = 73.3 dB
ACPR Adj Low = 74 dB
−20
Amplitude − dBFS
−20
Amplitude − dBFS
4
2
X
5
4
fS = 92.16 MSPS
fIN = 170 MHz
SNR = 71.6 dBc
SINAD = 69 dBc
SFDR = 73 dBc
THD = 73 dBc
−20
Amplitude − dBFS
−40
1
0
fS = 92.16 MSPS
fIN = 70 MHz
SNR = 73.9 dBc
SINAD = 73.8 dBc
SFDR = 96 dBc
THD = 95 dBc
−20
Amplitude − dBFS
SPECTRAL PERFORMANCE
1
0
−60
−80
−100
−120
−40
−60
−80
−100
−120
−140
−140
0
10
20
30
40
0
10
20
30
f − Frequency − MHz
f − Frequency − MHz
Figure 12
Figure 13
40
11
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SLWS157A − JANUARY 2005 − REVISED MAY 2005
Typical values are at TA = 25°C, AVDD = 5 V, DRVDD = 3.3 V, differential input amplitude = −1 dBFS, sampling rate = 105 MSPS, 3 VPP
sinusoidal clock, 50% duty cycle, 16k FFT points, unless otherwise noted
AC PERFORMANCE
vs
INPUT AMPLITUDE
AC PERFORMANCE
vs
INPUT AMPLITUDE
120
120
100
SFDR (dBFS)
AC Performance − dB
AC Performance − dB
100
80
SNR (dBFS)
60
SFDR (dBc)
40
20
SNR (dBc)
0
fS = 92.16 MSPS
fIN = 70 MHz
−80
−70
−60
−50
−40
−30
−20
−10
SNR (dBFS)
60
SFDR (dBc)
40
20
SNR (dBc)
−20
−90
0
−80
−70
−50
−40
−30
−20
AIN − Input Amplitude − dBFS
Figure 14
Figure 15
TWO-TONE SPURIOUS-FREE DYNAMIC RANGE
vs
INPUT AMPLITUDE
−10
0
NOISE HISTOGRAM WITH INPUTS SHORTED
40
120
100
35
SFDR (dBFS)
30
80
60
40
SFDR (dBc)
20
90 dBFS Line
0
25
20
15
10
fIN1 = 69 MHz
fIN2 = 71 MHz
fS = 92.16 MSPS
−20
−110−100 −90 −80 −70 −60 −50 −40 −30 −20 −10
5
0
8174
0
8175
8176
8177
AIN − Input Amplitude − dBFS
Code Number
Figure 16
Figure 17
8178
8179
INPUT BANDWIDTH
1.90
2
fIN= 70 MHz
1.89
0
1.88
Power Output − dB
PT − Total Power − W
−60
AIN − Input Amplitude − dB
TOTAL POWER
vs
SAMPLING FREQUENCY
1.87
1.86
1.85
1.84
1.83
−2
−4
−6
−8
1.82
1.81
fS = 105 MSPS
AIN = −1 dBFS
−10
0
12
fS = 92.16 MSPS
fIN = 170 MHz
0
Percentage − %
SFDR − Two-Tone Spurious-Free Dynamic Range − dB
−20
−90
SFDR (dBFS)
80
20
40
60
80
100
120
140
1
10
100
fS − Sampling Frequency − MSPS
f − Frequency − MHz
Figure 18
Figure 19
1k
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SLWS157A − JANUARY 2005 − REVISED MAY 2005
AC PERFORMANCE
vs
CLOCK COMMON MODE
100
fS = 105 MSPS
fIN = 69.6 MHz
95
AC Performance − dB
SFDR
SFDR (dBc)
90
85
80
SNR (dBc)
SNR
75
70
65
60
0
1
2
3
4
5
SFDR − Spurious-Free Dynamic Range − dBc
Typical values are at TA = 25°C, AVDD = 5 V, DRVDD = 3.3 V, differential input amplitude = −1 dBFS, sampling rate = 105 MSPS, 3 VPP
sinusoidal clock, 50% duty cycle, 16k FFT points, unless otherwise noted
SPURIOUS-FREE DYNAMIC RANGE
vs
DUTY CYCLE
100
fIN = 2 MHz
95
90
85
fIN = 50 MHz
75
70
65
40
50
55
Duty Cycle − %
Figure 20
Figure 21
AC PERFORMANCE
vs
CLOCK LEVEL
AC PERFORMANCE
vs
CLOCK LEVEL
60
75
90
SFDR (dBc)
SFDR (dBc)
70
AC Performance − dB
85
80
75
70
SNR (dBc)
65
60
fS = 105 MSPS
fIN = 70 MHz
55
50
0
1
2
3
SNR (dBc)
65
60
55
0
2
3
Differential Clock Level − VPP
Figure 22
Figure 23
4
SIGNAL-TO-NOISE RATIO
vs
SUPPLY VOLTAGE AND AMBIENT TEMPERATURE
94
74.8
fS = 105 MSPS
fIN = 69.6 MHz
100°C
92
91
60°C
85°C
−20°C
90
89
88
87
86
85
2.6
1
Differential Clock Level − VPP
SPURIOUS-FREE DYNAMIC RANGE
vs
SUPPLY VOLTAGE AND AMBIENT TEMPERATURE
93
fS = 105 MSPS
fIN = 170 MHz
50
4
SNR − Signal-to-Noise Ratio − dBc
AC Performance − dB
45
Clock Common Mode − V
95
SFDR − Sprious-Free Dynamic Range − dBc
fIN = 70 MHz
80
20°C
−40°C
2.8
3.0
3.2
3.4
3.6
3.8
74.6
fS = 105 MSPS
fIN = 69.6 MHz
−40°C
74.4
74.2
−20°C
20°C
74.0
73.8
60°C
73.6
85°C
73.4
100°C
73.2
73.0
2.6
2.8
3.0
3.2
3.4
DRVDD − Supply Voltage − V
DRVDD − Supply Voltage − V
Figure 24
Figure 25
3.6
3.8
13
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SLWS157A − JANUARY 2005 − REVISED MAY 2005
SPURIOUS-FREE DYNAMIC RANGE
vs
SUPPLY VOLTAGE AND AMBIENT TEMPERATURE
SIGNAL-TO-NOISE RATIO
vs
SUPPLY VOLTAGE AND AMBIENT TEMPERATURE
74.6
91.0
90.5
fS = 105 MSPS
fIN = 69.6 MHz
60°C
SNR − Signal-to-Noise Ratio − dBc
SFDR − Sprious-Free Dynamic Range − dBc
Typical values are at TA = 25°C, AVDD = 5 V, DRVDD = 3.3 V, differential input amplitude = −1 dBFS, sampling rate = 105 MSPS, 3 VPP
sinusoidal clock, 50% duty cycle, 16k FFT points, unless otherwise noted
90.0
89.5
−20°C
85°C
89.0
88.5
88.0
87.5
87.0
20°C
86.5
−40°C
86.0
4.6
4.7
4.8
4.9
5.0
5.1
5.2
5.3
−40°C
74.2
0°C
74.0
40°C
73.8
73.6
60°C
100°C
73.4
85°C
73.2
73.0
4.6
5.4
5.0
5.2
AVDD − Supply Voltage − V
Figure 26
Figure 27
DIFFERENTIAL NONLINEARITY
5.4
INTEGRAL NONLINEARITY
1.5
0.8
INL − Integral Nonlinearity − LSB
DNL − Differential Nonlinearity − LSB
4.8
AVDD − Supply Voltage − V
1.0
0.6
0.4
0.2
−0.0
−0.2
−0.4
−0.6
−0.8
−1.0
1.0
0.5
0.0
−0.5
−1.0
−1.5
0
5000
10000
Code
Figure 28
14
fS = 105 MSPS
fIN = 69.6 MHz
74.4
15000
0
5000
10000
Code
Figure 29
15000
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SLWS157A − JANUARY 2005 − REVISED MAY 2005
Typical values are at TA = 25°C, AVDD = 5 V, DRVDD = 3.3 V, differential input amplitude = −1 dBFS, sampling rate = 105 MSPS, 3 VPP
sinusoidal clock, 50% duty cycle, 16k FFT points, unless otherwise noted
73
120
71
74
fS − Sampling Frequency − MHz
110
72
74
100
90
73
71
80
70
74
72
73
70
60
71
74
69
50
72
74
40
73
69
71
70
30
73
71
70
69
10
20
0
40
68
60
80
67
66
120
100
68
69
72
20
68
70
67
64
65
140
160
66
65
62
63
180
200
220
fIN − Input Frequency − MHz
62
64
66
68
70
72
74
SNR − dBc
Figure 30.
120
88
91
76
88
110
fS − Sampling Frequency − MHz
79
82
85
85
91
94
100
73
67
82
79
85
91
90
94
91
94
80
94
94
94
70
73
76
70
67
88
82
94
85
94
60
64
70
79
91
94
94
94
94
91
94
91
85
82
79
94
91
40
60
64
80
100
120
140
61
70
73
76
85
10
20
67
70
91
94
20
0
73
94
40
30
76
88
50
160
180
200
220
fIN − Input Frequency − MHz
60
65
70
75
80
85
90
SFDR − dBc
Figure 31.
15
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SLWS157A − JANUARY 2005 − REVISED MAY 2005
EQUIVALENT CIRCUITS
AVDD
AIN
BUF
T/H
AVDD
500 Ω
BUF
VREF
AVDD
VREF
−
Bandgap
1.2 kΩ
500 Ω
AIN
25 Ω
+
BUF
1.2 kΩ
T/H
Figure 35. Reference
Figure 32. Analog Input
DRVDD
AVDD
−
DAC
Bandgap
+
IOUTP
IOUTM
C1, C2
Figure 33. Digital Output
Figure 36. Decoupling Pin
AVDD
DRVDD
10 kΩ
CLK
1 kΩ
Clock Buffer
DMID
Bandgap
AVDD
1 kΩ
10 kΩ
CLK
Figure 34. Clock Input
16
Figure 37. DMID Generation
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SLWS157A − JANUARY 2005 − REVISED MAY 2005
APPLICATION INFORMATION
THEORY OF OPERATION
The ADS5424 is a 14 bit, 105 MSPS, monolithic
pipeline analog to digital converter. Its bipolar analog
core operates from a 5 V supply, while the output uses
3.3 V supply for compatibility with the CMOS family. The
conversion process is initiated by the rising edge of the
external input clock. At that instant, the differential input
signal is captured by the input track and hold (T&H) and
the input sample is sequentially converted by a series
of small resolution stages, with the outputs combined in
a digital correction logic block. Both the rising and the
falling clock edges are used to propagate the sample
through the pipeline every half clock cycle. This process
results in a data latency of three clock cycles, after
which the output data is available as a 14 bit parallel
word, coded in binary two’s complement format.
INPUT CONFIGURATION
The analog input for the ADS5424 (see Figure 32)
consists of an analog differential buffer followed by a
bipolar track-and-hold. The analog buffer isolates the
source driving the input of the ADC from any internal
switching. The input common mode is set internally
through a 500 Ω resistor connected from 2.4 V to each
of the inputs. This results in a differential input
impedance of 1 kΩ.
of 2.2 VPP. The maximum swing is determined by the
internal reference voltage generator eliminating any
external circuitry for this purpose.
The ADS5424 obtains optimum performance when the
analog inputs are driven differentially. The circuit in
Figure 38 shows one possible configuration using an
RF transformer with termination either on the primary or
on the secondary of the transformer. If voltage gain is
required a step up transformer can be used. For higher
gains that would require impractical higher turn ratios on
the transformer, a single-ended amplifier driving the
transformer can be used (see Figure 39). Another
circuit optimized for performance would be the one on
Figure 40, using the THS4304 or the OPA695. Texas
Instruments has shown excellent performance on this
configuration up to 10 dB gain with the THS4304 and at
14 dB gain with the OPA695. For the best performance,
they need to be configured differentially after the
transformer (as shown) or in inverting mode for the
OPA695 (see SBAA113); otherwise, HD2 from the op
amps limits the useful frequency.
R0
50W
VIN
AIN
1:1
R
50W
AC Signal
Source
For a full-scale differential input, each of the differential
lines of the input signal (pins 11 and 12) swings
symmetrically between 2.4 +0.55 V and 2.4 –0.55 V.
This means that each input is driven with a signal of up
to 2.4 ±0.55 V, so that each input has a maximum signal
swing of 1.1 VPP for a total differential input signal swing
5V
Z0
50W
ADS5424
AIN
ADT1−1WT
Figure 38. Converting a Single-Ended Input to a
Differential Signal Using RF Transformers
−5 V
RS
100 Ω
+
OPA695
−
0.1 µF
1000 µF
RIN
1:1
RT
100 Ω
RIN
AIN
CIN
ADS5424
AIN
R1
400 Ω
R2
57.5 Ω
AV = 8V/V
(18 dB)
Figure 39. Using the OPA695 With the ADS5424
17
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SLWS157A − JANUARY 2005 − REVISED MAY 2005
APPLICATION INFORMATION
RG
RF
CM
5V
−
THS4304
+
1:1
VIN
49.9 Ω
CM
From
50 Ω
Source
5V
AIN
ADS5424
VREF
AIN
+
THS4304
−
RG
CM
RF
CM
Figure 40. Using the THS4304 With the ADS5424
Besides these, Texas Instruments offers a wide
selection of single-ended operational amplifiers
(including the THS3201, THS3202 and OPA847) that
can be selected depending on the application. An RF
gain block amplifier, such as Texas Instrument’s
THS9001, can also be used with an RF transformer for
high input frequency applications. For applications
requiring dc-coupling with the signal source, instead of
using a topology with three single ended amplifiers, a
differential input/differential output amplifier like the
THS4509 (see Figure 41) can be used, which
minimizes board space and reduce number of
components.
Figure 43 shows their combined SNR and SFDR
performance versus frequency with −1 dBFS input
signal level and sampling at 80MSPS.
On this configuration, the THS4509 amplifier circuit
provides 10 dB of gain, converts the single-ended input
to differential, and sets the proper input common-mode
voltage to the ADS5424.
The 225 Ω resistors and 2.7 pF capacitor between the
THS4509 outputs and ADS5424 inputs (along with the
input capacitance of the ADC) limit the bandwidth of the
signal to about 100 MHz (−3 dB).
18
For this test, an Agilent signal generator is used for the
signal source. The generator is an ac-coupled 50 Ω
source. A band-pass filter is inserted in series with the
input to reduce harmonics and noise from the signal
source.
Input termination is accomplished via the 69.8 Ω
resistor and 0.22 µF capacitor to ground in conjunction
with the input impedance of the amplifier circuit. A
0.22 µF capacitor and 49.9 Ω resistor is inserted to
ground across the 69.8 Ω resistor and 0.22 µF capacitor
on the alternate input to balance the circuit.
Gain is a function of the source impedance, termination,
and 348 Ω feedback resistor. See the THS4509 data
sheet for further component values to set proper 50 Ω
termination for other common gains.
Since
the
ADS5424
recommended
input
common-mode voltage is +2.4 V, the THS4509 is
operated from a single power supply input with VS+ =
+5 V and VS− = 0 V (ground). This maintains maximum
headroom on the internal transistors of the THS4509.
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SLWS157A − JANUARY 2005 − REVISED MAY 2005
APPLICATION INFORMATION
From VIN
50 Ω
Source
348 Ω
100 Ω
69.8 Ω
+5V
225 Ω
0.22 µF
CM
69.8 Ω
0.22 µF
AIN
ADS5424
AIN VREF
2.7 pF
225 Ω
THS 4509
100 Ω
49.9 Ω
14-Bit
105 MSPS
49.9 Ω
0.22 µF
0.1 µF
348 Ω
0.1 µF
Figure 41. Using the THS4509 With the ADS5424
configurations. In low input frequency applications,
where jitter may not be a big concern, the use of
single-ended clock (see Figure 43) could save some
cost and board space without any trade-off in
performance. When driven on this configuration, it is
best to connect CLKM (pin 11) to ground with a 0.01 µF
capacitor, while CLKP is ac-coupled with a 0.01 µF
capacitor to the clock source, as shown in Figure 40.
Clock
Source
0.1 µF
1:4
CLK
MA3X71600LCT−ND
PERFORMANCE
vs
INPUT FREQUENCY
CLK
95
Figure 44. Differential Clock
Nevertheless, for jitter sensitive applications, the use of
a differential clock will have some advantages (as with
any other ADCs) at the system level. The first
advantage is that it allows for common-mode noise
rejection at the PCB level. A further analysis (see
Clocking High Speed Data Converters, SLYT075)
reveals one more advantage. The following formula
describes the different contributions to clock jitter:
90
Performance − dB
ADS5424
SFDR (dBc)
85
80
SNR (dBFS)
75
70
10
20
30
40
50
60
70
fIN − Input Frequency − MHz
Figure 42. Performance vs Input Frequency for
the THS4509 + ADS5424 Configuration
Square Wave or
Sine Wave
CLK
0.01 µF
ADS5424
CLK
0.01 µF
Figure 43. Single-Ended Clock
CLOCK INPUTS
The ADS5424 clock input can be driven with either a
differential clock signal or a single-ended clock input,
with little or no difference in performance between both
(Jittertotal)2 = (EXT_jitter)2+ (ADC_jitter)2=
(EXT_jitter) 2 + (ADC_int)2 + (K/clock_slope)2
The first term would represent the external jitter, coming
from the clock source, plus noise added by the system
on the clock distribution, up to the ADC. The second
term is the ADC contribution, which can be divided in
two portions. The first does not depend directly on any
external factor. That is the best we can get out of our
ADC. The second contribution is a term inversely
proportional to the clock slope. The faster the slope, the
smaller this term will be. As an example, we could
compute the ADC jitter contribution from a sinusoidal
input clock of 3 Vpp amplitude and Fs = 80 MSPS:
ADC_jitter = sqrt ((150fs)2+ (5 x 10−5/(1.5 x 2 x PI x 80
x 106))2) = 164fs
The use of differential clock allows for the use of bigger
clock amplitudes without exceeding the absolute
maximum ratings. This, on the case of sinusoidal clock,
results on higher slew rates which minimizes the impact
of the jitter factor inversely proportional to the clock
slope.
19
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SLWS157A − JANUARY 2005 − REVISED MAY 2005
APPLICATION INFORMATION
Figure 44 shows this approach. The back-to-back
Schottky can be added to limit the clock amplitude in
cases where this would exceed the absolute maximum
ratings, even when using a differential clock. Figure 22
and Figure 23 show the performance versus input clock
amplitude for a sinusoidal clock.
100 nF
MC100EP16DT
100 nF
D
D
CLK
Q
VBB Q
499 W
100 nF
100 nF
ADS5424
CLK
499 W
50 Ω
50 Ω
100 nF
113 Ω
Figure 45. Differential Clock Using PECL Logic
Another possibility is the use of a logic based clock, as
PECL. In this case, the slew rate of the edges will most
likely be much higher than the one obtained for the
same clock amplitude based on a sinusoidal clock. This
solution would minimize the effect of the slope
dependent ADC jitter. Nevertheless, observe that for
the ADS5424, this term is small and has been
optimized. Using logic gates to square a sinusoidal
clock may not produce the best results as logic gates
may not have been optimized to act as comparators,
adding too much jitter while squaring the inputs.
The common-mode voltage of the clock inputs is set
internally to 2.4 V using internal 1 kΩ resistors. It is
recommended to use an ac coupling, but if for any
reason, this scheme is not possible, due to, for
instance, asynchronous clocking, the ADS5424
presents a good tolerance to clock common-mode
variation (see Figure 20).
Additionally, the internal ADC core uses both edges of
the clock for the conversion process. This means that,
ideally, a 50% duty cycle should be provided. Figure 21
shows the performance variation of the ADC versus
clock duty cycle.
20
DIGITAL OUTPUTS
The ADC provides 14 data outputs (D13 to D0, with D13
being the MSB and D0 the LSB), a data-ready signal
(DRY, pin 52), and an out-of-range indicator (OVR, pin
32) that equals 1 when the output reaches the full-scale
limits.
The output format is two’s complement. When the input
voltage is at negative full scale (around −1.1 V
differential), the output will be, from MSB to LSB, 10
0000 0000 0000. Then, as the input voltage is
increased, the output switches to 10 0000 0000 0001,
10 0000 0000 0010 and so on until 11 1111 1111 1111
right before mid-scale (when both inputs are tight
together if we neglect offset errors). Further increases
on input voltage, outputs the word 00 0000 0000 0000,
to be followed by 00 0000 0000 0001, 00 0000 0000
0010 and so on until reaching 01 1111 1111 1111 at
full-scale input (1.1-V differential).
Although the output circuitry of the ADS5424 has been
designed to minimize the noise produced by the
transients of the data switching, care must be taken
when designing the circuitry reading the ADS5424
outputs. Output load capacitance should be minimized
by minimizing the load on the output traces, reducing
their length and the number of gates connected to them,
and by the use of a series resistor with each pin. Typical
numbers on the data sheet tables and graphs are
obtained with 100 Ω series resistor on each digital
output pin, followed by a 74AVC16244 digital buffer as
the one used in the evaluation board.
POWER SUPPLIES
The use of low noise power supplies with adequate
decoupling is recommended, being the linear supplies
the first choice versus switched ones, which tend to
generate more noise components that can be coupled
to the ADS5424.
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SLWS157A − JANUARY 2005 − REVISED MAY 2005
APPLICATION INFORMATION
The ADS5424 uses two power supplies. For the analog
portion of the design, a 5 V AVDD is used, while for the
digital outputs supply (DRVDD), we recommend the use
of 3.3 V. All the ground pins are marked as GND,
although AGND pins and DRGND pins are not tied
together inside the package. Customers willing to
experiment with different grounding schemes should
know that AGND pins are 4, 7, 10, 13, 15, 17, 19, 21,
23, 25, 27, and 29, while DRGND pins are 2, 34, and 42.
Nevertheless, we recommend that both grounds are
tied together externally, using a common ground plane.
That is the case on the production test boards and
modules provided to customer for evaluation. In order
to obtain the best performance, user should layout the
board to guarantee that the digital return currents do not
flow under the analog portion of the board. This can be
achieved without the need to split the board and just
with careful component placing and increasing the
number of vias and ground planes.
Finally, notice that the metallic heat sink under the
package is also connected to analog ground.
LAYOUT INFORMATION
The evaluation board represents a good guideline of
how to layout the board to obtain the maximum
performance out of the ADS5424. General design rules
as the use of multilayer boards, single ground plane for
both, analog and digital ADC ground connections and
local decoupling ceramic chip capacitors should be
applied. The input traces should be isolated from any
external source of interference or noise, including the
digital outputs as well as the clock traces. Clock should
also be isolated from other signals, especially on
applications where low jitter is required, as high IF
sampling.
Besides performance oriented rules, special care has
to be taken when considering the heat dissipation out
of the device. The thermal heat sink (octagonal, with
2,5 mm on each side) should be soldered to the board,
and provision for more than 16 ground vias should be
made. The thermal package information describes the
TJA values obtained on the different configurations.
21
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SLWS157A − JANUARY 2005 − REVISED MAY 2005
MECHANICAL DATA
Center Power Pad Solder Stencil
Stencil Thicknes s
X
7.0
0.1m m
6.5
0.127m m
0.152m m
6.0
0.178m m
5.6
22
Opening
Y
7.0
6.5
6.0
5.6
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SLWS157A − JANUARY 2005 − REVISED MAY 2005
MECHANICAL DATA
PJY (S−PQFP−G52)
PLASTIC QUAD FLATPACK
23
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms
and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
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Following are URLs where you can obtain information on other Texas Instruments products and application
solutions:
Products
Applications
Amplifiers
amplifier.ti.com
Audio
www.ti.com/audio
Data Converters
dataconverter.ti.com
Automotive
www.ti.com/automotive
DSP
dsp.ti.com
Broadband
www.ti.com/broadband
Interface
interface.ti.com
Digital Control
www.ti.com/digitalcontrol
Logic
logic.ti.com
Military
www.ti.com/military
Power Mgmt
power.ti.com
Optical Networking
www.ti.com/opticalnetwork
Microcontrollers
microcontroller.ti.com
Security
www.ti.com/security
Telephony
www.ti.com/telephony
Video & Imaging
www.ti.com/video
Wireless
www.ti.com/wireless
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