High Speed Super Low Power SRAM 256K-Word By 8 Bit CS18LV20483 Revision History Rev. No. 1.0 History Initial issue 1 Issue Date Jan.26,2005 Remark Rev. 1.0 Chiplus reserves the right to change product or specification without notice. High Speed Super Low Power SRAM CS18LV20483 256K-Word By 8 Bit GENERAL DESCRIPTION The CS18LV20483 is a high performance, high speed, and super low power CMOS Static Random Access Memory organized as 262,144 words by 8 bits and operates from a wide range of 2.7 to 3.6V supply voltage. Advanced CMOS technology and circuit techniques provide both high speed and low power features with a typical CMOS standby current of 0.50uA and maximum access time of 55/70ns in 3.0V operation. Easy memory expansion is provided by an active LOW chip enable inputs (/CE1,CE2) and active LOW output enable (/OE) and three-state output drivers. The CS18LV20483 has an automatic power down feature, reducing the power consumption significantly when chip is deselected. The CS18LV20483 is available in JEDEC standard 32-pin sTSOP (8x13.4 mm), TSOP (8x20mm), TSOP (II) (400mil) and SOP (450 mil) packages. . FEATURES Low operation voltage : 2.7 ~ 3.6V Ultra low power consumption : 2mA＠1MHz (Max.) operating current 0.50 uA (Typ.) CMOS standby current High speed access time : 55/70ns (Max.) at Vcc = 3.0V. Automatic power down when chip is deselected. Three state outputs and TTL compatible Data retention supply voltage as low as 1.5V. Easy expansion with /CE and /OE options. Product Family Product Family Operating Temp Vcc. Range Speed (ns) Standby (Typ.) Package Type 32 SOP 0~70oC 2.7~3.6 55/70 0.50 uA (Vcc = 3.0V) 32 STSOP 32 TSOP 32 TSOP (II) Dice CS18LV20483 32 SOP o -40~85 C 2.7~3.6 55/70 0.8 uA (Vcc= 3.0V) 32 STSOP 32 TSOP 32 TSOP (II) Dice 2 Rev. 1.0 Chiplus reserves the right to change product or specification without notice. High Speed Super Low Power SRAM 256K-Word By 8 Bit CS18LV20483 PIN CONFIGURATIONS FUNCTIONAL BLOCK DIAGRAM 3 Rev. 1.0 Chiplus reserves the right to change product or specification without notice. High Speed Super Low Power SRAM CS18LV20483 256K-Word By 8 Bit PIN DESCRIPTIONS Type Function Input Address inputs for selecting one of the 262,144 x 8 bit words in the RAM Name A0 – A17 /CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active when data read from or write to the device. If either chip enable is /CE1, CE2 Input not active, the device is deselected and in a standby power down mode. The DQ pins will be in high impedance state when the device is deselected. The Write enable input is active LOW. It controls read and write /WE Input operations. With the chip selected, when /WE is HIGH and /OE is LOW, output data will be present on the DQ pins, when /WE is LOW, the data present on the DQ pins will be written into the selected memory location. The output enable input is active LOW. If the output enable is active /OE Input while the chip is selected and the write enable is inactive, data will be present on the DQ pins and they will be enabled. The DQ pins will be in the high impedance state when /OE is inactive. These 8 bi-directional ports are used to read data from or write data into DQ0~DQ7 I/O Vcc Power Power Supply Gnd Power Ground the RAM. No connection NC TRUTH TABLE MODE /CE1 CE2 /WE /OE H X X X X L X L H H Standby DQ0~7 Vcc Current High Z ICCSB, ICCSB1 H High Z ICC Output Disabled L Read L H H L DOUT ICC Write L H L X DIN ICC 4 Rev. 1.0 Chiplus reserves the right to change product or specification without notice. High Speed Super Low Power SRAM CS18LV20483 256K-Word By 8 Bit ABSOLUTE MAXIMUM RATINGS (1) Symbol Parameter VTERM Terminal Voltage with Respect to GND TBIAS Temperature Under Bias Rating Unit -0.5 to Vcc+0.5 V -40 to +125 O -60 to +150 O C TSTG Storage Temperature PT Power Dissipation 1.0 W IOUT DC Output Current 25 mA C 1.Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. OPERATING RANGE Range Ambient Temperature Commercial o 0~70 C 2.7V ~ 3.6V o -40~85 C Industrial Vcc 2.7V ~ 3.6V 1. Overshoot : Vcc +2.0V in case of pulse width ≦20ns. 2. Undershoot : - 2.0V in case of pulse width ≦20ns. 3. Overshoot and undershoot are sampled, not 100% tested. CAPACITANCE (1) (TA = 25oC, f =1.0 MHz) Symbol Parameter Conditions MAX. Unit CIN Input Capacitance VIN=0V 6 pF CDQ Input/Output Capacitance VI/O=0V 8 pF 1. This parameter is guaranteed and not tested. 5 Rev. 1.0 Chiplus reserves the right to change product or specification without notice. High Speed Super Low Power SRAM CS18LV20483 256K-Word By 8 Bit DC ELECTRICAL CHARACTERISTICS Parameter Name VIL Parameter Test Conduction Guaranteed Input Low Voltage VIH MIN TYP(1) MAX Unit -0.5 0.8 V 2.0 Vcc+0.2 V (2) Guaranteed Input High Voltage o ( TA = 0 to + 70 C , Vcc = 3.0V ) (2) IIL Input Leakage Current VCC=MAX, VIN=0 to VCC -1 1 uA IOL Output Leakage VCC=MAX, /CE=VIN, or -1 1 uA Current /OE=VIN , VIO=0V to VCC VOL Output Low Voltage VCC=MAX, IOL = 2mA 0.4 V VOH Output High Voltage VCC=MIN, IOH = -1mA ICC Operating Power /CE=VIL, IDQ=0mA, 2.4 V F=FMAX(3) 25 mA 1 mA 4 uA Supply Current ICCSB Standby Supply - TTL /CE=VIH, IDQ=0mA, ICCSB1 Standby Current /CE≧VCC-0.2V, VIN≧ -CMOS VCC-0.2V or VIN≦0.2V 0.5 o 1. Typical characteristics are at TA = 25 C. 2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included. 3. Fmax = 1/tRC. DATA RETENTION CHARACTERISTICS ( TA = 0 to + 70oC) Parameter Name VDR ICCDR TCDR tR Parameter Test Conduction VCC for Data Retention /CE≧VCC-0.2V, VIN≧VCC-0.2V or VIN≦0.2V MIN 1.5 Data Retention Current /CE≧VCC-0.2V, VCC=1.5V Retention Time Operation Recovery V 0.3 VIN≧VCC-0.2V or VIN≦0.2V Chip Deselect to Data TYP MAX Unit 2 uA 0 ns tRC (1) ns See Retention Waveform Time 1. Read Cycle Time. 6 Rev. 1.0 Chiplus reserves the right to change product or specification without notice. High Speed Super Low Power SRAM CS18LV20483 256K-Word By 8 Bit LOW Vcc DATA RETENTION WAVEFORM 1 ( /CE1 Controlled ) LOW Vcc DATA RETENTION WAVEFORM 2 ( CE2 Controlled ) AC TEST CONDITIONS Input Pulse Levels Vcc/0V Input Rise and Fall Times Input and Output Timing Reference Level Output Load KEY TO SWITCHING WAVEFORMS WAVEFORMS 5ns INPUTS OUTPUTS MUST BE STEADY MUST BE STEADY 0.5Vcc See FIGURE 1A MAY CHANGE FROM H TO L WILL BE CHANGE FROM H TO L MAY CHANGE FROM L TO H WILL BE CHANGE FROM L TO H DON’T CARE ANY CHANGE PERMITTED CHANGE STATE UNKNOWN DOES NOT APPLY CENTER LINE IS HIGH IMPEDANCE OFF STATE and 1B 7 Rev. 1.0 Chiplus reserves the right to change product or specification without notice. High Speed Super Low Power SRAM CS18LV20483 256K-Word By 8 Bit AC TEST LOADS AND WAVEFORMS TERMINAL EQUIVALENT 667Ω OUTPUT 1.73V ALL INPUT PULSES VCC GND FIGURE 1A 90% FIGURE 2 FIGURE 1B 90% 10% 10% 5ns 5ns AC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70oC , Vcc = 3.3V ) < READ CYCLE > JEDEC Parameter Parameter Name Name Description -55 -70 MIN MAX MIN MAX tAVAX tRC Read Cycle Time tAVQV tAA Address Access Time 55 70 ns tELQV tCO Chip Select Access Time 55 70 ns tGLQV tOE Output Enable to Output Valid 25 35 ns tELQX tLZ Chip Select to Output Low Z 10 10 ns tGLQX tOLZ Output Enable to Output in Low Z 5 5 ns tEHQZ tCHZ Chip Deselect to Output in High Z 0 20 0 25 ns tGHQZ tOHZ Output Disable to Output in High Z 0 20 0 25 ns tAXOX tOH Out Disable to Address Change 10 8 55 Unit 70 ns 10 ns Rev. 1.0 Chiplus reserves the right to change product or specification without notice. High Speed Super Low Power SRAM 256K-Word By 8 Bit CS18LV20483 SWITCHING WAVEFORMS (READ CYCLE) NOTES: 1. tHZ and tOHZ are defined as the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device interconnection. 9 Rev. 1.0 Chiplus reserves the right to change product or specification without notice. High Speed Super Low Power SRAM CS18LV20483 256K-Word By 8 Bit AC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70oC , Vcc = 3.3V ) < WRITE CYCLE > JEDEC Parameter Parameter Name Name Description -55 -70 MIN MAX MIN Unit MAX tAVAX tWC Write Cycle Time 55 70 ns tE1LWH tCW Chip Select to End of Write 45 60 ns tAVWL tAS Address Setup Time 0 0 ns tAVWH tAW Address Valid to End of Write 45 60 ns tWLWH tWP Write Pulse Width 40 50 ns tWHAX tWR Write Recovery Time 0 0 ns tWLQZ tWHZ Write to Output in High Z tDVWH tDW Data to Write Time Overlap 25 30 ns tWHDX tDH Data Hold from Write Time 0 0 ns tWHOX tOW End of Write to Output Active 5 5 ns 10 20 20 ns Rev. 1.0 Chiplus reserves the right to change product or specification without notice. High Speed Super Low Power SRAM 256K-Word By 8 Bit CS18LV20483 SWITCHING WAVEFORMS (WRITE CYCLE) 11 Rev. 1.0 Chiplus reserves the right to change product or specification without notice. High Speed Super Low Power SRAM 256K-Word By 8 Bit CS18LV20483 NOTES: 1. A write occurs during the overlap(tWP) of low /CE1, a high CE2 and low /WE. A write begins when /CE1 goes low, CE2 going high and /WE goes low. A write ends at the earliest transition when /CE1 goes high , CE2 goes high an /WE goes high. The tWP is measured from the beginning of the write to the end of write. 2. tCW is measured from the /CE1 going low or CE2 going low to end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end or write to the address change. TWR applied in case a write ends as /CE1 or /WE going high or CE2 going low. ORDER INFORMATION 12 Rev. 1.0 Chiplus reserves the right to change product or specification without notice.