TI1 CRCW08051471F 100v current mode pwm controller Datasheet

SM74202
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SNOSBA4A – NOVEMBER 2011 – REVISED APRIL 2013
100V Current Mode PWM Controller
Check for Samples: SM74202
FEATURES
DESCRIPTION
•
•
•
•
•
•
•
•
The SM74202 high voltage pulse-width-modulation
(PWM) controller contains all of the features needed
to implement single ended primary power converter
topologies. Output voltage regulation is based on
current-mode control, which eases the design of loop
compensation while providing inherent line feedforward. The SM74202 includes a high-voltage startup regulator that operates over a wide input range up
to 100V. The PWM controller is designed for high
speed capability including an oscillator frequency
range to 1MHz and total propagation delays less than
100ns. Additional features include an error amplifier,
precision reference, line under-voltage lockout, cycleby-cycle current limit, slope compensation, softstart,
oscillator synchronization capability and thermal
shutdown. The controller is available in the MSOP-10
package.
1
2
•
•
•
•
Renewable Energy Grade
Internal Start-up Bias Regulator
Error Amplifier
Precision Voltage Reference
Programmable Softstart
1A Peak Gate Driver
Maximum Duty Cycle Limiting (50%)
Programmable Line Under Voltage Lockout
(UVLO) with Adjustable Hysteresis
Cycle-by-Cycle Over-Current Protection
Programmable Oscillator Frequency with
Synchronization Capability
Current Sense Leading Edge Blanking
Thermal Shutdown Protection
APPLICATIONS
•
•
•
•
Photovoltaic
Telecommunication Power Converters
Industrial Power Converters
+42V Automotive Systems
Typical Application Circuit
VIN
VIN
VOUT
VCC
UVLO
SM74202
SS
OUT
CS
RT/ SYNC
FB
GND
COMP
COMPENSATION
Figure 1. Non-Isolated Flyback Converter
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011–2013, Texas Instruments Incorporated
SM74202
SNOSBA4A – NOVEMBER 2011 – REVISED APRIL 2013
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Connection Diagram
1
10
2
9
3
8
4
7
5
6
VIN
FB
SS
RT/SYNC
CS
COMP
UVLO
VCC
OUT
GND
Figure 2. 10-Lead VSSOP, WSON
Package Number DGS0010A
Top View
PIN DESCRIPTIONS
Pin
Name
Description
Application Information
1
VIN
Source Input Voltage
Input to the start-up regulator. Input range is 13V to 100V.
2
FB
Feedback Signal
Inverting input of the internal error amplifier. The noninverting input is internally connected to a 1.25V reference.
3
COMP
The output of the error amplifier and input to the
Pulse Width Modulator
COMP pull-up is provided by an internal 5K resistor which
may be used to bias an opto-coupler transistor.
4
VCC
Output of the internal high voltage series pass
regulator. Regulated output voltage is 7.7V
If an auxiliary winding raises the voltage on this pin above
the regulation set point, the internal series pass regulator
will shut down, reducing the internal power dissipation.
5
OUT
Output of the PWM controller
Gate driver output with a 1A peak current capability.
6
GND
Ground return
7
UVLO
Line Under-Voltage Shutdown
An external resistor divider from the power converter
source voltage sets the shutdown levels. The threshold at
this pin is 1.25V. Hysteresis is set by a switched internal
20µA current source.
8
CS
Current Sense input
Current sense input for current mode control and overcurrent protection. Current limiting is accomplished using a
dedicated current sense comparator. If the CS pin voltage
exceeds 0.5V the OUT pin switches low for cycle-by-cycle
current limiting. CS is held low for 50ns after OUT switches
high to blank leading edge current spikes.
9
RT / SYNC
Oscillator timing resistor pin and synchronization
input
An external resistor connected from RT to GND sets the
oscillator frequency. This pin also accepts synchronization
pulses from an external clock.
10
SS
Softstart Input
An external capacitor and an internal 10µA current source
set the soft-start ramp rate.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
2
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Absolute Maximum Ratings
(1) (2)
VIN to GND
-0.3V to 100V
VCC to GND
-0.3V to 16V
All other pins to GND
-0.3V to 7V
Power Dissipation
Internally Limited
ESD Rating (3)
Human Body Model
2kV
Storage Temperature
-65°C to +150°C
Junction Temperature
150°C
(1)
Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which
operation of the device is intended to be functional. For ensured specifications and test conditions, see the Electrical Characteristics.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
The human body model is a 100 pF capacitor discharged through a 1.5kΩ resistor.
(2)
(3)
Operating Ratings
VIN Voltage
13V to 90V
External Voltage applied to VCC
8V to 15V
Operating Junction Temperature
-40°C to +125°C
Electrical Characteristics
Specifications in standard type face are for TJ= +25°C and those in boldface type apply over the full operating junction
temperature range. Unless otherwise specified: VIN = 48V, VCC = 10V, and RT = 31.6kΩ. (1)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
7.4
7.7
8.0
V
Startup Regulator
VCCReg
VCC Regulation
VCC Current Limit
VCC = Open
(2)
15
22
mA
I-VIN
Startup Regulator Leakage
VIN = 100V
150
500
µA
IIN
Shutdown Current
VUVLO = 0V, VCC = open
250
350
µA
VCC Supply
ICC
VCC UVLO (Rising)
VccReg
- 300mV
VccReg 100mV
VCC UVLO (Falling)
5.3
6.0
6.7
V
2
3
mA
Supply Current
Cload = 0
V
Error Amplifier
GBW
Gain Bandwidth
4
DC Gain
MHz
75
Reference Voltage
FB = COMP
COMP Sink Capability
FB = 1.5V COMP= 1V
1.225
1.25
5
17
dB
1.275
V
mA
UVLO Pin
Shutdown Threshold
1.25
Undervoltage Shutdown Hysteresis
Current Source
16
20
V
24
µA
Current Limit
ILIM Delay to Output
(1)
(2)
CS step from 0 to 0.6V
Time to onset of OUT
Transition (90%)
30
ns
Cycle by Cycle CS Threshold
Voltage
0.5
V
Leading Edge Blanking Time
50
ns
Limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlation using Statistical
Quality Control (SQC) methods. The limits are used to calculate TI's Average Outgoing Quality Level (AOQL).
Device thermal limitations may limit usable range.
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Electrical Characteristics (continued)
Specifications in standard type face are for TJ= +25°C and those in boldface type apply over the full operating junction
temperature range. Unless otherwise specified: VIN = 48V, VCC = 10V, and RT = 31.6kΩ. (1)
Symbol
Parameter
Conditions
Min
CS Sink Impedance (clocked)
Typ
Max
Units
Ω
35
Soft Start
Softstart Current Source
7
10
13
µA
Softstart to COMP Offset
0.35
0.55
0.75
V
Oscillator
Frequency1 (RT = 31.6k)
(3)
175
200
225
kHz
Frequency2 (RT = 9.76k)
(3)
560
630
700
kHz
2.4
3.2
3.8
V
Sync threshold
PWM Comparator
Delay to Output
COMP set to 2V,
CS stepped 0 to 0.4V,
Time to onset of OUT
transition low
Min Duty Cycle
COMP=0V
25
0
Max Duty Cycle
50
COMP to PWM Comparator Gain
%
%
0.33
COMP Open Circuit Voltage
COMP Short Circuit Current
ns
COMP=0V
4.3
5.2
6.1
V
0.6
1.1
1.5
mA
V
Output Section
Output High Saturation
Iout = 50mA, VCC - VOUT
0.25
0.75
Output Low Saturation
IOUT = 100mA, VOUT
0.25
0.75
Rise Time
Cload = 1nF
18
ns
Fall Time
Cload = 1nF
15
ns
Thermal Shutdown Temp.
165
°C
Thermal Shutdown Hysteresis
25
°C
V
Thermal Shutdown
Tsd
(3)
4
Specification applies to the oscillator frequency. The operational frequency of the SM74202 is divided by two.
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Typical Performance Characteristics
Unless otherwise specified: TJ = 25°C.
VCC and VIN
vs
VIN
VCC
vs
ICC (VIN = 48V)
20
9
18
8
16
7
14
6
VCC (V)
VCC (V)
12
10
5
8
4
6
3
4
2
2
1
0
0
0
5
10
20
10
15
20
25
ICC (mA)
VIN (V)
Figure 3.
Figure 4.
Oscillator Frequency
vs
RT (Note 5)
Oscillator Frequency
vs
Temperature
RT = 31.6kΩ (Note 5)
210
1.00E+06
FREQUENCY (kHz)
1.00E+05
200
195
190
1.00E+04
1
10
-40
100
10
Figure 5.
_
50
13.0
GAIN (dB)
11.8
10.6
9.4
8.2
Error Amp. Gain/Phase Plot
225
_
40
180
_
30
135
_
20
90
_
10
45
_0
0
_
-10
-45
_
-20
-90
_
-30
-135
-180
-40
_
7.0
-40
10
110
Figure 6.
Soft Start Current
vs
Temperature
CURRENT (PA)
60
TEMPERATURE (oC)
RT (k:)
-50
_
10k
110
60
o
TEMPERATURE ( C)
PHASE (o)
FREQUENCY (Hz)
205
100k
1M
-225
10M
FREQUENCY (Hz)
Figure 7.
Figure 8.
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Block Diagram
7.7V SERIES
REGULATOR
VCC
VIN
REFERENCE
ENABLE
5V
1.25V
UVLO
+
-
LOGIC
1.25V
UVLO
HYSTERESIS
(20 PA)
RT/SYNC
CLK
OSC
VCC
DRIVER
OUT
Max Duty Limit
SM74202 (50%)
S
Q
R
Q
5V
COMP
1.25V
5k
2R
FB
GND
PWM
+
-
LOGIC
1.4V
R
SS
SS
CS
0.5V
2k
+
-
10 PA
SS
CLK + LEB
6
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DETAILED OPERATING DESCRIPTION
The SM74202 High Voltage PWM controller contains all of the features needed to implement single ended
primary power converter topologies. The SM74202 includes a high-voltage startup regulator that operates over a
wide input range to 100V. The PWM controller is designed for high speed capability including an oscillator
frequency range to 1MHz and total propagation delays less than 100ns. Additional features include an error
amplifier, precision reference, line under-voltage lockout, cycle-by-cycle current limit, softstart, oscillator sync
capability and thermal shutdown. The functional block diagram of theSM74202 is shown in the Block Diagram.
The SM74202 is designed for current-mode control power converters, which require a single drive output, such
as Flyback and Forward topologies. The SM74202 provides all of the advantages of current-mode control
including line feed-forward, cycle-by-cycle current limiting and simplified loop compensation .
High Voltage Start-Up Regulator
The SM74202 contains an internal high voltage startup regulator, that allows the input pin (Vin) to be connected
directly to line voltages as high as 100V. The regulator output is internally current limited to 15mA. When power
is applied, the regulator is enabled and sources current into an external capacitor connected to the VCC pin. The
recommended capacitance range for the Vcc regulator is 0.1µF to 100µF. When the voltage on the VCC pin
reaches the regulation level of 7.7V, the controller output is enabled. The controller will remain enabled until VCC
falls below 6V.
In typical applications, a transformer auxiliary winding is connected through a diode to the VCC pin. This winding
should raise the VCC voltage above 8V to shut off the internal startup regulator. Powering VCC from an auxiliary
winding improves conversion efficiency while reducing the power dissipated in the controller. The external VCC
capacitor must be selected such that the capacitor maintains the Vcc voltage greater than the VCC UVLO falling
threshold (6V) during the initial start-up. During a fault condition when the converter auxiliary winding is inactive,
external current draw on the VCC line should be limited such that the power dissipated in the start-up regulator
does not exceed the maximum power dissipation capability of the controller.
An external start-up or other bias rail can be used instead of the internal start-up regulator by connecting the VCC
and the Vin pins together and feeding the external bias voltage (8-15V) to the two pins.
Line Under Voltage Detector
The SM74202 contains a line Under Voltage Lock Out (UVLO) circuit. An external set-point voltage divider from
Vin to GND sets the operational range of the converter. The resistor divider must be designed such that the
voltage at the UVLO pin is greater than 1.25V when Vin is in the desired operating range. If the under voltage
threshold is not met, all functions of the controller are disabled and the controller remains in a low power standby
state.
UVLO hysteresis is accomplished with an internal 20µA current source that is switched on or off into the
impedance of the set-point divider. When the UVLO threshold is exceeded, the current source is activated to
instantly raise the voltage at the UVLO pin. When the UVLO pin voltage falls below the 1.25V threshold the
current source is turned off, causing the voltage at the UVLO pin to fall. The UVLO pin can also be used to
implement a remote enable / disable function. If an external transistor pulls the UVLO pin below the 1.25V
threshold, the converter is disabled.
Error Amplifier
An internal high gain error amplifier is provided within the SM74202. The amplifier's non-inverting input is
internally set to a fixed reference voltage of 1.25V. The inverting input is connected to the FB pin. In non-isolated
applications, the power converter output is connected to the FB pin via voltage scaling resistors. Loop
compensation components are connected between the COMP and FB pins. For most isolated applications the
error amplifier function is implemented on the secondary side of the converter and the internal error amplifier is
not used. The internal error amplifier is configured as an open drain output and can be disabled by connecting
the FB pin to ground. An internal 5K pull-up resistor between a 5V reference and COMP can be used as the pullup for an optocoupler in isolated applications.
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Current Limit/Current Sense
The SM74202 provides a cycle-by-cycle over current protection function. Current limit is accomplished by an
internal current sense comparator. If the voltage at the current sense comparator input exceeds 0.5V, the output
is immediately terminated. A small RC filter, located near the controller, is recommended to filter noise from the
current sense signal. The CS input has an internal MOSFET which discharges the CS pin capacitance at the
conclusion of every cycle. The discharge device remains on an additional 50ns after the beginning of the new
cycle to attenuate the leading edge spike on the current sense signal.
The SM74202 current sense and PWM comparators are very fast, and may respond to short duration noise
pulses. Layout considerations are critical for the current sense filter and sense resistor. The capacitor associated
with the CS filter must be located very close to the SM74202 and connected directly to the pins of the controller
(CS and GND). If a current sense transformer is used, both leads of the transformer secondary should be routed
to the sense resistor and the current sense filter network. A sense resistor located in the source of the primary
power MOSFET may be used for current sensing, but a low inductance resistor is required. When designing with
a current sense resistor all of the noise sensitive low power ground connections should be connected together
local to the controller and a single connection should be made to the high current power ground (sense resistor
ground point).
Oscillator and Sync Capability
A single external resistor connected between the RT and GND pins sets the SM74202 oscillator frequency.
Internal to the device is an oscillator divide by two circuit. This divide by two circuit creates an exact 50% duty
cycle limit function. Because of this, the internal oscillator actually operates at twice the frequency of the output
(OUT). To set a desired output operational frequency (F), the RT resistor can be calculated from:
1
RT =
F x 158 x 10-12
(1)
The SM74202 can also be synchronized to an external clock. The external clock must have a higher frequency
than the free running oscillator frequency set by the RT resistor. The clock signal should be capacitively coupled
into the RT pin through a 100pF capacitor. A peak voltage level greater than 3.7 Volts at the RT pin is required
for detection of the sync pulse. The sync pulse width should be set between 15 to 150ns by the external
components. The RT resistor is always required, whether the oscillator is free running or externally synchronized.
The voltage at the RT pin is internally regulated at 2 Volts. The RT resistor should be located very close to the
device and connected directly to the pins of the controller (RT and GND).
PWM Comparator
The PWM comparator compares the current ramp signal with the loop error voltage derived from the error
amplifier output. The error amplifier output voltage at the COMP pin is offset by 1.4V and then further attenuated
by a 3:1 resistor divider. The PWM comparator polarity is such that 0 Volts on the COMP pin will result in a zero
duty cycle at the controller output.
Soft Start
The softstart feature allows the power converter to gradually reach the initial steady state operating point, thereby
reducing start-up stresses and current surges. At power on, after the VCC and the line undervoltage lockout
thresholds are satisfied, an internal 10µA current source charges an external capacitor connected to the SS pin.
The capacitor voltage will ramp up slowly and will limit the COMP pin voltage and the duty cycle of the output
pulses.
Gate Driver and Maximum Duty Cycle Limit
The SM74202 provides an internal gate driver (OUT), which can source and sink a peak current of 1 Amp. The
maximum output duty cycle is precisely equal to 50%. The maximum duty cycle function is accomplished with an
internal toggle flip-flop which ensures an accurate duty cycle limit. The internal oscillator frequency is therefore
twice the operating frequency of the PWM controller (OUT pin).
8
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Thermal Protection
Internal thermal shutdown circuitry is provided to protect the integrated circuit in the event the maximum junction
temperature is exceeded. This feature prevents catastrophic failures from accidental device overheating. When
activated, typically at 165 degrees Celsius, the controller is forced into a low power standby state, disabling the
output driver and the bias regulator. After the temperature is reduced (typical hysteresis = 25°C) the VCC
regulator is enabled and a softstart sequence initiated.
Typical Application Circuit: 36V - 75 VIN and 3.3V, 4.5A OUT
C9
R10
R13
T1
V+
J1
30-75V IN
1
J2
+3.3V
2
C12
470 pF
D2
CMPD2838E
20
0.1 PF
10, 1W
1
C13
100 PF
GND
D3
MBRD835L
2
R2
61.9k
R1
10
C4
0.1 PF
Shutdown
R3
2.87k
GND
C10
4.7 PF
1
7
VIN
VCC
UVLO
OUT
3
R5
15.0k
C6
220 pF
COMP
CS
FB
9 RT/
10 SYNC
GND
SS
C8
100 pF
R6
12.4k
GND
Q1
Si7898DP
R11
2.43k
4
5
R12
1.47k
R7
8
2
100
6
R8
0.47
R9
0.47
GND
C11
1000 pF
SM74202
C5
0.01 PF
C7
3300 pF
D1
CMPD2838E
GND GND
U1
R4
1.00k
GND
SYNC
Input
GND
GND
GND
C3
0.01 PF
GND
Z1
GND
1SMB5936B
5
6
7
8
GND
C2
2.2 PF
OUT RTN
4
3
2
1
C1
2.2 PF
GND
C15
270 PF
GND
GND
GND
C14
100 PF
GND
GND
GND
GND
Bill Of Materials
ITEM
PART NUMBER
DESCRIPTION
VALUE
C
1
C4532X7R2A225M
CAPACITOR, CER, TDK
2.2µF, 100V
C
2
C4532X7R2A225M
CAPACITOR, CER, TDK
2.2µF, 100V
C
3
C2012X7R1H103K
CAPACITOR, CER, TDK
0.01µF, 50V
C
4
C3216X7R2A104K
CAPACITOR, CER, TDK
0.1µF, 100V
C
5
C2012X7R1H103K
CAPACITOR, CER, TDK
0.01µF, 50V
C
6
C2012C0G1H221J
CAPACITOR, CER, KEMET
220pF, 50V
C
7
C2012C0G1H332J
CAPACITOR, CER, TDK
3300pF, 50V
C
8
C2012C0G1H101J
CAPACITOR, CER, TDK
100pF, 50V
C
9
C2012X7R1H104K
CAPACITOR, CER, TDK
0.1µF, 50V
C
10
C3216X7R1C475K
CAPACITOR, CER, TDK
4.7µF, 16V
C
11
C2012C0G1H102J
CAPACITOR, CER, TDK
1000pF, 50V
C
12
C2012C0G1H471J
CAPACITOR, CER, TDK
470p, 50V
C
13
C4532X7S0G107M
CAPACITOR, CER, TDK
100µF, 4V
C
14
C4532X7S0G107M
CAPACITOR, CER, TDK
100µF, 4V
C
15
A700X277M0004AT
CAPACITOR, ALUM ORGANIC, KEMET
270µF, 4V
D
1
CMPD2838E-NSA
DIODE, SIGNAL, CENTRAL
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ITEM
10
www.ti.com
PART NUMBER
DESCRIPTION
VALUE
D
2
CMPD2838E-NSA
DIODE, SIGNAL, CENTRAL
D
3
MBRD835L
DIODE, RECTIFIER, ON
SEMICONDUCTOR
J
1
MKDS 1/2-3.81
TERM BLK, MINI, 2 POS, PHOENIX
CONTACT
J
2
MKDS 1/2-3.81
TERM BLK, MINI, 2 POS, PHOENIX
CONTACT
Q
1
SI7898DP
FET, SILICONIX
150V, 85mΩ
R
1
CRCW120610R0F
RESISTOR
10
R
2
CRCW12066192F
RESISTOR
61.9kΩ
R
3
CRCW08052871F
RESISTOR
2.87kΩ
R
4
CRCW08051001F
RESISTOR
1.00kΩ
R
5
CRCW08051502F
RESISTOR
15.0kΩ
R
6
CRCW08051242F
RESISTOR
12.4kΩ
R
7
CRCW08051000F
RESISTOR
100
R
8
CRCW12060R47F
RESISTOR
0.47
R
9
CRCW12060R47F
RESISTOR
0.47
R
10
CRCW251210R0F
RESISTOR
10, 1W
R
11
CRCW08052431F
RESISTOR
2.43K
R
12
CRCW08051471F
RESISTOR
1.47K
R
13
CRCW080520R0F
RESISTOR
20
T
1
B0695-A COILCRAFT
TRANSFORMER, FLYBACK, EFD20 CORE
T
1
PA0751 PULSE
TRANSFORMER, FLYBACK, EFD20 CORE
U
1
SM74202MM-2
CONTROLLER, SINGLE OUT, PWM, TI
Z
1
1SMB5936B
DIODE, ZENER, SMB, 30V
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ALTERNATE
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REVISION HISTORY
Changes from Original (April 2013) to Revision A
•
Page
Changed layout of National Data Sheet to TI format ............................................................................................................ 9
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