e5530 128-Bit IDIC for Radio Frequency Identification via an internal load. This damping-in-turn can be detected by the interrogator. The identifying data are stored in a 128 bit PROM on the e5530, realized as an array of laserprogrammable fuses. The logic block diagram for the e5530 is shown in figure 2. The data are output bitserially as a code of length 128, 96, 64 or 32 bits. The chips are factory-programmed with a unique code. Description The e5530 is part of a closed coupled identification system. It receives power from an RF transmitter which is coupled inductively to the IDIC. The frequency is typically 100 to 450 kHz. Receiving RF, the IDIC responds with a data stream by damping the incoming RF Features Bitrate [bit/s]: D Low power, low voltage CMOS D Rectifier, voltage limiter, clock extraction RF/8,RF/16, RF/32, RF/40, RF/50, RF/64, RF/80, RF/100, RF/128, RF/256 FSK, PSK, BIPH, Manchester BIPH-FSK Modulation: on-chip (no battery) D Small size Application D Factory laser programmable ROM D Operating temperature range –40 to +125°C RF transmitter and interrogator D Radio Frequency (RF): 100 to 450 kHz IDIC e5530 RF D Transmission options 95 10318 Code length: 128, 96, 64, 32 bits Figure 1. Application Analog front end Load 95 10155 Mod Modulator FSK PSK BIPH Manchester Data Clk R7 R6 R5 R4 R3 R2 R1 R0 128 bit PROM C15 C14 C13 C12 C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 C0 Clock extractor Row decoder Coil Coil VDD Bitrate A6 A5 A4 A3 Rectifier A2 A1 A0 Column decoder Counter VSS Figure 2. Block diagram IDIC stands for IDentification Integrated Circuit and is a trademark of TEMIC. Rev. A3, 17-Sep-98 1 (5) e5530 Ordering Information Extended Type Number Package e5530H-232-DOW e5530H-232-DIT e5530H-232-S8 e5530H-zzz-DOW * e5530H-zzz-DIT * e5530H-zzz-S8 * DOW DIT SO8 DOW DIT SO8 * Checksum Header IP Code no checksum E6 fixed and unique code SPQ (Minimum Volume) 10 kpcs 10 kpcs 1120 defined by customer Minimum Order Volume 10 kpcs 10 kpcs 1120 > 600 kpcs p.a. > 600 kpcs p.a. > 400 kpcs p.a. 1) Definition of customized part number basing on orders for first year volume (300 kpcs) 2) Definition of header, ID code, checksum etc. according to customers data base 3) 8.000 US$ initial cost for metal mask 4) Lead time 5 month 5) Low volume customized application can be covered by TK5550F–PP programming. With identical features of TK5530H–zzz–pPP possible Chip Dimensions Functional Description Read Operation 0.175 mm e5530 1.17 mm 0.447 mm Coil 1 Coil 2 Pad: 150 m x 150 m (Metal: 99% Al, 1% Si) Padwindow: 138 m x 138 m 1.62 mm 13368 Figure 3. Chip size Pads ÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ Name Coil1 Coil2 Pad Window Function 138 138 mm2 1st coil pad 138 138 mm2 2nd coil pad Coil 2 1 8 2 7 Coil 1 e5530 3 4 Once the IC detects the incoming RF, the IC repetively reads out the code data as long as the RF signal is applied. The transition from the last bit to bit 1 of the next sequence occurs without interruption. Data is transmitted by alternating damping of the incoming RF via a load. Different kinds of modulation and bitrates are optionally available. Rectifier For internal power supply, an on-chip bridge rectifier is used which consists of two diodes and two n-channel transistors. A Zener diode, which protects the circuit against overvoltage on the coil inputs, and a smoothing capacitor for the internal supply are also provided. Damping Load Incoming RF will be damped by the power consumption of the IC itself and by an internal load, which is controlled by the modulator. The loads are p-channel transistors connected between VDD and the coil inputs. The layout includes metal mask options for the load circuit: single-side, double-side and alternate-side modulation. Modulator 6 One of four methods of modulation can be selected by fuses. The timing diagram is shown in figure 5. 5 FSK Note: Pins 2 to 7 have to be open. They are not specified for applications Figure 4. Pinning SO8 2 (5) 13367 Logical “1” and “0” are distinguished via different frequencies of damping. The frequency for “1” is the RF divided by 10, a “0” divides by 8. Rev. A3, 17-Sep-98 e5530 PSK Manchester A logical “1” causes (at the end of the bit period) a 180° phase shift on the carrier frequency, while a logical “0” causes no phase shift. The carrier frequency is RF/2. A logical “1” causes a positive edge in the middle of a bit period, while a logical “0” causes negative edge. BIPH Logical “1” produces a signal which is the same as the bitclock and a logical “0” produces a signal of twice the bitclock period. A combination of BIPH- and FSK-modulation is also optionally available. The available combinations between the modulation types and the bitrates are shown in table “Transmission Options”. DataClk Data 1 0 1 1 0 0 1 FSK PSK Man Biph 95 10278 Figure 5. Timing diagram for modulation options Absolute Maximum Ratings Parameters Maximum current into Coil1 and Coil2 Maximum power dissipation (dice) Maximum ambient air temperature with voltage applied Storage temperature * Symbol Icoil Ptot Tamb Tstg Value 10 100 –40 to +125 –65 to +150 Unit mA mW* °C °C Free-air condition. Time of application: 1 s Stresses above those listed under ‘Absolute Maximum Ratings’ may cause permanent damage to the device. Functional operation of the device at these conditions is not imlied. Rev. A3, 17-Sep-98 3 (5) e5530 Operating Characteristics Tamb = 25°C, reference terminal is VDD, operating voltage VDD – VSS = 3 V dc, unless otherwise specified Parameters Operating voltage Operating temperature Input frequency (RF) Operating current Test Conditions / Pins Condition for logic test fCLK = 125 kHz, VSS = –2 V I = 4 mA Clamp voltage * Symbol VSS Tamb fCLK ICC Min. –1.5 –40 100 VCL 6.7 Typ. * Max. –5.0 125 450 Unit V °C kHz mA 10 V 3 Typical parameters represent the statistical mean values Transmission Options Modulation Carrier Frequency (CF) RF/8, RF/10 FSK PSK BIPH Bitrate [bit/s] RF/32, RF/40, RF/50, RF/64, RF/80, RF/100, RF/128 CF/4, 8, 16, 32 RF/8, RF/16, RF/32, RF/64, RF/100, RF/128 RF/8, RF/16, RF/32, RF/64, RF/100, RF/128 RF/2 Manchester IDD 100 VDD = Vpp Coil ≅ 1.5 V Figure 6. Measurement setup for IDD Mod 2V Coil 2 Coil 2 VSS 4 (5) ~2V Coil 1 Coil 1 ~ W 100 W ~2V 96 12304 96 12303 Figure 7. Simplified damping circuit Rev. A3, 17-Sep-98 e5530 Application Example From oscillator IAC 740 mH 4.05 mH 390 pF Input capacitance 5 pF static, 4 pF dynamic Energy 125 kHz Coil1 (Pin 8) e5530 (SO8) Coil2 (Pin 1) Data To read amplifier 2.2 nF fres + 2p Ǹ1LC + 125 kHz 13369 Figure 8. Typical application circuit Package Information Package SO8 Dimensions in mm 5.2 4.8 5.00 4.85 3.7 1.4 0.25 0.10 0.4 1.27 6.15 5.85 3.81 8 0.2 3.8 5 technical drawings according to DIN specifications 13034 1 4 We reserve the right to make changes to improve technical design and may do so without further notice. Parameters can vary in different applications. All operating parameters must be validated for each customer application by the customer. Should the buyer use TEMIC products for any unintended or unauthorized application, the buyer shall indemnify TEMIC against all claims, costs, damages, and expenses, arising out of, directly or indirectly, any claim of personal damage, injury or death associated with such unintended or unauthorized use. TEMIC Semiconductor GmbH, P.O.B. 3535, D-74025 Heilbronn, Germany Telephone: 49 ( 0 ) 7131 67 2594, Fax number: 49 ( 0 ) 7131 67 2423 Rev. A3, 17-Sep-98 5 (5)