Anpec APW7060 Dual controllers - step down synchronous pwm and linear controller Datasheet

APW7060
Dual Controllers - Step Down Synchronous PWM and Linear Controller
Features
General Description
• Provides Two Regulated Voltages
- One Synchronous DC/DC Buck Controller
The APW7060 integrates a synchronous buck PWM
controller and a linear controller to provide two regulated voltages in a single package. The PWM controller drives external N-channel MOSFETs and operates
at a fixed 600kHz frequency. When the input supply
drops close to the output, the upper MOSFET remains
on, achieving 100% duty cycle. Internal loop compensation is optimized for fast transient response, eliminating external compensation network. The linear controller drives an external N-channel MOSFET to form a
linear regulator. The internal 0.8V reference makes this
part suitable for a wide variety of low voltage
applications.
The APW7060 has an undervoltage lockout circuitry
to ensures that both the 5VCC and 12VCC must be
present before its internal circuitry is power up. Soft
start is internally set to 2ms and will bring both outputs into regulation in a controlled manner. When either output goes into short, soft start will be initiated.
If the short condition still remains after three cycles,
both regulators will be shut down. To restart both
regulators, recycle the voltage at 5VCC or 12VCC pin
or momentarily pull the FB2 pin above 1.28V.
The APW7060 can be shutdown by pulling the FB2
pin above 1.28V. In shutdown, all gate drive signals
will be low. This dual controller is available in SO-14
package.
- One Linear Controller
• 0.8V Internal Reference Voltage
- Both Controllers: 0.8V ± 2% Line, Load
and Temp.
• Output Voltage Range
- PWM Controller : 0.8V to VIN
- Linear Controller : 0.8V to (12VCC-VGSpass)
• Full Duty Cycle Range for PWM Controller
- 0% to 100%
• Internal Loop Compensation for PWM Controller
• Internal 2ms Soft Start and Short Circuit Protec
tion for both Controllers
• Both Controllers Drive N-Channel MOSFETs
• Small Converter Size
- 600kHz Constant Switching Frequency
- Simple SO-14 Package
• Shutdown Control
Applications
•
•
•
•
•
Motherboard
Pinouts
Graphics Cards
12V, 5V and 3.3V Inputs DC-DC Converter
DSP Supplies
Embedded processor and I/O supplies
LGATE
1
14
UGATE
GND
2
13
12VCC
GND
3
12
NC
5VCC
4
11
NC
DRIVE2
5
10
NC
FB2
6
9
FB
NC
7
8
NC
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise
customers to obtain the latest version of relevant information to verify before placing orders.
Copyright  ANPEC Electronics Corp.
Rev. A.3 - Oct., 2003
1
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APW7060
Ordering and Marking Information
APW 7060
P ackage C ode
K : S O P -1 4
O p e ra tin g J u n c tio n T e m p . R a n g e
C : 0 to 7 0 ° C
H a n d lin g C o d e
TU : Tube
TR : Tape & R eel
H a n d lin g C o d e
Tem p. R ange
P a ck ag e C o d e
A P W 7060
XXXXX
A P W 7060 K :
X X X X X - D a te C o d e
Block Diagram
12VCC
5VCC
UGATE
Under
Voltage
Lockout
PW M
UVLO
0.5V
Gate
Control
Soft-Start
and Fault
Logic
UVP1
5VC C
LGATE
Inhibit /
Soft-Start
FB2
UVP2
C O MP
FB
0.5V
12VC C
Error
Am plifier
VREF
0.8V
Shutdown
Oscillator
F O SC
600kH z
1.28V
Linear
C ontroller
DRIVE2
GND
.ECKH/Figure 1.
Copyright  ANPEC Electronics Corp.
Rev. A.3 - Oct., 2003
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APW7060
Typical Application
R4
+12 V
+5V
C8
1uF
VIN 2
+3.3V
VIN 1
+3.3V
4
13
C1
1uF
L2
1uH
2. 2
C4
4. 7uF
5VC C
12VC C
C 2, C 3
2 x 470uF
Q1
C 10
Q3
470uF
UGATE
5
L1
1uH
14
D R IVE2
R 10
6. 8k
D1
1
C 5, C 6
2 x 470uF
LGA TE
U1
AP W 7060
C9
Q2
VOU T1
+1.26 3 V
/10 A
R1
590
470pF
9
FB
VOU T2
+2.5V/3A
6
R7
2. 37k
C 11
470uF
FB2
R8
1. 13k
GN D
GN D
3
2
R2
1. 02k
C7
68nF
Q1 : APM2014N UC
Q2 : APM2014N UC
Q3 : APM2055N UC
D1 : 3A Schottky Diode
C2, C3, C5, C6, C10, C11 : 470uF/6.3V, ESR=30mΩ
.ECKH/Figure 2.
Absolute Maximum Ratings
Symbol
Parameter
Rating
Unit
5V CC
5VCC Supply Voltage (5VCC to GND)
-0.3 ~ 7
V
12V CC
12VCC Supply Voltage (12VCC to GND)
-0.3 ~ 15
V
UAGTE, DRIVE2 to GND
-0.3 ~ 12V CC
V
LGATE, FB, FB2 to GND
-0.3 ~ 5V CC
Maximum Junction Temperature
T STG
Storage Temperature
V
150
o
C
-65 ~ 150
o
C
o
C
T SDR
Maximum Soldering Temperature, 10 Seconds
300
V ESD
Minimum ESD Rating (Human body model)
±2
KV
Thermal Characteristics
Symbol
θJA
Parameter
Value
Junction-to-Ambient Resistance in free air (SOP-14)
Copyright  ANPEC Electronics Corp.
Rev. A.3 - Oct., 2003
3
160
Unit
o
C/W
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APW7060
Recommended Operating Conditions
Symbol
(Note)
Parameter
Range
Unit
5 ± 5%
V
5V CC
5VCC Supply Voltage
12V CC
12VCC Supply Voltage
12 ± 10%
V
V OUT1
Output Voltage of the Buck converter
0.8 ~ 3.3
V
3.3/5 ± 5%
V
0.8 ~ 3.3
V
V IN1
V OUT2
V IN2
TA
TJ
Input Voltage of the Buck converter
Output Voltage of the Linear Regulator
3.3/5 ± 5%
Input Voltage of the Linear Regulator
Ambient Temperature
Junction Temperature
V
0 ~ 70
o
C
0 ~ 125
o
C
Note : Refer to the typical application circuit
Electrical Characteristics
Unless otherwise specified, these specifications apply over 5VCC=5V, 12VCC=12V and TA= 0~70 oC. Typical
values are at TA=25oC.
APW7060
Symbol
Parameter
Test Conditions
Min
Typ Max
Unit
SUPPLY CURRENT
ICC
5VCC Supply Current
LGATE Open, FB2=DRIVE2
2.5
mA
12VCC Supply Current
UGATE Open
2.5
mA
UNDER VOLTAGE LOCKOUT
Rising 5VCC Threshold
12VCC=12V
4.0
4.2
4.4
V
Falling 5VCC Threshold
12VCC=12V
3.5
3.7
3.9
V
Rising 12VCC Threshold
5VCC=5V
9.6
10.3 10.8
V
Falling 12VCC Threshold
5VCC=5V
9.3
9.7
10.2
V
550
600
650
kHz
OSCILLATOR
FOSC
∆VOSC
Free Running Frequency
Ramp Upper Threshold
2.85
V
Ramp Lower Threshold
0.95
V
Ramp Amplitude
1.9
VP-P
0.8
V
REFERENCE VOLTAGE
VREF
Reference Voltage
System Accuracy
Over Line, Load and
Temperature
-2
+2
%
Copyright  ANPEC Electronics Corp.
Rev. A.3 - Oct., 2003
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APW7060
Electrical Characteristics (Cont.)
Unless otherwise specified, these specifications apply over 5VCC=5V, 12VCC=12V and TA= 0~70 oC. Typical
values are at TA=25oC.
APW7060
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
BUILT-IN PWM FEEDBACK COMPENSATION
DC Gain
75
dB
FP
First Pole Frequency
10
Hz
FZ
First Zero Frequency
1
kHz
UGATE Duty Range
0
FB Input Current
100
%
0.1
µA
PWM CONTROLLER GATE DRIVERS
TD
UGATE Source
VUAGTE=1V
0.6
A
UGATE Sink
VUGATE=1V
7.3
Ω
LGATE Source
VLGATE=1V
0.6
A
LGATE Sink
VLGATE=1V
1.8
Ω
50
nS
78
1.6
1
dB
Dead Time
LINEAR CONTROLLER
DC Gain
Gain Bandwidth Product
CL=0.5nF
CL=1nF
FB Input Current
MHz
0.1
µA
DRIVE2 Source Current
VFB2=VREF-20mV, VDRIVE2=7V
9.8
mA
DRIVE2 Sink Current
VFB2=VREF+20mV, VDRIVE2=3V
2.6
mA
DRIVE2 Output High Voltage
DRIVE2 Open
11.7
V
DRIVE2 Output Low Voltage
DRIVE2 Open
0.01
V
FB or FB2 Falling
0.5
V
15
mV
2
mS
1.28
V
30
mV
UNDER-VOLTAGE PROTECTION
UVFB
FB/FB2 Under-Voltage Level
FB/FB2 Under-Voltage
Hysteresis
SOFT-START AND SHUTDOWN
T SS
Soft-Start Interval
FB2 Shutdown Threshold
FB2 Rising
FB2 Shutdown Hysteresis
Copyright  ANPEC Electronics Corp.
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APW7060
Functional Pin Description
LGATE (Pin 1)
NC (Pin 7, 8, 10, 11, 12)
No internal connection.
This pin provides the gate drive signal for the low side
MOSFET .
FB (Pin 9)
GND (Pin 2, 3)
Signal and power ground for the IC. All voltage levels
are measured with respect to this pin. Tie this pin to
the ground plane through the lowest impedance connection available.
This pin is the inverting input of the internal error amplifier of the buck controller. Connect this pin to the
output (VOUT1) of the DC/DC converter via a proper sized
resistor divider to form a complete feedback loop. The
VOUT1 is determined using the following formula :
R1
VOUT1=0.8V x (1+ R2 )
5VCC (Pin 4)
This is the main bias supply for the DC/DC controller
and its low side MOSFET driver. Must be closely
decoupled to GND (Pin 2,3). The voltage at this pin is
monitored for undervoltage lockout (UVLO) purposes.
DO NOT apply a voltage greater than 5.5V to this pin.
where R1 is the resistor connected from VOUT1 to FB,
and R2 is the resistor connected from FB to GND.
This pin is also monitored for under-voltage events.
12VCC (Pin 13)
This pin provides the supply voltage to the high side
MOSFET driver and the linear controller. A voltage no
greater than 13V can be connected to this pin. The
voltage at this pin is monitored for undervoltage lockout (UVLO) purposes.
DRIVE2 (Pin 5)
This pin provides the gate drive voltage for the linear
regulator N-channel MOSFET pass transistor. It also
provides a means of compensating the linear controller for applications where the user needs to optimize
the regulator transient response.
UGATE (Pin 14)
This pin provides gate drive for the high-side MOSFET.
FB2 (Pin 6)
Connect this pin to the output (VOUT2) of the linear
regulator via a proper sized resistor divider. The voltage at this pin is regulated to 0.8V and the VOUT2 is
determined using the following formula :
R7
VOUT2=0.8V x (1+ R8 )
where R7 is the resistor connected from VOUT2 to FB2,
and R8 is the resistor connected from FB2 to GND.
This pin is also monitored for under-voltage events.
Pulling and holding FB2 above 1.28V shuts down both
regulators. Releasing FB2 initiates soft-start on both
regulators.
Copyright  ANPEC Electronics Corp.
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APW7060
Typical Characteristics
Reference Voltage
vs. Junction Temperature
Switching Frequency
vs. Junction Temperature
650
Switching Frequency, FOSC (kHz)
Reference Voltage, VREF (V)
0.816
0.812
0.808
0.804
0.800
0.796
0.792
0.788
0.784
-50
-25
0
25
50
75
100
125
630
620
610
600
590
580
570
560
550
-50
150
-25
0
25
50
75
100
125
150
Junction Temperature (°C)
Junction Temperature (oC)
Copyright  ANPEC Electronics Corp.
Rev. A.3 - Oct., 2003
640
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APW7060
Operating Waveforms
(Refer to the typical application circuit)
1.VOUT1 Load Transient Response : IOUT = 0A -> 10A -> 0A
- IOUT1 slew rate = ±10A/µS
IOUT = 0A -> 10A
IOUT = 0A -> 10A -> 0A
IOUT = 10A -> 0A
VOUT1
VOUT1
VOUT1
VUGATE
VUGATE
10A
IOUT1
IOUT1
0A
Ch1 : VOUT1, 100mV/Div, DC,
Offset = 1.25V
Ch2 : VUGATE, 10V/Div, DC
Ax1 : IOUT1, 5A/Div
Time : 5µS/Div
BW = 20MHz
IOUT1
Ch1 : VOUT1, 100mV/Div, DC,
Offset = 1.25V
Ax1 : IOUT1, 5A/Div
Time : 100µS/Div
BW = 20MHz
Ch1 : VOUT1, 100mV/Div, DC,
Offset = 1.25V
Ch2 : VUGATE, 10V/Div, DC
Ax1 : IOUT1, 5A/Div
Time : 5µS/Div
BW = 20MHz
2.VOUT2 Load Transient Response : IOUT = 0.2A -> 3A -> 0.2A
- IOUT2 slew rate = ±3A/µS
IOUT = 0.2A -> 3A
IOUT = 0.2A -> 3A -> 0.2A
IOUT = 3A -> 0.2A
VOUT2
VOUT2
VOUT2
3A
IOUT2
IOUT2
0.2A
IOUT2
Ch1 : VOUT2, 50mV/Div, DC,
Offset = 2.50V
Ax1 : IOUT2, 1A/Div
Time : 1µS/Div
BW = 20MHz
Copyright  ANPEC Electronics Corp.
Rev. A.3 - Oct., 2003
Ch1 : VOUT2, 50mV/Div, DC,
Offset = 2.50V
Ax1 : IOUT2, 1A/Div
Time : 50µS/Div
BW = 20MHz
8
Ch1 : VOUT2, 50mV/Div, DC,
Offset = 2.50V
Ax1 : IOUT2, 1A/Div
Time : 1µS/Div
BW = 20MHz
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APW7060
Operating Waveforms (Cont.)
3. Powering ON / OFF
Soft-start at Powering ON
Powering OFF
+12V
+12V
+5V
+5V
VOUT2
VOUT2
VOUT1
VOUT1
Ch1 : +5V, 1V/Div, DC
Ch2 : +12V, 2V/Div, DC
Ch3 : VOUT1, 1V/Div, DC
Ch1 : +5V, 1V/Div, DC
Ch2 : +12V, 2V/Div, DC
Ch3 : VOUT1, 1V/Div, DC
Ch4 : VOUT2, 1V/Div, DC
Time : 5mS/Div
BW = 20MHz
Ch4 : VOUT2, 1V/Div, DC
Time : 1mS/Div
BW = 20MHz
4. UGATE and LGATE
UGATE Rising
UGATE Falling
IOUT=10A
IOUT=10A
VUGATE
VUGATE
VLGATE
VLGATE
Ch1 : VUGATE, 2V/Div, DC
Ch2 : VLGATE, 2V/Div, DC
Time : 50nS/Div
BW = 500MHz
Copyright  ANPEC Electronics Corp.
Rev. A.3 - Oct., 2003
Ch1 : VUGATE, 2V/Div, DC
Ch2 : VLGATE, 2V/Div, DC
Time : 50nS/Div
BW = 500MHz
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APW7060
Application Information
Soft Start
Soft start can be initiated in several ways. One way is
when the input bias supply to the 5VCC and 12VCC
is above 4.2V and 10.2V respectively. The other way
is when the part comes out of shutdown. In both ways,
the soft start cycle will last for 2ms. During this period,
the reference to the error amplifier of the PWM controller and linear controller will gradually slew up to its
final value of 0.8V. This effectively will force both output voltages to track this reference ramp rate. Hence
both outputs will reach regulation at the same time.
Figure 3 illustrates this graphically.
Maximum Output Voltage of Linear Controller
The maximum drive voltage at DRIVE2 is determined
by the applied voltage at 12VCC pin. Since this pin
drives an external N-channel pass MOSFET, therefore the maximum output voltage of the linear regulator is dependent upon the required gate-to-source voltage to sustain the load current.
VOUT2MAX = 12VCC - VGSpass
Component Selection Guidelines
PWM Regulator Output Capacitor
The selection of COUT is determined by the required
effective series resistance (ESR) and voltage rating
rather than the actual capacitance requirement. Therefore select high performance low ESR capacitors that
are intended for switching regulator applications. In
some applications, multiple capacitors have to be
paralled to achieve the desired ESR value. If tantalum
capacitors are used, make sure they are surge tested
by the manufactures. If in doubt, consult the capacitors manufacturer.
Soft-start at Powering ON
+12V
+5V
VOUT2
VOUT1
Ch1 : +5V, 1V/Div, DC
Ch2 : +12V, 2V/Div, DC
Ch3 : VOUT1, 1V/Div, DC
Ch4 : VOUT2, 1V/Div, DC
Time : 1mS/Div
BW = 20MHz
Input Capacitor Selection
The input capacitor is chosen based on the voltage
rating and the RMS current rating. For reliable
operation, select the capacitor voltage rating to be at
least 1.3 times higher than the maximum input voltage.
The maximum RMS current rating requirement is approximately IOUT/2 , where IOUT is the load current.
During power up, the input capacitors have to handle
large amount of surge current. If tantalum capacitors
are used, make sure they are surge tested by the
manufactures. If in doubt, consult the capacitors
manufacturer.
For high frequency decoupling, a ceramic capacitor
between 0.1uF to 1uF can be connected between
5VCC and ground pin.
.ECKH/Figure 3.
Linear Regulator Transient Response Optimization
The linear regulator is stable over all load current.
However, the transient response can be further enhanced by connecting a RC network between the FB2
and DRIVE2 pin. Depending on the output capacitance
and load current of the application, the value of this
RC network is then varied. A good starting point for
the resistor value is 6.8kΩ and 470pF for the capacitor.
Copyright  ANPEC Electronics Corp.
Rev. A.3 - Oct., 2003
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APW7060
Application Information
PUPPER = Iout2 (1+ TC)(RDS(ON))D + (0.5)(Iout)(VIN)(tsw)FS
Inductor Selection
The inductance of the inductor is determined by the
output voltage requirement. The larger the inductance,
the lower the inductor’s current ripple. This will translate into lower output ripple voltage. The ripple current
and ripple voltage can be approximated by:
IRIPPLE =
PLOWER = Iout2 (1+ TC)(RDS(ON))(1-D)
where IOUT is the load current
TC is the temperature dependency of RDS(ON)
FS is the switching frequency
tsw is the switching interval
D is the duty cycle
V OUT
VIN - VOUT
×
Fs× L V IN
Note that both MOSFETs have conduction losses while
the upper MOSFET include an additional transition
loss.The switching internal, tsw, is a function of the
∆VOUT = IRIPPLE x ESR
where Fs is the switching frequency of the regulator.
reverse transfer capacitance CRSS. Figure 4 illustrates
the switching waveform of the MOSFET.
The (1+TC) term is to factor in the temperature dependency of the RDS(ON) and can be extracted from the
“RDS(ON) vs Temperature” curve of the power MOSFET.
There is a tradeoff exists between the inductor’s ripple
current and the regulator load transient response time
A smaller inductor will give the regulator a faster load
transient response at the expense of higher ripple current and vice versa. The maximum ripple current occurs at the maximum input voltage. A good starting
point is to choose the ripple current to be approximately 30% of the maximum output current.
Linear Regulator Input/Output Capacitor Selection
The input capacitor is chosen based on its voltage
rating. Under load transient condition, the input capacitor will momentarily supply the required transient
current. A 1uF ceramic capacitor will be sufficient in
most applications.
The output capacitor for the linear regulator is chosen
to minimize any droop during load transient condition.
In addition, the capacitor is chosen based on its voltage rating.
Once the inductance value has been chosen, select
an inductor that is capable of carrying the required
peak current without going into saturation. In some
type of inductors, especially core that is make of
ferrite, the ripple current will increase abruptly when it
saturates. This will result in a larger output ripple
voltage.
Linear Regulator MOSFET Selection
In addition to choosing the pass MOSFET for its ability to sustain the load current requirement (see Maximum Output Voltage of Linear Controller), another criteria is its efficiency of heat removal. The power dissipated by the MOSFET is given by:
PWM Regulator MOSFET Selection
The selection of the N-channel power MOSFETs are
determined by the RDS(ON), reverse transfer capacitance
(CRSS) and maximum output current requirement.The
losses in the MOSFETs have two components: conduction loss and transition loss. For the upper and
lower MOSFET, the losses are approximately given
by the following :
Copyright  ANPEC Electronics Corp.
Rev. A.3 - Oct., 2003
Pdiss = Iout * (VIN - VOUT2)
11
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APW7060
Application Information
• The ground return of CIN must return to the combine
where Iout is the maximum load current
Vout2 is the nominal output voltage
COUT (-) terminal.
• Capacitor CHFis to improve noise performance and
In some applications, heatsink maybe required to help
maintain the junction temperature of the MOSFET below its maximum rating.
a small 1uF ceramic capacitor will be sufficient. Place
this capacitor close of the drain of Q1.
• Inductor L1 should be connected closely to the
PHASE node.
V DS
• Bypass capacitors, CBP, should be placed as close
Voltage across
drain and source of MOSFET
to the 5VCC and 12VCC pins.
VIN
CHF
5VCC
5VCC
CBP
GND
GND
t sw
+
CBP
CIN
12VCC
Time
12VCC
Figure 4. Switching waveform across MOSFET
UGATE
Q1
LGATE
Layout Considerations
In high power switching regulator, a correct layout is
important to ensure proper operation of the regulator.
In general, interconnecting impedances should be minimized by using short, wide printed circuit traces. Signal and power grounds are to be kept separate and
finally combined using ground plane construction or
single point grounding. Figure 5 illustrates the layout,
with bold lines indicating high current paths. Components along the bold lines should be placed close
together. Below is a checklist for your layout:
APW7060
PHASE
+
Q2
L1
COUT
VOUT
Figure 5. Recommended Layout Diagram
• Keep the switching nodes (UGATE, LGATE and
the PHASE) away from sensitive small signal nodes
since these nodes are fast moving signals. There
fore keep traces to these nodes as short as
possible.
• Decoupling capacitor CIN provides the bulk capaci
tance and needs to be placed close to the drain of
Q1.
Copyright  ANPEC Electronics Corp.
Rev. A.3 - Oct., 2003
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APW7060
Package Information
E
H
0 . 01 5 x 4 5
SOP – 14 (150mil)
A
0 . 0 10
A1
A
D
Ee
B
L
Dim
A
A1
B
C
D
E
e
H
L
θ°
Millimeters
Min.
1.477
0.102
0.331
0.191
8.558
3.82
Inches
Max.
1.732
0.255
0.509
0.2496
8.762
3.999
Min.
0.058
0.004
0.013
0.0075
0.336
0.150
6.215
1.274
8°
0.228
0.015
0°
1.274
5.808
0.382
0°
Copyright  ANPEC Electronics Corp.
Rev. A.3 - Oct., 2003
Max.
0.068
0.010
0.020
0.0098
0.344
0.157
0.050
13
0.244
0.050
8°
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APW7060
Physical Specifications
Terminal Material
Lead Solderability
Packaging
Solder-Plated Copper (Solder Material : 90/10 or 63/37 SnPb
Meets EIA Specification RSI86-91, ANSI/J-STD-002 Category 3.
2500 devices per reel
Reflow Condition
(IR/Convection or VPR Reflow)
temperature
Reference JEDEC Standard J-STD-020A APRIL 1999
Peak temperature
183°C
Pre-heat temperature
Time
Classification Reflow Profiles
Average ramp-up rate(183 °C to Peak)
Preheat temperature 125 ± 25 °C)
Temperature maintained above 183 °C
Time within 5 °C of actual peak temperature
Peak temperature range
Ramp-down rate
Time 25 °C to peak temperature
Convection or IR/
Convection
3 °C/second max.
120 seconds max.
60 ~ 150 seconds
10 ~ 20 seconds
220 +5/-0 °C or 235 +5/-0 °C
6 °C /second max.
6 minutes max.
VPR
10 °C /second max.
60 seconds
215~ 219 °C or 235 +5/-0 °C
10 °C /second max.
Package Reflow Conditions
pkg. thickness ≥ 2.5mm
and all bags
Convection 220 +5/-0 °C
VPR 215-219 °C
IR/Convection 220 +5/-0 °C
pkg. thickness < 2.5mm and
pkg. volume ≥ 350 mm
Copyright  ANPEC Electronics Corp.
Rev. A.3 - Oct., 2003
14
pkg. thickness < 2.5mm and pkg.
volume <
Convection 235 +5/-0 °C
VPR 235 +5/-0 °C
IR/Convection 235 +5/-0 °C
www.anpec.com.tw
APW7060
Reliability test program
Test item
SOLDERABILITY
HOLT
PCT
TST
ESD
Latch-Up
Method
MIL-STD-883D-2003
MIL-STD-883D-1005.7
JESD-22-B, A102
MIL-STD-883D-1011.9
MIL-STD-883D-3015.7
JESD 78
Description
245°C , 5 SEC
1000 Hrs Bias @ 125 °C
168 Hrs, 100 % RH , 121°C
-65°C ~ 150°C, 200 Cycles
VHBM > 2KV, VMM > 200V
10ms , Itr > 100mA
Carrier Tape & Reel Dimension
t
D
P
Po
E
P1
F
W
Ao
D1
Ko
T2
J
C
A
B
T1
Application
A
330REF
SOP-14
(150mil)
F
7.5
B
C
13.0 + 0.5
100REF
- 0.2
D
D1
φ0.50 +
0.1
φ1.50
(MIN)
J
T1
2 ± 0.5
T2
16.5REF 2.5 ± 025
W
16.0 ± 0.3
P
E
8
1.75
Po
P1
Ao
Ko
t
4.0
2.0
6.5
2.10
0.3±0.05
(mm)
Copyright  ANPEC Electronics Corp.
Rev. A.3 - Oct., 2003
15
www.anpec.com.tw
APW7060
Cover Tape Dimensions
Application
SOP- 14
Carrier Width
24
Cover Tape Width
21.3
Devices Per Reel
2500
Customer Service
Anpec Electronics Corp.
Head Office :
5F, No. 2 Li-Hsin Road, SBIP,
Hsin-Chu, Taiwan, R.O.C.
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
7F, No. 137, Lane 235, Pac Chiao Rd.,
Hsin Tien City, Taipei Hsien, Taiwan, R. O. C.
Tel : 886-2-89191368
Fax : 886-2-89191369
Copyright  ANPEC Electronics Corp.
Rev. A.3 - Oct., 2003
16
www.anpec.com.tw