FDMF6705V – XS™ DrMOS – Extra-Small, HighPerformance, High-Frequency DrMOS Module Benefits Single 12V Input Power Supply Operation Ultra-Compact 6x6mm PQFN, 72% Space-Saving Compared to Conventional Discrete Solutions Fully Optimized System Efficiency Clean Switching Waveforms with Minimal Ringing High-Current Handling Features Over 93% Peak-Efficiency High-Current Handling of 43A High-Performance PQFN Copper Clip Package 3-State 5V PWM Input Driver Shorter Propagation Delays than FDMF6704V Shorter Dead Times than FDMF6704V Skip-Mode SMOD# (Low-Side Gate Turn Off) Input Thermal Warning Flag for Over-Temperature Condition Driver Output Disable Function (DISB# Pin) Fairchild PowerTrench® Technology MOSFETs for Clean Voltage Waveforms and Reduced Ringing Fairchild SyncFET™ (Integrated Schottky Diode) Technology in the Low-Side MOSFET Integrated Bootstrap Schottky Diode Internal Pull-Up and Pull-Down for SMOD# and DISB# Inputs, Respectively Adaptive Gate Drive Timing for Shoot-through Protection Under-Voltage Lockout (UVLO) Description The XS™ DrMOS family is Fairchild’s next-generation, fully optimized, ultra-compact, integrated MOSFET plus driver power stage solutions for high-current, highfrequency, synchronous buck DC-DC applications. The FDMF6705V integrates a driver IC, two power MOSFETs, and a bootstrap Schottky diode into a thermally enhanced, ultra-compact 6x6mm PQFN package. With an integrated approach, the complete switching power stage is optimized with regards to driver and MOSFET dynamic performance, system inductance, and Power MOSFET RDS(ON). XS™ DrMOS uses Fairchild's high-performance PowerTrench® MOSFET technology, which dramatically reduces switch ringing, eliminating the need for a snubber circuit in most buck converter applications. A new driver IC with reduced dead times and propagation delays further enhances the performance of this part. A thermal warning function has been included to warn of a potential over-temperature situation. The FDMF6705V also incorporates features, such as Skip Mode (SMOD), for improved light-load efficiency along with a 3-state PWM input for compatibility with a wide range of PWM controllers. Applications High-Performance Gaming Motherboards Compact Blade Servers, V-Core and Non-V-Core DC-DC Converters Desktop Computers, V-Core and Non-V-Core DC-DC Converters Workstations Networking and Telecom Microprocessor Voltage Regulators Small Form-Factor Voltage Regulator Modules Optimized for Switching Frequencies up to 1MHz Low-Profile SMD Package Fairchild Green Packaging and RoHS Compliant Based on the Intel® 4.0 DrMOS Standard High-Current DC-DC Point-of-Load (POL) Converters Ordering Information Part Number Current Rating Input Voltage Switching Frequency FDMF6705V 40A 12V 1000kHz © 2011 Fairchild Semiconductor Corporation FDMF6705V • Rev. 1.0 1 Package 40-Lead, Clipbond PQFN DrMOS, 6.0x6.0mm Package Top Mark FDMF6705V www.fairchildsemi.com FDMF6705V - XS™ DrMOS - Extra-Small High-Performance, High-Frequency DrMOS Module March 2011 VCIN VIN = 3V to 15V THWN# VDRV = 8V to 15 V VIN CVIN Temp Sense VDRV 5V Linear Reg . C VDRV DBoot BOOT VCIN Q1 HDRV C VCIN CGND PWM Control PHASE PWM COUT VSWH LDRV OFF Disabled VOUT VCIN Control Enabled LOUT Q2 SMOD # ON DISBL# CGND Figure 1. PGND Typical Application Circuit DrMOS Block Diagram VCIN VDRV VIN UVLO BOOT VIN 5V LDO Q1 HS Power MOSFET D Boot VCC UVLO DISB# GH GH Logic Level Shift 10µA 30kΩ VCIN PHASE RUP_PWM Deadtime Control Input 3-State Logic PWM RDN_PWM VSWH VCIN GL GL Logic THWN# 30kΩ VCIN Temp. Sense FDMF6705V - XS™ DrMOS - Extra-Small High-Performance, High-Frequency DrMOS Module Typical Application Circuit Q2 LS Power MOSFET 10µA CGND SMOD# Figure 2. © 2011 Fairchild Semiconductor Corporation FDMF6705V • Rev. 1.0.1 PGND DrMOS Block Diagram www.fairchildsemi.com 2 Figure 3. Bottom View Figure 4. Top View Pin Definitions Pin # 1 Name Description When SMOD#=HIGH, the low-side driver is the inverse of PWM input. When SMOD#=LOW, SMOD# the low-side driver is disabled. This pin has a 10µA internal pull-up current source. Do not leave this pin floating. Do not add a noise filter capacitor. 2 VCIN Linear regulator 5V output. IC bias supply for gate drive output stage. Minimum 1µF ceramic capacitor is required and should be connected as close as possible from this pin to CGND 3 VDRV Linear regulator input. Minimum 1µF ceramic capacitor is recommended and should be connected as close as possible from this pin to CGND. 4 BOOT Bootstrap supply input. Provides voltage supply to high-side MOSFET driver. Connect bootstrap capacitor from this pin to PHASE. 5, 37, 41 CGND IC ground. Ground return for driver IC. 6 GH 7 For manufacturing test only. This pin must float. Must not be connected to any pin. PHASE Switch node pin for bootstrap capacitor routing. Electrically shorted to VSWH pin. 8 NC No connect. The pin is not electrically connected internally, but can be connected to VIN for convenience. 9 - 14, 42 VIN Power input. Output stage supply voltage. 15, 29 35, 43 VSWH Switch node input. Provides return for high-side bootstrapped driver and acts as a sense point for the adaptive shoot-through protection. 16 – 28 PGND Power ground. Output stage ground. Source pin of low-side MOSFET. 36 GL 38 THWN# 39 DISB# Output disable. When LOW, this pin disables Power MOSFET switching (GH and GL are held LOW). This pin has a 10µA internal pull-down current source. Do not leave this pin floating. Do not add a noise filter capacitor. 40 PWM PWM signal input. This pin accepts a 3-state logic-level PWM signal from the controller. FDMF6705V - XS™ DrMOS - Extra-Small High-Performance, High-Frequency DrMOS Module Pin Configuration For manufacturing test only. This pin must float. Must not be connected to any pin. Thermal warning flag, open collector output. When temperature exceeds the trip limit, the output is pulled LOW. THWN# does not disable the module. © 2011 Fairchild Semiconductor Corporation FDMF6705V • Rev. 1.0.1 www.fairchildsemi.com 3 Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol IO(AV) (1) Parameter Min. Max. VCIN, DISB#, PWM, SMOD#, GL, THWN# to CGND Pins 6 VIN to PGND, CGND Pins 25 VDRV to PGND, CGND 16 BOOT, GH to VSWH, PHASE Pins 6 BOOT, VSWH, PHASE, GH to GND Pins 25 BOOT to VCIN Pins 22 VIN=12V, VO=1.0V fSW =300kHz 43 fSW =1MHz 40 θJPCB Junction-to-PCB Thermal Resistance TSTG Operating and Storage Temperature Range ESD Electrostatic Discharge Protection -55 Human Body Model, JESD22-A114 2000 Charged Device Model, JESD22-C101 2000 Unit V A 3.5 °C/W +150 °C V Note: 1. IO(AV) is measured in Fairchild’s evaluation board. This rating can be changed with different application settings. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol VDRV VIN Parameter Gate Drive Control Circuit Input Supply Voltage Output Stage Supply Voltage (2) Note: 2. May be operated at lower input voltage. © 2011 Fairchild Semiconductor Corporation FDMF6705V • Rev. 1.0.1 Min. Typ. Max. Unit 8 12 15 V 3 12 15 V FDMF6705V - XS™ DrMOS - Extra-Small High-Performance, High-Frequency DrMOS Module Absolute Maximum Ratings www.fairchildsemi.com 4 Typical values are VIN=12V, VDRV=12V, and TA=+25°C unless otherwise noted. Symbol Parameter IDRV Operating Current Condition Min. Typ. Max. Unit VDRV=14V, PWM=LOW or HIGH or Float 2 5 12 14 mA Internal 5V Linear Regulator VDRV Input Voltage IDRV Input Current 8V<VIN<14V, fSW =1MHz VCIN Output Voltage VDRV=8V, ILOAD=5mA Power Dissipation VDRV=12V, fSW =1MHz PVDRV 8 36 4.8 5.0 5.2 250 1 V mA V mW CVCIN VCIN Bypass Capacitor X7R or X5R Ceramic VRLINE Line Regulation 8V<VIN<14V, ILOAD=5mA 20 mV VRLOAD Load Regulation VDRV=8V, 5mA<ILOAD<100mA 75 mV Short-Circuit Current Limit UVLO UVLO Threshold 10 200 VDRV Rising 6.8 UVLO_Hyst UVLO Hysteresis 7.3 µF mA 7.8 V 0.435 V 10 kΩ 10 kΩ PWM Input RUP_PWM Pull-Up Impedance RDown_PWM Pull-Down Impedance VIH_PWM PWM High Level Voltage 3.30 3.55 3.80 V VTRI_HI 3-State Rising Threshold 3.20 3.45 3.70 V VTRI_LO 3-State Falling Threshold 1.00 1.25 1.50 V VIL_PWM PWM Low Level Voltage 0.85 1.15 1.40 V 160 200 ns 2.5 2.7 V tD_HOLD-OFF 3-State Shutoff Time VHiZ_PWM 3-State Open Voltage 2.3 DISB# Input VIH_DISB High-Level Input Voltage VIL_DISB Low-Level Input Voltage IPLD 2 V 0.8 Pull-Down Current tPD_DISBL Propagation Delay PWM=GND, Delay Between DISB# from HIGH to LOW to GL from HIGH to LOW tPD_DISBH Propagation Delay PWM=GND, Delay Between DISB# from LOW to HIGH to GL from LOW to HIGH V 10 µA 25 ns 25 ns SMOD# Input VIH_SMOD High-Level Input Voltage VIL_SMOD Low-Level Input Voltage IPLM 2 V 0.8 Pull-Up Current FDMF6705V - XS™ DrMOS - Extra-Small High-Performance, High-Frequency DrMOS Module Electrical Characteristics V 10 µA tPD_SLGLL Propagation Delay PWM=GND, Delay Between SMOD# from HIGH to LOW to GL from HIGH to LOW 10 ns tPD_SHGLH Propagation Delay PWM=GND, Delay Between SMOD# from LOW to HIGH to GL from LOW to HIGH 10 ns Continued on the following page… © 2011 Fairchild Semiconductor Corporation FDMF6705V • Rev. 1.0.1 www.fairchildsemi.com 5 Typical values are VIN=12V, VDRV=12V, and TA=+25°C unless otherwise noted. Symbol Parameter Condition Min. Typ. Max. Unit Thermal Warning Flag TACT Activation Temperature 150 °C TRST Reset Temperature 135 °C IPLD=5mA 30 Ω SW=0V, Delay Between GH from HIGH to LOW and GL from LOW to HIGH 250 ns 1 Ω RTHWN Pull-Down Resistance 250ns Timeout Circuit tD_TIMEOUT Timeout Delay High-Side Driver RSOURCE_GH Output Impedance, Sourcing Source Current=100mA RSINK_GH Output Impedance, Sinking Sink Current=100mA 0.8 Ω tR_GH Rise Time GH=10% to 90%, CLOAD=1.1nF 12 ns tF_GH Fall Time GH=90% to 10%, CLOAD=1.1nF 11 ns tD_DEADON LS to HS Deadband Time GL Going LOW to GH Going HIGH, 2V GL to 10 % GH 10 ns tPD_PLGHL PWM LOW Propagation Delay PWM Going LOW to GH Going LOW, VIL_PWM to 90% GH 16 tPD_PHGHH PWM HIGH Propagation Delay (SMOD Held LOW) PWM Going HIGH to GH Going HIGH, VIH_PWM to 10% GH (SMOD=LOW) 30 ns tPD_TSGHH Exiting 3-State Propagation Delay PWM (from 3-State) Going HIGH to GH Going HIGH, VIH_PWM to 10% GH 30 ns 1 Ω 30 ns Low-Side Driver RSOURCE_GL Output Impedance, Sourcing Source Current=100mA RSINK_GL Output Impedance, Sinking Sink Current=100mA 0.5 Ω tR_GL Rise Time GL=10% to 90%, CLOAD=2.7nF 12 ns tF_GL Fall Time GL=90% to 10%, CLOAD=2.7nF 8 ns SW Going LOW to GL Going HIGH, 2.2V SW to 10% GL 12 ns tD_DEADOFF HS to LS Deadband Time tPD_PHGLL PWM-HIGH Propagation Delay PWM Going HIGH to GL Going LOW, VIH_PWM to 90% GL 9 tPD_TSGLH Exiting 3-State Propagation Delay PWM (from 3-State) Going LOW to GL Going HIGH, VIL_PWM to 10% GL 20 VF Forward-Voltage Drop IF=10mA VR Breakdown Voltage IR=1mA 25 ns ns Boot Diode © 2011 Fairchild Semiconductor Corporation FDMF6705V • Rev. 1.0.1 0.35 22 V FDMF6705V - XS™ DrMOS - Extra-Small High-Performance, High-Frequency DrMOS Module Electrical Characteristics (Continued) V www.fairchildsemi.com 6 V IL_PWM PWM 90% GL 2.0V 10% 90% GH to SW 10% 1.2V t D_TIMEOUT (250ns Timeout) 2.2V SW t PD_PLGHL t PD_PHGLL tD_DEADOFF t D_DEADON Figure 5. © 2011 Fairchild Semiconductor Corporation FDMF6705V • Rev. 1.0.1 PWM Timing Diagram FDMF6705V - XS™ DrMOS - Extra-Small High-Performance, High-Frequency DrMOS Module V IH_PWM www.fairchildsemi.com 7 Test Conditions: VIN=12V, VOUT=1.0V, VDRV=12V, LOUT=320nH, TA=25°C, and natural convection cooling, unless otherwise specified. 300kHz 1MHz Figure 6. Safe Operating Area Figure 7. Module Power Loss vs. Output Current IOUT=30A Figure 8. fSW =300kHz IOUT=30A Power Loss vs. Switching Frequency Figure 9. fSW =300kHz IOUT=30A fSW =300kHz IOUT=30A Figure 10. Power Loss vs. Driver Supply Voltage © 2011 Fairchild Semiconductor Corporation FDMF6705V • Rev. 1.0.1 Power Loss vs. Input Voltage FDMF6705V - XS™ DrMOS - Extra-Small High-Performance, High-Frequency DrMOS Module Typical Performance Characteristics Figure 11. Power Loss vs. Output Voltage www.fairchildsemi.com 8 Test Conditions: VIN=12V, VOUT=1.0V, VDRV=12V, LOUT=320nH, TA=25°C, and natural convection cooling, unless otherwise specified. IOUT=0A fSW =300kHz IOUT=30A Figure 12. Power Loss vs. Output Inductance Figure 13. Driver Supply Current vs. Frequency fSW =300kHz IOUT=0A Figure 14. Driver Supply Current vs. Driver Supply Voltage Figure 15. Driver Supply Current vs. Output Current Figure 16. UVLO Thresholds vs. Temperature Figure 17. LDO Line and Load Regulations © 2011 Fairchild Semiconductor Corporation FDMF6705V • Rev. 1.0.1 FDMF6705V - XS™ DrMOS - Extra-Small High-Performance, High-Frequency DrMOS Module Typical Performance Characteristics (Continued) www.fairchildsemi.com 9 Test Conditions: VIN=12V, VOUT=1.0V, VDRV=12V, LOUT=320nH, TA=25°C, and natural convection cooling, unless otherwise specified. Figure 18. LDO Output Voltage vs. Temperature Figure 19. PWM Thresholds vs. Temperature Figure 20. DISB# Thresholds vs. Temperature Figure 21. SMOD# Thresholds vs. Temperature FDMF6705V - XS™ DrMOS - Extra-Small High-Performance, High-Frequency DrMOS Module Typical Performance Characteristics (Continued) Figure 22. BOOT Diode VF vs. Temperature © 2011 Fairchild Semiconductor Corporation FDMF6705V • Rev. 1.0.1 www.fairchildsemi.com 10 The FDMF6705V is a driver-plus-FET module optimized for the synchronous buck converter topology. A single PWM input signal is all that is required to properly drive the high-side and the low-side MOSFETs. Each part is capable of driving speeds up to 1MHz. 3-State PWM Input The FDMF6705V incorporates a 3-state PWM input gate drive design. The 3-state gate drive has both logic HIGH level and LOW level, along with a 3-state shutdown window. When the PWM input signal enters and remains within the 3-state window for a defined hold-off time (tD_HOLD-OFF), both GL and GH are pulled LOW. This feature enables the gate drive to shut down both high-and low-side MOSFETs to support features such as phase shedding, which is a common feature on multiphase voltage regulators. VDRV and Disable The VDRV pin is monitored by an under-voltage lockout (UVLO) circuit. When VDRV rises above ~7.3V, the driver is enabled for operation. When VDRV falls below ~6.95V, the driver is disabled (GH, GL=0). The driver can also be disabled by pulling the DISB# pin LOW (DISB# < VIL_DISB), which holds both GL and GH LOW regardless of the PWM input state. The driver can be enabled by raising the DISB# pin voltage HIGH (DISB# > VIH_DISB). Table 1. Operation when Exiting 3-State Condition When exiting a valid 3-state condition, the FDMF6705V design follows the PWM input command. If the PWM input goes from 3-state to LOW, the low side MOSFET is turned on. If the PWM input goes from 3-state to HIGH, the high-side MOSFET is turned on. This is illustrated in Figure 24. The FDMF6705V design allows for short propagation delays when exiting the 3-state window (see Electrical Characteristics). UVLO and Disable Logic UVLO DISB# Driver State 0 X Disabled (GH, GL=0) 1 0 Disabled (GH, GL=0) 1 1 Enabled (See Table 2) 1 Open Disabled (GH, GL=0) Low-Side Driver The low-side driver (GL) is designed to drive a groundreferenced low RDS(ON) N-channel MOSFET. The bias for GL is internally connected between VCIN and CGND. When the driver is enabled, the driver's output is 180° out of phase with the PWM input. When the driver is disabled (DISB#=0V), GL is held LOW. Note: 3. DISB# has an internal pull-down current source of 10µA. Thermal Warning Flag THWM Logic State The FDMF6705V provides a thermal warning flag (THWN) to warn of over-temperature conditions. The thermal warning flag uses an open-drain output that pulls to CGND when the activation temperature (150°C) is reached. The THWN output returns to a highimpedance state once the temperature falls to the reset temperature (135°C). For use, the THWN output requires a pull-up resistor, which can be connected to VCIN. THWN does NOT disable the DrMOS module. ° 135° C Reset Temp. High Normal Operation High-Side Driver The high-side driver is designed to drive a floating Nchannel MOSFET. The bias voltage for the high-side driver is developed by a bootstrap supply circuit, consisting of the internal Schottky diode and external bootstrap capacitor (CBOOT). During startup, VSWH is held at PGND, allowing CBOOT to charge to VCIN through the internal diode. When the PWM input goes HIGH, GH begins to charge the gate of the high-side MOSFET (Q1). During this transition, the charge is removed from CBOOT and delivered to the gate of Q1. As Q1 turns on, VSWH rises to VIN, forcing the BOOT pin to VIN + VBOOT, which provides sufficient VGS enhancement for Q1. To complete the switching cycle, Q1 is turned off by pulling GH to VSWH. CBOOT is then recharged to VCIN when VSWH falls to PGND. GH output is inphase with the PWM input. The high-side gate is held LOW when the driver is disabled or the PWM signal is held within the 3-state window for longer than the 3state hold-off time, tD_HOLD-OFF. 150 ° C Activation Temp. Thermal Warning Low TJ_driver IC FDMF6705V - XS™ DrMOS - Extra-Small High-Performance, High-Frequency DrMOS Module Functional Description Figure 23. THWN Operation © 2011 Fairchild Semiconductor Corporation FDMF6705V • Rev. 1.0.1 www.fairchildsemi.com 11 The driver IC advanced design ensures minimum MOSFET dead-time while eliminating potential shoot through (cross-conduction) currents. It senses the state of the MOSFETs and adjusts the gate drive adaptively to ensure they do not conduct simultaneously. Figure 24 provides the relevant timing waveforms. To prevent overlap during the LOW-to-HIGH switching transition (Q2 off to Q1 on), the adaptive circuitry monitors the voltage at the GL pin. When the PWM signal goes HIGH, Q2 begins to turn off after some propagation delay (tPD_PHGLL). Once the GL pin is discharged below ~2V, Q1 begins to turn on after adaptive delay tD_DEADON. V IH_PWM V IH_PWM V IH_PWM V IH_PWM V TRI_HI V TRI_HI V TRI_LO V IL_PWM V IL_PWM tR_GH PWM less than t D_HOLD -OFF GH to SW tF_GHS 90% tD_HOLD -OFF 10% V IN CCM DCM DCM V OUT 2.2V SW GL 90% 90% 2.0V tPD_PHGLL tD_DEADON 10% 10% tPD_PLGHL tR_GL tF_GL tD_DEADOFF Enter 3-State tPD_TSGHH tD_HOLD -OFF Enter 3 -State Exit 3-State tPD_TSGHH Exit 3- State less than t D_HOLD -OFF tD_HOLD-OFF tPD_TSGLH Enter 3 -State Exit 3-State . Notes: t PD_xxx = propagation delay from external signal (PWM, SMOD, etc.) to IC generated signal. Example (t PD_PHGLL - PWM going high to LS Vgs (GL) going low). t D_xxx = delay from IC generated signal to IC generated signal. Example (t D_DEADON – LS Vgs (GL) low to HS Vgs (GH) high). PWM t PD_PHGLL t PD_PLGHL t PD_PHGHH SMOD t PD_SLGLL t PD_SHGLH = PWM rise to GL fall , V IH_PWM to 90% GL = PWM fall to GH fall, V IL_PWM to 90% GH = PWM rise to GH rise, V IH_PWM to 10% GH (assumes SMOD held low). = SMOD fall to GL fall, V IL_SMOD to 90% GL = SMOD rise to GL rise, V IH_SMOD to 10% GL Exiting 3-State t PD_TSGHH = PWM t PD_TSGLH = PWM 3-state to high to GH rise, V IH_PWM to 10% GH 3-state to low to GL rise, V IL_PWM to 10% GL FDMF6705V - XS™ DrMOS - Extra-Small High-Performance, High-Frequency DrMOS Module To preclude overlap during the HIGH-to-LOW transition (Q1 off to Q2 on), the adaptive circuitry monitors the voltage at the VSWH pin. When the PWM signal goes LOW, Q1 begins to turn off after some propagation delay (tPD_PLGHL). Once the VSWH pin falls below ~2.2V, Q2 begins to turn on after adaptive delay tD_DEADOFF. Additionally, VGS(Q1) is monitored. When VGS(Q1) is discharged below ~1.2V, a secondary adaptive delay is initiated, which results in Q2 being driven on after tD_TIMEOUT, regardless of SW state. This function is implemented to ensure CBOOT is recharged each switching cycle in the event that the SW voltage does not fall below the 2.2V adaptive threshold. Secondary delay tD_TIMEOUT is longer than tD_DEADOFF. Adaptive Gate Drive Circuit Dead Times t D_DEADON = GL fall to GH rise, LS -comp trip value (~2.0V GL ) to 10% GH t D_DEADOFF = SW -node fall off to GL rise, SW -comp trip value (~ 2.2V) to 10% GL Figure 24. PWM and 3-StateTiming Diagram © 2011 Fairchild Semiconductor Corporation FDMF6705V • Rev. 1.0.1 www.fairchildsemi.com 12 The SMOD function allows for higher converter efficiency under light-load conditions. During SMOD, the low-side FET gate signal is disabled (held LOW), preventing discharging of the output capacitors as the filter inductor current attempts reverse current flow – also known as “Diode Emulation” Mode. Table 2. When the SMOD pin is pulled HIGH, the synchronous buck converter works in Synchronous Mode, gating on the low-side FET. When the SMOD pin is pulled LOW, the low-side FET is gated off. The SMOD pin is connected to the PWM controller, which enables or disables the SMOD automatically when the controller detects light-load condition from output current sensing. Normally this pin is active LOW. See Figure 25 for timing delays. SMOD Logic DISB# PWM SMOD# GH GL 0 X X 0 0 1 3-State X 0 0 1 0 0 0 0 1 1 0 1 0 1 0 1 0 1 1 1 1 1 0 Note: 4. The SMOD feature is intended to have low propagation delay between the SMOD signal and the low-side FET VGS response time to control diode emulation on a cycle-by-cycle basis. SMOD# V IH_SMOD V IL_SMOD V IH_PWM VIH_PWM V IL_PWM PWM 90% GH to SW 10% 10% DCM VOUT CCM CCM 2.2V SW GL 90% 2.0V 2.2V tPD_PHGLL tD_DEADON 10% tPD_PLGHL tD_DEADOFF 10% tPD_PHGHH tPD_SLGLL Delay from SMOD going low to LS VGS low HS turn-on with SMOD low. tPD_SHGLH Delay from SMOD going high to LS VGS high FDMF6705V - XS™ DrMOS - Extra-Small High-Performance, High-Frequency DrMOS Module Skip Mode (SMOD) Figure 25. SMOD Timing Diagram © 2011 Fairchild Semiconductor Corporation FDMF6705V • Rev. 1.0.1 www.fairchildsemi.com 13 for specific applications to improve switching noise immunity. Supply Capacitor Selection For the supply input (VDRV), a local ceramic bypass capacitor is required to have regulator stable and to reduce noise. For the regulator output on VCIN, another local ceramic bypass capacitor is needed to supply the peak power MOSFET low-side gate current and boot capacitor charging current. Use at least a 1µF, X7R or X5R capacitors. Keep these capacitors close to the FDMF6705V VDRV and VCIN pin and connect them to GND plane with vias. Do not tie VDRV and VCIN pins each other. Power Loss and Efficiency Measurement and Calculation Refer to Figure 26 for power loss testing method. Power loss calculations are: PIN=(VIN x IIN) + (VDRV x IDRV) (W) PSW =VSW x IOUT (W) POUT=VOUT x IOUT (W) PLOSS_MODULE=PIN - PSW (W) PLOSS_BOARD=PIN - POUT (W) EFFMODULE=100 x PSW /PIN (%) EFFBOARD=100 x POUT/PIN (%) Bootstrap Circuit The bootstrap circuit uses a charge storage capacitor (CBOOT), as shown in Figure 26. A bootstrap capacitance of 100nF X7R or X5R capacitor is adequate. A series bootstrap resistor would be needed VDRV A A IDRV IIN CVCIN CVDRV VDRV DISB# VCIN CVIN VIN VIN DISB# RBOOT PWM Input BOOT PWM CBOOT FDMF6705V OFF IOUT VSWH ON Open-Drain Output SMOD# A L OUT PHASE THWN CGND Figure 26. © 2011 Fairchild Semiconductor Corporation FDMF6705V • Rev. 1.0.1 V PGND VSW Power Loss Measurement Block Diagram COUT VOUT FDMF6705V - XS™ DrMOS - Extra-Small High-Performance, High-Frequency DrMOS Module Application Information www.fairchildsemi.com 14 7. The layout should include the option to insert a small-value series boot resistor between the boot capacitor and BOOT pin. The boot-loop size, including RBOOT and CBOOT, should be as small as possible. The boot resistor is normally not required, but is effective at controlling the highside MOSFET turn-on slew rate. This can improve noise operating margin in synchronous buck designs that may have noise issues due to ground bounce or high positive and negative VSWH ringing. Inserting a boot resistance lowers the DrMOS efficiency. Efficiency versus noise tradeoffs must be considered. Figure 27 provides an example of a proper layout for the FDMF6705V and critical components. All of the high-current paths, such as VIN, VSWH, VOUT, and GND copper, should be short and wide for low inductance and resistance. This technique aids in achieving a more stable and evenly distributed current flow, along with enhanced heat radiation and system performance. The following guidelines are recommendations for the PCB designer: 1. Input ceramic bypass capacitors must be placed close to the VIN and PGND pins. This helps reduce the high-current power loop inductance and the input current ripple induced by the power MOSFET switching operation. The VIN and PGND pins handle large current transients with frequency components greater than 100MHz. If possible, these pins should be connected directly to the VIN and board GND planes. The use of thermal relief traces in series with these pins is discouraged since this adds inductance to the power path. This added inductance in series with either the VIN or PGND pin degrades system noise immunity by increasing positive and negative VSWH ringing. 2. The VSWH copper trace serves two purposes. In addition to being the high-frequency current path from the DrMOS package to the output inductor, it also serves as a heat sink for the low-side MOSFET in the DrMOS package. The trace should be short and wide enough to present a low-impedance path for the high-frequency, highcurrent flow between the DrMOS and inductor to minimize losses and temperature rise. Note that the VSWH node is a high voltage and highfrequency switching node with high noise potential. Care should be taken to minimize coupling to adjacent traces. Since this copper trace also acts as a heat sink for the lower FET, balance using the largest area possible to improve DrMOS cooling while maintaining acceptable noise emission. 8. CGND pad and PGND pins should be connected by plane GND copper with multiple vias for stable grounding. Poor grounding can create a noise transient offset voltage level between CGND and PGND. This could lead to faulty operation of gate driver and MOSFET. 9. Ringing at the BOOT pin is most effectively controlled by close placement of the boot capacitor. Do not add an additional BOOT to the PGND capacitor. This may lead to excess current flow through the BOOT diode. 3. An output inductor should be located close to the FDMF6705V to minimize the power loss due to the VSWH copper trace. Care should also be taken so the inductor dissipation does not heat the DrMOS. 10. The SMOD# and DISB# pins have weak internal pull-up and pull-down current sources, respectively. They should not be left floating. These pins should not have any noise filter capacitors. 4. PowerTrench® MOSFETs are used in the output stage. The Power MOSFETs are effective at minimizing ringing due to fast switching. In most cases, no VSWH snubber is required. If a snubber is used, it should be placed close to the VSWH and PGND pins. The resistor and capacitor need to be of proper size for the power dissipation. 11. Use multiple vias on each copper area to interconnect top, inner, and bottom layers to help distribute current flow and heat conduction. Vias should be relatively large and of reasonably low inductance. Critical high-frequency components, such as RBOOT, CBOOT, the RC snubber, and bypass capacitors should be located as close to the respective DrMOS module pins as possible on the top layer of the PCB. If this is not feasible, they should be connected from the backside through a network of low-inductance vias. 5. VCIN, VDRV, and BOOT capacitors should be placed as close as possible to the VCIN to CGND, VDRV to CGND, and BOOT to PHASE pins to ensure clean and stable power. Routing width and length should be considered as well. 6. Include a trace from PHASE to VSWH to improve noise margin. Keep the trace as short as possible. © 2011 Fairchild Semiconductor Corporation FDMF6705V • Rev. 1.0.1 FDMF6705V - XS™ DrMOS - Extra-Small High-Performance, High-Frequency DrMOS Module PCB Layout Guidelines www.fairchildsemi.com 15 Bottom View Figure 27. PCB Layout Example © 2011 Fairchild Semiconductor Corporation FDMF6705V • Rev. 1.0.1 FDMF6705V - XS™ DrMOS - Extra-Small High-Performance, High-Frequency DrMOS Module Top View www.fairchildsemi.com 16 FDMF6705V - XS™ DrMOS - Extra-Small High-Performance, High-Frequency DrMOS Module Physical Dimensions B 0.10 C PIN#1 INDICATOR 6.00 2X 5.80 A 4.50 30 21 31 6.00 20 2.50 0.40 0.65 0.25 1.60 0.10 C 11 40 2X 1 SEE 0.60 DETAIL 'A' 0.50 TYP TOP VIEW 10 0.35 0.15 2.10 0.40 21 FRONT VIEW 4.40±0.10 (2.20) 0.10 C A B 0.05 C 0.30 30 0.20 (40X) 31 2.10 LAND PATTERN RECOMMENDATION 20 0.50 2.40±0.10 (0.70) 0.20 PIN #1 INDICATOR 1.50±0.10 11 10 0.40 2.00±0.10 (0.20) 40 1 2.00±0.10 0.50 NOTES: UNLESS OTHERWISE SPECIFIED (0.20) BOTTOM VIEW 1.10 0.90 0.10 C 0.08 C 0.30 0.20 0.50 (40X) 0.30 0.05 0.00 DETAIL 'A' C A) DOES NOT FULLY CONFORM TO JEDEC REGISTRATION MO-220, DATED MAY/2005. B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE BURRS OR MOLD FLASH. MOLD FLASH OR BURRS DOES NOT EXCEED 0.10MM. D) DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994. E) DRAWING FILE NAME: PQFN40AREV2 SEATING PLANE SCALE: 2:1 Figure 28. 40-Lead, Clipbond PQFN DrMOS, 6.0x6.0mm Package Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. © 2011 Fairchild Semiconductor Corporation FDMF6705V • Rev. 1.0.1 www.fairchildsemi.com 17 FDMF6705V - XS™ DrMOS - Extra-Small High-Performance, High-Frequency DrMOS Module © 2011 Fairchild Semiconductor Corporation FDMF6705V • Rev. 1.0.1 www.fairchildsemi.com 18