77 CY7C277 32K x 8 Reprogrammable Registered PROM Features • Programmable address latch enable input • Programmable synchronous or asynchronous output enable • On-chip edge-triggered output registers • EPROM technology, 100% programmable • Slim 300-mil, 28-pin plastic or hermetic DIP • 5V ±10% VCC, commercial and military • TTL-compatible I/O • Direct replacement for bipolar PROMs • Capable of withstanding greater than 2001V static discharge • Windowed for reprogrammability • CMOS for optimum speed/power • High speed — 30-ns address set-up — 15-ns clock to output • Low power — 60 mW (commercial) — 715 mW (military) Logic Block Diagram A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Pin Configurations ROW DECODER 1 OF 256 256 x 1024 PROGRAMMABLE ARRAY A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 O0 O1 O2 GND O6 8-BIT 1 OF 128 MUX O5 8-BIT EDGETRIGGERED REGISTER 15-BIT ADDRESS TRANSPARENT/ LATCH O4 O3 O2 Y ADDRESS O1 COLUMN DECODER 1 OF 32 ALE DIP/Flatpack Top View O7 X ADDRESS O0 CP 1 2 3 4 5 6 7 8 9 10 11 12 13 28 27 26 14 15 25 24 23 22 21 20 19 18 17 16 VCC A10 A11 A12 A13 A14 ALE CP E/ES O7 O6 O5 O4 O3 PROGRAMMABLE CP/ALE OPTIONS LCC/PLCC (Opaque Only) Top View E/E S Q PROGRAMMABLE MULTIPLEXER C A6 A5 A4 A3 A2 A1 A0 NC O0 4 3 2 1 32 31 30 29 5 28 6 27 7 26 8 25 9 24 10 23 11 22 12 21 13 14151617 181920 A12 A13 A14 NC ALE CP E/ES O7 O6 O1 O2 GND NC O3 O4 O5 CP D A7 A8 A9 NC VCC A10 A11 ALE Selection Guide 7C277-30 7C277-40 7C277-50 Minimum Address Set-Up Time (ns) 30 40 50 Maximum Clock to Output (ns) 15 20 25 120 120 120 130 130 Maximum Operating Current (mA) Cypress Semiconductor Corporation Document #: 38-04006 Rev. ** Com’l Mil • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised March 4, 2002 CY7C277 Functional Description The user may define the polarity of the ALE signal, with the default being active HIGH. The CY7C277 is a high-performance 32K word by 8-bit CMOS PROMs. It is packaged in the slim 28-pin 300-mil package. The ceramic package may be equipped with an erasure window; when exposed to UV light, the PROM is erased and can then be reprogrammed. The memory cells utilize proven EPROM floating-gate technology and byte-wide algorithms. The CY7C277 offers the advantages of low power, superior performance, and high programming yield. The EPROM cell requires only 12.5V for the supervoltage and low current requirements allow for gang programming. The EPROM cells allow for each memory location to be 100% tested, as each location is written into, erased, and repeatedly exercised prior to encapsulation. Each PROM is also tested for AC performance to guarantee that the product will meet DC and AC specification limits after customer programming. On the 7C277, the outputs are pipelined through a master-slave register. On the rising edge of CP, data is loaded into the 8-bit edge triggered output register. The E/ES input provides a programmable bit to select between asynchronous and synchronous operation. The default condition is asynchronous. When the asynchronous mode is selected, the E/ES pin operates as an asynchronous output enable. If the synchronous mode is selected, the E/ES pin is sampled on the rising edge of CP to enable and disable the outputs. The 7C277 also provides a programmable bit to enable the Address Latch input. If this bit is not programmed, the device will ignore the ALE pin and the address will enter the device asynchronously. If the ALE function is selected, the address enters the PROM while the ALE pin is active, and is captured when ALE is deasserted. Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ....................................−65°C to +150°C Ambient Temperature with Power Applied.................................................−55°C to +125°C Supply Voltage to Ground Potential .................−0.5V to +7.0V (Pin 24 to Pin 12) DC Voltage Applied to Outputs in High Z State.....................................................−0.5V to +7.0V DC Input Voltage ................................................. −3.0V to +7.0V DC Program Voltage (Pins 7, 18, 20) ........................... 13.0V UV Erasure................................................... 7258 Wsec/cm2 Static Discharge Voltage ........................................... >2001V (per MIL-STD-883, Method 3015) Latch-Up Current..................................................... >200 mA Operating Range Range Ambient Temperature VCC 0° C to +70 °C 5V ±10% −40°C to +85° C 5V ±10% −55°C to +125° C 5V ±10% Commercial Industrial [1] Military[2] Electrical Characteristics Over the Operating Range[3, 4] 7C277-30 Parameter Description Test Conditions Min. VOH Output HIGH Voltage VCC = Min., IOH = − 2.0 mA VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA VIH Input HIGH Level Guaranteed Input Logical HIGH Voltage for All Inputs VIL Input LOW Level Guaranteed Input Logical LOW Voltage for All Inputs IIX Input Leakage Current GND < VIN < VCC VCD Input Clamp Diode Voltage 7C277-40, 50 Max. 2.4 Min. 2.4 0.4 2.0 VCC 2.0 0.8 −10 Max. +10 −10 Unit V 0.4 V VCC V 0.8 V +10 µA Note 4 IOZ Output Leakage Current 0 < VOUT < VCC, Output Disabled −40 +40 −40 +40 µA IOS Output Short Circuit Current VCC = Max., VOUT = 0.0V[6] −20 −90 −20 −90 mA ICC Power Supply Current VCC = Max., CS > VIH Commercial IOUT = 0 mA Military 120 mA VPP Programming Supply Voltage IPP Programming Supply Current VIHP Input HIGH Programming Voltage VILP Input LOW Programming Voltage [5] 120 130 12 13 12 50 3.0 13 V 50 mA 3.0 0.4 V 0.4 V Notes: 1. Contact a Cypress representative for industrial temperature range specifications. 2. TA is the “instant on” case temperature. 3. See the last page of this specification for Group A subgroup testing information. 4. See “Introduction to CMOS PROMs” in this Book for general information on testing. 5. For devices using the synchronous enable, the device must be clocked after applying these voltages to perform this measurement. 6. For test purposes, not more than one output at a time should be shorted. Short circuit test duration should not exceed 30 seconds. Document #: 38-04006 Rev. ** Page 2 of 13 CY7C277 Capacitance[4] Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions Max. Unit 10 pF 10 pF TA = 25°C, f = 1 MHz, VCC = 5.0V AC Test Loads and Waveforms[4] R1 500Ω (658Ω MIL) 5V R1 500Ω (658Ω MIL) 5V OUTPUT ALL INPUT PULSES OUTPUT R2 5 pF 333Ω (403Ω MIL) INCLUDING JIG AND SCOPE 30 pF INCLUDING JIG AND SCOPE (a) NormalLoad Equivalent to: 3.0V R2 333Ω (403Ω MIL) 90% 10% 90% 10% GND < 5 ns < 5 ns (b) High Z Load THÉVENIN EQUIVALENT 200Ω OUTPUT 2.0V 250Ω OUTPUT 1.9V Military Commercial CY7C277 Switching Characteristics Over the Operating Range[3, 4] 7C277-30 Parameter Description Min. Max. 7C277-40 Min. Max. 7C277-50 Min. Max. Unit tAL Address Set-Up to ALE Inactive 5 10 10 ns tLA Address Hold from ALE Inactive 10 10 15 ns tLL ALE Pulse Width 10 10 15 ns tSA Address Set-Up to Clock HIGH 30 40 50 ns tHA Address Hold from Clock HIGH 0 0 0 ns tSES ES Set-Up to Clock HIGH 12 15 15 ns tHES ES Hold from Clock HIGH 5 tCO Clock HIGH to Output Valid tPWC Clock Pulse Width tLZC[7] Output Valid from Clock HIGH 15 20 30 ns tHZC Output High Z from Clock HIGH 15 20 30 ns tLZE[8] Output Valid from E LOW 15 20 30 ns tHZE[8] Output High Z from E HIGH 15 20 30 ns 10 15 15 10 20 20 ns 25 20 ns ns Notes: 7. Applies only when the synchronous (ES) function is used. 8. Applies only when the asynchronous (E) function is used. Document #: 38-04006 Rev. ** Page 3 of 13 CY7C277 Architecture Configuration Bits Architecture Bit Architecture Verify D7 - D0 ALE D1 ALEP D2 E/ES D0 Function 0 = DEFAULT Input Transparent 1 = PGMED Input Latched 0 = DEFAULT ALE = Active HIGH 1 = PGMED ALE = Active LOW 0 = DEFAULT Asynchronous Output Enable (E) 1 = PGMED Synchronous Output Enable (ES) Architecture Byte (8000) D7 D0 C7 C6 C5 C4 C3 C2 C1 C0 Bit Map Programmer Address (Hex.) 0000 . . . 7FFF 8000 RAM Data Data . . . Data Control Byte Timing Diagram (Input Latched)[9] A0 - A14 tAL ALE ES (SYNCH) CP tLA tSA tHA tLL tHES tCO tSES tPWC tHZC tHES tSES tPWC HIGH Z tLZC HIGHZ O0 - O7 tHZE tLZE ES (ASYNCH) Timing Diagram (Input Transparent) A0 - A14 tHA tSA ES (SYNCH) CP tHES tCO tSES tHZC tPWC tHES tSES tPWC HIGH Z tLZC HIGHZ O0 - O7 tHZE tLZE ES (ASYNCH) Note: 9. ALE is shown with positive polarity. Document #: 38-04006 Rev. ** Page 4 of 13 CY7C277 Programming Information programming information, including a listing of software packages, please see the PROM Programming Information located at the end of this section. Programming algorithms can be obtained from any Cypress representative. Programming support is available from Cypress as well as from a number of third-party software vendors. For detailed Table 1. Mode Selection Pin Function[10] Read or Output Disable A14–A0 E, ES CP ALE O7–O0 A14–A0 VFY PGM VPP D7–D0 Read A14–A0 VIL VIH VIL O7–O0 Output Disable A14–A0 VIH X X High Z Program A14–A0 VIHP VILP VPP D7–D0 Program Verify A14–A0 VILP VIHP/VILP VPP O7–O0 Program Inhibit A14–A0 VIHP VIHP VPP High Z Blank Check A14–A0 VILP VIHP/VILP VPP O7–O0 Mode Other Note: 10. X = “don’t care” but not to exceed VCC ±5%. 1 2 3 4 5 6 7 8 9 10 11 12 13 28 27 26 14 15 25 24 23 22 21 20 19 18 17 16 VCC A10 A11 A12 A13 A14 VPP PGM VFY D7 D6 D5 D4 D3 A7 A8 A9 NC VCC A10 A11 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D0 D1 D2 GND LCC/PLCC (Opaque Only) Top View A6 A5 A4 A3 A2 A1 A0 NC D0 4 3 2 1 32 31 30 29 5 28 6 27 7 26 8 25 9 24 10 23 11 22 12 21 13 14151617 181920 A12 A13 A14 NC VPP PGM VFY D7 D6 D1 D2 GND NC D3 D4 D5 DIP Top View Figure 1. Programming Pinouts Document #: 38-04006 Rev. ** Page 5 of 13 CY7C277 Typical DC and AC Characteristics NORMALIZED ACCESS TIME 1.2 1.4 NORMALIZED ICC NORMALIZED I CC 1.6 1.2 1.0 TA =25°C f = fMAX 0.8 0.6 4.0 4.5 5.0 5.5 1.1 1.0 0.9 0.8 −55 6.0 25 1.0 0.8 0.6 TA =25°C 0.4 4.0 125 1.4 1.2 1.0 0.8 125 OUTPUT SOURCE CURRENT vs. VOLTAGE 60 30.0 50 25.0 40 30 20 0 1.0 AMBIENT TEMPERATURE (°C) 2.0 3.0 4.0 OUTPUT VOLTAGE (V) OUTPUT SINK CURRENT (mA) 5.5 6.0 20.0 15.0 10.0 TA =25°C VCC =4.5V 5.0 10 0 5.0 TYPICAL ACCESS TIME CHANGE vs. OUTPUT LOADING (ns) 1.6 4.5 SUPPLYVOLTAGE (V) DELTA AA t OUTPUT SOURCE CURRENT (mA) NORMALIZED SET -UP TIME NORMALIZED SET-UP TIME vs. TEMPERATURE 25 1.2 AMBIENTTEMPERATURE (°C) SUPPLYVOLTAGE (V) 0.6 −55 NORMALIZED ACCESS TIME vs. SUPPLY VOLTAGE NORMALIZED SUPPLY CURRENT vs. AMBIENT TEMPERATURE NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE 0.0 0 200 400 600 800 1000 CAPACITANCE (pF) OUTPUT SINK CURRENT vs. OUTPUT VOLTAGE 175 150 125 100 75 VCC =5.0V TA =25°C 50 25 0 0.0 1.0 2.0 3.0 4.0 OUTPUT VOLTAGE (V) C277-12 Document #: 38-04006 Rev. ** Page 6 of 13 CY7C277 Ordering Information[11] Speed (ns) Ordering Code 30 40 50 Package Name Operating Range Package Type CY7C277-30JC J65 32-Lead Plastic Leaded Chip Carrier Commercial CY7C277-30PC P21 28-Lead (300-Mil) Molded DIP CY7C277-30WC W22 28-Lead (300-Mil) Windowed CerDIP CY7C277-40JC J65 32-Lead Plastic Leaded Chip Carrier CY7C277-40PC P21 28-Lead (300-Mil) Molded DIP CY7C277-40WC W22 28-Lead (300-Mil) Windowed CerDIP CY7C277-40DMB D22 28-Lead (300-Mil) CerDIP CY7C277-40KMB K74 28-Lead Rectangular Cerpack CY7C277-40LMB L55 32-Pin Rectangular Leadless Chip Carrier CY7C277-40QMB Q55 32-Pin Windowed Rectangular Leadless Chip Carrier CY7C277-40TMB T74 28-Lead Windowed Cerpack CY7C277-40WMB W22 28-Lead (300-Mil) Windowed CerDIP CY7C277-50JC J65 32-Lead Plastic Leaded Chip Carrier CY7C277-50PC P21 28-Lead (300-Mil) Molded DIP CY7C277-50WC W22 28-Lead (300-Mil) Windowed CerDIP CY7C277-50DMB D22 28-Lead (300-Mil) CerDIP CY7C277-50KMB K74 28-Lead Rectangular Cerpack CY7C277-50LMB L55 32-Pin Rectangular Leadless Chip Carrier CY7C277-50QMB Q55 32-Pin Windowed Rectangular Leadless Chip Carrier CY7C277-50TMB T74 28-Lead Windowed Cerpack CY7C277-50WMB W22 28-Lead (300-Mil) Windowed CerDIP Commercial Military Commercial Military Note: 11. Most of the above products are available in industrial temperature range. Contact a Cypress representative for specifications and product availability. MILITARY SPECIFICATIONS Group A Subgroup Testing DC Characteristics Switching Characteristics Parameter Subgroups Parameter Subgroups VOH 1, 2, 3 tSA 7, 8, 9, 10, 11 VOL 1, 2, 3 tHA 7, 8, 9, 10, 11 VIH 1, 2, 3 tCO 7, 8, 9, 10, 11 VIL 1, 2, 3 IIX 1, 2, 3 IOZ 1, 2, 3 ICC 1, 2, 3 Document #: 38-04006 Rev. ** Page 7 of 13 CY7C277 Package Diagrams 28-Lead (300-Mil) CerDIP D22 MIL-STD-1835 D-15 Config. A 51-80032 32-Lead Plastic Leaded Chip Carrier J65 51-85002-B Document #: 38-04006 Rev. ** Page 8 of 13 CY7C277 Package Diagrams (continued) 28-Lead Rectangular Cerpack K74 MIL-STD-1835 F-11 Config. A 51-80061 Document #: 38-04006 Rev. ** Page 9 of 13 CY7C277 Package Diagrams (continued) 32-Pin Rectangular Leadless Chip Carrier L55 MIL-STD-1835 C-12 51-80068 28-Lead (300-Mil) Molded DIP P21 51-85014-B Document #: 38-04006 Rev. ** Page 10 of 13 CY7C277 Package Diagrams (continued) 32-Pin Windowed Rectangular Leadless Chip Carrier Q55 MIL-STD-1835 C-12 51-80103-*A Document #: 38-04006 Rev. ** Page 11 of 13 CY7C277 Package Diagrams (continued) 28-Lead Windowed Cerpack T74 28-Lead (300-Mil) Windowed CerDIP W22 MIL-STD-1835 D-15 Config. A 51-80087 Document #: 38-04006 Rev. ** Page 12 of 13 © Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY7C277 Document Title: CY7C277 32K x 8 Programmable Registered PROM Document Number: 38-04006 REV. ECN NO. Issue Date Orig. of Change ** 113862 3/8/02 DSG Document #: 38-04006 Rev. ** Description of Change Change from Spec number: 38-00085 to 38-04006 Page 13 of 13