www.fairchildsemi.com FAN5240 Multi-Phase PWM Controller for AMD Mobile AthlonTM and DuronTM Features General Description • • • • • • • • The FAN5240 is a single output 2-Phase synchronous buck controller to power AMD’s mobile CPU core. The FAN5240 includes a 5-bit digital-to-analog converter (DAC) that adjusts the core PWM output voltage from 0.925VDC to 2.0VDC, which may be changed during operation. Special measures are taken to allow the output to transition with controlled slew rate to comply with AMD’s Power Now technology. The FAN5240 includes a precision reference, and a proprietary architecture with integrated compensation providing excellent static and dynamic core voltage regulation. The regulator includes special circuitry which balances the 2 phase currents for maximum efficiency. • • • • • • CPU Core power: 0.925V to 2.0V output range ±1% reference precision over temperature Dynamic voltage setting with 5-bit DAC 5V to 24V input voltage range 2 phase interleaved switching Active droop to reduce output capacitor size Differential remote voltage sense High efficiency: >90% efficiency over wide load range >80% efficiency at light load Excellent dynamic response with Voltage Feed-Forward and Average Current Mode control Dynamic duty cycle clamp minimizes inductor current build up Lossless current sensing on low-side MOSFET or Precision current sensing using sense resistor Fault protections: Over-voltage, Over-current, and Thermal Shut-down Controls: Enable, Forced PWM, Power Good, Power Good Delay QSOP28, TSSOP28 Applications • AMD Mobile Athlon CPU VCORE Regulator • AMD Mobile Duron CPU VCORE Regulator At light loads, when the filter inductor current becomes discontinuous, the controller operates in a hysteretic mode, dramatically improving system efficiency. The hysteretic mode of operation can be inhibited by the FPWM control pin. The FAN5240 monitors the output voltage and issues a PGOOD (Power-Good) when soft start is completed and the output is in regulation. A pin is provided to add delay to PGOOD with an external capacitor. A built-in over-voltage protection (OVP) forces the lower MOSFET on to prevent the output from exceeding a set voltage. The PWM controller's overcurrent circuitry monitors the converter load by sensing the voltage drop across the lower MOSFET. The overcurrent threshold is set by an external resistor. If precision overcurrent protection is required, an optional external current-sense resistor may be used. REV. 1.1.7 8/29/02 FAN5240 PRODUCT SPECIFICATION Typical Application VIN (BATTERY) = 5 to 24V VIN C1 21 VCC +5 C3 28 25 Q1 HDRV1 24 +5 Phase 1 SW1 23 Q2 EN R2 26 PGND1 19 ISNS1 22 14 C5 VCORE + 18 FPWM VID0 VID1 12 ILIM AGND 4 Phase 2 5 20 16 1 13 2 15 6 C16 L2 R4 Q4 8 7 C15 +5 VIN C9 9 VID4 C14 D1 BOOT2 3 10 C13 VCORE D 17 11 VID3 DELAY V CORE R6 C12 VID2 SS Q3 LDRV1 27 PGOOD C8 L1 R1 C10 +5 C7 C4 C11 C2 D2 BOOT1 C6 HDRV2 SW2 Q6 Q5 LDRV2 R3 PGND2 ISNS2 Figure 1. AMD Mobile Athlon/Duron CPU Core Supply Table 1. BOM for Figure 1 Description 2 Qty Ref. Vendor Capacitor 22µF, Ceramic X7R 25V 2 C1, C2 TDK Capacitor 1µF, Ceramic 3 C3,C7,C9 Any Capacitor 0.1µF, Ceramic 6 C4–C6, C8, C11, C12 Any Capacitor 0.22µF, Ceramic 1 C10 Any Capacitor 270µF, 2V, ESR 15mΩ 4 C13–C16 Panasonic 10KΩ, 5% Resistor 2 R1 Any 1KΩ, 1% Resistor 1 R2, R3, R6 Any 56.2KΩ, 1% Resistor 2 R4 Any Part Number EEFUE0D271R Schottky Diode 40V 2 D1, D2 Fairchild MBR0540 Inductor 1.6µH, 20A, 2.4mΩ 1 L1, L2 Panasonic ETQP6F0R8LFA N-Channel SO-8 MOSFET, 11mΩ 1 Q1, Q4 Fairchild FDS6694 N-Channel SO-8 SyncFET™ MOSFET, 6mΩ 1 Q2, Q3, Q5, Q6 Fairchild FDS6676S REV. 1.1.7 8/29/02 PRODUCT SPECIFICATION FAN5240 Pin Configuration LDRV2 PGND2 BOOT2 HDRV2 SW2 ISNS2 VID4 VID3 VID2 VID1 VID0 FPWM ILIM EN 1 2 28 27 VCC 3 4 26 25 PGND1 5 6 24 23 HDRV1 22 7 FAN5240 21 8 LDRV1 BOOT1 SW1 ISNS1 VIN 9 10 20 19 SS 11 12 18 17 VCORE+ 13 14 16 15 DELAY PGOOD VCORED AGND QSOP-28 or TSSOP-28 θJA = 90°C/W Pin Definitions Pin Number Pin Name 1 27 LDRV2 LDRV1 Low-Side Drive. The low-side (lower) MOSFET driver output. 2 26 PGND2 PGND1 Power Ground. The return for the low-side MOSFET driver. 3 25 BOOT2 BOOT1 BOOT. The positive supply for the upper MOSFET driver. Connect as shown in Figure 1. 4 24 HDRV2 HDRV1 High-Side Drive. The high-side (upper) MOSFET driver output. 5 23 SW2 SW1 6 22 ISNS2 ISNS1 Current Sense input. Monitors the voltage drop across the lower MOSFET or external sense resistor for current feedback. 7 - 11 VID4 VID0 Voltage Identification Code. Input to VID DAC. Sets the output voltage according to the codes set as defined in Table 2. These inputs have 1µA internal pull-up. 12 FPWM Forced PWM mode. When logic high, inhibits the chip from entering hysteretic operating mode. If tied low, hysteretic mode will be allowed. 13 ILIM Current Limit. A resistor from this pin to GND sets the current limit. 14 EN ENABLE. This pin enables IC operation when either left open, or pulled up to VCC. Toggling EN will also reset the chip after a latched fault condition. 15 AGND Analog Ground. This is the signal ground reference for the IC. All voltage levels are measured with respect to this pin. 16 DELAY Power Good / Over-Current Delay. A capacitor to GND on this pin delays the PGOOD from going high as well delaying the over-current shutdown. Pin Function Description Switching node. The return for the high-side MOSFET driver. 18 17 VCORE+ VCORE Output Sense. Differential sensing of the output voltage. Used for regulation as VCORE– well as PGOOD, under-voltage and over-voltage protection and monitoring. A resistor in series with this VCORE+ sets the output voltage droop. 19 PGOOD REV. 1.1.7 8/29/02 Power Good Flag. An open-drain output that will pull LOW when the core output below 825mV. PGOOD delays its low to high transition for a time determined by CDELAY when VCORE rises above 875mV. 3 FAN5240 PRODUCT SPECIFICATION Pin Definitions (continued) Pin Number Pin Name 20 SS Soft Start. A capacitor from this pin to GND programs the slew rate of the converter during initialization as well as in operation. This pin is used as the reference against which the output is compared. During initialization, this pin is charged with a 25µA current source. Once this pin reaches 0.5V, its function changes, and it assumes the value of the voltage as set by the VID programming. The current driving this pin is then limited to ±500µA, that together with CSS sets a controlled slew rate for VID code changes. 21 VIN Input voltage from battery. This voltage is used by the oscillator for feed-forward compensation of input voltage variation. 28 VCC VCC. This pin powers the chip. The IC starts to operate when voltage on this pin exceeds 4.6V (UVLO rising) and shuts down when it drops below 4.3V (UVLO falling). Pin Function Description Absolute Maximum Ratings Absolute maximum ratings are the values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Parameter Min. Typ. Max. Units VCC Supply Voltage: 6.5 V VIN 27 V BOOT, SW, HDRV Pins 33 V BOOT to SW 6.5 V All Other Pins –0.3 VCC+0.3 V Junction Temperature (TJ ) –10 150 °C Storage Temperature –65 150 °C 300 °C Lead Soldering Temperature, 10 seconds Recommended Operating Conditions Parameter Min. Typ. Max. Supply Voltage VCC 4.75 5 5.25 V Supply Voltage VIN 6 24 V –20 85 °C Ambient Temperature (TA ) 4 Conditions Units REV. 1.1.7 8/29/02 PRODUCT SPECIFICATION FAN5240 Electrical Specifications (VCC = 5V, VIN = 6V–24V, and TA = recommended operating ambient temperature range using circuit of Figure 1, unless otherwise noted.) Parameter Conditions Min. Typ. Max. Units Power Supplies VCC Current Operating, CL = 10pF 2 mA 10 µA Operating 25 µA Shut-down (EN=0) 1 µA Shut-down (EN=0) VIN Current UVLO Threshold 1 Rising VCC 4.3 4.45 4.6 V Falling VCC 3.8 3.95 4.10 V per Table 2 0.925 Regulator / Control Functions Output voltage 2.00 V Error Amplifier Gain 86 dB Error Amplifier GBW 2.7 MHz Error Amplifier Slew Rate 25 ILIM Voltage RILIM = 30KΩ ILIM THOLDOFF CDELAY = 22nF Over-voltage Threshold 35 µA 0.91 V 1.16 2.2 2.35 mS 2.5 Logic LOW V µS 2 Logic HIGH Phase to Phase current mismatch 30 0.89 Over-voltage Protection delay EN, input threshold V/µS 1 VCORE+ Input Current 0.8 2 V V IC contribution only Guaranteed by design ±5 % Over-Temperature Shut-down 150 °C Over-Temperature Hysteresis 25 °C Output Drivers (note 1) HDRV Output Resistance LDRV Output Resistance Sourcing 3.8 5 Ω Sinking 1.6 3 Ω Sourcing 3.8 5 Ω Sinking 0.8 1.5 Ω 300 345 KHz Oscillator Frequency Ramp Amplitude, pk–pk 255 VIN = 16V Ramp Offset Ramp Gain RampAmplitude ---------------------------------------------V IN 2 V 0.5 V 125 mV/V Reference, DAC and Soft-Start VID input threshold Logic LOW Logic HIGH VID pull-up current 2.0 to VCC DAC output accuracy Soft Start Charging current (ISS) 0.8 V V µA 1 –1 1 % VSS < 90% of Programmed output 20 27 34 µA VSS > 90% of Programmed output 350 500 650 µA Note 1: Guaranteed by slew rate testing. REV. 1.1.7 8/29/02 5 FAN5240 PRODUCT SPECIFICATION Electrical Specifications (continued) Conditions Min. Typ. Max. Units Falling Edge 800 825 850 mV Rising Edge 850 875 900 mV Parameter PGOOD VCORE Lower Threshold PGOOD Output Delay Low to High, CDELAY = 22nF 12 mS PGOOD Output Low IPGOOD = 4mA 0.5 V Leakage Current VPULLUP = 5V 1 µA 5V VDD CBOOT BOOT EN VIN POR/UVLO Q1 SS HYST HDRV HYST L OUT SW VOUT' DAC Soft Start & OVP PGOOD Q2 FPWM VCORE + COUT VDD LDRV VIN Q OSC RAMP CLK PGND PWM S R S/H PWM EA1 PWM/HYST DUTY CYCLE CLAMP A ILIM det. ISNS1-ISNS2 ISNS1+ISNS2 5 MODE ISNS1 CURRENT PROCESSING ISNS2 RSENSE1 RSENSE2 ISNS1 ISNS2 A2 VCORE+ A1 VOUT' 30mA ILIM VCORE- ISNS2-ISNS1 1K TO PH 2 MODULATOR RILIM B R6 Figure 2. IC Block Diagram 6 REV. 1.1.7 8/29/02 PRODUCT SPECIFICATION FAN5240 Circuit Description Output Voltage Programming Overview The output voltage of the converter is programmed by an internal DAC in discrete steps of 25mV from 0.925V to 1.300V and then in 50mV steps from 1.300V to 2.00V: The FAN5240 is a 2-phase, single output power management IC, which supplies the low-voltage, high-current power to modern processors for notebook PCs. Using very few external components, the IC controls a precision programmable synchronous buck converter driving external N-Channel power MOSFETs. The output voltage is adjustable from 0.925V to 2.0V by changing the DAC (VID) code settings (see Table 2). The output voltage of the core converter can be changed on-the-fly with programmable slew rate, which meets a key requirement of AMD's Mobile Athlon/Duron processors. The converter can operate in two modes: fixed frequency PWM, and variable frequency hysteretic depending on the load. At loads lower than the point where filter inductor current becomes discontinuous, hysteretic mode of operation is activated. Switchover from PWM to hysteretic operation at light loads improves the converter's efficiency and prolongs battery run time. As the filter inductor resumes continuous current, the PWM mode of operation is restored. Table 2. Output voltage VID VID4 VID3 VID2 VID1 VID0 VOUT to CPU 1 1 1 1 1 0.000 1 1 1 1 0 0.925 1 1 1 0 1 0.950 1 1 1 0 0 0.975 1 1 0 1 1 1.000 1 1 0 1 0 1.025 1 1 0 0 1 1.050 1 1 0 0 0 1.075 1 0 1 1 1 1.100 1 0 1 1 0 1.125 1 0 1 0 1 1.150 1 0 1 0 0 1.175 1 0 0 1 1 1.200 1 0 0 1 0 1.225 1 0 0 0 1 1.250 1 0 0 0 0 1.275 0 1 1 1 1 0.000 0 1 1 1 0 1.300 0 1 1 0 1 1.350 0 1 1 0 0 1.400 0 1 0 1 1 1.450 0 1 0 1 0 1.500 0 1 0 0 1 1.550 0 1 0 0 0 1.600 0 0 1 1 1 1.650 0 0 1 1 0 1.700 0 0 1 0 1 1.750 0 0 1 0 0 1.800 0 0 0 1 1 1.850 0 0 0 1 0 1.900 0 0 0 0 1 1.950 0 0 0 0 0 2.000 1 - Logic High or open, 0 = Logic Low VID0–4 pins will assume a logic 1 level if left open as each input is pulled up with a 1µA internal current source. REV. 1.1.7 8/29/02 7 FAN5240 PRODUCT SPECIFICATION Initialization, Soft Start and PGOOD Assuming EN is high, FAN5240 is initialized when power is applied on VCC. Should VCC drop below the UVLO threshold, an internal Power-On Reset function disables the chip. The IC attempts to regulate the VCORE output according to the voltage that appears on the SS pin (VSS). During start-up of the converter, this voltage is initially 0, and rises linearly to 90% of the VID programmed voltage via the current supplied to CSS by the 25µA internal current source. The time it takes to reach this threshold is: 0.9 × V VID × C SS T 90% = -------------------------------------------25 (1) where T90% is in seconds if CSS is in µF. At that point, the current source changes to 500µA, which establishes the slew rate of voltage changes at the output in response to changes in VID. This dual slope approach helps to provide safe rise of voltages and currents in the converters during initial start-up and at the same time sets a controlled speed of the core voltage change when the processor commands to do so. 1.5V 1.35V SS EN TDLY PGOOD Figure 3. Soft-Start function CSS typically is chosen based on the slew rate desired in response to a VID change. For example, if the spec requires a 500mV step to occur in 100µS: I SS 500µA C SS = ------------------∆t = ------------------- 100µS = 0.1µF 500mV ∆V DAC (2) Assuming VID is set to 1.5V, with this value of CSS , the time for the output voltage to rise to 0.9 of VVID is found using equation 1: 1.35V × 0.1 T 90% = ------------------------------ = 5.4mS 25 The transition from 90% VID to 100% VID occupies 0.5% of the total soft-start time, so TSS is essentially T90%. 8 The PGOOD delay (TDLY, Figure 3) can be programmed with a capacitor to GND on pin 16 (CDELAY): C DELAY ( in nF ) = 1.8 × TDLY ( in mS ) (3) For 12mS of TDLY, CDELAY = 22nF. CDELAY is typically chosen to provide 1mS of "blanking" for the over-current shut-down (see Over-Current Sensing, on page 12). The following conditions set the PGOOD pin low: 1. Under-voltage - VCORE is below a fixed voltage. 2. Chip shut-down due to over-temperature or over-current as defined below. Converter Operation (see Figure 2) At nominal current the converter operates in fixed frequency PWM mode. The output voltage is compared with a reference voltage set by the DAC, which appears on the SS pin. The derived error signal is amplified by an internally compensated error amplifier and applied to the inverting input of the PWM comparator. To provide output voltage droop for enhanced dynamic load regulation, a signal proportional to the output current is added to the voltage feedback signal at the + input of A1. Since the processor specifies a +100mV/ -50mV tolerance on VCORE, a fixed positive offset of 30 mV is created with a 30µA current source and external 1K resistor. Phase load balancing is accomplished by adding a signal proportional to the difference of the two phase currents before the error amplifier (at nodes A and B). This feedback scheme in conjunction with a PWM ramp proportional to the input voltage allows for fast and stable loop response over a wide range of input voltage and output current variations. For the sake of efficiency and maximum simplicity, the current sense signal is derived from the voltage drop across the lower MOSFET during its conduction time. This current sense signal is used to set droop levels as well as for phase balancing and current limiting. The PWM controller has a built-in duty cycle clamp in the path from the error amplifier to the PWM comparator. During a severe load step, the output signal from the error amp can go to its rail, pushing the duty cycle to almost 100% for a significant amount of time. This could cause a severe rise in the inductor current, especially at high battery voltage, and lead to a long recovery time or even failure of the converter. To prevent this, the output of the error amplifier is clamped to a fixed value after two clock cycles if a large output voltage excursion is detected. Sensitivity of this circuit is set in such a way as not to affect the PWM control during transients normally expected from the load. REV. 1.1.7 8/29/02 PRODUCT SPECIFICATION FAN5240 Operation Mode Control causes the output voltage (as presented at VSNS) to drop below the hysteretic regulation level (20mV below VREF), the mode is changed to PWM on the next clock cycle. This insures the full power required by the increase in output current. The mode-control circuit changes the converter’s mode of operation from PWM to Hysteretic and visa versa, based on the voltage polarity of the SW node when the lower MOSFET is conducting and just before the upper MOSFET turns on. For continuous inductor current, the SW node is negative when the lower MOSFET is conducting and the converters operate in fixed-frequency PWM mode as shown in Figure 4. This mode of operation achieves high efficiency at nominal load. When the load current decreases to the point where the inductor current flows through the lower MOSFET in the ‘reverse’ direction, the SW node becomes positive, and the mode is changed to hysteretic, which achieves higher efficiency at low currents by decreasing the effective switching frequency. In hysteretic mode, the PWM comparator and the error amplifier that provide control in PWM mode are inhibited and the hysteretic comparator is activated. In hysteretic mode the low side MOSFET is operated as a synchronous rectifier, where the voltage across VDS(ON) is monitored, and its gate switched off when VDS(ON) goes positive (current flowing back from the load) blocking reverse conduction The hysteretic comparator initiates a PFM signal to turn on HDRV when the output voltage (at VSNS) falls below the lower threshold (10mV below VREF) and terminates the PFM signal when VSNS rises over the higher threshold (5mV above VREF). To prevent accidental mode change or “mode chatter” the transition from PWM to Hysteretic mode occurs when the SW node is positive for eight consecutive clock cycles (see Figure 4). The polarity of the SW node is sampled at the end of the lower MOSFET's conduction time. At the transition between PWM and hysteretic mode both the upper and lower MOSFETs are turned off. The phase node will ‘ring’ based on the output inductor and the parasitic capacitance on the phase node and settle out at the value of the output voltage. The switching frequency is primarily a function of: The boundary value of inductor current, where current becomes discontinuous, can be estimated by the following expression. ( V IN – V OUT )V OUT I LOAD ( DIS ) = ------------------------------------------------2F SW L OUT V IN 1. Spread between the two hysteretic thresholds 2. ILOAD 3. Output Inductor and Capacitor ESR A transition back to PWM (Continuous Conduction Mode or CCM) mode occurs when the inductor current rises sufficiently to stay positive for 8 consecutive cycles. This occurs when: (4) ∆V HYSTERESIS I LOAD ( CCM ) = ---------------------------------------2 ESR (5) Hysteretic Mode where ∆VHYSTERESIS = 15mV and ESR is the equivalent series resistance of COUT. Conversely, the transition from Hysteretic mode to PWM mode occurs when the SW node is negative for 8 consecutive cycles. Because of the different control mechanisms, the value of the load current where transition into CCM operation takes place is typically higher compared to the load level at which transition into hysteretic mode occurs. A sudden increase in the output current will also cause a change from hysteretic to PWM mode. This load increase causes an instantaneous decrease in the output voltage due to the voltage drop on the output capacitor ESR. If the load VCORE PWM Mode IL Hysteretic Mode 0 1 2 3 4 5 6 7 8 VCORE IL Hysteretic Mode 0 1 2 3 PWM Mode 4 5 6 7 8 Figure 4. Transitioning between PWM and Hysteretic Mode REV. 1.1.7 8/29/02 9 FAN5240 PRODUCT SPECIFICATION Current Processing Section With Active Droop, the output voltage varies with the load as if a resistor were connected in series with the converter’s output, in other words, it's effect is to raise the output resistance of the converter. The following discussion refers to Figure 6. Setting RSENSE Each phase current is sampled about 200nS after the SW node crosses 0V. For proper converter operation, choose an RSENSE value of: 1.2 VCORE VDROOP R DS ( ON ) • I MAX R SENSE = ---------------------------------------40µA which is about 1K for the components in Figure 1. ILOAD Active Droop The core converter incorporates a proprietary output voltage droop method for optimum handling of fast load transients found in modern processors. “Active droop” or voltage positioning is now widely used in the computer power applications. The technique is based on raising the converter voltage at light load in anticipation of a step increase in load current, and conversely, lowering VCORE in anticipation of a step decrease in load current. I MAX Figure 5. Active Droop To get the most from the Active Droop, its magnitude should be scaled to match the output capacitor’s ESR voltage drop. V DROOP = I MAX × ESR (6) Active Droop allows the size and cost of the output capacitors required to handle CPU current transients to be reduced. The reduction may be almost a factor of 2 when compared to a system without Active Droop. S/H B-A ISNS1-ISNS2 A ISNS2 ISNS2-ISNS1 ISNS2 5 Σ V to I B ISNS1 in + ISNS1 R SENSE A-B ISNS1 5 ISNS1 8 LDRV1 in D To A1 (+) PGND1 0.9V ILIM det. 1 2.5V I2 = ILIM RILIM ILIM ILIM mirror Figure 6. Current Limit and Active Droop Circuits 10 REV. 1.1.7 8/29/02 PRODUCT SPECIFICATION FAN5240 Additionally, the CPU power dissipation is also slightly reduced as it is proportional to the applied voltage squared and even slight voltage decrease translates to a measurable reduction in power dissipated. ILOAD upper lim Vout (no droop) VES The current through each RSENSE resistor (ISNS) is sampled shortly after LDRV is turned on. That current is held for the remainder of the cycle, and then injected to produce an offset to VCORE+ through the external 1K resistor (R6 in Figure 1). This creates a voltage at the input to the error amplifier that rises with increasing current, causing the regulator’s output to droop as the current increases. I LOAD • R DS ( ON ) V DROOP = ------------------------------------------3 • R SENSE (7) lower lim upper lim VES Vout droop ≈ ESR lower lim Figure 7. Effect of Active Droop on ESR The processor regulation window including transients is specified as +100mV..–50mV. To accommodate the droop, the output voltage of the converter is raised by about 30mV at no load. The converter response to the load step is shown in Figure 8. At zero load current, the output voltage is raised ~30mV above nominal value of 1.5V. When the load current increases, the output voltage droops down approximately 55mV. Due to use of Active Droop, the converter’s output voltage adaptively changes with the load current allowing better utilization of the regulation window. Gate Driver section The gate control logic translates the internal PWM control signal into the MOSFET gate drive signals providing necessary amplification, level shifting and shoot-through protection. Also, it has functions that help optimize the IC performance over a wide range of operating conditions. Since MOSFET switching time can vary dramatically from type to type and with the input voltage, the gate control logic provides adaptive dead time by monitoring the gate-tosource voltages of both upper and lower MOSFETs. The lower MOSFET drive is not turned on until the gate-tosource voltage of the upper MOSFET has decreased to less than approximately 1 volt. Similarly, the upper MOSFET is not turned on until the gate-to-source voltage of the lower MOSFET has decreased to less than approximately 1 volt. This allows a wide variety of upper and lower MOSFETs to be used without a concern for simultaneous conduction, or shoot-through. There must be a low – resistance, low – inductance path between the driver pin and the MOSFET gate for the adaptive dead-time circuit to work properly. Any delay along that path will subtract from the delay generated by the adaptive dead-time circit and a shoot-through condition may occur. Frequency Loop Compensation Due to the implemented current mode control, the modulator has a single pole response with -1 slope at frequency determined by load 1 F PO = -----------------------2πR O C O Figure 8. Converter response to 5A load step REV. 1.1.7 8/29/02 (8) where RO is load resistance, CO is load capacitance. For this type of modulator Type 2 compensation circuit is usually sufficient. To reduce the number of external components and simplify the design task, the PWM controller has an internally compensated error amplifier. Figure 9 shows a Type 2 amplifier and its response along with the responses of a current mode modulator and of the converter. The Type 2 amplifier, in addition to the pole at the origin, has a zero-pole pair that causes a flat gain region at frequencies between the zero and the pole. 11 FAN5240 PRODUCT SPECIFICATION Over-Current sensing (see Figure 10) C2 When the circuit's current limit signal (“ILIM det” as shown in Figure 6) goes high, a pulse-skipping circuit is activated and a 16-clock cycle counter is started. HDRV will be inhibited as long as the sensed current is higher than the ILIM value. This limits the current supplied by the DC input. R2 C1 R1 VIN – + REF Clock C Err or on ve Am rte p 18 14 0 EAOut ILIM det. 1 ILIM det. 2 r Modulator RESET 16 Clock Counter and Logic Q TIMER START Shut-down DELAY FP0 FZ FP Figure 10. Over-current shut-down delay logic Figure 9. Compensation 1 F Z = ---------------------- = 6 kHz 2πR 2 C 1 (9a) 1 F P = ---------------------- = 600 kHz 2πR 2 C 2 (9b) This region is also associated with phase ‘bump’ or reduced phase shift. The amount of phase shift reduction depends on how wide the region of flat gain is and has a maximum value of 90 degrees. To further simplify the converter compensation, the modulator gain is kept independent of the input voltage variation by providing feed-forward of VIN to the oscillator ramp. The zero frequency, the amplifier high frequency gain and the modulator gain are chosen to satisfy most typical applications. The crossover frequency will appear at the point where the modulator attenuation equals the amplifier high frequency gain. The only task that the system designer has to complete is to specify the output filter capacitors to position the load main pole somewhere within one decade lower than the amplifier zero frequency. With this type of compensation plenty of phase margin is easily achieved due to zero-pole pair phase ‘boost’. Conditional stability may occur only when the main load pole is positioned too much to the left side on the frequency axis due to excessive output filter capacitance. In this case, the ESR zero placed within the 10kHz...50kHz range gives some additional phase ‘boost’. Fortunately, there is an opposite trend in mobile applications to keep the output capacitor as small as possible. Protection The converter output is monitored and protected against short circuit (over-current), and over-voltage conditions. If ILIM det goes high during counts 9-16 of the counter, the overcurrent delay timer is started and the 16-clock counter starts again. This timer delays the shut-down of the chip and its time is a function of the value of CDELAY. C DELAY ( in nF ) T HOLDOFF ( in mS ) = --------------------------------------19 (10) Over-current must detected at least once during the first 8 clock cycles and once during the 2nd 8 clock cycles of the 16-cycle counter for the timer to continue timing. If the overcurrent condition does not occur at least once per 8 clock counts during any clock counter cycle while the timer is high, the timer and the over-current detection circuit are reset, preventing shutdown. The clock counter coutinues to count and look for ILIM det pulses in this manner until either: 1. the IC is shut-down because the timer timed out: If the timer pulse is allowed to finish by timing out, the IC is shut-down and can only be restarted by removing power or toggling the EN pin. 2. ILIM det does not go high at least once per 8 clock counts. In this case, the timer and over-current shutdown logic are reset, and a chip shut-down is averted. PGOOD will go LOW if the IC shuts down from overcurrent. Setting the Current Limit ISNS is compared to the current established when a 0.9 V internal reference drives the ILIM pin. The threshold is determined at the point when the I LOAD • R DS ( ON ) ISNS 0.9V --------------- > -------------- . Since ISNS = ------------------------------------------8 R ILIM R SENSE therefore, 0.9V 8 • ( R SENSE ) R ILIM = --------------- × ----------------------------------R DS ( ON ) I LIMIT 12 (11) REV. 1.1.7 8/29/02 PRODUCT SPECIFICATION FAN5240 Since the tolerance on the current limit is largely dependent on the ratio of the external resistors it is fairly accurate if the voltage drop on the Switching Node side of RSENSE is an accurate representation of the load current. When using the MOSFET as the sensing element, the variation of RDS(ON) causes proportional variation in the ISNS. This value not only varies from device to device, but also has a typical junction temperature coefficient of about 0.4% / °C (consult the MOSFET datasheet for actual values), so the actual current limit set point will decrease propotional to increasing MOSFET die temperature. The same discussion applies to the VDROOP calculation. The over-current comparator is sampled just after LDRV is turned on, when the current is near its peak in the cycle. Assuming 20% inductor ripple current, we can then add 1/2 of the ripple current, or 10%. An additional factor of 1.2 accounts for the inaccuracy in the initial (room temperature) RDS(ON) of the MOSFETs with an additional factor of 1.4 to accommodate the rise of the MOSFET RDS(ON) when operating with TJ @ 125°C. With a maximum load current of 12.5A/phase, the target for ILIMIT (per phase) would be: 20A I LIMIT > 1.1 • 1.2 • 1.4 • 12.5A + ----------- ≈ 42A 2 (12c) so using equation 11, with RDS(ON) = 3mΩ for the 2 parallel FDS6688 MOSFETs, RILIM ≈ 56K: Q2 LDRV 21 ISNS Over-Voltage Protection RSENSE R1 22 PGND Figure 11. Improving current sensing accuracy More accurate sensing can be achieved by using a resistor (R1) instead of the RDS(ON) of the FET as shown in Figure 11. This approach causes higher losses, but yields greater accuracy in both VDROOP and ILIMIT. R1 is a low value (e.g. 10mΩ) resistor. The current limit (ILIMIT) set point chosen needs to accommodate ripple current, slew current, and variability in the MOSFET's RDS(ON). dV I LIMIT > I LOAD + C OUT ------dt (12a) Should the output voltage exceed 2.35V due to an upper MOSFET failure, or for other reasons, the overvoltage protection comparator will force the LDRV high. This action actively pulls down the output voltage and, in the event of the upper MOSFET failure, will eventually blow the battery fuse. As soon as the output voltage drops below the threshold, the OVP comparator is disengaged. This OVP scheme provides a ‘soft’ crowbar function which helps to tackle severe load transients and does not invert the output voltage when activated — a common problem for OVP schemes with a latch. Over-Temperature Protection The chip incorporates an over temperature protection circuit that shuts the chip down when a die temperature of 150°C is reached. Normal operation is restored at die temperature below 125°C with internal Power On Reset asserted, resulting in a full soft-start cycle. dV dt Slew current ( C OUT ------- ) is the current required for the output voltage to slew upwards during VID code changes, since the circuit will limit the regulator’s output current by dV pulse skipping when ILIMIT is reached. The ------- term we dt used earlier in the discussion (set up by the CSS) was 500mV/100µS or 5V/mS. Assuming COUT of 4000µF, the current required to slew COUT at this rate is: dV C OUT ------- = 4mF • 5V/mS = 20A dt (12b) which is contributed roughly equally from each phase, therefore, 1/2 of the slew current comes from a single phase. REV. 1.1.7 8/29/02 13 FAN5240 PRODUCT SPECIFICATION Design and Component Selection Guidelines As an initial step, define operating voltage range and minimum and maximum load currents for the controller. For this discussion, IOUT Max 25A VIN 5.5 to 21 V VOUT 0.925 to 2 V Output Inductor Selection The minimum practical output inductor value is the one that keeps inductor current just on the boundary of continuous conduction at some minimum load. The industry standard practice is to choose the ripple current to be somewhere from 15% to 35% of the nominal current. At light load, the ripple current also determines the point where the converter will automatically switch to hysteretic mode of operation (IMIN) to sustain high efficiency. The following equations help to choose the proper value of the output filter inductor. ∆V OUT , ∆I = 2 × I MIN = -----------------ESR where ∆I is the inductor ripple current, which we will choose for 20% of the full load current (12.5A in each phase) and ∆VOUT is the maximum output ripple voltage allowed. V IN – V OUT V OUT L = ------------------------------ × -------------F SW × ∆I V IN (13) for this example we’ll use: The load transient requirements are a function of the slew rate (di/dt) and the magnitude of the transient load current. Modern microprocessors produce transient load rates in excess of 10A/µs. High frequency ceramic capacitors placed beneath the processor socket initially supply the transient and reduce the slew rate seen by the bulk capacitors. The bulk capacitor values are generally determined by the total allowable ESR rather than actual capacitance requirements. High frequency decoupling capacitors should be placed as close to the processor power pins as physically possible. Consult with the processor manufacturer for specific decoupling requirements. Use only specialized low-ESR electrolytic capacitors intended for switching-regulator applications for the bulk capacitors. The bulk capacitor’s ESR will determine the output ripple voltage and the initial voltage drop after a transient. In most cases, multiple electrolytic capacitors of small case size perform better than a single large case capacitor. Input Capacitor Selection The input capacitor should be selected by its ripple current rating. For a 2 phase converter, the RMS currents is calculated: I PK 2 I RMS = -------- 2D – 4D 2 (14) This equation produces the worst case value at maximum duty cycle. For our example, that occurs when VIN = 5.5V and VOUT = 2V. For 25A maximum output the maximum RMS current at CIN: I RMS ( MAX ) = 5.6A VIN = 20V, VOUT = 1.5V ∆I = 20% *12.5A (per phase) = 2.5A FSW = 300KHz. Power MOSFET Selection Therefore, L ≈ 1.8µH VIN from 5V to 20V VOUT = 1.5V @ ILOAD(MAX) = 12.5A/phase The inductor's current rating should be chosen per the ILIMIT calculated above. Some transient currents over the inductor current rating may be tolerable if the inductor’s The FAN5240 converter’s output voltage is very low with respect to the input voltage, therefore the Lower MOSFET (Q2) is conducting the full load current for most of the cycle. Therefore, Q2 should be selected to be a MOSFET with low RDS(ON) to minimize conduction losses. dL saturation characteristic ------- is sufficiently “soft”. dI For the example in the following discussion, we will be selecting components for: Output Capacitor Selection The output capacitor serves two major functions in a switching power supply. Along with the inductor it filters the sequence of pulses produced by the switcher, and it supplies the load transient currents. The filtering requirements are a function of the switching frequency and the ripple current allowed, and are usually easy to satisfy in high frequency converters. 14 In contrast, Q1 is on for a maximum of 20% (when VIN = 5V) of the cycle, and its conduction loss will have less of an impact. Q1, however, sees most of the switching losses, so Q1’s primary selection criteria should be gate charge (QG(SW)). REV. 1.1.7 8/29/02 PRODUCT SPECIFICATION FAN5240 High-Side Losses: C ISS CRSS most of tS occurs when VGS = VSP we can use a constant current assumption for the driver to simplify the calculation of tS : CISS VDS Q G ( SW ) Q G ( SW ) t S = --------------------- ≈ -----------------------------------------------------I DRIVER VDD – V SP ----------------------------------------------- R DRIVER + R GATE ID VGS QGS QGD 4.5V VSP VTH t2 For the high-side MOSFET, VDS = VIN, which can be as high as 20V in a typical portable application. Q2, however, switches on or off with its parallel shottky diode conducting, therefore VDS ≈ 0.5V. Since PSW is proportional to VDS , Q2's switching losses are negligible and we can select Q2 based on RDS(ON) only. Care should also be taken to include the delivery of the MOSFET's gate power ( PGATE ) in calculating the power dissipation required for the FAN5240: QG(SW) t1 (16) t3 t4 t5 P GATE = Q G × VDD × F SW CISS = CGS || CGD (17) Low-Side Losses Figure 12. Switching losses and QG Conduction losses for Q2 are given by: VIN 5V 2 P COND = ( 1 – D ) × I OUT × R DS ( ON ) CGD RD 19 HDRV RGATE G where RDS(ON) is the RDS(ON) of the MOSFET at the V V IN the minimum duty cycle for the converter. Since DMIN is 5% CGS 20 (18) OUT highest operating junction temperature and D = -------------is SW for portable computers, (1-D) ≈ 1, further simplifying the calculation. Figure 13. Drive Equivalent Circuit Assuming switching losses are about the same for both the rising edge and falling edge, Q1’s switching losses, as can be seen by Figure 12, are given by: P UPPER = P SW + P COND (15a) V DS × I L P SW = --------------------- × 2 × t S F SW 2 (15b) V OUT 2 P COND = -------------- × I OUT × R DS ( ON ) V IN (15c) The maximum power dissipation (PD(MAX) ) is a function of the maximum allowable die temperature of the low-side MOSFET, the θJ-A, and the maximum allowable ambient temperature rise: T J ( MAX ) – T A ( MAX ) P D ( MAX ) = -----------------------------------------------θJ – A θJ-A, depends primarily on the amount of PCB area that can be devoted to heat sinking (see FSC app note AN-1029 for SO-8 MOSFET thermal information). where RDS(ON) is @TJ(MAX) and: tS is the switching period (rise or fall time) and is predominantly the sum of t2, t3 (Figure 12), a function of the impedance of the driver and the QG(SW) of the MOSFET. Since REV. 1.1.7 8/29/02 15 FAN5240 Layout Considerations Switching converters, even during normal operation, produce short pulses of current which could cause substantial ringing and be a source of EMI if layout constrains are not observed. There are two sets of critical components in a DC-DC converter. The switching power components process large amounts of energy at high rate and are noise generators. The low power components responsible for bias and feedback functions are sensitive to noise. A multi-layer printed circuit board is recommended. Dedicate one solid layer for a ground plane. Dedicate another solid layer as a power plane and break this plane into smaller islands of common voltage levels. Notice all the nodes that are subjected to high dV/dt voltage swing such as SW, HDRV and LDRV, for example. All surrounding circuitry will tend to couple the signals from these nodes through stray capacitance. Do not oversize copper traces connected to these nodes. Do not place traces connected to the feedback components adjacent to these traces. It is not recommended to use High Density Interconnect Systems, or micro-vias on these signals. The use of blind or buried vias should be limited to the low current signals only. The use of normal thermal vias is left to the discretion of the designer. 16 PRODUCT SPECIFICATION Keep the wiring traces from the IC to the MOSFET gate and source as short as possible and capable of handling peak currents of 2A. Minimize the area within the gate-source path to reduce stray inductance and eliminate parasitic ringing at the gate. Locate small critical components like the soft-start capacitor and current sense resistors as close as possible to the respective pins of the IC. The FAN5240 utilizes advanced packaging technology that will have lead pitch of 0.6mm. High performance analog semiconductors utilizing narrow lead spacing may require special considerations in PWB design and manufacturing. It is critical to maintain proper cleanliness of the area surrounding these devices. It is not recommended to use any type of rosin or acid core solder, or the use of flux in either the manufacturing or touch up process as these may contribute to corrosion or enable electromigration and/or eddy currents near the sensitive low current signals. When chemicals such as these are used on or near the PWB, it is suggested that the entire PWB be cleaned and dried completely before applying power. REV. 1.1.7 8/29/02 PRODUCT SPECIFICATION FAN5240 Mechanical Dimensions 28-Pin QSOP Inches Symbol Min. Max. Min. 0.053 0.069 0.004 0.010 0.061 0.008 0.012 0.007 0.010 0.386 0.394 0.150 0.157 0.025 BSC 1.35 1.75 0.10 0.25 1.54 0.20 0.30 0.18 0.25 9.81 10.00 3.81 3.98 0.635 BSC 0.228 0.244 5.80 6.19 h L N α 0.0099 0.016 0.0196 0.050 0.26 0.41 0.49 1.27 28 Notes Max. A A1 A2 B C D E e H 0° Notes: Millimeters 0° Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusions shall not exceed 0.25mm (0.010 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamber on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the maximum number of terminals. 8. Terminal numbers are shown for reference only. 9. Dimension "B" does not include dambar protrusion. Allowable dambar protrusion shall be 0.10mm (0.004 inch) total in excess of "B" dimension at maximum material condition. 9 3 4 5 6 7 28 8° 1. 8° 10. Controlling dimension: INCHES. Converted millimeter dimensions are not necessarily exact. D E A H C A1 A2 B e SEATING PLANE –C– α L LEAD COPLANARITY ccc C REV. 1.1.7 8/29/02 17 FAN5240 PRODUCT SPECIFICATION Mechanical Dimensions 28-Pin TSSOP –A– 9.7 ± 0.1 0.51 TYP 15 28 14 7.72 1.78 3.2 6.4 4.4 ± 0.1 4.16 –B– B A 0.2 ALL Lead Tips 0.65 0.42 PIN # 1 IDENT LAND PATTERN RECOMMENDATION 1.2 MAX 0.1 C ALL LEAD TIPS +0.15 0.90 –0.10 See Detail A 0.09–0.20 –C– 0.10 ± 0.05 0.65 0.19–0.30 0.13 A B C 12.00° Top & Botom R0.16 GAGE PLANE R0.31 DIMENSIONS ARE IN MILLIMETERS .025 0°–8° NOTES: 0.61 ± 0.1 A. Conforms to JEDEC registration MO-153, variation AB, Ref. Note 6, dated 7/93. B. Dimensions are in millimeters. C. Dimensions are exclusive of burrs, mold flash, and tie bar extensions. D Dimensions and Tolerances per ANsI Y14.5M, 1982 18 SEATING PLANE 1.00 DETAIL A REV. 1.1.7 8/29/02 FAN5240 PRODUCT SPECIFICATION Ordering Information Part Number Temperature Range Package Packing FAN5240QSC -10°C to 85°C QSOP-28 Rails FAN5240QSCX -10°C to 85°C QSOP-28 Tape and Reel FAN5240MTC -10°C to 85°C TSSOP-28 Rails FAN5240MTCX -10°C to 85°C TSSOP-28 Tape and Reel DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com 8/29/02 0.0m 003 Stock#DS30005240 2002 Fairchild Semiconductor Corporation