-.. CMOS10- & 12-BitMonolithic Multiplying OfA Converters ANALOG W DEVICES AD7520/AD7521 I 1.1 Scope. This specification covers the detail requirements for a 10- and a 12-bit monolithic CMOS multiplying digital-to-analog converters. 1.2 Part Number. OBS The complete part numbers per Tables 1 and 2 of this specification are as follows: Device Part Number -I AD7520SQ/883B AD7521 SQ/883B -2 AD7520TQ/883B AD7521 TQ/883B -3 AD7520UQ/883B AD7521 UQ/883B 1.2.3 Case Outline. OLE TE SeeAppendix 1of General SpecificationADI-M-lOOO:package outline: Q-16-AD7520 Q-18-AD7521 1.3 Absolute Maximum Ratings. (TA = 25°Cunless otherwise noted) VootoGND VREFtOGND Digital Input Voltage Range Output Voltage (Pins 1 and 2) Power Dissipation Upto+75°C Deratesabove+75°C Digital Input Voltage Range +17V ::!:25V VootoGND -IOOmVtoVoo OperatingTemperature Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . StorageTemperature Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450mW 6mW/oC VootoGND - 55°C to + 125°C -65°C to + 150°C 1.5 Thermal Characteristics. Thermal Resistance alC alA = 35°C/W for Q-16 or Q-18 = 120°C/WforQ-16orQ-18 REV.B ~-- 401 AD1520/AD7521 SPECIFICATIONS AD7520 Test Resolption , Symbol Device IRES -1,2,3 I-1 Relative Accuracy ilRA I ,- Sub Group T min-T max 1 10 Sub Sub Group Group 4 2,3 2 2 2 1 1/2 Design Limit " Test ConditionI VDD= +15V Units Bits 1 I -2 1 2 1 -3 1/2 2 1/2 :t LSB Max .. :t ppnifC Max Nonlinearity T empco TCNL -1,2,3 Gain Tempco TCAE -1,2,3 2 20 Output Leakage Current Pin 1 lOUT! -1,2,3 200 200 200 DigitalInputs =VIL. :t nA Max loUTI -1,2,3 200 200 200 Digital Inputs =VIH. :t nA Max Pin2 ' :t ppnifC Max Output Current Settling Time2 tSL -1,2,3 500 To :t 1/2LSB. All Digital Inputs os Max VILto Vm and Vm to VIL. Feedthrough Erro,3 FT -1,2,3 30 VREF=20Vp-p,lookHz,All Reference Input Resistance RIN OBS Digital Input High Voltage Digital Input Low Voltage VIH VIL -1,2,3 -1,2,3 -1,2,3 Digital Input Leakage Current IIN -1,2,3 Output Capacitance Pin 1 Pin 2 COUT! COUTI -1,2,3 -1,2,3 CoU"rI COUTI -1,2,3 -1,2,3 IDD -1,2,3 Pin 1 Pin 2 Supply Current from VDD mVp-pmax DigitalInput = VIL. 5 20 5 20 5 20 2.4 2.4 2.4 Vmin 0.8 Vmax OLE 0.8 0.8 1.0 MeasuredatPin 15. kO min kO Max :t j.LAMax TE 120 37 All Digital Inputs Vm. All Digital Inputs VIH. pF Max pF Max 37 120 All Digital Inputs VIL. All Digital Inputs VIL. pF Max pF Max mA Max 2 2 2 NOTES 'VREF= + tOY, unless otherwise stated. 2Thesedesignlimitsare + 25°C only. 3Feedthrough error can be further minimized by connecting the metal lid to ground. All Digital Inputs VILor Vm. Table 1. REV.B 402 - AD7520/AD7521 Sub Sub Group Group 2,3 TIJIin-Tmax 1 12 Design Limit AD7521 Resolution Symbol Device RES -1,2,3 Relative Accuracy RA Test Sub Group 4 :t LSB max 8 8 -2 4 8 4 4 8 2 2 2 2 20 Units Bits -I -3 Test Condition 1 Voo= + lSV 8 :t ppm/°C max Nonlinearity Tempco TCNL -1,2,3 Gain Tempco TCAE -1,2,3 Output Leakage Current Pin 1 lOUT! -1,2,3 200 200 200 Digital Inputs = VIL.- :t nA max IouT2 -1,2,3 200 200 200 Digital Inputs = V1H- :t nA max -1,2,3 500 :t ppm/°C max OBS Pin 2 Output Current Settling Time2 tSL To :t 1/2LSB. All Digital Inputs ns max V1L to VIH and VIH tOV1L- OLE Feedthrough Error2,3 FT -1,2,3 30 Reference Input Resistance RIN -1,2,3 5 20 5 20 5 20 VREF= 20V pop, 100kHz, All Digital Input = V1LMeasured at Pin 17 mV popmax kil min kil max - TE Vmin Digital Input High Voltage VIH -1,2,3 2.4 2.4 2.4 Digital Input Low Voltage V1L -1,2,3 0,8 0,8 0,8 Digital Input Leakage Current IIN -1,2,3 1.0 Output Capacitance Pin 1 Pin 2 COOT! -1,2,3 COUT2 -1,2,3 120 37 All Digital Inputs VIH All Digital Inputs VIH' pFmax pFmax COOT! COUT2 -1,2,3 -1,2,3 37 120 All Digital Inputs VIL' All Digital Inputs VIL. IDD -1,2,3 2 pF max pF max mAmax Pin 1 Pin 2 Supply Current from VDD 2 2 Vmax :t !-LA max - All Digital Inputs V1Lor VIH- NOTES IV REF = + lOV, unless otherwise stated. 2These design limits are + 25°C only3Feedthrough error can be further minimized by connecting the metal lid to ground- Table2, REV,B --- - -- - --- ----- 4tH AD7520/AD7521 3.2.1 Functional BlockDiagram and Terminal Assignments. 101e VREF 101e 101e 2Ok 201e 2Ok 2Ok loon louT1 I I L__~,.__J I I 0 0 BIT1 (MSB) BIT2 I 0 BIT3 I 1Ok I L JvvI 0 BITN (LSB) RFEEDBACK AD7520: DIGITALINPUTS(DTUTTL/CMOS COMPATIBLE)AD7521: OBS N=10 N=12 OLE BIT 1 (MSB) I 4 BIT 2 BIT 4 BIT 1 (MSBII 4 BIT 12 (LSB) TE 3.2.4 Microcircuit Technology Group. This microcircuitis coveredby technologygroup(80). 4.2.1 Life TestIBurn-In Circuit. Steadystatelifetest isper MIL-STD-883Method 1005.Bum-in isper MIL-STD-883 Method 1015 test condition(B). AD7520 AD7521 +10V loun +10V 1k 1k +15V +15V 2k DATA -- 100k -: STANDARD BURN.IN-DATA LINE 2k IS+15V DATA ONEPERBOARD 100k ":" "-ONEPERBOARD STANDARD BURN.IN-DATA LINE IS +15V REV.B 404 -.. CMOS10- & 12-Bit Monolithic ANALOG W DEVICES 0/A Converters Multiplying AD7520,AD7521 I I FEATURES AD7520: 10-Bit Resolution AD7521: 12-Bit Resolution End Point Linearity: 8-,9- and 10-Bit Nonlinearity Tempco: 2ppm of FSRfc Low Power Dissipation: 2OmW Current Settling Time: 5OOns Feedthrough Error: 1/2LSB @ 100kHz TTL/DTL/CMOS Compatible AD7520, AD752I FUNCTIONAL 101< 101< BLOCK DIAGRAM 101< VREF 2Ok OBS 201< 201< 201< 20k IoUT2 Note: AD7533 i. recommended for new 10-bit designs. AD7541A or AD7545 is recommended for new 12-bit designs. louT1 101< RFEEDBACK OLE DIGITAL INPUTS (DTL/TTl/CMOS COMPATIBLE) AD7520: AD752I: Logic: GENERAL DESCRIPTION The AD7520 (AD752I) is a low cost, monolithic to-bit (12-bit) multiplying digital-to-analog converter packaged in a I6-pin (I8-pin) DIP. The devices use advanced CMOS and thin fdm technologies providing up to to-bit accuracy with TTL/ DTL/CMOS compatibility. N=10 N=12 PIN CONFIGURATIONS The AD7520 (AD7521) operates from +5V to +15V supply and dissipates only 20mW, including the ladder network. Typical AD7520 (AD752I) applications include: digital/ analog multiplication, CRT character generation, programmable power supplies, digitally controlled gain circuits, etc. ORDERING BIT 1 IMSBJ I4 BIT 10 IlSBI BIT 1 CMSBI BIT 12 IlSBI INFORMATION TemperatUre Nonlinearity Range to +85°C 16-PIN DIP 0 to +70oC -25°C AD7520JN AD7521JN AD7520JD AD7520SD AD7521JD AD7521SD 0.1% (9-Bit) AD7520KN AD7521KN AD7520KD AD7521KD AD752OTD AD7521TD 0.05% (lo-Bit) AD7520LN AD7521LN AD7520LD AD7521LD AD7520UD AD7521UD 0.2% (8-Bit) TE A switch is closed to 'oUTl for its digital input in a "HIGH" state. -55°C to +125°C 18-PIN DIP PACKAGEIDENTIFICATION 1 Suffix D: Ceramic DIP Package AD7520: (DI6B) AD752I: (DI8B) Suffix N: Plastic DIP Package AD7520 (NI6B) AD752I (NI8B) 1 See Section 19 for package outline information. . SPECIFICA JIONS(Voo=+15,VREF= +10V,TA= +25°Cunlessotherwisenoted) PARAMETER AD7520 DC ACCURACY! Resolution Relative Accuracy (See Figure 5) Nonlineari7 Gain Error 10 Bits 12 Bits J, 0.2% of FSR max (8 Bit) S, 0.2% of FSR max (8 Bit) K, 0.1% of FSR max (9 Bit) T, 0.1% of FSR max (9 Bit) L, 0.05% of FSR max (10 Bit) U, 0.05% of FSR max (10 Bit) . 2ppm Tempco AD7521 of FSR/ C max 0.3% of FSR ty~ Gain Error Tempc02 Output Leakage Current (either output) Power Supply Rejection (See Figure 6) AC ACCURACY lOppm of F!)R/ C max 200nA max 50ppm of FSR/% typ OBS Output Current Settling Time (See Figure 10) . 4 Feedthrough Error (See Figure 9) .. . . . S,T,U: over -55°C to +125°C -10V~VREF~+10V . -10V~VREF~+ 10V -10V~VREF~+10V -lOV~VREF~+lOV . . Over specified temperature . . .. * 500ns typ 5kil min 10kil typ 20kil max 'oun 'oun 'oun 'oun 120pF typ 37pF typ 37pF typ 120pF typ Equivalent to 10kil typ Johnson noise Output Noise (both outputs) (See Figure 7) DIGITAL INPUTS5 Low State Threshold High State Threshold Input Current (low to high state) Input Coding POWER REQUIREMENTS Power Supply Voltage Range IDD * * . . * * * * 0.8V max 2.4V min 1JlA typ Binary All digital inputs low to high and high to low VREF = 20V p-p, 100kHz All digital inputs low All All All All TE digital digital digital digital inputs inputs inputs inputs Over specified temperature range Over specified temperature range Over specified temperature range See Tables I & II under Applications * * * 20mW typ All digital inputs at GND All digital inputs high or low NOTES Full scale range (FSR) is 10V for unipolar mode and :t10V for bipolar mode. Using the internal RFEEDBACK 3 Ladder and feedback resistor temp co is approximately -1 SOppmf C. I 2 4To minimize feedthrough with the ceramic package, the user must ground grounded, then the feedthrough is lOmV typical and 3OmV maximum. s Digital input levels should Specifications subject VOL. I, 9-154 not go below ground to, change without or exceed the positive notice. DIGITAL-TO-ANALOG CONVERTERS high high low low * +5V to +15V 5nA typ 2mA max Total Dissipation (Including ladder) . range To 0.05% of FSR OLE 10m V p-p max REFERENCE INPUT Input Resistance3 ANALOG OUTPUT Output Capacitance (See Figure 8) . . TEST CONDITIONS the metal supply voltage, lid. If the lid is not otherwise damage may occur. 1000 ABSOLUTE MAXIMUM RATINGS (TA = +25°C DIGITAL INPUT VOLTAGE unless otherwise noted) VDD(toGND) VREF(toGND) Digital Input Voltage Range. Output Voltage (Pin 1, Pin 2) Power Dissipation (package) upto+75°c derates above +75°C by . . Operating Temperature jN,KN,LNVersions jD, KD, LD Versions. . . . SO, TD, UD Versions. . . . Storage Temperature. . .. . . +I7V i25V . . . . . . . . . . . . . VDD to GND . . . . . . . . . . -IOOmV to VDD 450mW . . . . . . . . . . . . . . . .6mW/C ./" -; 1.0 I a "",-I .P +./" ,\1'° 0\-1°"":"" 0.1 Oto+70°C . . . . . . . . . . . -25°C to +85°C . . . . . . . . . . -55°C to +I25°C . . . . . . . . . . -65°C to +I50°C OBS ""vV> 0\1"'/ 0'(>'/ 0.01 / ./ 0.001 -55 -50 -4D -20 20 0 1. Do not apply voltages higher than VDD or less than GND potential on any terminal except VREF' 2. The digital control inputs are zener protected; however, permanent damage may occur on unconnected units under high energy electrostatic fields. Keep unused units in conductive foam at all times. PERFORMANCE CURVES TA = +25°C, VDD= +15V unlessotherwisenoted OLE Figure 2. Supply Current 1000 IZ w a: a: ::> u I::> 80 120 125 100 ::> 0 ----- vs. Temperature - "" TE 100 ~ 1000 60 40 TEMPERATURE - °C <t "I '" ./'" "[;IGITAL INPUTVOLTAGE= +5V 100 10 1~ 104 <t "- / 10 1~ 107 REFERENCE FREQUENCY - Hz /' I a +5V 10 CAUTION: TYPICAL - 100 Figure 3. Output Current Bandwidth .P 700 1! I J 1.0 ..w I I DIGITAL INPUT VOLTAGE I / 0.001 5 6 7 8 9 10 VDD 11 - 12 13 = VDD 14 15 16 .!I' .... "' 0 0 0 t: w \ 500 400 :;: Volts t:) z Figure 1. Supply Current vs. Supply Voltage 600 300 "" ....... ::::; IIw en I- Z w a: a: ::> u 200 100 0 2.0 2.5 3.0 3.5 4.0 DIGITAL INPUT VOL TAGE STEP - Volts Figure 4. Output Current Settling Time vs. Digital Input Voltage 4.5 5.0 II CIRCUIT DESCRIPTION RFEEDBACK GENERAL CIRCUIT INFORMATION The AD7520 (AD7521), a to-bit (I2-bit) multiplying D/A converter, consists of a highly stable thin film R-2R ladder and ten (twelve) CMOS current switches on a monolithic chip. Most applications require the addition of only an output operational amplifier and a voltage or current reference. IOUT1 R IREF --- VREF The simplified D/A circuit is shown in Figure 11. An inverted R-2R ladder structure is used - that is, the binarily weighted currents are switched between the loUT! and louT2 bus lines, thus maintaining a constant current in each ladder leg independent of the switch state. OBS 10k VREF 2Ok 10k 20k "" 1Ok11 IOUT2 'CO"", ~"'" Figure 13. AD7520 (AD7521) Equivalent CircuitAl/ Digital Inputs Low 10k 20k EQUIV ALENT CIRCUIT ANALYSIS 20k OLE The equivalent circuits for all digital inpu ts high and all digital inputs low are shown in Figures 13 and 14. In Figure 13 with all digital inputs low, the reference current is switched to louTZ' The current source ILEAKAGE is composed of surface and. IoUT2 IOUT1 I I I I 0 0 BIT 1 (MSB) BIT2 L_--5t-_J L 10k I I 0 0 BIT 3 BIT N (lSB) RFEEDBACK AD7520: DIGITAL INPUTS (DTl/TTL/CMOS COMPATIBLE) AD7521: (Switches shown for TE junction leakages to the substrate while the Id24 Inputs N=10 N=12 "High") Figure 11. AD7520 (AD7521) Functional Diagram One of the CMOS current switches is shown in Figure 12. The geometries of devices 1, 2 and 3 are optimized to make the digital control inputs DTL/TTL/CMOS compatible over the full military temperature range. The input stage drives two inverters (devices 4,5,6 and 7) which in turn drive the two output N-channels. The "ON" resistances of the first six switches are binarilyscaled so the voltage drop across each switch is the same. For example, switch-l of Figure 12 was designed for an "ON" resistance of 20 ohms, switch-2 of 40 ohms and so on. For a 10V reference input, the current through switch 1 is 0.5mA, the current through switch 2 is O.25mA, and so on, thus maintaining a constant 10mV drop across each switch. It is essential that each switch voltage drop be equal if the binarily weighted current division property of the ladder is to be maintained. current source represents a constant I-bit current drain through the termination resistor on the R-2R ladder. The "ON" capacitance of the output N channel switch is 120pF, as shown on the IoUT2 terminal. The "OFF" switch capacitance is 37pF, as shown on the IoUTl terminal. Analysis of the circuit for all digital inputs high, as shown in Figure 14 is similar to Figure 13; however, the "ON" switches are now on terminalloUTl ' hence the 120pF at that terminal. RFEEDBACK --- 'REF R '" 10k11 R VREF R ~ IoUT2 Figure 14. AD7520 DTL/TTL/CMOS INPUT Figure 12. CMOS Switch R 'Dun (AD7521) Al/ Digital Inputs High V+ ( 4~96) Equivalent Circuit- I TEST CIRCUITS Note: +15V VREF The following test circuits apply for the AD7S20. Similar circuits can be used for the AD7S 21. . 2QV P1' 100kHz SINE WAVE 15 DC PARAMETERS BIT 1 IMSOI 10 BIT BINARY COUNTER 13 1~ Ilou12 VOUT 2 BIT 10 (LSB) I. 15 14 5 ~I 16 5 AD7520 -'5V Vo.. I. BIT 1 IMSB) I. ..o..c. ~ ," 1 Ioun LINEARITY AO1520 ~'3 IUBI ERROR X 100 211ou12 Figure 9. Feedthrough Error ""0.0'" JV'I... CLOCK -15V BIT, iMSii 12 BIT REFERENCE OAC +100mV 0JJ..D... -Figure 5. Relative Accuracy OBS +15V UNGROUNDED SINE WAVE GENERATOR 40Hz. -10V Figure 70. Output Current Settling Time 5001< 2V p.p 51< 0.01% VRE> BIT 1 (MSB) I 15 ,. 5. 1611ou11 1 Iou11 AD7520 13 BIT VERnoR X 100 OLE ~B'C. 10 CLSB) TERMINOLOGY RELATIVE ACCURACY: Relative accuracy or end-point nonlinearity is a measure of the maximum deviation from a straight line passing through the end-points of the DAC transfer function. It is measured after adjusting for ideal zero and full scale and is expressed in % or ppm of full scale range or (sub) multiples of lLSB. TE Figure 6. Power Supply Rejection RESOLUTION: Value of the LSB. For example, a unipolar converter with n bits has a resolution ot (2-0) (VREF)' A bipolar converter of n bits has a resolution of [2-(0-1)] [V REF]' Resolution in no way implies linearity. AC PARAMETERS -ITV IADJUST FOR VOUT ~ OV) Ik loon IOk F'lkHz BW'IHz SETTLING TIME: Time required for the output function of the DAC to settle to within 1/2 LSB for a given digital input stimulus, i.e., 0 to Full Scale. OUAN VOUT I .:~g~L 130.0 WAVE ANALYZER O.I.FI. V GAIN: Ratio of the DAC's operational amplifier output voltage to the input voltage. FEEDTHROUGH ERROR: Error caused by capacitive coupling from VREF to output with all switches OFF. < Ik -SOV Figure 7. Noise OUTPUT CAPACITANCE: Capacity from 'oUTl and 'oUT2 terminals to ground. +15V b NC Ik Figure 8. Output Capacitance VOL. I, !J-756 DIGITAL-TO-ANALOGCONVERTERS OUTPUT LEAKAGE CURRENT: Current which appears on 'oUTl terminal with all digital inputs LOW or on 'oUT2 terminal when all inputs are HIGH. APPLICATIONS UNIPOLAR BINARY OPERATION (2-QUADRANT MULTIPLICATION) Figure 15 shows the analog circuit connections required for unipolar binary (2-quadrant multiplication) operation. The logic inputs are omitted for clarity. With a dc reference voltage or current (positive or negative polarity) applied at pin 15, the circuit is a unipolar D/ A converter. With an ac reference voltage or current the circuit provides 2-quadrant multiplication (digitally controlled attenuation). The input/output relationship is shown in Table I. Protection Schottky shown in Figure 15 is not required when using TRlFET output amplifiers such as the AD542 or AD544. R1 provides full scale trim capability [i.e.-load the DAC register to 11 1111 1111, adjsut R1 for VOUT = -VREF (1 - 2-1°)]. Alternatively, Full Scale can be adjusted by omitting Rl and R2 and trimming the reference voltage magnitude. OBS C1 phase compensation (10 to 25pF) may be required for stability when using high speed amplifiers. (C1 is used to cancel the pole formed by the DAC internal feedback resistance and output capacitance at loUT 1). BIPOLAR OPERATION (4-QUADRANT MULTIPLICATION) Figure 16 and Table II illustrate the circuitry and code relationship for bipolar operation. With a dc reference (positive or negative polarity) or an ac reference the circuit provides offset biiuty operation. Protection Schottky shown in Figure 16 is not required when using TRlFET output amplifiers such as the AD542 or AD544. With the DAC register loaded to 10 0000 0000, adjust R1 for VOUT = OV (alternatively, one can omit R1 and R2 and adjust the ratio of R3 to R4 for VOUT = OV). Offset Adjustment 1. Make VREF approximately 2. Tie all digital inputs to +15V (Logic "I"). 3. Adjust amplifier #2 offset trimpot for OV :tlmV at amplifier #2 output. 4. Tie MSB (Bit 1) to +15V, all other bits to ground. 5. Adjust amplifier #1 offset trimpot for OV :tlmV at VOUT' OLE DIGITAL INPUT 1111111111 1000000001 1000000000 0111111111 GNO NOTE: lOGIC INPUTSOMITTED FOR CLARITY. Figure 15. Unipolar Binary Operation (2-Quadrant Multiplication) -VREF (1 - 2-1°) 1 11 1 11 1000000001 VREF (1 - Z-9) 0000000000 VREF = 2-9 VREF -VREF -L 11 1 1 1 111 VDD +15V . an "'0 15 14 1-CI -,- 22DF R4 20k I Your -VREF (Z-1O) 0 0000000000 1 LSB Bipolar (Offset Binary) Operation -VREF (1/2 - 2-1°) 0000000001 NOTE: - -VREF (1/2 + 2-1°) 1000000000 01 -VREF (1 - 2-9) 0000000001 NOTE: 1 LSB UOV VREF TE ANALOG OUTPUT VREF (2-9) Table II. Code Table 1 1 11 +10V. -VREF (2-9) 0 Your ANALOG OUTPUT = 2-10 VREF NOTE: lOGIC INPUTS OMITTEDFOR CLARITY. Table I. Code Table - Unipolar Binary Operation Figure 16. Bipolar Operation (4-Quadrant Multiplication) VOL. I, 9-158 can As in unipolar operation, Al must be chosen for low Vas and low lB' R3, R4 and R5 must be selected for matching and tracking. Mismatch of 2R3 to R4 causes both offset and Full Scale error. Mismatch of R5 to R4 or 2R3 causes Full Scale error. Cl phase compensation (lOpF to 25pF) may be required for stability. Amplifier Al should be selected or trimmed to provide Vas < 10% of the voltage resolution at VOUT' Additionally, the amplifier should exhibit a bias current which is low over the temperature range of interest (bias current causes output offset at VOUT equal to lB times the DAC feedback resistance, nominally 15kD.). DIGITAL INPUT Full scale trimming be accomplished by adjusting the amplitude of VREF or by varying the value of R5. DIGITAL-TO-ANALOG CONVERTERS Applications 10-BIT AND SIGN MULTIPLYING DAC Figure 17 shows an alternative method of achieving bipolar output. The circuit operates with sign plus magnitude code and has the advantage that it gives lO-bit resolution in each quadrant. The 10 magnitude bits provide digitally controlled attenuation ity control. over switch. error. Table Figure 17. of the reference while the sign bit provides polarThe AD7512 is a fully protected CMOS changeMismatch between R4 and R5 introduces a gain III shows the Code Table for the circuit of nov BIPOLAR ANALOG INPUT Binary Numbers in DAC Register 11 11111111 Analog Output +VIN' 1 - Z-10 0 00 0000 0000 0 Volts 1 00 0000 0000 0 Volts 1 1111111111 -VIN' Sign Bit 0 OBS Figure 17. 10-Bitand Sign Multiplying DAC Table III. 10-Bit Plus Sign Magnitude Table OLE DIGITALLY PROGRAMMABLE LIMIT DETECTOR TEST VREF +15V INPUT 1 - 2-10 TE The circuit of Figure 18 shows how the AD7520 is used to implement a programmable limit detector. If the test input does not meet the test limit set by the digital input, then the pass/fail output will indicate a fail. (OTO-VREF) FAIL/PASS TEST Figure 18. Programmable Limit Detector VOLTAGE MODE OPERATION The AD7520 can also be used in the voltage-switching mode and the circuit of Figure 19 shows how the DAC can be connected for voltage switching by reversing the roles of the reference input and IOUTl. It is a single supply application with the DAC and the CMOS operational amplifier both powered from a single +15V supply. With a single supply operational amplifier, offset is difficult to remove completely; therefore, some offset may have to be tolerated usually amounting to less than one-half LSB at 3.5V reference. The voltage switching mode permits only a single polarity of input (positive with respect to common). +15V +10V AD584 VREF = 3.5V MAX +5V 0.1"F 14 AD7520 5k +2.5V n DIGITAL INPUT Figure 19. Single Supply Voltage Mode Operation . DIGITAL INPUT BIT 1 BIT 10 IMSBI ILSBI AN ALOG/DIGIT AL DIVISION With the AD7520 connected in its normal multiplying configuration as shown in Figure 15, the transfer function is Vo = -V IN ( Al 21 + A2 22 + A3 23 + . . . An 2n ) 4 5 VIN16 13 141--+15V 2 AD7520 15 where the coefficients Ax assume a value of 1 for an ON bit and 0 for an OFF bit. By connecting the DAC in the feedback of an operational amplifier, as shown in Figure 20, the transfer function becomes Your -VIN Vo = Al ( 21 + A2 22 + A3 23 + . . . An 2n ) Figure 20. Analog/Digital Divider This is division of an analog variable (VIN) by a digital word. With all bits off, the amplifier saturates to its bound, since division by zero isn't defined. With the LSB (Bit 10) ON, the gain is 1024. With all bits ON, the gain is I (:tl LSB). OBS OLE VOL. I, 9-160 DIGITAL-TO-ANALOG CONVERTERS TE