82527 SERIAL COMMUNICATIONS CONTROLLER CONTROLLER AREA NETWORK PROTOCOL Automotive Y Y Y Y Supports CAN Specification 2.0 Ð Standard Data and Remote Frames Ð Extended Data and Remote Frames Programmable Global Mask Ð Standard Message ldentifier Ð Extended Message ldentifier 15 Message Objects of 8-Byte Data Length Ð 14 Tx/Rx Buffers Ð 1 Rx Buffer with Programmable Mask Flexible CPU Interface Ð 8-Bit Multiplexed Ð 16-Bit Multiplexed Ð 8-Bit Non-Multiplexed (Synchronous/Asynchronous) Ð Serial Interface Y Programmable Bit Rate Y Programmable Clock Output Y Flexible Interrupt Structure Y Flexible Status Interface Y Configurable Output Driver Y Configurable Input Comparator Y Two 8-Bit Bidirectional I/O Ports Y 44-Lead PLCC Package Y 44-Lead QFP Package Y Pinout Compatibility with the 82526 The 82527 serial communications controller is a highly integrated device that performs serial communication according to the CAN protocol. It performs all serial communication functions such as transmission and reception of messages, message filtering, transmit search, and interrupt search with minimal interaction from the host microcontroller, or CPU. The 82527 is Intel’s first device to support the standard and extended message frames in CAN Specification 2.0 Part B. It has the capability to transmit, receive, and perform message filtering on extended message frames. Due to the backwardly compatible nature of CAN Specification 2.0, the 82527 also fully supports the standard message frames in CAN Specification 2.0 Part A. The 82527 features a powerful CPU interface that offers flexibility to directly interface to many different CPUs. It can be configured to interface with CPUs using an 8-bit multiplexed, 16-bit multiplexed, or 8-bit non-multiplexed address/data bus for Intel and non-Intel architectures. A flexible serial interface (SPI) is also available when a parallel CPU interface is not required. The 82527 provides storage for 15 message objects of 8-byte data length. Each message object can be configured as either transmit or receive except for the last message object. The last message object is a receive-only buffer with a special mask design to allow select groups of different message identifiers to be received. The 82527 also implements a global masking feature for message filtering. This feature allows the user to globally mask any identifier bits of the incoming message. The programmable global mask can be used for both standard and extended messages. The 82527 PLCC offers hardware, or pinout, compatibility with the 82526. It is pin-to-pin compatible with the 82526 except for pins 9, 30, and 44. These pins are used as chip selects on the 82526 and are used as CPU interface mode selection pins on the 82527. The 82527 is fabricated using Intel’s reliable CHMOS III 5V technology and is available in either 44-lead PLCC or 44-lead QFP for the automotive temperature range ( b 40§ C to a 125§ C). *Other brands and names are the property of their respective owners. Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Intel retains the right to make changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata. COPYRIGHT © INTEL CORPORATION, 1995 December 1995 Order Number: 272250-006 82527 272250 – 1 Figure 1. 82527 Block Diagram 272250 – 2 Figure 2. 44-Pin PLCC Package 2 82527 272250 – 15 Figure 3. 44-Pin QFP Package 3 82527 PIN DESCRIPTION The 82527 pins are described in this section. Table 1 presents the legend for interpreting the pin types. Table 1. Pin Type Legend Symbol I O I/O Description Input only pin Output only pin Pin can be either input or output PIN DESCRIPTIONS Pin Name 4 Pin Type Pin Description VSS1 Ground GROUND connection must be connected externally to a VSS board plane. Provides digital ground. VSS2 Ground GROUND connection must be connected externally to a VSS board plane. Provides ground for analog comparator. VCC Power POWER connection must be connected externally to a 5V DC. Provides power for entire device. XTAL1 I Input for an external clock. XTAL1 (along with XTAL2) are the crystal connections to an internal oscillator. XTAL2 O Push-pull output from the internal oscillator. XTAL2 (along with XTAL1) are the crystal connections to an internal oscillator. If an external oscillator is used XTAL2 must be floated, or not be connected. XTAL2 must not be used as a clock output to drive other CPUs. CLKOUT O Programmable clock output. This output may be used to drive the oscillator of the host microcontroller. RESETÝ I Warm Reset: (VCC remains valid while RESETÝ is asserted), RESETÝ must be driven to a valid low level for 1 ms minimum. Cold Reset: (VCC is driven to a valid level while RESETÝ is asserted), RESETÝ must be driven low for 1 ms minimum measured from a valid VCC level. No falling edge on the reset pin is required during a cold reset event. CSÝ I A low level on this pin enables CPU access to the 82527 device. INTÝ (VCC/2) O O The interrupt pin is an open-drain output to the host microcontroller. VCC/2 is the power supply for the ISO low speed physical layer. The function of this pin is determined by the MUX bit in the CPU Interface Register (Address 02H) as follows: MUX e 1: pin 24 (PLCC) e VCC/2, pin 11 e INTÝ MUX e 0: pin 24 (PLCC) e INTÝ RX0 RX1 I I Inputs from the CAN bus line(s) to the input comparator. A recessive level is read when RX0 l RX1. A dominant level is read when RX1 l RX0. When the CoBy bit (Bus Configuration register) is programmed as a ‘‘1’’, the input comparator is bypassed and RX0 is the CAN bus line input. TX0 TX1 O O Serial data push-pull output to the CAN bus line. During a recessive bit TX0 is high and TX1 is low. During a dominant bit TX0 is low and TX1 is high. 82527 Pin Name Pin Type AD0/A0/ICP AD1/A1/CP AD2/A2/CSAS AD3/A3/STE AD4/A4/MOSI AD5/A5 AD6/A6/SCLK AD7/A7 I/O-I-I I/O-I-I I/O-I-I I/O-I I/O-I-I I/O-I I/O-I-I I/O-I Address/Data bus in 8-bit multiplexed mode. Address bus in 8-bit non-multiplexed mode. Low byte of A/D bus in 16-bit multiplexed mode. In Serial Interface mode, the following pins have the following meaning: AD0: ICP Idle Clock Polarity AD1: CP Clock Phase AD2: CSAS Chip Select Active State AD3: STE Sync Transmit Enable AD6: SCLK Serial Clock Input AD4: MOSI Serial Data Input AD8/D0/P1.0 AD9/D1/P1.1 AD10/D2/P1.2 AD11/D3/P1.3 AD12/D4/P1.4 AD13/D5/P1.5 AD14/D6/P1.6 AD15/D7/P1.7 I/O-O-I/O I/O-O-I/O I/O-O-I/O I/O-O-I/O I/O-O-I/O I/O-O-I/O I/O-O-I/O I/O-O-I/O High byte of A/D bus in 16-bit multiplexed mode. Data bus in 8-bit non-multiplexed mode. Low speed I/O port. P1 pins in 8-bit multiplexed mode and serial mode. Port pins have weak pullups until the port is configured by writing to 9FH and AFH. P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6/INTÝ P2.7/WRHÝ I/O I/O I/O I/O I/O I/O I/O-O I/O-I Pin Description P2 in all modes. P2.6 is INTÝ when MUX e 1 and is open-drain. P2.7 is WRHÝ in 16-bit multiplexed mode. Mode0 Mode1 I I These pins select one of the four parallel interfaces. These pins are weakly held low during reset. Mode1 Mode0 0 0 8-bit multiplexed Ð Intel 0 0 Serial Interface mode entered when RDÝ e 0, WRÝ e 0 upon reset. 0 1 16-bit multiplexed Ð Intel 1 0 8-bit multiplexed Ð non-Intel 1 1 8-bit non-multiplexed ALE/AS I-I ALE used for Intel modes. AS used for non-Intel modes, except Mode 3 this pin must be tied high. RDÝ E I I RDÝ used for Intel modes. E used for non-Intel modes, except Mode 3 Asynchronous this pin must be tied high. WRÝ/WRLÝ R/WÝ I I WRÝ in 8-bit Intel mode and WRLÝ in 16-bit Intel mode. R/WÝ used for non-Intel modes. READY MISO O O READY is an output to synchronize accesses from the host microcontroller to the 82527. READY is an open-drain output to the host microcontroller. MISO is the serial data output for the serial interface mode. DSACK0Ý O DSACK0Ý is an open-drain output to synchronize accesses from the host microcontroller to the 82527. 5 82527 ELECTRICAL CHARACTERISTICS NOTICE: This is a production data sheet. The specifications are subject to change without notice. ABSOLUTE MAXIMUM RATINGS* *WARNING: Stressing the device beyond the ‘‘Absolute Maximum Ratings’’ may cause permanent damage. These are stress ratings only. Operation beyond the ‘‘Operating Conditions’’ is not recommended and extended exposure beyond the ‘‘Operating Conditions’’ may affect device reliability. Storage Temperature ÀÀÀÀÀÀÀÀÀÀ b 60§ C to a 150§ C Voltage from Any Pin to VSS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ b 0.5V to a 7.0V Laboratory testing shows the 82527 will withstand up to 10 mA of injected current into both RX0 and RX1 pins for a total of 20 days without sustaining permanent damage. This high current condition may be the result of shorted signal lines. The 82527 will not function properly if the RX0/RX1 input voltage exceeds VCC a 0.5V. D.C. Characteristics VCC e 5V g 10%; TA e b 40§ C to a 125§ C Symbol 6 Min Max VIL Input Low Voltage (All except RX0, RX1, AD0–AD7 in Mode 3) Parameter b 0.5V 0.8V VIL1 Input Low Voltage for AD0–AD7 in Mode 3 b 0.5V 0.5V VIL2 Input Low Voltage (RX0) for Comparator Bypass Mode 0.5V VIL3 Input Low Voltage for Port 1 and Port 2 Pins Not Used for Interface to Host CPU 0.3 VCC VIH Input High Voltage (All except RX0, RX1, RESETÝ) VIH1 Input High Voltage (RESETÝ) Hysteresis on RESETÝ VIH2 Input High Voltage (RX0) for Comparator Bypass Mode 4.0V VIH3 Input High Voltage for Port 1 and Port 2 Pins Not Used for Interface to Host CPU 0.7 VCC VOL Output Low Voltage (All Outputs except TX0, TX1) VOH Output High Voltage (All Outputs except TX0, TX1, CLOCKOUT) VOHR1 Output High Voltage (CLOCKOUT) ILK Input Leakage Current CIN PIN Capacitance** 3.0V VCC a 0.5V 3.0V 200 mV VCC a 0.5V 0.45V VCC b 0.8V Conditions IOL e 1.6 mA IOH e b 200 mA 0.8 VCC IOH e b 80 mA g 10 mA 10 pF VSS k VIN k VCC fXTAL e 1 KHz 82527 D.C. Characteristics VCC e 5V g 10%; TA e b 40§ C to a 125§ C Symbol Max Conditions ICC Supply Current(1) 50 mA fXTAL e 16 MHz ISLEEP Sleep Current(1) with VCC/2 Output Enabled, No Load with VCC/2 Output Disabled 700 mA 100 mA Powerdown Current(1) 25 mA IPD Parameter Min XTAL1 Clocked NOTES: **Typical value based on characterization data. Port pins are weakly held after reset until the port configuration registers are written (9FH, AFH). 1. All pins are driven to VSS or VCC including RX0 and RX1. PHYSICAL LAYER SPECIFICATIONS Load Condition: 100 pF D.C. Characteristics VCC e 5V g 10%; TA e b 40§ C to a 125§ C RX0/RX1 and TX0/TX1 Min Max b 0.5V VCC a 0.5V Common Mode Range VSS a 1V VCC b 1V Differential Input Threshold g 100 mV Input Voltage Conditions Internal Delay 1: Sum of the Comparator Input Delay and the TX0/TX1 Output Driver Delay 60 ns Load on TX0, TX1 e 100 pF, a 100 mV to b 100 mV RX0/RX1 differential Internal Delay 2: Sum of the RX0 Pin Delay (if the Comparator is Bypassed) and the TX0/TX1 Output Driver Delay 50 ns Load on TX0, TX1 e 100 pF b 10 mA VOUT e VCC b 1.0V Source Current on Each TX0, TX1 Sink Current on Each TX0, TX1 10 mA Input Hysteresis for RX0/RX1 0V VOUT e 1.0V VCC/2 VCC/2 2.38V 2.62V IOUT s 75 mA, VCC e 5V CLOCKOUT SPECIFICATIONS Load Condition: 50 pF Parameter Min Max CLOCKOUT Frequency XTAL/15 XTAL 7 82527 A.C. Characteristics for 8/16-Bit Multiplexed Intel Modes (Modes 0, 1) Conditions: VCC e 5V g 10%, VSS e 0V, TA e b 40§ C to a 125§ C, CL e 100 pF Min Max 1/tXTAL Symbol Oscillator Frequency Parameter 8 MHz 16 MHz 1/tSCLK System Clock Frequency 4 MHz 10 MHz 1/tMCLK Memory Clock Frequency 2 MHz 8 MHz tAVLL Address Valid to ALE Low 7.5 ns tLLAX Address Hold after ALE Low 10 ns tLHLL ALE High Time 30 ns tLLRL ALE Low to RDÝ Low 20 ns tCLLL CSÝ Low to ALE Low 10 ns tQVWH Data Setup to WRÝ High 27 ns tWHQX Input Data Hold after WRÝ High 10 ns tWLWH WRÝ Pulse Width 30 ns tWHLH WRÝ High to Next ALE High 8 ns tWHCH WRÝ High to CSÝ High 0 ns tRLRH RDÝ Pulse Width This time is long enough to initiate a double read cycle by loading the High Speed Registers (04H, 05H), but is too short to READ from 04H and 05H (See tRLDV) 40 ns tRLDV RDÝ Low to Data Valid (Only for Registers 02H, 04H, 05H) 0 ns tRLDV1 RDÝ Low Data to Data Valid (for Registers except 02H, 04H, 05H) for Read Cycle without a Previous Write(1) for Read Cycle with a Previous Write(1) tRHDZ Data Float after RDÝ High tCLYV CSÝ Low to READY Setup Condition: Load Capacitance on the READY Output: 50 pF 8 Conditions 55 ns 1.5 tMCLK a 100 ns 3.5 tMCLK a 100 ns 0 ns 45 ns 32 ns 40 ns tWLYZ WRÝ Low to READY Float for a Write Cycle if No Previous Write is Pending(2) 145 ns tWHYZ End of Last Write to READY Float for a Write Cycle if a Previous Write Cycle is Active(2) 2 tMCLK a 100 ns tRLYZ RDÝ Low to READY Float (for registers except 02H, 04H, 05H) for Read Cycle without a Previous Write(1) for Read Cycle with a Previous Write(1) 2 tMCLK a 100 ns 4 tMCLK a 100 ns VOL e 1.0V VOL e 0.45V 82527 A.C. Characteristics for 8/16-Bit Multiplexed Intel Modes (Modes 0, 1) Conditions: VCC e 5V g 10%, VSS e 0V, TA e b 40§ C to a 125§ C, CL e 100 pF (Continued) Parameter Min Max tWHDV Symbol WRÝ High to Output Data Valid on Port 1/2 tMCLK 2 tMCLK a 500 ns tCOPO CLKOUT Period tCHCL CLKOUT High Period Conditions (CDV a 1) * tOSC(3) (CDV a 1) * (/2 tOSC b 10 (CDV a 1) * (/2 tOSC a 15 NOTES: References to WRÝ also pertain to WRHÝ. 1. Definition of ‘‘read cycle without a previous write’’: The time between the rising edge of WRÝ/WRHÝ (for the previous write cycle) and the falling edge of RDÝ (for the current read cycle) is greater than 2 tMCLK. 2. Definition of ‘‘write cycle with a previous write’’: The time between the rising edge of WRÝ/WRHÝ (for the previous write cycle) and the rising edge of WRÝ/WRHÝ (for the current write cycle) is less than 2 tMCLK. 3. Definition of CDV is the value loaded in the CLKOUT register representing the CLKOUT divisor. A.C. Characteristics for 8/16-Bit Multiplexed Intel Modes (Modes 0, 1) 272250 – 3 9 82527 A.C. Characteristics for 8/16-Bit Multiplexed Intel Modes (Modes 0, 1) Ready Output Timing for a Write Cycle if No Previous Write is Pending 272250 – 4 Ready Output Timing for a Write Cycle if a Previous Write Cycle is Active 272250 – 5 Ready Output Timing for a Read Cycle 272250 – 6 10 82527 A.C. Characteristics for 8-Bit Multiplexed Non-Intel Mode (Mode 2) Conditions: VCC e 5V g 10%, VSS e 0V, TA e b 40§ C to a 125§ C, CL e 100 pF Min Max 1/tXTAL Symbol Oscillator Frequency Parameter 8 MHz 16 MHz 1/tSCLK System Clock Frequency 4 MHz 10 MHz 1/tMCLK Memory Clock Frequency 2 MHz 8 MHz tAVSL Address Valid to AS Low 7.5 ns tSLAX Address Hold after AS Low 10 ns tELDZ Data Float after E Low 0 ns 45 ns tEHDV E High to Data Valid for Registers 02H, 04H, 05H 0 ns 45 ns for Read Cycle without a Previous Write(1) for Read Cycle with a Previous Write (for Registers except for 02H, 04H, 05H) 1.5 tMCLK a 100 ns 3.5 tMCLK a 100 ns tQVEL Data Setup to E Low 30 ns tELQX Input Data Hold after E Low 20 ns tELDV E Low to Output Data Valid on Port 1/2 tMCLK tEHEL E High Time tELEL End of Previous Write (Last E Low) to E Low for a Write Cycle tSHSL AS High Time tRSEH Setup Time of R/WÝ to E High 30 ns tSLEH AS Low to E High 20 ns tCLSL CSÝ Low to AS Low 20 ns tELCH E Low to CSÝ High 0 ns tCOPD CLKOUT Period tCHCL CLKOUT High Period 2 tMCLK a 500 ns 45 ns 2 tMCLK 30 ns (CDV a 1) * tOSC(3) (CDV a 1) * (/2 tOSC b 10 (CDV a 1) * (/2tOSC a 15 NOTES: 1. Definition of ‘‘Read Cycle without a Previous Write’’: The time between the falling edge of E (for the previous write cycle) and the rising edge of E (for the current read cycle) is greater than 2 tMCLK. 2. Definition of ‘‘Write Cycle with a Previous Write’’: The time between the falling edge of E (for the previous write cycle) and the falling edge of E (for the current write cycle) is less than 2 tMCLK. 3. Definition of CDV is the value loaded in the CLKOUT register representing the CLKOUT divisor. 11 82527 A.C. Characteristics for 8-Bit Multiplexed Non-Intel Mode (Mode 2) 272250 – 7 12 82527 A.C. Characteristics for 8-Bit Non-Multiplexed Asynchronous (Mode 3) Conditions: VCC e 5V g 10%, VSS e 0V, TA e b 40§ C to a 125§ C, CL e 100 pF Symbol Min Max 8 MHz 16 MHz 1/tSCLK System Clock Frequency 4 MHz 10 MHz 1/tMCLK Memory Clock Frequency 2 MHz 8 MHz 1/tXTAL Parameter Oscillator Frequency tAVCL Address or R/WÝ Valid to CSÝ Low Setup 3 ns tCLDV CSÝ Low to Data Valid for High Speed Registers (02H, 04H, 05H) 0 ns 55 ns For Low Speed Registers (Read Cycle without Previous Write)(1) 0 ns 1.5 tMCLK a 100 ns For Low Speed Registers (Read Cycle with Previous Write)(1) 0 ns 3.5 tMCLK a 100 ns tKLDV DSACK0Ý Low to Output Data Valid for High Speed Read Register 23 ns For Low Speed Read Register k 0 ns tCHDV 82527 Input Data Hold after CSÝ High 15 ns tCHDH 82527 Output Data Hold after CSÝ High 0 ns tCHDZ CSÝ High to Output Data Float tCHKH1 CSÝ High to DSACK0Ý e 2.4V(3) tCHKH2 CSÝ High to DSACK0Ý e 2.8V tCHKZ CSÝ High to DSACK0Ý Float 0 ns tCHCL CSÝ Width between Successive Cycles 25 ns tCHAI CSÝ High to Address Invalid 7 ns tCHRI CSÝ High to R/WÝ Invalid 5 ns tCLCH CSÝ Width Low 65 ns tDVCH CPU Write Data Valid to CSÝ High 20 ns tCLKL CSÝ Low to DSACK0Ý Low 0 ns 67 ns 0 ns 2 tMCLK a 145 ns 35 ns 0 ns 55 ns 150 ns 100 ns for High Speed Registers and Low Speed Registers Write Access without Previous Write(2) tCHKL End of Previous Write (CSÝ High) to DSACK0Ý Low for a Write Cycle with a Previous Write(2) tCOPD CLKOUT Period tCHCL CLKOUT High Period (CDV a 1) * tOSC(4) (CDV a 1) * (/2 tOSC b 10 (CDV a 1) * (/2 tOSC a 15 NOTES: E and AS must be tied high in this mode. 1. Definition of ‘‘Read Cycle without a Previous Write’’: The time between the rising edge of CSÝ (for the previous write cycle) and the falling edge of CSÝ (for the current read cycle) is greater than 2 tMCLK. 2. Definition of ‘‘Write Cycle without a Previous Write’’: The time between the rising edge of CSÝ (for the previous write cycle) and the rising edge of CSÝ (for the current write cycle) is greater than 2 tMCLK. 3. An on-chip pullup will drive DSACK0Ý to approximately 2.4V. An external pullup is required to drive this signal to a higher voltage. 4. Definition of CDV is the value loaded in the CLKOUT register representing the CLKOUT divisor. 13 82527 A.C. Characteristics for 8-Bit Non-Multiplexed Asynchronous Mode (Mode 3) Timing of the Asynchronous Mode (Read Cycle) 272250 – 10 A.C. Characteristics for 8-Bit Non-Multiplexed Asynchronous Mode (Mode 3) Timing of the Asynchronous Mode (Write Cycle) 272250 – 11 14 82527 A.C. Characteristics for 8-Bit Non-Multiplexed Synchronous Mode (Mode 3) Conditions: VCC e 5V g 10%, VSS e 0V, TA e b 40§ C to a 125§ C, CL e 100 pF Min Max 1/tXTAL Symbol Oscillator Frequency Parameter 8 MHz 16 MHz 1/tSCLK System Clock Frequency 4 MHz 10 MHz 1/tMCLK Memory Clock Frequency 2 MHz 8 MHz tEHDV E High to Data Valid out of High Speed Register (02H, 04H, 05H) 55 ns Read Cycle without Previous Write for Low Speed Registers(1) 1.5 tMCLK a 100 ns Read Cycle with Previous Write for Low Speed Registers(1) 3.5 tMCLK a 100 ns tELDH Data Hold after E Low for a Read Cycle 5 ns tELDZ Data Float after E Low tELDV Data Hold after E Low for a Write Cycle 15 ns tAVEH Address and R/WÝ to E Setup 25 ns tELAV Address and R/WÝ Valid after E Falls 15 ns tCVEH CSÝ Valid to E High 0 ns tELCV CSÝ Valid after E Low 0 ns tDVEL Data Setup to E Low 55 ns tEHEL E Active Width 100 ns tAVAV Start of a Write Cycle after a Previous Write Access 2 tMCLK tAVCL Address or R/WÝ to CSÝ Low Setup 3 ns tCHAI CSÝ High to Address Invalid 7 ns tCOPD CLKOUT Period tCHCL CLKOUT High Period 35 ns (CDV a 1) * tOSC(2) (CDV a 1) * (/2 tOSC b 10 (CDV a 1) * (/2 tOSC a 15 NOTES: 1. Definition of ‘‘Read Cycle without a Previous Write’’: The time between the falling edge of E (for the previous write cycle) and the rising edge of E (for the current read cycle) is greater than 2 tMCLK. 2. Definition of CDV is the value loaded in the CLKOUT register representing the CLKOUT divisor. 15 82527 A.C. Characteristics for 8-Bit Non-Multiplexed Synchronous Mode (Mode 3) Timing of the Synchronous Mode (Read Cycle) 272250 – 8 A.C. Characteristics for 8-Bit Non-Multiplexed Synchronous Mode (Mode 3) Timing of the Synchronous Mode (Write Cycle) 272250 – 9 16 82527 A.C. Characteristics for Serial Interface Mode Conditions: VCC e 5V g 10%, VSS e 0V, TA e b 40§ C to a 125§ C, CL e 100 pF Symbol Parameter Min Max 0.5 MHz 8 MHz 1/SCLK 125 ns 2000 ns Minimum Clock High Time 84 ns tSKLO Minimum Clock Low Time 84 ns tLEAD ENABLE Lead Time 70 ns tLAG Enable Lag Time 109 ns tACC Access Time tPDO Maximum Data Out Delay Time tHO Minimum Data Out Hold Time tDIS Maximum Data Out Disable Time tSETUP Minimum Data Setup Time 35 ns tHOLD Minimum Data Hold Time 84 ns tRISE Maximum Time for Input to go from VOL to VOH 100 ns tFALL Maximum Time for Input to go from VOH to VOL 100 ns tCS Minimum Time between Consecutive CSÝ Assertions tCOPD CLKOUT Period tCHCL CLKOUT High Period SCLK SPI Clock tCYC tSKHI 60 ns 59 ns 0 ns 665 ns 670 ns (CDV a 1) * tOSC(1) (CDV a 1) * (/2 tOSC b 10 (CDV a 1) * (/2 tOSC a 15 NOTE: 1. Definition of CDV is the value loaded in the CLKOUT register representing the CLKOUT divisor. 17 82527 A.C. Characteristics for Serial Interface Mode 272250 – 12 272250 – 13 DATA SHEET REVISION HISTORY A.C. TESTING INPUT Input, Output Waveforms 272250 – 14 NOTE: AC Inputs during testing are driven at VCC b 0.5V for a Logic ‘‘1’’ and 0.1V for a Logic ‘‘0’’. Timing measurements are made at VOH Min for a Logic ‘‘1’’ and VOL Max for a Logic ‘‘0’’. 18 This is the -006 revision of the 82527 data sheet. The following differences exist between the -005 version and the -006 revision. There were no specification changes between the -004 version and the -005 revision. 1. The 82527 44-ld QFP was added to the product description, the pinmap for the QFP package is also included. 2. The pin numbers were removed from the pin description list to accommodate the new 44-ld QFP package. 82527 3. Removed XTAL1 and XTAL2 from the exceptions for VIL spec. XTAL1 VIL is now specified at min e b 0.5V, max e 0.8V. XTAL2 is an output. This is the -004 revision of the 82527 data sheet. The following differences exist between the -003 version and the -004 revision. 4. Removed XTAL1 and XTAL2 from the exceptions for VIH spec. XTAL1 VIH is now specified at min e 3.0V, max e VCC a 0.5V. XTAL2 is an output. 1. Remove notice on page 1 concerning Advance Information Data Sheet. 5. Source and Sink current for TX0 and TX1 were corrected from minimum values to maximum values. 6. Mode 2; The tAVSL specification was decreased to 7.5 ns from 33 ns. 3. Page 4, E pin description, add ‘‘pin tied high in mode 3’’. 4. Page 5, add VIH e 0.7 VCC and VIL e 0.3 VCC for LSIO port pins (pins not used to interface to host-CPU). 7. Mode 2; The tSLAX specification was decreased to 10 ns from 20 ns. 8. Mode 3, Asynchronous; The tDVCH specification was decreased to 20 ns from 32 ns. 5. Page 6, change Differential Input Threshold from MAX spec to MIN spec. 6. Page 6, add Input Hysteresis spec for RX0/RX1 e 0V maximum. 9. All modes; Two specifications were added for CLKOUT. These specifications are tCOPD (CLKOUT Period) e (CDV a 1)*tOSC, and tCHCL (CLKOUT High Period) e min (CDv a 1) * (/2 tOSC b 10 ns and max (CDV a 1) * (/2 tOSC a 15 ns. NOTE: CDV represented the value loaded in the lower nibble of the CLKOUT Register (1FH). 10. Serial Interface Mode; The maximum SCLK (SPI Clock) rate was increased to 8 MHz from 4.2 MHz. The minimum tCYC (1/SCLK) was set at 125 ns from 238 ns to reflect the increased maximum SPI clock rate. 11. MODE0/1, the tWHQX Specifications was decreased to 10 ns from 12.5 ns. 7. Page 7, tLLAX decreased from 20 ns to 10 ns (to interface to 20 MHz C196). 8. Page 7, tQVWH decreased from 30 ns to 27 ns (to interface to 20 MHz C196). 9. Page 7, tWLWH decreased from 40 ns to 30 ns (to interface to 20 MHz C196). 10. Page 7, tRLDV increased from 45 ns to 55 ns. 11. Page 12, tCHKH specification added for VIH e 2.8V e 150 ns. 12. Page 12, tCHAI decreased from 10 ns to 7 ns. 2. Page 4, AS pin description, add ‘‘pin tied high in Asycnhronous mode 3’’. 13. Page 13, timing diagram for tAVCL revised to show common CL low level. 14. Page 14, tCHAI decreased from 10 ns to 7 ns. 19 82527 15. Page 7, tCLLL decreased from 20 ns to 10 ns. 16. Page 3, RESETÝ description addition: Warm reset: (VCC remains valid while RESETÝ is asserted), RESETÝ must be driven to a valid low level for 1 ms minimum. Cold reset: (VCC is driven to a valid level while RESETÝ is asserted, RESETÝ must be driven low for 1 ms minimum measured from a valid VCC level. No falling edge on the reset pin is required during a cold reset event. 17. Page 2, Figure 2: Pin 7 name changed to (WRÝ/WRLÝ)/(R/WÝ) from WRÝ/(R/WÝ). 18. Page 4, pin description name changed to (WRÝ/WRLÝ)/(R/WÝ) from WRÝ/(R/WÝ) and WRÝ in 8-bit Intel mode and WRLÝ in 16-bit Intel mode replaces the description WRÝ used for Intel modes. 19. Page 5, ABSOLUTE MAXIMUM RATINGS addition: Laboratory testing shows the 82527 will withstand up to 10 mA for injected current into both RX0 and RX1 pins for a total of 20 days without sustaining permanent damage. This high current condition may be the result of shorted signal lines. The 82527 will not function properly if the RX0/RX1 input voltage exceeds VCC a 0.5V. 20. Page 12, tCHDV decreased from 25 ns to 15 ns. 21. Page 14, tELDV decreased from 25 ns to 15 ns. 22. Page 7, tAVLL decreased from 20 ns to 7.5 ns. 23. Page 7, tWHQX decreased from 20 ns to 12.5 ns. This is the -003 revision of the 82527 data sheet. The following differences exist between the -002 version and the -003 revision. 1. The data sheet has been revised to ADVANCE from PRELIMINARY, indicating the specifications have been verified through electrical tests. 2. ABSOLUTE MAXIMUM RATINGS have been added. 3. VIL no longer applies to the AD0–AD7 pins in CPU Interface mode 3. 4. VIL1 has been added to specify Input Low Voltage for AD0–AD7 pins in CPU Interface mode 3 as b 0.5V minimum and a 0.5V maximum. 5. ICC supply current has been reduced to 50 mA from 100 mA. 6. Note 2 was added stating during IPD testing, all pins are driven to VSS or VCC, including RX0 and RX1. 7. tAVLL has been decreased to 20 ns from 33 ns. 20 8. tRLDV1 has been decreased to 1.5 tMCLK a 100 ns from 2 tMCLK a 100 ns for a Read Cycle without a previous Write (Modes 0, 1). tRLDV1 has been decreased to 3.5 tMCLK a 100 ns from 4 tMCLK a 100 ns for a Read Cycle with a previous Write (Modes 0, 1). 9. tCLYV has added the condition of VOL e 1.0V for a 32 ns delay. tCLYV is 40 ns for VOL e 0.45 (Modes 0, 1). 10. tWHYZ has been decreased to 2 tMCLK a 100 ns from 2 tMCLK a 145 ns (Modes 0, 1). 11. tEHDV has been decreased to 1.5 tMCLK a 100 ns from 2 tMCLK a 100 ns for a Read Cycle without a previous Write (Mode 2). tEHDV has been decreased to 3.5 tMCLK a 100 ns from 4 tMCLK a 100 ns for a Read Cycle with a previous Write (Mode 2). 12. tELEL has been decreased to 2 tMCLK from 2 tMCLK a 145 ns (Mode 2). 13. tCLDV has been decreased to 55 ns from 65 ns (Mode 3). 14. tCHKH is specified for VIH e 2.4V, decreased from VIH e 3.0V. Note 3 has been added which states an on-chip pullup will drive DSACK0Ý to approximately 2.4V. An external pullup is required to drive this signal to a higher voltage (Mode 3). 15. tCHAI has been increased to 10 ns from 5 ns. tCHAI no longer includes CSÝ High to R/WÝ Invalid (Mode 3). 16. tCHRI e 5 ns has been added to specify CSÝ High to R/WÝ Invalid (Mode 3). 17. tEHDV has been decreased to 55 ns from 65 ns for Reads of the High Speed Registers (Mode 3). 18. tEHDV has been decreased to 1.5 tMCLK a 100 ns from 2 tMCLK a 100 ns for a Read Cycle without a previous Write (Mode 3). tEHDV has been decreased to 3.5 tMCLK a 100 ns from 4 tMCLK a 100 ns for a Read Cycle with a previous Write (Mode 3). 19. The tAVAL specification name has been corrected to tAVAV (Mode 3). 20. tCHAI has been increased to 10 ns from 5 ns (Mode 3). 21. The input voltage in the A.C. Testing Input Diagram have been revised to VCC b 0.5V from 3.0V (high level) and revised to 0.1V from 0.8V (low level). 82527 The following differences exist between the -001 version and the -002 revision. 1. The RAM block in Figure 1. 82527 Block Diagram was previously called DPRAM. 2. The INTÝ/(VCC/2) pin in Figure 2. 44-Pin PLCC Package and in other descriptions was previously called the INTÝ/(VDD/2) pin. 3. The Mode0 and Mode1 pin descriptions were modified to include the following note: These pins are weakly held low during reset. 4. The DSACK0Ý pin description was changed to reflect an open-drain output. 5. VIL1 for RX0 in comparator bypass mode was added. 6. VIH1 hysteresis on RESETÝ was added. 7. VIH2 for RX0 in comparator bypass mode was added. 8. ISLEEP current with VCC/2 output enabled was corrected from 700 mA minimum to 700 mA maximum. 9. ISLEEP current with VCC/2 output disabled was corrected from 100 mA minimum to 100 mA maximum. 10. IPD current was changed from 10 mA minimum to 25 mA maximum. 11. The following note was added to the electrical characteristics: Port pins are weakly held high after reset until the port configuration registers are written (9FH, AFH). 12. The following D.C. Characteristics Specifications have been removed and replaced by the Internal Delay 1 and Internal Delay 2 specifications. These specifications reflect the production test methodology which requires these two delays to be tested together. a. Delay Dominant to Recessive b. Delay Recessive to Dominant c. Input Delay with Comparator Bypassed 13. The following A.C. Characteristics for 8-Bit/ 16-Bit Multiplexed Intel Modes (Modes 0,1) have been changed: a. 1/tMCLK has been increased to 8 MHz from 5 MHz. b. tLLAX has been decreased to 20 ns from 22.5 ns. c. tLLRL has been increased to 20 ns from 0 ns. d. tCLLL has been added. e. tWHLH has been increased to 8 ns from 0 ns. f. tWHCH has been added. tRLDV1 has been added. tWLYH has been changed to tWLYZ to reflect the READY pin is an open-drain output. g. h. i. tWHYH has been changed to tWHYZ to reflect the READY pin is an open-drain output. j. tRLYH has been changed to tRLYZ to reflect the READY pin is an open-drain output. k. tWHDV has been increased to 2 tMCLK a 250 ns from 2 tMCLK a 100 ns. l. The following note was added: References to WRÝ also pertain to WRHÝ. m. The following definition was added for a ‘‘read cycle without a previous write’’: The time between the rising edge of WRÝ/ WRHÝ (for the previous write cycle) and the falling edge of RDÝ (for the current read cycle) is greater than 2 tMCLK. n. The following definition was added for a ‘‘write cycle with a previous write’’: The time between the rising edge of WRÝ/WRHÝ (for the previous write cycle) and the next rising edge of WRÝ/WRHÝ (for the current write cycle) is less than 2 tMCLK. d. Rise Time e. Fall Time 21 82527 14. The timing diagrams for 8-Bit/16-Bit Multiplexed Intel Modes (Modes 0,1) have been changed to show ALE rising before CSÝ falls. 15. The following A.C. Characteristics for 8-Bit Multiplexed Non-Intel Modes (Modes 2) have been changed: a. 1/tMCLK has been increased to 8 MHz from 5 MHz. b. tSLAX has been decreased to 20 ns from 22.5 ns. c. tEVDV has been decreased to (2, 4) tMCLK a 100 ns from (2, 4) tMCLK a 145 ns. d. tELDV minimum has been decreased to tMCLK from tMCLK a 100 ns. e. tELDV maximum has been increased to 2 tMCLK a 500 ns from 2 tMCLK a 100 ns. f. tEHEL for registers except 02H, 04H, 05H has been renamed to tELEL and the specification has been decreased to 2 tMCLK a 145 ns from 4 tMCLK a 145 ns. g. tSLEH has been increased to 20 ns from 0 ns. h. tCLSL has been added. i. tELCH has been added. j. The following definition was added for a ‘‘read cycle without a previous write’’: The time between the falling edge of E (for the previous write cycle) and the rising edge of E (for the current read cycle) is greater than 2 tMCLK. k. The following definition was added for a ‘‘write cycle with a previous write’’: The time between the falling edge of E (for the previous write cycle) and the next falling edge of E (for the current write cycle) is less than 2 tMCLK. 16. The following A.C. Characteristics for 8-Bit NonMultiplexed Asynchronous Mode (Mode 3) have been changed: a. 1/tMCLK has been increased to 8 MHz from 5 MHz. b. tCLDV has been decreased for low speed registers to (2, 4) tMCLK a 100 ns from (2, 4) tMCLK a 145 ns. c. tCHKH comment ‘‘with 3.3 KX Pullup and 100 pF Load’’ has been removed since tCHKH is tested with a current source. d. tCLKL for a Write Access with a Previous Write has been renamed to tCHKL. e. The note ‘‘E and AS must be tied high in this mode’’ has been added. 22 f. The following definition was added for a ‘‘read cycle without a previous write’’: The time between the rising edge of CSÝ (for the previous write cycle) and the falling edge of CSÝ (for the current read cycle) is greater than 2 tMCLK. g. The following definition was added for a ‘‘write cycle with a previous write’’: The time between the rising edge of CSÝ (for the previous write cycle) and the next rising edge of CSÝ (for the current write cycle) is less than 2 tMCLK. 17. The following A.C. Characteristics for 8-Bit NonMultiplexed Synchronous Mode (Mode 3) have been changed: a. 1/tMCLK has been increased to 8 MHz from 5 MHz. b. tELDZ minimum has been removed. c. tAVCL has been added. d. tCHAI has been added. e. The following definition was added for a ‘‘read cycle without a previous write’’: The time between the falling edge of E (for the previous write cycle) and the rising edge of E (for the current read cycle) is greater than 2 tMCLK. f. The following definition was added for a ‘‘write cycle with a previous write’’: The time between the falling edge of E (for the previous write cycle) and the next falling edge of E (for the current write cycle) is less than 2 tMCLK. 18. The following A.C. Characteristics for Serial Interface Mode have been changed: a. tSKHI has been decreased to 84 ns from 119 ns. b. tSKLO has been decreased to 84 ns from 119 ns. c. tPDO has been decreased to 59 ns from 84 ns. d. tSETUP has been decreased to 35 ns from 59 ns. e. tHOLD has been decreased to 84 ns from 109 ns. 19. The note in the A.C. Testing Input diagram referenced VOH was previously named VIH.