ADC1213D065/080/105/125
Dual 12-bit ADC; 65, 80, 105 or 125 Msps
Rev. 02 — 17 June 2009
Objective data sheet
1. General description
The ADC1213D is a dual channel 12-bit Analog-to-Digital Converter (ADC) optimized for
high dynamic performances and low power at sample rates up to 125 Msps. Pipelined
architecture and output error correction ensure the ADC1213D is accurate enough to
guarantee zero missing codes over the entire operating range. Supplied from a 3.3 V
source for analog and a 1.8 V source for the output driver, it can output data in serial
mode, because of the two lanes of differential outputs, which are compliant with the
JESD204A standard. An integrated Serial Peripheral Interface (SPI) allows the user to
easily configure the ADC. A set of IC configurations is also available via the binary level
control pins, which are used at power-up. The device also includes a programmable gain
amplifier with flexible input voltage range.
Excellent dynamic performance is maintained from the baseband to input frequencies of
170 MHz or more, making the ADC1213D ideal for use in communications, imaging and
medicine.
2. Features
n
n
n
n
n
n
SNR, 73 dB
SFDR, 90 dBc
Sample rate up to 125 Msps
Dual channel 12-bit pipelined ADC core
3.3 V, 1.8 V single supplies
Flexible input voltage range:
1 V (p-p) to 2 V (p-p) with 6 dB
programmable fine gain
n 2 configurable serial outputs
n Compliant with JESD204A serial
transmission standard
n INL ± 1 LSB; DNL ± 0.5 LSB
n
n
n
n
n
n
Input bandwidth, 600 MHz
Power dissipation, 995 mW at 80 Msps
SPI interface
Duty cycle stabilizer
High IF capability
Offset binary, 2’s complement, gray
code
n Power-down and Sleep modes
n HVQFN56 package
3. Applications
n Wireless and wired broadband communications
n Spectral analysis
n Portable instrumentation
n Ultrasound equipment
n Imaging systems
ADC1213D065/080/105/125
NXP Semiconductors
Dual 12-bit ADC; 65, 80, 105 or 125 Msps
4. Ordering information
Table 1.
Ordering information
Type number
Sampling
frequency
(Msample/s)
Package
Name
Description
ADC1213D125HN/C1
125
HVQFN56
plastic thermal enhanced very thin quad flat package; SOT684-7
no leads; 56 terminals; body 8 × 8 × 0.85 mm
ADC1213D105HN/C1
105
HVQFN56
plastic thermal enhanced very thin quad flat package; SOT684-7
no leads; 56 terminals; body 8 × 8 × 0.85 mm
ADC1213D080HN/C1
80
HVQFN56
plastic thermal enhanced very thin quad flat package; SOT684-7
no leads; 56 terminals; body 8 × 8 × 0.85 mm
ADC1213D065HN/C1
65
HVQFN56
plastic thermal enhanced very thin quad flat package; SOT684-7
no leads; 56 terminals; body 8 × 8 × 0.85 mm
ADC1213D065_080_105_125_2
Objective data sheet
Version
© NXP B.V. 2009. All rights reserved.
Rev. 02 — 17 June 2009
2 of 38
ADC1213D065/080/105/125
NXP Semiconductors
Dual 12-bit ADC; 65, 80, 105 or 125 Msps
PGA
ERROR
CORRECTION AND
DIGITAL
PROCESSING
CSB
SDIO/DCS
SCLK/DFS
CFG (0 TO 3)
5. Block diagram
SPI INTERFACE
SYNCP
SYNCN
INAP
SWING
OTR
INAM
8b
DLL
PLL
CLKM
ERROR
CORRECTION AND
DIGITAL
PROCESSING
8b
OTR
INBP
T/H
INPUT
STAGE
ADCB CORE
12-BIT
PIPELINED
8b
ENCODER 8b/10b B
CLKP
PGA
SERIALIZER A
CMLAP
OUTPUT BUF A
CMLAN
SERIALIZER B
CMLBP
OUTPUT BUF B
CMLBN
10b
FRAME ASSEMBLY
CLOCK INPUT
STAGE & DUTY
CYCLE CONTROL
8b
ENCODER 8b/10b A
D11 to D0
SCRAMBLER A
ADCA CORE
12-BIT
PIPELINED
SCRAMBLER B
T/H
INPUT
STAGE
10b
D11 to D0
SWING
INBM
SYSTEM
REFERENCE AND
POWER
MANAGEMENT
CLOCK INPUT
STAGE & DUTY
CYCLE CONTROL
Fig 1.
SENSE
VDDD
DGND
VDDA
AGND
RESET
SCRAMBLER
ADC1213D
005aaa120
Block diagram
ADC1213D065_080_105_125_2
Objective data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 02 — 17 June 2009
3 of 38
ADC1213D065/080/105/125
NXP Semiconductors
Dual 12-bit ADC; 65, 80, 105 or 125 Msps
6. Pinning information
43 SYNCP
44 SYNCN
45 DGND
46 VDDD
47 SWING-0
48 SWING_1
49 PLL_LOCK
50 VDDA
51 AGND
52 AGND
53 VDDA
54 SENSE
55 VREF
56 VDDA
6.1 Pinning
INAP
1
42 DGND
INAM
2
41 DGND
VCMA
3
40 VDDD
REFAT
4
39 CMLPA
REFAB
5
38 CMLNA
AGND
6
37 VDDD
CLKP
7
CLKN
8
35 DGND
AGND
9
34 VDDD
36 DGND
ADC1213D
REFBB 10
33 CMLNB
REFBT 11
32 CMLPB
DGND 28
VDDD 27
CFG3 26
CFG2 25
CFG1 24
CFG0 23
SCRAMBLER 22
RESET 21
AGND 20
CSB 19
SDIO/DCS 18
29 DGND
SCLK/DFS 17
30 DGND
INBP 14
VDDA 16
31 VDDD
INBM 13
VDDA 15
VCMB 12
005aaa121
Transparent top view
Fig 2.
Pinning diagram
6.2 Pin description
Table 2.
Pin description
Symbol
Pin
Type [1]
Description
INAP
1
I
channel A complementary analog input
INAM
2
I
channel A analog input
VCMA
3
O
channel A output common voltage
REFAT
4
O
channel A top reference
REFAB
5
O
Channel A bottom reference
AGND
6
G
analog ground
CLKP
7
I
clock input
CLKN
8
I
complementary clock Input
AGND
9
G
analog ground
REFBB
10
O
channel B bottom reference
REFBT
11
O
channel B top reference
VCMB
12
O
channel B output common voltage
INBM
13
I
channel B complementary analog input
ADC1213D065_080_105_125_2
Objective data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 02 — 17 June 2009
4 of 38
ADC1213D065/080/105/125
NXP Semiconductors
Dual 12-bit ADC; 65, 80, 105 or 125 Msps
Table 2.
Pin description …continued
Symbol
Pin
Type [1]
Description
INBP
14
I
channel B analog input
VDDA
15
P
analog power supply 3.3 V
VDDA
16
P
analog power supply 3.3 V
SCLK/DFS
17
I
SPI clock / data format select
SDIO/DCS
18
I/O
SPI data IO/duty cycle stabilizer
CSB
19
I
chip select bar
AGND
20
G
analog ground
RESET
21
I
JEDEC digital IP reset
SCRAMBLER
22
I
scrambler enable /disable
CFG0
23
I/O
JEDEC link config or OTRA
CFG1
24
I/O
JEDEC link config or OTRB
CFG2
25
I/O
JEDEC link config
CFG3
26
I/O
JEDEC link config
VDDD
27
P
digital power supply 1.8 V
DGND
28
G
digital ground
DGND
29
G
digital ground
DGND
30
G
digital ground
VDDD
31
P
digital power supply 1.8 V
CMLPB
32
O
channel B output
CMLNB
33
O
channel B complementary output
VDDD
34
P
digital power supply 1.8 V
DGND
35
G
digital ground
DGND
36
G
digital ground
VDDD
37
P
digital power supply 1.8 V
CMLNA
38
O
channel A complementary output
CMLPA
39
O
channel A output
VDDD
40
P
digital power supply 1.8 V
DGND
41
G
digital ground
DGND
42
G
digital ground
SYNCP
43
I
synchronization from FPGA
SYNCN
44
I
synchronization from FPGA
DGND
45
G
digital ground
VDDD
46
P
digital power supply 1.8 V
SWING_0
47
I
JESD204 serial buffer programmable output swing
SWING_1
48
I
JESD204 serial buffer programmable output swing
PLL_LOCK
49
O
Set when internal PLL is locked
VDDA
50
P
analog power supply 3.3 V
AGND
51
G
analog ground
AGND
52
G
analog ground
VDDA
53
P
analog power supply 3.3 V
SENSE
54
I
reference programming pin
VREF
55
I/O
voltage reference input/output
VDDA
56
P
analog power supply 3.3 V
[1]
P: power supply; G: ground; I: input; O: output; I/O: input/output.
ADC1213D065_080_105_125_2
Objective data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 02 — 17 June 2009
5 of 38
ADC1213D065/080/105/125
NXP Semiconductors
Dual 12-bit ADC; 65, 80, 105 or 125 Msps
7. Limiting values
Table 3.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Min
Max
Unit
analog supply voltage
[1]
2.85
3.6
V
VDDD
digital supply voltage
[2]
1.65
1.95
V
∆VCC
supply voltage difference
<tbd>
<tbd>
V
Tstg
storage temperature
−55
+125
°C
Tamb
ambient temperature
−40
+85
°C
Tj
junction temperature
-
125
°C
VDDA
Conditions
VDDA − VDDD
[1]
The supply voltage VDDA may have any value between −0.5 V and +7.0 V provided that the supply voltage
differences ∆VCC are respected.
[2]
The supply voltage VDDD may have any value between −0.5 V and +5.0 V provided that the supply voltage
differences ∆VCC are respected.
8. Thermal characteristics
Table 4.
Thermal characteristics
Symbol
Parameter
Typ
Unit
Rth(j-a)
thermal resistance from junction to ambient
[1]
20.9[2]
K/W
thermal resistance from junction to case
[1]
<tbd>
K/W
Rth(j-c)
Conditions
[1]
In compliance with JEDEC test board, in free air.
[2]
Value for 4 layers and 36 vias.
9. Static characteristics
Table 5.
Characteristics
Typical values measured at VDDA = 3 V, VDDD = 1.8 V, Tamb = 25 °C and CL = 5 pF.
Min. and max. values are across the full temperature range Tamb = −40 °C to +85 °C at VDDA = 3V, VDDD = 1.8 V ;
Vi (INAP, INBP) − Vi (INAM, INBM) = −1 dBFS; internal reference mode; 100 Ω differential applied to serial outputs; unless
otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Supplies
VDDA
analog supply voltage
2.85
3.0
3.4
V
VDDD
digital supply voltage
1.65
1.8
3.6
V
IDDA
analog supply current
fclk = 125 Msample/s;
fi =70 MHz
-
310
-
mA
IDDD
digital supply current
fclk = 125 Msample/s;
fi = 70 MHz
-
145
-
mA
Ptot
total power dissipation
fclk = 125 Msample/s
-
1177
-
mW
fclk = 105 Msample/s
-
1045
-
mW
fclk = 80 Msample/s
-
995
-
mW
fclk = 65 Msample/s
-
885
-
mW
ADC1213D065_080_105_125_2
Objective data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 02 — 17 June 2009
6 of 38
ADC1213D065/080/105/125
NXP Semiconductors
Dual 12-bit ADC; 65, 80, 105 or 125 Msps
Table 5.
Characteristics …continued
Typical values measured at VDDA = 3 V, VDDD = 1.8 V, Tamb = 25 °C and CL = 5 pF.
Min. and max. values are across the full temperature range Tamb = −40 °C to +85 °C at VDDA = 3V, VDDD = 1.8 V ;
Vi (INAP, INBP) − Vi (INAM, INBM) = −1 dBFS; internal reference mode; 100 Ω differential applied to serial outputs; unless
otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
P
power dissipation
Power-down mode
-
30
-
mW
Standby mode
-
200
-
mW
0.2
0.8
<tbd>
V (p-p)
0.3VDDA
-
0.7VDDA
V
-
V
Digital inputs
Clock inputs: pins CLKP and CLKM, AC coupled
LVPECL, LVDS and Sinewave modes compatible
Vi(clk)dif
differential clock input
voltage
peak-to-peak
LVCMOS mode
VI
input voltage
Logic Inputs: Power-down: pin CF 0 to 3, pin Scrambler , Swing_0, Swing_1
VIL
LOW-level input voltage
-
0
VIH
HIGH-level input voltage
-
0.66VDDD
-
V
IIL
LOW-level input current
−6
-
+6
µA
IIH
HIGH-level input current
−30
-
+30
µA
Serial Peripheral Interface: pin CSB, SDIO, SCLK, pin DFS, pin DCS
VIL
LOW-level input voltage
0
-
0.3VDDA
V
VIH
HIGH-level input voltage
0.7VDDA
-
VDDA
V
IIL
LOW-level input current
−10
-
+10
µA
IIH
HIGH-level input current
−50
-
+50
µA
CI
Input capacitance
-
4
-
pF
Analog inputs: pins INAP and INAM, pins INBP and INBM
II
Input current
−5
-
+5
µA
Ri
input resistance
-
15
-
Ω
CI
input capacitance
-
5
-
pF
VI(cm)
common-mode input
voltage
0.9
1.5
2
V
Bi
input bandwidth
-
600
-
MHz
VI(dif)
differential input voltage
1
-
2
Vpp
Voltage controlled regulator output: pin VCMA, VCMB
VO(cm)
common-mode output
voltage
-
0.5VDDA
-
V
IO(cm)
common-mode output
current
-
<tbd>
-
µA
output
-
0.5 to 1
-
V
input
0.5
-
1
V
-
pin AGND;
VVREF; VDDA
-
V
Reference voltage input/output: pin VREF
VVREF
voltage on pin VREF
Reference mode selection: pin SENSE
VSENSE
voltage on pin SENSE
ADC1213D065_080_105_125_2
Objective data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 02 — 17 June 2009
7 of 38
ADC1213D065/080/105/125
NXP Semiconductors
Dual 12-bit ADC; 65, 80, 105 or 125 Msps
Table 5.
Characteristics …continued
Typical values measured at VDDA = 3 V, VDDD = 1.8 V, Tamb = 25 °C and CL = 5 pF.
Min. and max. values are across the full temperature range Tamb = −40 °C to +85 °C at VDDA = 3V, VDDD = 1.8 V ;
Vi (INAP, INBP) − Vi (INAM, INBM) = −1 dBFS; internal reference mode; 100 Ω differential applied to serial outputs; unless
otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Data outputs: CMLPA, CMLNA
Output levels, VDDD = 1.8 V. {Swing_2, Swing_1, Swing_0} = {0,0,0}
VOL
LOW-level output
voltage
DC coupled, output
-
1.5
-
V
AC coupled
-
1.65
-
V
VOH
HIGH-level output
voltage
DC coupled; output
-
1.8
-
V
AC coupled
-
1.35
-
V
Output levels, VDDD = 1.8 V {Swing_2, Swing_1, Swing_0} = {0,0,1}
VOL
VOH
LOW-level output
voltage
DC coupled; output
-
1.45
-
V
AC coupled
-
1.625
-
V
HIGH-level output
voltage
DC coupled; output
-
1.8
-
V
AC coupled
-
1.275
-
V
Output levels, VDDD = 1.8 V {Swing_2, Swing_1, swing_0} = {0,1,0}
VOL
VOH
LOW-level output
voltage
DC coupled; output
-
1.4
-
V
AC coupled
-
1.6
-
V
HIGH-level output
voltage
DC coupled; output
-
1.8
-
V
AC coupled
-
1.2
-
V
Output levels, VDDD = 1.8 V {Swing_2, Swing_1, Swing_0} = {0,1,1}
VOL
VOH
LOW-level output
voltage
DC coupled; output
-
1.35
-
V
AC coupled
-
1.575
-
V
HIGH-level output
voltage
DC coupled; output
-
1.8
-
V
AC coupled
-
1.125
-
V
Output levels, VDDD = 1.8 V {Swing_2, Swing_1,Swing_0} = {1,0,0}
VOL
LOW-level output
voltage
DC coupled; output
-
1.3
-
V
AC coupled
-
1.55
-
V
VOH
HIGH-level output
voltage
DC coupled; output
-
1.8
-
V
AC coupled
-
1.05
-
V
Serial configuration : SYNC_P, SYNC_N
VIL
LOW-level input voltage
Differential; input
-
0.95
-
V
VIH
High-level input voltage
Differential; input
-
1.47
-
V
−1.25
±0.25
+1.25
LSB
−0.25
±0.12
+0.25
LSB
Accuracy
INL
integral non-linearity
DNL
differential non-linearity
Eoffset
offset error
-
±2
-
mV
EG
gain error
-
± 0.5
-
% FS
no missing codes
guaranteed
ADC1213D065_080_105_125_2
Objective data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 02 — 17 June 2009
8 of 38
ADC1213D065/080/105/125
NXP Semiconductors
Dual 12-bit ADC; 65, 80, 105 or 125 Msps
Table 5.
Characteristics …continued
Typical values measured at VDDA = 3 V, VDDD = 1.8 V, Tamb = 25 °C and CL = 5 pF.
Min. and max. values are across the full temperature range Tamb = −40 °C to +85 °C at VDDA = 3V, VDDD = 1.8 V ;
Vi (INAP, INBP) − Vi (INAM, INBM) = −1 dBFS; internal reference mode; 100 Ω differential applied to serial outputs; unless
otherwise specified.
Symbol
Parameter
MG(CTC)
channel-to-channel gain
matching
Conditions
Min
Typ
Max
Unit
-
<tbd>
-
%
-
35
-
dBc
Supply
PSRR
Power Supply Rejection
Ratio
100 mV (p-p) on VDDA
10. Dynamic characteristics
Table 6.
Characteristics
Typical values measured at VDDA = 3 V, VDDD = 1.8 V, Tamb = 25 °C and CL = 5 pF.
Min. and max. values are across the full temperature range Tamb = −40 °C to +85 °C at VDDA = 3 V, VDDD = 1.8 V ;
Vi (INAP, INBP) − Vi (INAM, INBM) = −1 dBFS; internal reference mode; 100 Ω differential applied to serial outputs; unless
otherwise specified.
Symbol Parameter
Conditions
ADC1213D065 ADC1213D080
ADC1213D105
ADC1213D125
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
fi = 3 MHz
-
94
-
-
94
-
-
96
-
-
96
-
dBc
fi = 30 MHz
-
93
-
-
93
-
-
92
-
-
93
-
dBc
fi = 70 MHz
-
90
-
-
91
-
-
91
-
-
91
-
dBc
fi = 170 MHz
-
88
-
-
88
-
-
85
-
-
85
-
dBc
fi = 3 MHz
-
92
-
-
93
-
-
91
-
-
90
-
dBc
fi = 30 MHz
-
91
-
-
92
-
-
91
-
-
89
-
dBc
fi = 70 MHz
-
90
-
-
90
-
-
90
-
-
87
-
dBc
fi = 170 MHz
-
88
-
-
87
-
-
88
-
-
87
-
dBc
fi = 3 MHz
-
88
-
-
88
-
-
87
-
-
87
-
dBc
fi = 30 MHz
-
87
-
-
87
-
-
87
-
-
86
-
dBc
fi = 70 MHz
-
86
-
-
86
-
-
85
-
-
84
-
dBc
fi = 170 MHz
-
83
-
-
83
-
-
82
-
-
82
-
dBc
fi = 3 MHz
-
11.3 -
-
11.3 -
-
11.3 -
-
11.2 -
Bits
fi = 30 MHz
-
11.2 -
-
11.2 -
-
11.2 -
-
11.2 -
Bits
fi = 70 MHz
-
11.1 -
-
11.1 -
-
11.1 -
-
11.1 -
Bits
fi = 170 MHz
-
11.3 -
-
11.3 -
-
11.3 -
-
11.3 -
Bits
-
tbd
-
-
tbd
-
-
tbd
-
-
tbd
tbd
fi = 3 MHz
-
70.7 -
-
70.6 -
-
70.5 -
-
70.3 -
dBFS
fi = 30 MHz
-
70.2 -
-
70.2 -
-
70.2 -
-
70.1 -
dBFS
fi = 70 MHz
-
69.9 -
-
69.9 -
-
69.8 -
-
69.7 -
dBFS
fi = 170 MHz
-
69.5 -
-
69.5 -
-
69.4 -
-
69.3 -
dBFS
Analog signal processing
α2H
α3H
THD
ENOB
second
harmonic level
third harmonic
level
total harmonic
distortion
effective
number of bits
Nth(RMS) RMS thermal
noise
SNR
signal-to-noise
ratio
ADC1213D065_080_105_125_2
Objective data sheet
-
© NXP B.V. 2009. All rights reserved.
Rev. 02 — 17 June 2009
9 of 38
ADC1213D065/080/105/125
NXP Semiconductors
Dual 12-bit ADC; 65, 80, 105 or 125 Msps
Table 6.
Characteristics …continued
Typical values measured at VDDA = 3 V, VDDD = 1.8 V, Tamb = 25 °C and CL = 5 pF.
Min. and max. values are across the full temperature range Tamb = −40 °C to +85 °C at VDDA = 3 V, VDDD = 1.8 V ;
Vi (INAP, INBP) − Vi (INAM, INBM) = −1 dBFS; internal reference mode; 100 Ω differential applied to serial outputs; unless
otherwise specified.
Symbol Parameter
SFDR
IMD
αct(ch)
Conditions
ADC1213D065 ADC1213D080
ADC1213D105
ADC1213D125
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
fi = 3 MHz
-
91
-
-
91
-
-
90
-
-
90
-
dBc
fi = 30 MHz
-
90
-
-
90
-
-
90
-
-
89
-
dBc
fi = 70 MHz
-
89
-
-
89
-
-
88
-
-
87
-
dBc
fi = 170 MHz
-
86
-
-
86
-
-
85
-
-
85
-
dBc
intermodulation fi = 3 MHz
distortion
fi = 30 MHz
-
94
-
-
94
-
-
93
-
-
93
-
dBc
-
93
-
-
93
-
-
93
-
-
92
-
dBc
fi = 70 MHz
-
92
-
-
92
-
-
91
-
-
90
-
dBc
fi = 170 MHz
-
89
-
-
89
-
-
88
-
-
88
-
dBc
fi = 70 MHz
-
87
-
-
85
-
-
86
-
-
85
-
dB
spurious-free
dynamic range
crosstalk
between
channels
Unit
11. Clock and digital output timing
Table 7.
Characteristics
Typical values measured at VDDA = 3 V, VDDD = 1.8 V, Tamb = 25 °C and CL = 5 pF.
Min. and max. values are across the full temperature range Tamb = −40 °C to +85 °C at VDDA = 3 V, VDDD = 1.8 V ;
VI (INAP, INBP) − VI (INAM, INBM) = −1 dBFS; internal reference mode; 100 Ω differential applied to serial outputs; unless
otherwise specified.
Symbol
Parameter
Conditions
ADC1213D065
ADC1213D080
ADC1213D105
ADC1213D125
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
-
65
60
-
80
60
-
105
60
-
125
Msps
Clock timing input: pins CLKP and CLKM
fclk
clock
frequency
20
tlat(data)
data latency
time
17
-
20
17
-
20
17
-
20
17
-
20
clk/cy
δclk
clock duty
cycle
30
50
70
30
50
70
30
50
70
30
50
70
%
45
50
55
45
50
55
45
50
55
45
50
55
%
td(s)
sampling
delay time
-
0.8
-
-
0.8
-
-
0.8
-
-
0.8
-
ns
twake
wake-up time
-
tbd
-
tbd
-
-
tbd
-
-
tbd
-
ns
DCS en
DCS dis
11.1 Serial output timings
The eye diagram of the serial output is shown in Figure 3 and Figure 4. Test conditions
are:
• 3.125 Gbps data rate
• Tamb = 25 ˚C
• DC coupling with 2 different receiver common-mode voltages.
ADC1213D065_080_105_125_2
Objective data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 02 — 17 June 2009
10 of 38
ADC1213D065/080/105/125
NXP Semiconductors
Dual 12-bit ADC; 65, 80, 105 or 125 Msps
005aaa088
Fig 3. Eye diagram at 1 V receiver Common mode
005aaa089
Fig 4. Eye diagram at 2 V receiver Common mode
12. SPI timing
Table 8.
Characteristics
Typical values measured at VDDA = 3 V, VDDD = 1.8 V, Tamb = 25 °C and CL = 5 pF.
Min. and max. values are across the full temperature range Tamb = −40 °C to +85 °C at VDDA = 3 V, VDDD = 1.8 V ;
Vi (INAP, INBP) − Vi (INAM, INBM) = −1 dBFS; internal reference mode; 100 Ω differential applied to serial outputs; unless
otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Serial Peripheral Interface timings
tw(SCLK)
SCLK pulse width
40
-
-
ns
tw(SCLKH)
SCLK pulse width HIGH
16
-
-
ns
tw(SCLKL)
SCLK pulse width LOW
tsu
set-up time
16
-
-
ns
data to SCLKH
5
-
-
ns
CSB to SCLKH
5
-
-
ns
ADC1213D065_080_105_125_2
Objective data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 02 — 17 June 2009
11 of 38
ADC1213D065/080/105/125
NXP Semiconductors
Dual 12-bit ADC; 65, 80, 105 or 125 Msps
Table 8.
Characteristics …continued
Typical values measured at VDDA = 3 V, VDDD = 1.8 V, Tamb = 25 °C and CL = 5 pF.
Min. and max. values are across the full temperature range Tamb = −40 °C to +85 °C at VDDA = 3 V, VDDD = 1.8 V ;
Vi (INAP, INBP) − Vi (INAM, INBM) = −1 dBFS; internal reference mode; 100 Ω differential applied to serial outputs; unless
otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
th
hold time
data to SCLKH
2
-
-
ns
CSB to SCLKH
2
-
-
ns
-
-
25
MHz
fclk(max)
maximum clock
frequency
13. Application information
13.1 Analog inputs
13.1.1 Input stage description
The ADC1213D inputs can be configured as single-ended or differential (selected via SPI
control bit DIFF/SE; see Table 20). Optimal performance is achieved using differential
inputs with the common-mode input voltage, VI(CM), set to 0.5VDDA.
The full scale analog input voltage range is configurable between ±1 V (p-p) and
±2 V (p-p) via a programmable internal reference (see Section 13.2 and Table 21 for
further details).
The equivalent circuit of the sample and hold input stage, including ESD protection and
circuit and package parasitics, is shown in Figure 5.
Package
ESD
Parasitics
Switch
INAP
INBP
1, 14
INAM
INBM
2, 13
Ron = 14 Ω
4 pF
Sampling
internal Capacitor
clock
Switch
Ron = 14 Ω
4 pF
Sampling
internal Capacitor
clock
005aaa069
Fig 5.
Input sampling circuit
The sample phase HIGH, because of the NMOS transistors. The voltage is then held on
the sampling capacitors. When the clock signal goes LOW, the stage enters the hold
phase and the voltage information is transmitted to the ADC core.
ADC1213D065_080_105_125_2
Objective data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 02 — 17 June 2009
12 of 38
ADC1213D065/080/105/125
NXP Semiconductors
Dual 12-bit ADC; 65, 80, 105 or 125 Msps
13.1.2 Anti-kickback circuitry
Anti-kickback circuitry is needed to counteract the effects of charge injection generated by
the sampling capacitance. This consists of an RC filter containing a resistor in series
(typically 12 Ω to 25 Ω) and a capacitor in parallel (typically 8 pF to 12 pF).
The RC filter is also used to filter noise from the signal before it reaches the sampling
stage. The value of the capacitor should be chosen to maximize noise attenuation without
degrading the settling time too much.
The RC coupling is determined by the input frequency and should be selected so as not to
affect the input bandwidth.
Table 9.
RC coupling versus input frequency
Input frequency
R
C
3 MHz
25 Ω
12 pF
70 MHz
12 Ω
8 pF
170 MHz
12 Ω
8 pF
13.1.3 Transformer
The configuration of the transformer circuit is determined by the input frequency. The
configuration shown in Figure 6 would be suitable for a baseband application.
100 nF
Analog
lnput
100 nF
25 Ω
ADT1-1WT
INAP
INBP
25 Ω
12 pF
100 nF
100 nF
25 Ω
25 Ω
INAM
INBM
VCM
100 nF
100 nF
005aaa070
Fig 6.
Single transformer configuration
ADC1213D065_080_105_125_2
Objective data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 02 — 17 June 2009
13 of 38
ADC1213D065/080/105/125
NXP Semiconductors
Dual 12-bit ADC; 65, 80, 105 or 125 Msps
ADT1-1WT
Analog
lnput
ADT1-1WT
100 nF
50 Ω
12 Ω
INAP
INBP
50 Ω
8.2 pF
50 Ω
50 Ω
12 Ω
100 nF
INAM
INBM
VCM
100 nF
100 nF
005aaa071
Fig 7.
Dual transformer configuration
The configuration shown in Figure 7 is recommended for high frequency applications. In
both cases, the choice of transformer will be a compromise between cost and
performance.
13.2 System reference and power management
13.2.1 Internal/external reference
The ADC1213D has a stable and accurate built-in internal reference voltage. This
reference voltage can be set internally, externally or programmed, in 1 dB steps between
0 dB and −6 dB, via SPI control bits INTREF (when bit INTREF_EN = 1; see Table 21).
The equivalent reference circuit is shown in Figure 8.
REFT
REFERENCE
AMP
VREF
BUFFER
REFB
BANDGAP
REFERENCE
ADC CORE
SENSE
SELECTION
LOGIC
005aaa072
Fig 8.
Reference equivalent schematic
ADC1213D065_080_105_125_2
Objective data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 02 — 17 June 2009
14 of 38
ADC1213D065/080/105/125
NXP Semiconductors
Dual 12-bit ADC; 65, 80, 105 or 125 Msps
The following Table 10 show how to chose between the different internal/external modes:
Table 10.
Reference modes
Mode
SPI Bit, “Internal
reference”
SENSE pin
VREF pin
Full Scale,
V (p-p)
Internal
0
Gnd
330 pF capacitor 2
to GND
Internal
0
VREF PIN = SENSE PIN and
330 pF capacitor to GND
External
0
VDDA
Internal, SPI mode
1
VREF PIN = SENSE PIN and
330 pF capacitor to GND
1
External voltage 1 to 2
from 0.5 V to 1 V
1 to 2
Figure 9, Figure 10, Figure 11 and Figure 12 indicate how to connect the SENSE and
VREF pins.
VREF
VREF
REFT
SENSE
REFB
REFT
330 pF
330 pF
REFB
SENSE
005aaa074
005aaa100
Fig 9.
Internal reference, 2 V (p-p) full scale
VREF
Fig 10. Internal reference, 1 V (p-p) full scale
VREF
REFT
V
330 pF
SPI SETTINGS
int_Ref = 1, active
Programmable_int_ref = XXX
VCCA
005aaa075
Fig 11. Internal reference, SPI, 1 V (p-p) to 2 V (p-p)
full scale
REFB
005aaa076
Fig 12. External reference, 1 V (p-p) to 2 V (p-p) full
scale
ADC1213D065_080_105_125_2
Objective data sheet
0.1 µF
SENSE
REFB
SENSE
REFT
© NXP B.V. 2009. All rights reserved.
Rev. 02 — 17 June 2009
15 of 38
ADC1213D065/080/105/125
NXP Semiconductors
Dual 12-bit ADC; 65, 80, 105 or 125 Msps
13.2.2 Gain control
The gain is programmable between 0 dB to −6 dB in steps of 1 dB via the SPI
(see Table 21). This makes it possible to improve the Spurious-Free Dynamic Range
(SFDR) of the ADC1213D. The corresponding full scale input voltage range varies
between 2 V (p-p) and 1 V (p-p), as shown in Table 11:
Table 11.
Reference SPI gain control
Programmable_int_ref
Level
Full Scale, V (p-p)
000
0dB
2
001
−1dB
1.78
010
−2dB
1.59
011
−3dB
1.42
100
−4dB
1.26
101
−5dB
1.12
110
−6dB
1
111
not used
x
13.2.3 Common-mode output voltage (VI(CM))
An 0.1 µF filter capacitor should be connected between on the one hand the pins VCMA
and VCMB and on the other hand ground to ensure a low-noise common-mode output
voltage. When AC-coupled, these pins can be used to set the common-mode reference
for the analog inputs, for instance via a transformer middle point.
PACKAGE
ESD
PARASITICS
COMMON MODE
REFERENCE
1.5 V
VCMA
VCMB
0.1 µF
ADC CORE
005aaa077
Fig 13. Reference equivalent schematic
13.2.4 Biasing
The common-mode output voltage, VO(cm, should be set externally to 1.5 V (typical).
The common-mode input voltage , VI(cm), at the inputs to the sample and hold stage
(pins INAM, INBM, INAP, and INBP) must be between 0.9 V and 2 V for optimal
performance. The graph in Figure 14 illustrates how the SFDR and SNR characteristics
vary with changes in the common-mode input voltage.
ADC1213D065_080_105_125_2
Objective data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 02 — 17 June 2009
16 of 38
ADC1213D065/080/105/125
NXP Semiconductors
Dual 12-bit ADC; 65, 80, 105 or 125 Msps
dB
SFDR (x MHz)
SNR (x MHz)
2V
0.9 V
VI(cm)
005aaa052
Fig 14. SFDR and SNR performances versus common-mode voltage
13.3 Clock input
13.3.1 Drive modes
The ADC1213D can be driven differentially (SINE, LVPECL or LVDS) without the
performance being affected by the choice of configuration. It can also be driven by a
single-ended LVCMOS signal connected to pin CLKP (CLKM should be connected to
ground via a capacitor).
LVCMOS
clock input
CLKP
CLKP
CLKM
LVCMOS
clock input
CLKM
005aaa078
Fig 15. LVCMOS single-ended clock input
CLKP
Sine
Clock lnput
Sine
Clock lnput
CLKM
CLKP
CLKM
005aaa079
Fig 16. Sine differential clock input
ADC1213D065_080_105_125_2
Objective data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 02 — 17 June 2009
17 of 38
ADC1213D065/080/105/125
NXP Semiconductors
Dual 12-bit ADC; 65, 80, 105 or 125 Msps
CLKP
LVDS
Clock lnput
CLKM
005aaa080
Fig 17. LVDS differential clock input
13.3.2 Equivalent input circuit
The equivalent circuit of the input clock buffer is shown in Figure 18. The common-mode
voltage of the differential input stage is set via internal resistors of 5 kΩ resistors.
PACKAGE
ESD
PARASITICS
CLKP
Vcm(clk)
Sel_SE
Sel_SE
5k
5k
CLKM
005aaa081
Fig 18. Equivalent input circuit
Single-ended or differential clock inputs can be selected via the SPI interface
(see Table 20). If single-ended is selected, the input pin (CLKM or CLKP) is selected via
control bit SE_SEL.
If single-ended is implemented without setting SE_SEL accordingly, the unused pin
should be connected to ground via a capacitor.
13.3.3 Duty cycle stabilizer
The duty cycle stabilizer can improve the overall performances of the ADC by
compensating the input clock signal duty cycle. When the duty cycle stabilizer is active
(bit DCS_EN = 1; see Table 20), the circuit can handle signals with duty cycles of between
30 % and 70 % (typical). When the duty cycle stabilizer is disabled (DCS_EN = 0), the
input clock signal should have a duty cycle of between 45 % and 55 %.
ADC1213D065_080_105_125_2
Objective data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 02 — 17 June 2009
18 of 38
ADC1213D065/080/105/125
NXP Semiconductors
Dual 12-bit ADC; 65, 80, 105 or 125 Msps
Table 12.
Duty cycle stabilizer
DCS_enable SPI
Description
0
Duty cycle stabilizer disable
1
Duty cycle stabilizer enable
13.4 Digital outputs
13.4.1 Serial output equivalent circuit
The JESD204A standard specifies that in case of connecting the receiver and the
transmitter in DC coupling, both of them need to be provided by the same supply.
VDDD
50 Ω
+
CMLP
100 Ω
CMLN
RECEIVER
−
+
12 to 26 mA
AGND
005aaa082
Fig 19. CML output connection to the receiver in DC coupling
The output should be terminated when 100 Ω (typical) has been reached at the receiver
side.
VDDD
50 Ω
+
+
CMLP
10 nF
CMLN
10 nF
100 Ω
RECEIVER
−
12 to 26 mA
005aaa083
Fig 20. CML output connection to the receiver in AC coupling
ADC1213D065_080_105_125_2
Objective data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 02 — 17 June 2009
19 of 38
ADC1213D065/080/105/125
NXP Semiconductors
Dual 12-bit ADC; 65, 80, 105 or 125 Msps
13.5 JESD204A serializer
13.5.1 Digital JESD204A formatter
The block placed after the ADC cores is used to implement all functionalities of the
JESD204A standard. This ensures signal integrity and guarantees the clock and the data
recovery at the receiver side.
The block is highly parameterized and can be configured in various ways depending on
the sampling frequency and the number of lanes used.
M CONVERTERS
N bits from Cr0 +
CS bits for control
L LANES
F octets
TX transport layer
FRAME
TO
OCTETS
SCRAMBLER
ALIGNMENT
CHARACTER
GENERATOR
8b/10b
SER
LANE0
8b/10b
SER
LANE−1
TX CONTROLLER
SYNC~
samples stream to
lane stream mapping
N bits from CrM−1 +
CS bits for control
N' = N+CS
S samples per frame cycle
F octets
FRAME
TO
OCTETS
SCRAMBLER
ALIGNMENT
CHARACTER
GENERATOR
CF: position of controls bits
HD: frame boundary break
Padding with Tails bits (TT)
Mx(N'xS) bits
Lx(F) octets
L octets
005aaa084
Fig 21. General overview of the JESD204A serializer
ADC1213D065_080_105_125_2
Objective data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 02 — 17 June 2009
20 of 38
ADC1213D065/080/105/125
NXP Semiconductors
Dual 12-bit ADC; 65, 80, 105 or 125 Msps
ADC_mode [1-0]
PRBS
DUMMY
scramb_in_mode [1-0]
11
14 + 1
10
14 + 1
N
&
CS
8
N + CS
lane_mode [1-0]
00
SCR
PRBS
8b/10b
01
10
00
ADC_power down
ADC0
14 + 1
x1
xF
x 10F
14 + 1
'0/1'
10
PRBS
11
SER
frame CLK
FRAME
ASSEMBLY
char CLK
FSM (f assy,
char repl, ILA,
test mode)
swing [2-0]
bit CLK
sync_request
ADC1
01
00
bypass alignment
disable_char_repl
PLL
&
DLL
'0'
lane_polarity
PRBS
11
'0/1'
10
'0'
01
SER
00
ADC_power down
PRBS
DUMMY
14 + 1 10
14 + 1
11
PRBS
N
&
CS
lane_polarity
01
SCR
N + CS
8
00
8b/10b
10
00
lane_mode [1-0]
scramb_in_mode [1-0]
005aaa085
ADC_mode [1-0]
Fig 22. Detailed view of the JESD204A serializer with debug functionality
ADC1213D065_080_105_125_2
Objective data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 02 — 17 June 2009
21 of 38
ADC1213D065/080/105/125
NXP Semiconductors
Dual 12-bit ADC; 65, 80, 105 or 125 Msps
13.5.2 ADC core output codes versus input voltage
Table 13 shows the data output codes for a given analog input voltage.
Table 13.
Output codes versus input voltage
INP-INM (V)
Offset binary
Two’s complement
OTR
< −1
00 0000 0000 0000
10 0000 0000 0000
1
−1
00 0000 0000 0000
10 0000 0000 0000
0
−0.9998779
00 0000 0000 0001
10 0000 0000 0001
0
−0.9997559
00 0000 0000 0010
10 0000 0000 0010
0
−0.9996338
00 0000 0000 0011
10 0000 0000 0011
0
−0.9995117
00 0000 0000 0100
10 0000 0000 0100
0
....
....
....
0
−0.0002441
01 1111 1111 1110
11 1111 1111 1110
0
−0.0001221
01 1111 1111 1111
11 1111 1111 1111
0
0
10 0000 0000 0000
00 0000 0000 0000
0
0.0001221
10 0000 0000 0001
00 0000 0000 0001
0
0.0002441
10 0000 0000 0010
00 0000 0000 0010
0
....
....
....
0
0.9995117
11 1111 1111 1011
01 1111 1111 1011
0
0.9996338
11 1111 1111 1100
01 1111 1111 1100
0
0.9997559
11 1111 1111 1101
01 1111 1111 1101
0
0.9998779
11 1111 1111 1110
01 1111 1111 1110
0
1
11 1111 1111 1111
01 1111 1111 1111
0
>1
11 1111 1111 1111
01 1111 1111 1111
1
13.6 Serial Peripheral Interface (SPI)
13.6.1 Register description
The ADC1213D serial interface is a synchronous serial communications port allowing for
easy interfacing with many industry microprocessors. It provides access to the registers
that control the operation of the chip in both read and write modes.
This interface is configured as a 3-wire type (SDIO as bidirectional pin).
SCLK acts as the serial clock, and CSB acts as the serial chip select bar.
Each read/write operation is sequenced by the CSB signal and enabled by a LOW level to
to drive the chip with 2 bytes to 5 bytes, depending on the content of the instruction byte
(see Table 14).
Table 14.
Instruction bytes for the SPI
MSB
LSB
Bit
7
6
5
4
3
2
1
0
Description
R/W[1]
W1
W0
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
[1]
R/W indicates whether a read or write transfer occurs after the instruction byte
ADC1213D065_080_105_125_2
Objective data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 02 — 17 June 2009
22 of 38
ADC1213D065/080/105/125
NXP Semiconductors
Dual 12-bit ADC; 65, 80, 105 or 125 Msps
Table 15.
Read or Write mode access description
R/W[1]
Description
0
Write mode operation
1
Read mode operation
[1]
Bits W1 and W0 indicate the number of bytes transferred after the instruction byte.
Table 16.
Number of bytes to be transferred
W1
W0
Number of bytes
0
0
1 byte transferred
0
1
2 bytes transferred
1
0
3 bytes transferred
1
1
4 or more bytes transferred
Bits A12 to A0 indicate the address of the register being accessed. In the case of a
multiple byte transfer, this address is the first register to be accessed. An address counter
is incremented to access subsequent addresses.
The steps involved in a data transfer are as follows:
1. The falling edge on CSB in combination with a rising edge on SCLK determine the
start of communications.
2. The first phase is the transfer of the 2-byte instruction.
3. The second phase is the transfer of the data which can be vary in length but will
always be a multiple of 8 bits. The MSB is always sent first (for instruction and data
bytes):
CSB
SCLK
SDIO
R/W
W1
W0
A12 A11 A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
D7
Instruction bytes
D6
D5
D4
D3
D2
Register N (data)
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
Register N + 1 (data)
005aaa086
Fig 23. Transfer diagram for two data bytes (3 wires mode)
13.6.2 Channel control
The two ADC channels can be configured at the same time or separately. By using the
register “Channel index”, the user can choose which ADC channel will receive the next
SPI-instruction. By default the channel A and B will receive the same instructions.
ADC1213D065_080_105_125_2
Objective data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 02 — 17 June 2009
23 of 38
ADC1213D065/080/105/125
NXP Semiconductors
Dual 12-bit ADC; 65, 80, 105 or 125 Msps
Table 17.
Register allocation map
Addr Register name
Hex
R/W Bit definition
0003 Channel index
Bit 7
Default
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bin
R/W
-
-
-
-
-
ADCB
ADCA
1111
1111
0005 Reset and
Operating mode
R/W SW_
RST
-
-
-
-
-
PD[1:0]
0006 Clock
R/W -
-
-
SE_SEL DIFF/SE
-
CLKDIV2_ DCS_EN 0000
SEL
000X
0008 Vref
R/W -
-
-
-
INTREF_
EN
INTREF[2:0]
0000
0000
0011 Output data
standard
R/W -
-
-
LVDS/
CMOS
OUTBUF
-
000X
0XXX
0013 Offset
R/W -
-
DIG_OFFSET[5:0]
0014 Test pattern 1
R/W -
-
-
0015 Test pattern 2
R/W TESTPAT_2[13:6]
0000
0000
0016 Test pattern 3
R/W TESTPAT_3[5:0]
0000
0000
-
0000
0000
DATA_FORMAT
0000
0000
-
TESTPAT_1[2:0]
0000
0000
JESD204A control
0801 Ser_Status
R
0
RESERVED[2:0]
0
0802 Ser_Reset
R/W SW_
RST
0
0
0
FSM_SW_ 0
RST
0803 Ser_Cfg_Setup
R/W 0
0
0
0
CFG_SETUP[3:0]
0805 Ser_Control1
R/W 0
TriState SYNC_
_CFG_ POL
PAD
SYNC_ 1
SINGLE
ENDED
RESERVED[2:0]
0806 Ser_Control2
R/W 0
0
0
0
0
0
0808 Ser_Analog_Ctrl
R/W 0
0
0
0
0
SWING_SEL[2:0]
0809 Ser_ScramblerA
R/W 0
LSB_INIT[6:0]
080A Ser_ScramblerB
R/W MSB_INIT[7:0]
080B Ser_PRBS_Ctrl
R/W 0
0
0820 Cfg_0_DID
R/W*
DID[7:0]
0821 Cfg_1_BID
R/W* 0
0
0
0
BID[3:0]
0822 Cfg_3_SCR_L
R/W* SCR
0
0
0
0
0
0823 Cfg_4_F
R/W* 0
0
0
0
0
F[2:0]
POR_TST PLL_
0000
INLOCK 0000
0
0
0000
0000
0000 ****
0100
1000
SWAP_
SWAP_ 0000
LANE_1_2 ADC_0_ 00**
1
0000
01**
0000
0000
1111
1111
0
0
0
0
PRBS_TYPE[1:0]
0000
0000
1110
1101
ADC1213D065_080_105_125_2
Objective data sheet
0
0000
1010
0
L
*000
000*
0000
0***
© NXP B.V. 2009. All rights reserved.
Rev. 02 — 17 June 2009
24 of 38
ADC1213D065/080/105/125
NXP Semiconductors
Dual 12-bit ADC; 65, 80, 105 or 125 Msps
Table 17.
Register allocation map …continued
Addr Register name
Hex
R/W Bit definition
0824 Cfg_5_K
Bit 7
Default
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bin
R/W* 0
0
0
K[4:0]
0825 Cfg_6_M
R/W* 0
0
0
0
0
0
0826 Cfg_7_CS_N
R/W* 0
CS[0]
0
0
0
N[2:0]
0827 Cfg_8_Np
R
0
0
0
NP[4:0]
0828 Cfg_9_S
R/W* 0
0
0
0
0
0
0
0829 Cfg_10_HD_CF
R/W* HD
0
0
0
0
0
CF[1:0]
082C Cfg_01_2_LID
R/W* 0
0
0
LID[4:0]
0001
1011
082D Cfg_02_2_LID
R/W* 0
0
0
LID[4:0]
0001
1100
084C Cfg01_13_FCHK
R
FCHK[7:0]
0000
0000
084D Cfg02_13_FCHK
R
FCHK[7:0]
0000
0000
0870 Lane01_0_Ctrl
R/W 0
SCR_ LANE_MODE[1:0] 0
IN_
MODE
LANE_ LANE_
LANE_
POL
CLK_POS PD
_EDGE
0000
000*
0871 Lane02_0_Ctrl
R/W 0
SCR_ LANE_MODE[1:0] 0
IN_
MODE
LANE_ LANE_
LANE_
POL
CLK_POS PD
_EDGE
0000
000*
0890 Adc01_0_Ctrl
R/W 0
0
ADC_MODE[1:0]
0
0
0
ADC_PD 0000
000*
0891 Adc02_0_Ctrl
R/W 0
0
ADC_MODE[1:0]
0
0
0
ADC_PD 0000
000*
000* ****
0
M
0000
000*
0100
0***
0000
1111
S
0000
0000
*000
0000
[1]
an "*" in the Default column replaces a bit of which the value depends on the binary level of external pins (e.g. CFG[3:0], Swing[1:0],
Scrambler).
[2]
an "*" in the Access column means that this register is subject to control access conditions in Write mode.
13.6.3 Register description
Table 18.
Register channel Index(address 0003h)
Bit
Symbol
Access
1
ADCB
R/W
Value
ADCB will get the next SPI command:
0
1
0
ADCA
Description
R/W
ADCB not selected
ADCB selected
ADCA will get the next SPI command:
0
ADCA not selected
1
ADCA selected
ADC1213D065_080_105_125_2
Objective data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 02 — 17 June 2009
25 of 38
ADC1213D065/080/105/125
NXP Semiconductors
Dual 12-bit ADC; 65, 80, 105 or 125 Msps
Table 19.
Register reset and Power-down mode (address 0005h)
Bit
Symbol
Access
7
SW_RST
R/W
1 to 0
PD
Table 20.
Symbol
Access
SE_SEL
R/W
0
DIFF/SE
CLKDIV2_SEL
DCS_EN
Table 21.
no reset
1
performs a reset of the digital part
Power-down mode:
00
normal (power-up)
01
full power-down
10
sleep
11
normal (power-up)
Value
Description
Select SE clock input pin:
0
Select CLKM input
1
Select CLKP input
R/W
Differential/single ended clock input select:
0
Fully differential
1
Single-ended
R/W
Select clk input divider by 2:
0
disable
1
active
R/W
Duty cycle stabilizer enable:
0
disable
1
active
Register Vref (address 0008h)
Bit
Symbol
Access
3
INTREF_EN
R/W
2 to 0
0
Register clock (address 0006h)
4
1
Description
Reset digital part:
R/W
Bit
3
Value
INTREF
Value
Description
Enable internal programmable Vref mode:
0
disable
1
active
R/W
Programmable internal reference:
000
0dB (FS = 2 V)
001
−1dB (FS = 1.78 V)
010
−2dB (FS = 1.59 V)
011
−3dB (FS = 1.42 V)
100
−4dB (FS = 1.26 V)
101
−5dB (FS = 1.12 V)
110
−6dB (FS = 1 V)
111
not used
ADC1213D065_080_105_125_2
Objective data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 02 — 17 June 2009
26 of 38
ADC1213D065/080/105/125
NXP Semiconductors
Dual 12-bit ADC; 65, 80, 105 or 125 Msps
Table 22.
Digital offset adjust
Register offset: (address 0013h)
Dec
Digital_Offset_Adjust[5:0]
+31
011111
+31 LSB
...
...
...
0
000000
0
...
...
...
−32
100000
−32 LSB
Table 23.
Register test pattern 1 (address 0014h)
Bit
Symbol
Access
2 to 0
TESTPAT_1
R/W
Table 24.
Value
Description
Digital test pattern:
000
off
001
midscale
010
− FS
011
+ FS
100
toggle ‘1111..1111’/’0000..0000’
101
Custom test pattern, to be written in register 0015h & 0016h
110
‘010101...’
111
‘101010...’
Register test pattern 2 (address 0015h)
Bit
Symbol
Access
13 to 6
TESTPAT_2
R/W
Value
Description
Custom digital test pattern
Table 25.
Register test pattern 3 (address 0016h)
Bit
Symbol
Access
5 to 0
TESTPAT_3
R/W
Value
Description
Custom digital test pattern
-
13.6.4 JESD204A digital control registers
Table 26.
SER status (address 0801h)
Bit
Symbol
7 to 1
-
0
PLL_Inlock
Table 27.
Access
Value
Description
Not used
R
0
Indicates status of PLL
SER reset (address 0802h)
Bit
Symbol
Access
Value
Description
7
SW_RST
R/W
0
Initiates a software reset of the JEDEC204A unit
6 to 4
-
000
Not used
3
FSM_SW_RST
0
Initiates a software reset of the internal state machine of JEDEC204A
unit
2 to 0
-
000
Not used
R/W
ADC1213D065_080_105_125_2
Objective data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 02 — 17 June 2009
27 of 38
ADC1213D065/080/105/125
NXP Semiconductors
Dual 12-bit ADC; 65, 80, 105 or 125 Msps
Table 28.
SER cfg set-up (address 0803h)
Bit
Symbol
Access
Value
Description
7 to 4
-
R
0000
Not used
3 to 0
CFG_SETUP
R/W
0000
(reset)
Defines quick JEDEC204A configuration. These settings overrule the
CFG_PAD configuration
0000
ADC0: ON; ADC1: ON; Lane0: ON; Lane1: ON; F = 2; HD = 0; K = 9;
M = 2; L = 2[1]
0001
ADC0: ON; ADC1: ON; Lane0: ON; Lane1: OFF; F = 4; HD = 0; K = 5;
M = 2; L = 1[1]
0010
ADC0: ON; ADC1: ON; Lane0: OFF; Lane1: ON; F = 4; HD = 0; K = 5;
M = 2; L = 1 swap line = 1[1]
0011
ADC0: ON; ADC1: OFF; Lane0: ON; Lane1: ON; F = 1; HD = 1; K = 17;
M = 1; L = 2[1]
0100
ADC0: OFF; ADC1: ON; Lane0: ON; Lane1: ON; F = 1; HD = 1; K = 17;
M = 1; L = 2; swap adc = 1[1]
0101
ADC0: ON; ADC1: OFF; Lane0: ON; Lane1: OFF; F = 2; HD = 0; K = 9;
M = 1; L = 1[1]
0110
ADC0: ON; ADC1: OFF; Lane0: OFF; Lane1: ON; F = 2; HD = 0; K = 9;
M = 1; L = 1; swap line = 1[1]
0111
ADC0: OFF; ADC1: ON; Lane0: ON; Lane1: OFF; F = 2; HD = 0; K = 9;
M = 1; L = 1; swap adc = 1[1]
1000
ADC0: OFF; ADC1: ON; Lane0: OFF; Lane1: ON; F = 2; HD = 0; K = 9;
M = 1; L = 1; swap adc = 1; swap line = 1[1]
1001 to
1101
Reserved
1110
ADC0: OFF; ADC1: OFF; Lane0: ON; Lane1: ON; F = 2; HD = 0; K = 9;
M = 2; L = 2; loop alignment = 1[1]
1111
ADC0: OFF; ADC1: OFF; Lane0: OFF; Lane1: OFF; F = 2; HD = 0;
K = 9; M = 2; L = 2 → PD[1]
[1]
F : number of byte per frame; HD : High density; K : number of frames per multi frame; M : number of converters; L : number of lanes
See the information about the JESD204A standard on the JEDEC web site.
Table 29.
SER control1 (address 0805h)
Bit
Symbol
Access
Value
Description
7
-
R
0
Not used
6
TRISTATE_CFG_PAD
R/W
0
1 (default)
5
4
SYNC_POL
R/W
0 (default)
synchronization signal is active high
1
synchronization signal is active low
SYNC_SINGLE_ENDED R/W
3
-
R
2 to 0
RESERVED
-
CFG pads (3 to 0) are set to high-impedance
Defines the synchronization signal polarity:
Defines the input mode of the synchronization signal:
0 (default)
synchronization input mode is set in Differential mode
1
synchronization input mode is set in Single-ended mode
1
Not used
ADC1213D065_080_105_125_2
Objective data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 02 — 17 June 2009
28 of 38
ADC1213D065/080/105/125
NXP Semiconductors
Dual 12-bit ADC; 65, 80, 105 or 125 Msps
Table 30.
SER control2 (address 0806h)
Bit
Symbol
Access
Value
Description
7 to 2
-
R
000000
Not used
1
SWAP_LANE_1_2
R/W
Controls the JESD204A output mux:
0 (default)
1
0
SWAP_ADC_0_1
Outputs of the JESD204A unit are swapped. (Output0 is
connected to Lane1, Output1 is connected to Lane0)
R/W
Controls the JESD204A input multiplexer:
0 (default)
1
Table 31.
Inputs of the JESD204A unit are swapped. (ADC0 output is
connected to Input1, ADC1 is connected to Input0
SER analog ctrl (address 0808h)
Bit
Symbol
Access
Value
Description
7 to 3
-
R
0
Not used
2 to 0
SWING_SEL
R/W
000
Defines the swing output for the lane pads
Table 32.
SER scramblerA (address 0809h)
Bit
Symbol
Access
Value
Description
7
-
R
0
Not used
6 to 0
LSB_INIT
R/W
0000000
Defines the initialization vector for the scrambler polynomial
(Lower)
Table 33.
SER scramblerB (address 080Ah)
Bit
Symbol
Access
Value
7 to 0
UPP_VECT_INIT
R/W
11111111 Defines the initialization vector for the scrambler polynomial
(Upper)
Table 34.
Description
SER PRBS Ctrl (address 080Bh)
Bit
Symbol
Access
Value
Description
7 to 2
-
R
000000
Not used
1 to 0
PRBS_TYPE
R/W
00 (reset)
Defines the type of Pseudo-Random Binary Sequence (PRBS)
generator to be used
00
PRBS-7
01
PRBS-7
10
PRBS-23
11
PRBS-31
Table 35.
Cfg_0_DID (address 0820h)
Bit
Symbol
Access
Value
Description
7 to 0
DID
R
11101101 Defines the device (= link) identification number
ADC1213D065_080_105_125_2
Objective data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 02 — 17 June 2009
29 of 38
ADC1213D065/080/105/125
NXP Semiconductors
Dual 12-bit ADC; 65, 80, 105 or 125 Msps
Table 36.
Cfg_1_BID (address 0821h)
Bit
Symbol
Access
Value
Description
7 to 4
-
R
0000
Not used
3 to 0
BID
R/W
1010
Defines the bank ID – extension to DID
Table 37.
Cfg_3_SCR_L (address 0822h)
Bit
Symbol
Access
Value
Description
7
SCR
R/W
0
Scrambling enabled
6 to 1
-
R
000000
Not used
0
L
R/W
0
Defines the number of lanes per converter device
Table 38.
Cfg_4_F (address 0823h)
Bit
Symbol
Access
Value
Description
7 to 3
-
R
00000
Not used
2 to 0
F
R/W
000
Defines the number of octets per frame
Table 39.
Cfg_5_K (address 0824h)
Bit
Symbol
Access
Value
Description
7 to 5
-
R
000
Not used
4 to 0
K
R/W
00000
Defines the number of frames per multiframe
Table 40.
Cfg_6_M (address 0825h)
Bit
Symbol
Access
Value
Description
7 to 1
-
R
0000000
Not used
0
M
R/W
0
Defines the number of converters per device
Table 41.
Cfg_7_CS_N (address 0826h)
Bit
Symbol
Access
Value
Description
7
-
R
0
Not used
6
CS
R/W
0
Defines the number of control bits per sample
5 to 4
-
R
00
Not used
3 to 0
N
R/W
0000
Defines the converter resolution
Table 42.
Cfg_8_Np (address 0827h)
Bit
Symbol
Access
Value
Description
7 to 5
-
R
000
Not used
4 to 0
NP
R/W
00000
Defines the total number of bits per sample
Table 43.
Cfg_9_S (address 0828h)
Bit
Symbol
Access
Value
Description
7 to 1
-
R
0000000
Not used
0
S
R/W
0
Defines number of samples per converter per frame cycle
ADC1213D065_080_105_125_2
Objective data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 02 — 17 June 2009
30 of 38
ADC1213D065/080/105/125
NXP Semiconductors
Dual 12-bit ADC; 65, 80, 105 or 125 Msps
Table 44.
Cfg_10_HD_CF (address 0829h)
Bit
Symbol
Access
Value
Description
7
HD
R/W
0
Defines high density format
6 to 2
-
R
00000
Not used
1 to 0
CF
R/W
00
Defines number of control words per frame clock cycle per link
Table 45.
Cfg01_2_LID (address 082Ch)
Bit
Symbol
Access
Value
Description
7 to 5
-
R
000
Not used
4 to 0
LID
R/W
11011
Defines lane1 identification number
Table 46.
Cfg02_2_LID (address 082Dh)
Bit
Symbol
Access
Value
Description
7 to 5
-
R
000
Not used
4 to 0
LID
R/W
11100
Defines lane2 identification number
Table 47.
Cfg02_13_fchk (address 084Ch)
Bit
Symbol
Access
Value
Description
7 to 0
FCHK
R
00000000 Defines the checksum value for lane1
Checksum corresponds to the sum of all the link configuration
parameters modulo 256 (as defined in JEDEC Standard
No.204A)
Table 48.
Cfg01_13_fchk (address 084Dh)
Bit
Symbol
Access
Value
Description
7 to 0
FCHK
R
00000000 Defines the checksum value for lane1
Checksum corresponds to the sum of all the link configuration
parameters modulo 256 (as defined in JEDEC Standard
No.204A)
Table 49.
Lane01_0_ctrl (address 0870h)
Bit
Symbol
Access
Value
Description
7
-
R
0
Not used
6
SCR_IN_MODE
R/W
5 to 4
3
LANE_MODE
-
Defines the input type for scrambler and 8b/10b units:
0 (reset)
(Normal mode) = Input of the scrambler and 8b/10b units is the
output of the Frame Assembly unit.
1
Input of the scrambler and 8b/10b units is the PRSB generator
(PRBS type is defined with “PRBS_TYPE” (Ser_PRBS_ctrl
register)
R/W
R
Defines output type of lane output unit:
00 (reset)
Normal mode: Lane output is the 8b/10b output unit
01
Constant mode: Lane output is set to a constant (0 × 0)
10
Toggle mode: Lane output is toggling between 0 × 0 and 0 × 1
11
PRBS mode: Lane output is the PRSB generator (PRBS type is
defined with “PRBS_TYPE” (Ser_PRBS_ctrl register)
0
Not used
ADC1213D065_080_105_125_2
Objective data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 02 — 17 June 2009
31 of 38
ADC1213D065/080/105/125
NXP Semiconductors
Dual 12-bit ADC; 65, 80, 105 or 125 Msps
Table 49.
Lane01_0_ctrl (address 0870h) …continued
Bit
Symbol
Access
2
LANE_POL
R/W
1
0
Value
Defines lane polarity:
0 (default)
Lane polarity is normal
1
Lane polarity is inverted
LANE_CLK_POS_EDGE R/W
Lane_PD
Description
Defines lane clock polarity:
0 (default)
Lane clock provided to the serializer is active on positive edge
1
Lane clock provided to the serializer is active on negative edge
R/W
Lane power-down control:
0 (default)
1
Table 50.
Lane is in Power-down mode
Lane02_0_ctrl (address 0871h)
Bit
Symbol
Access
Value
Description
7
-
R
0
Not used
6
SCR_IN_MODE
R/W
5 to 4
LANE_MODE
Defines the input type for scrambler and 8b/10b units.
0 (reset)
Normal mode = Input of the scrambler and 8b/10b units is the
output of the Frame Assembly unit.
1
input of the scrambler and 8b/10b units is the PRSB generator
(PRBS type is defined with “PRBS_TYPE”
(Ser_PRBS_ctrl register)
R/W
Defines output type of lane output unit:
00 (reset)
Normal mode: Lane output is the 8b/10b output unit
01
Constant mode: Lane output is set to a constant (0 × 0)
10
Toggle mode: Lane output is toggling between 0 × 0 and 0 × 1
11
PRBS mode: Lane output is the PRSB generator (PRBS type is
defined with “PRBS_TYPE” (Ser_PRBS_ctrl register)
3
-
R
0
Not used
2
LANE_POL
R/W
0
Defines lane polarity:
0 (default)
1
1
0
Lane polarity is inverted
LANE_CLK_POS_EDGE R/W
Lane_PD
Lane polarity is normal
Defines lane clock polarity:
0 (default)
Lane clock provided to the serializer is active on positive edge
1
Lane clock provided to the serializer is active on negative edge
R/W
Lane power-down control:
0 (default)
1
Table 51.
Lane is in Power-down mode
ADC01_0_ctrl (address 0890h)
Bit
Symbol
Access
Value
Description
7 to 6
-
R
00
Not used
ADC1213D065_080_105_125_2
Objective data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 02 — 17 June 2009
32 of 38
ADC1213D065/080/105/125
NXP Semiconductors
Dual 12-bit ADC; 65, 80, 105 or 125 Msps
Table 51.
ADC01_0_ctrl (address 0890h) …continued
Bit
Symbol
Access
5 to 4
ADC_MODE
R/W
3 to 1
-
R
0
ADC_PD
R/W
Value
Description
Defines input type of JESD204A unit:
00 (reset)
ADC output is connected to the JESD204A input
01
Not used
10
JESD204A input is fed with a dummy constant (set to 0x0000)
11
JESD204A is fed with a PRBS generator (PRBS type is defined
with “PRBS_TYPE” (Ser_PRBS_ctrl register)
000
Not used
ADC power-down control:
0 (default)
1
ADC is in Power-down mode
ADC1213D065_080_105_125_2
Objective data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 02 — 17 June 2009
33 of 38
ADC1213D065/080/105/125
NXP Semiconductors
Dual 12-bit ADC; 65, 80, 105 or 125 Msps
Table 52.
ADC02_0_ctrl (address 0891h)
Bit
Symbol
Access
Value
Description
7 to 6
-
R
00
Not used
5 to 4
ADC_MODE
R/W
3 to 1
-
R
0
ADC_PD
R/W
Defines input type of JESD204A unit:
00 (reset)
ADC output is connected to the JESD204A input
01
Not used
10
JESD204A input is fed with a dummy constant (set to 0x0000)
11
JESD204A is fed with a PRBS generator (PRBS type is defined
with “PRBS_TYPE” (Ser_PRBS_ctrl register)
000
Not used
ADC power-down control:
0 (default)
1
ADC is in Power-down mode
13.6.5 Serial interface timings
The Figure 24 shows the SPI timings:
tsu
tsu
th
CS
tw(SCLKL)
th
tw(SCLKH)
tw(SCLK)
SCLK
SDIO
R/W
W1
W0
A12
A11
D2
D1
D0
005aaa065
Fig 24. SPI timings
The timing specification link to the Figure 24 is described in the Table 8.
ADC1213D065_080_105_125_2
Objective data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 02 — 17 June 2009
34 of 38
ADC1213D065/080/105/125
NXP Semiconductors
Dual 12-bit ADC; 65, 80, 105 or 125 Msps
14. Package outline
HVQFN56: plastic thermal enhanced very thin quad flat package; no leads;
56 terminals; body 8 x 8 x 0.85 mm
A
B
D
SOT684-7
terminal 1
index area
A
E
A1
c
detail X
e1
e
1/2 e
L
15
28
14
C
C A B
C
v
w
b
y1 C
y
29
e
e2
Eh
1/2 e
1
42
terminal 1
index area
56
43
X
Dh
0
2.5
scale
Dimensions
Unit
mm
5 mm
A(1)
A1
b
max 1.00 0.05 0.30
nom 0.85 0.02 0.21
min 0.80 0.00 0.18
c
D(1)
Dh
E(1)
Eh
0.2
8.1
8.0
7.9
5.95
5.80
5.65
8.1
8.0
7.9
6.55
6.40
6.25
e
e1
0.5
6.5
e2
L
v
6.5
0.5
0.4
0.3
0.1
w
y
0.05 0.05
y1
0.1
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
References
Outline
version
IEC
JEDEC
JEITA
SOT684-7
---
MO-220
---
sot684-7_po
European
projection
Issue date
08-11-19
09-03-04
Fig 25. Package outline SOT684-1 (HVQFN56)
ADC1213D065_080_105_125_2
Objective data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 02 — 17 June 2009
35 of 38
ADC1213D065/080/105/125
NXP Semiconductors
Dual 12-bit ADC; 65, 80, 105 or 125 Msps
15. Revision history
Table 53.
Revision history
Document ID
Release date
ADC1213D065_080_105_125_2 20090617
Modifications:
•
Data sheet status
Change
notice
Supersedes
Objective data sheet
-
ADC1213D065_080_105_125_1
-
-
Values in Table 7 have been updated.
ADC1213D065_080_105_125_1 20090528
Objective data sheet
ADC1213D065_080_105_125_2
Objective data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 02 — 17 June 2009
36 of 38
ADC1213D065/080/105/125
NXP Semiconductors
Dual 12-bit ADC; 65, 80, 105 or 125 Msps
16. Legal information
16.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
16.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
16.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
17. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
ADC1213D065_080_105_125_2
Objective data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 02 — 17 June 2009
37 of 38
NXP Semiconductors
ADC1213D065/080/105/125
Dual 12-bit ADC; 65, 80, 105 or 125 Msps
18. Contents
1
2
3
4
5
6
6.1
6.2
7
8
9
10
11
11.1
12
13
13.1
13.1.1
13.1.2
13.1.3
13.2
13.2.1
13.2.2
13.2.3
13.2.4
13.3
13.3.1
13.3.2
13.3.3
13.4
13.4.1
13.5
13.5.1
13.5.2
13.6
13.6.1
13.6.2
13.6.3
13.6.4
13.6.5
14
15
16
16.1
16.2
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pinning information . . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6
Thermal characteristics. . . . . . . . . . . . . . . . . . . 6
Static characteristics. . . . . . . . . . . . . . . . . . . . . 6
Dynamic characteristics . . . . . . . . . . . . . . . . . . 9
Clock and digital output timing . . . . . . . . . . . 10
Serial output timings . . . . . . . . . . . . . . . . . . . 10
SPI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Application information. . . . . . . . . . . . . . . . . . 12
Analog inputs . . . . . . . . . . . . . . . . . . . . . . . . . 12
Input stage description . . . . . . . . . . . . . . . . . . 12
Anti-kickback circuitry . . . . . . . . . . . . . . . . . . . 13
Transformer. . . . . . . . . . . . . . . . . . . . . . . . . . . 13
System reference and power management . . 14
Internal/external reference . . . . . . . . . . . . . . . 14
Gain control . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Common-mode output voltage (VI(CM)) . . . . . . 16
Biasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Drive modes . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Equivalent input circuit . . . . . . . . . . . . . . . . . . 18
Duty cycle stabilizer . . . . . . . . . . . . . . . . . . . . 18
Digital outputs . . . . . . . . . . . . . . . . . . . . . . . . . 19
Serial output equivalent circuit . . . . . . . . . . . . 19
JESD204A serializer. . . . . . . . . . . . . . . . . . . . 20
Digital JESD204A formatter . . . . . . . . . . . . . . 20
ADC core output codes versus input voltage . 22
Serial Peripheral Interface (SPI) . . . . . . . . . . . 22
Register description . . . . . . . . . . . . . . . . . . . . 22
Channel control. . . . . . . . . . . . . . . . . . . . . . . . 23
Register description . . . . . . . . . . . . . . . . . . . . 25
JESD204A digital control registers . . . . . . . . . 27
Serial interface timings . . . . . . . . . . . . . . . . . . 34
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 35
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 36
Legal information. . . . . . . . . . . . . . . . . . . . . . . 37
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 37
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
16.3
16.4
17
18
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . .
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . .
Contact information . . . . . . . . . . . . . . . . . . . .
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
37
37
37
38
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 17 June 2009
Document identifier: ADC1213D065_080_105_125_2