CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 1.8V 4k/8k/16k x 16 and 8k/16k x 8 ConsuMoBL Dual-Port Static RAM Features • Lead (Pb)-free 14 x 14 x 1.4 mm 100-pin TQFP Package • True dual-ported memory cells which allow simultaneous access of the same memory location • Full asynchronous operation • Pin select for Master or Slave • Expandable data bus to 32 bits with Master/Slave chip select when using more than one device • 4/8/16k × 16 and 8/16k × 8 organization • High-speed access: 40 ns • On-chip arbitration logic • Ultra Low operating power • On-chip semaphore logic — Active: ICC = 15 mA (typical) at 55 ns • Input Read Registers and Output Drive Registers — Active: ICC = 25 mA (typical) at 40 ns — Standby: ISB3 = 2 µA (typical) • INT flag for port-to-port communication • Separate upper-byte and lower-byte control • Port-independent 1.8V, 2.5V, and 3.0V I/Os • Commercial and industrial temperature ranges Selection Guide for VCC = 1.8V CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 -40 CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 -55 1.8V-1.8V 1.8V-1.8V Port I/O Voltages (P1-P2) Unit Maximum Access Time 40 55 ns Typical Operating Current 25 15 mA Typical Standby Current for ISB1 2 2 µA Typical Standby Current for ISB3 2 2 µA CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 -40 CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 -55 2.5V-2.5V 2.5V-2.5V Selection Guide for VCC = 2.5V Port I/O Voltages (P1-P2) Unit Maximum Access Time 40 55 ns Typical Operating Current 39 28 mA Typical Standby Current for ISB1 6 6 µA Typical Standby Current for ISB3 4 4 µA CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 -40 CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 -55 3.0V-3.0V 3.0V-3.0V Selection Guide for VCC = 3.0V Port I/O Voltages (P1-P2) Unit Maximum Access Time 40 55 ns Typical Operating Current 49 42 mA Typical Standby Current for ISB1 7 7 µA Typical Standby Current for ISB3 6 6 µA Cypress Semiconductor Corporation Document #: 001-01638 Rev. *E • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised January 25, 2007 [+] Feedback CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 I/O[15:0]R I/O[15:0]L UBR UBL LBL LBR IO Control IO Control 16K X 16 Dual Ported Array Address Decode Address Decode A[13:0]L CE L A [13:0]R CE R Interrupt Arbitration Semaphore OE L R/W L SEML BUSY L INTL IRR0 ,IRR1 Mailboxes INTR OE R R/W R SEMR BUSY R M/S Input Read Register and Output Drive Register CEL OEL R/WL CE R OE R R/W R ODR0 - ODR4 SFEN Figure 1. Top Level Block Diagram[1, 2] Notes: 1. A0–A11 for 4k devices; A0–A12 for 8k devices; A0–A13 for 16k devices. 2. BUSY is an output in master mode and an input in slave mode. Document #: 001-01638 Rev. *E Page 2 of 26 [+] Feedback CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 Pin Configurations [3, 4, 5, 6, 7] A3R A2R A1R A0R UBR LBR OER R/WR VSS ODR4 ODR3 ODR2 VSS ODR1 ODR0 VSS SFEN R/WL OEL LBL UBL A0L A1L A2L A3L 100-Pin TQFP (Top View) 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 A4L 1 75 A4R A5L 2 74 A5R A6L 3 73 A6R A7L 4 72 A7R A8L 5 71 A8R CEL 6 70 CER SEML 7 69 SEMR INTL 8 68 INTR BUSYL 9 67 BUSYR 66 A9R 65 A10R 64 VSS 63 VCC CYDC064B16 CYDC128B16 CYDC256B16 A9L 10 A10L 11 VSS 12 VCC 13 A11L 14 62 A11R A12L[3] 15 61 A12R[3] IRR0[5] 16 60 IRR1[6] M/S 17 59 NC[7] VDDIOL 18 58 VDDIOR I/O0L 19 57 I/O15R I/O1L 20 56 I/O14R I/O2L 21 55 I/O13R VSS 22 54 VSS I/O3L 23 53 I/O12R I/O4L 24 52 I/O11R I/O5L 25 51 I/O10R I/O9R I/O8R VDDIOR I/O7R I/O6R I/O5R VSS I/O4R I/O3R I/O2R I/O1R I/O0R NC[7] I/O15L I/O14L I/O13L I/O12L I/O11L VSS I/O10L I/O9L I/O8L VDDIOL I/O7L I/O6L 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Notes: 3. A12L and A12R are NC pins for CYDC064B16. 4. IRR functionality is not supported for the CYDC256B16 device. 5. This pin is A13L for CYDC256B16 device. 6. This pin is A13R for CYDC256B16 device. 7. Leave this pin unconnected. No trace or power component can be connected to this pin. Document #: 001-01638 Rev. *E Page 3 of 26 [+] Feedback CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 Pin Configurations (continued)[7, 8, 9, 10] A3R A2R A1R A0R UBR LBR OER R/WR VSS ODR4 ODR3 ODR2 VSS ODR1 ODR0 VSS SFEN R/WL OEL LBL UBL A0L A1L A2L A3L 100-pin TQFP (Top View) 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 A4L 1 75 A4R A5L 2 74 A5R A6L 3 73 A6R A7L 4 72 A7R A8L 5 71 A8R CEL 6 70 CER SEML 7 69 SEMR INTL 8 68 INTR BUSYL 9 67 BUSYR A9L 10 66 A9R A10L 11 65 A10R VSS 12 64 VSS VCC 13 63 VCC A11L 14 62 A11R A12L 15 61 A12R IRR0[9] 16 60 IRR1[10] M/S 17 59 NC[11] VDDIOL 18 58 VDDIOR I/O0L 19 57 VSS I/O1L 20 56 VSS I/O2L 21 55 VSS VSS 22 54 VSS I/O3L 23 53 VSS I/O4L 24 52 VSS I/O5L 25 51 VSS CYDC064B08 CYDC128B08 VSS VSS VDDIOR I/O7R I/O6R I/O5R VSS I/O4R I/O3R I/O2R I/O1R I/O0R NC[11] VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDIOL I/O7L I/O6L 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Notes: 8. IRR functionality is not supported for the CYDC128B08 device. 9. This pin is A13L for CYDC128B08 devices. 10. This pin is A13R for CYDC128B08 devices. Document #: 001-01638 Rev. *E Page 4 of 26 [+] Feedback CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 Pin Definitions Left Port Right Port Description CEL CER Chip Enable R/WL R/WR Read/Write Enable OEL OER Output Enable A0L–A13L A0R–A13R Address (A0–A11 for 4k devices; A0–A12 for 8k devices; A0–A13 for 16k devices). I/O0L–I/O15L I/O0R–I/O15R Data Bus Input/Output for x16 devices; I/O0–I/O7 for x8 devices. SEML SEMR Semaphore Enable UBL UBR Upper Byte Select (I/O8–I/O15 for x16 devices; Not applicable for x8 devices). LBL LBR Lower Byte Select (I/O0–I/O7 for x16 devices; Not applicable for x8 devices). INTL INTR Interrupt Flag BUSYL BUSYR Busy Flag IRR0, IRR1 ODR0-ODR4 SFEN Input Read Register for CYDC064B16, CYDC064B08, CYDC128B16. A13L, A13R for CYDC256B16 and CYDC128B08 devices. Output Drive Register; These outputs are Open Drain. Special Function Enable M/S Master or Slave Select VCC Core Power GND Ground VDDIOL Left Port I/O Voltage VDDIOR Right Port I/O Voltage NC No Connect. Leave this pin Unconnected. Functional Description The CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 are low-power CMOS 4k, 8k,16k x 16, and 8/16k x 8 dual-port static RAMs. Arbitration schemes are included on the devices to handle situations when multiple processors access the same piece of data. Two ports are provided, permitting independent, asynchronous access for reads and writes to any location in memory. The devices can be utilized as standalone 16-bit dual-port static RAMs or multiple devices can be combined in order to function as a 32-bit or wider master/slave dual-port static RAM. An M/S pin is provided for implementing 32-bit or wider memory applications without the need for separate master and slave devices or additional discrete logic. Application areas include interprocessor/multiprocessor designs, communications status buffering, and dual-port video/graphics memory. Each port has independent control pins: Chip Enable (CE), Read or Write Enable (R/W), and Output Enable (OE). Two flags are provided on each port (BUSY and INT). BUSY signals that the port is trying to access the same location currently being accessed by the other port. The Interrupt flag (INT) permits communication between ports or systems by means of a mail box. The semaphores are used to pass a flag, or token, from one port to the other to indicate that a shared resource is in use. The semaphore logic is comprised of eight shared latches. Only one side can control the latch (semaphore) at any time. Control of a semaphore indicates that a shared resource is in use. An automatic power-down feature is controlled independently on each port by a Chip Enable (CE) pin. Document #: 001-01638 Rev. *E The CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 are available in 100-pin TQFP packages. Power Supply The core voltage (VCC) can be 1.8V, 2.5V or 3.0V, as long as it is lower than or equal to the I/O voltage. Each port can operate on independent I/O voltages. This is determined by what is connected to the VDDIOL and VDDIOR pins. The supported I/O standards are 1.8V/2.5V LVCMOS and 3.0V LVTTL. Write Operation Data must be set up for a duration of tSD before the rising edge of R/W in order to guarantee a valid write. A write operation is controlled by either the R/W pin (see Write Cycle No. 1 waveform) or the CE pin (see Write Cycle No. 2 waveform). Required inputs for non-contention operations are summarized in Table 1. If a location is being written to by one port and the opposite port attempts to read that location, a port-to-port flowthrough delay must occur before the data is read on the output; otherwise the data read is not deterministic. Data will be valid on the port tDDD after the data is presented on the other port. Read Operation When reading the device, the user must assert both the OE and CE pins. Data will be available tACE after CE or tDOE after OE is asserted. If the user wishes to access a semaphore flag, Page 5 of 26 [+] Feedback CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 then the SEM pin must be asserted instead of the CE pin, and OE must also be asserted. Interrupts The upper two memory locations may be used for message passing. The highest memory location (FFF for the CYDC064B16, 1FFF for the CYDC128B16 and CYDC064B08, 3FFF for the CYDC256B16 and CYDC128B08) is the mailbox for the right port and the second-highest memory location (FFE for the CYDC064B16, 1FFE for the CYDC128B16 and CYDC064B08, 3FFE for the CYDC256B16 and CYDC128B08) is the mailbox for the left port. When one port writes to the other port’s mailbox, an interrupt is generated to the owner. The interrupt is reset when the owner reads the contents of the mailbox. The message is user-defined. Each port can read the other port’s mailbox without resetting the interrupt. The active state of the busy signal (to a port) prevents the port from setting the interrupt to the winning port. Also, an active busy to a port prevents that port from reading its own mailbox and, thus, resetting the interrupt to it. If an application does not require message passing, do not connect the interrupt pin to the processor’s interrupt request input pin. On power up, an initialization program should be run and the interrupts for both ports must be read to reset them. The operation of the interrupts and their interaction with Busy are summarized in Table 2. Busy The CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 provide on-chip arbitration to resolve simultaneous memory location access (contention). If both ports’ CEs are asserted and an address match occurs within tPS of each other, the busy logic will determine which port has access. If tPS is violated, one port will definitely gain permission to the location, but it is not predictable which port will get that permission. BUSY will be asserted tBLA after an address match or tBLC after CE is taken LOW. Master/Slave A M/S pin is provided in order to expand the word width by configuring the device as either a master or a slave. The BUSY output of the master is connected to the BUSY input of the slave. This will allow the device to interface to a master device with no external components. Writing to slave devices must be delayed until after the BUSY input has settled (tBLC or tBLA), otherwise, the slave chip may begin a write cycle during a contention situation. When tied HIGH, the M/S pin allows the device to be used as a master and, therefore, the BUSY line is an output. BUSY can then be used to send the arbitration outcome to a slave. Input Read Register The Input Read Register (IRR) captures the status of two external input devices that are connected to the Input Read pins. The contents of the IRR read from address x0000 from either port. During reads from the IRR, DQ0 and DQ1 are valid bits and DQ<15:2> are don’t care. Writes to address x0000 are not allowed from either port. Address x0000 is not available for standard memory accesses when SFEN = VIL. When SFEN = VIH, address x0000 is available for memory accesses. Document #: 001-01638 Rev. *E The inputs will be 1.8V/2.5V LVCMOS or 3.0V LVTTL, depending on the core voltage supply (VCC). Refer to Table 3 for Input Read Register operation. IRR is not available in the CYDC256B16 and CYDC128B08, as the IRR pins are used as extra address pins A13L and A13R. Output Drive Register The Output Drive Register (ODR) determines the state of up to five external binary state devices by providing a path to VSS for the external circuit. These outputs are Open Drain. The five external devices can operate at different voltages (1.5V ≤ VDDIO ≤ 3.5V) but the combined current cannot exceed 40 mA (8 mA max for each external device). The status of the ODR bits are set using standard write accesses from either port to address x0001 with a “1” corresponding to on and “0” corresponding to off. The status of the ODR bits can be read with a standard read access to address x0001. When SFEN = VIL, the ODR is active and address x0001 is not available for memory accesses. When SFEN = VIH, the ODR is inactive and address x0001 can be used for standard accesses. During reads and writes to ODR DQ<4:0> are valid and DQ<15:5> are don’t care. Refer to Table 4 for Output Drive Register operation. Semaphore Operation The CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 provide eight semaphore latches, which are separate from the dual-port memory locations. Semaphores are used to reserve resources that are shared between the two ports. The state of the semaphore indicates that a resource is in use. For example, if the left port wants to request a given resource, it sets a latch by writing a zero to a semaphore location. The left port then verifies its success in setting the latch by reading it. After writing to the semaphore, SEM or OE must be deasserted for tSOP before attempting to read the semaphore. The semaphore value will be available tSWRD + tDOE after the rising edge of the semaphore write. If the left port was successful (reads a zero), it assumes control of the shared resource, otherwise (reads a one) it assumes the right port has control and continues to poll the semaphore. When the right side has relinquished control of the semaphore (by writing a one), the left side will succeed in gaining control of the semaphore. If the left side no longer requires the semaphore, a one is written to cancel its request. Semaphores are accessed by asserting SEM LOW. The SEM pin functions as a chip select for the semaphore latches (CE must remain HIGH during SEM LOW). A0–2 represents the semaphore address. OE and R/W are used in the same manner as a normal memory access. When writing or reading a semaphore, the other address pins have no effect. When writing to the semaphore, only I/O0 is used. If a zero is written to the left port of an available semaphore, a one will appear at the same semaphore address on the right port. That semaphore can now only be modified by the side showing zero (the left port in this case). If the left port now relinquishes control by writing a one to the semaphore, the semaphore will be set to one for both sides. However, if the right port had requested the semaphore (written a zero) while the left port had control, the right port would immediately own the semaphore as soon as the left port released it. Table 5 shows sample semaphore operations. Page 6 of 26 [+] Feedback CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 When reading a semaphore, all sixteen/eight data lines output the semaphore value. The read value is latched in an output register to prevent the semaphore from changing state during a write from the other port. If both ports attempt to access the semaphore within tSPS of each other, the semaphore will definitely be obtained by one side or the other, but there is no guarantee which side will control the semaphore. On power-up, both ports should write “1” to all eight semaphores. Architecture The CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 consist of an array of 4k, 8k, or 16k words of 16 dual-port RAM cells, I/O and address lines, and control signals (CE, OE, R/W). The CYDC064B08 and CYDC128B08 consist of an array of 8k and 16k words of 8 each of dual-port RAM cells, I/O and address lines, and control signals (CE, OE, R/W).These control pins permit independent access for reads or writes to any location in memory. To handle simultaneous writes/reads to the same location, a BUSY pin is provided on each port. Two Interrupt (INT) pins can be utilized for port-to-port communication. Two Semaphore (SEM) control pins are used for allocating shared resources. With the M/S pin, the devices can function as a master (BUSY pins are outputs) or as a slave (BUSY pins are inputs). The devices also have an automatic power-down feature controlled by CE. Each port is provided with its own output enable control (OE), which allows data to be read from the device. Table 1. Non-Contending Read/Write Inputs Outputs I/O8–I/O15[11] CE R/W OE UB LB SEM I/O0–I/O7 H X X X X H X X X H H H High Z High Z Deselected: Power-down L L X L H H Data In High Z Write to Upper Byte Only L L X H L H High Z Data In Write to Lower Byte Only L L X L L H Data In Data In Write to Both Bytes L H L L H H Data Out High Z Read Upper Byte Only L H L H L H High Z Data Out Read Lower Byte Only L H L L L H Data Out Data Out Read Both Bytes X X H X X X High Z High Z Outputs Disabled H H L X X L Data Out Data Out Read Data in Semaphore Flag X H L H H L Data Out Data Out Read Data in Semaphore Flag H X X X L Data In Data In Write DIN0 into Semaphore Flag X X H H L Data In Data In Write DIN0 into Semaphore Flag High Z High Z Operation Deselected: Power-down L X X L X L Not Allowed L X X X L L Not Allowed Table 2. Interrupt Operation Example (Assumes BUSYL = BUSYR = HIGH)[12] Left Port Function Set Right INTR Flag R/WL L CEL L OEL X Right Port A0L–13L 3FFF INTL R/WR CER OER A0R–13R INTR X X X X X L[14] [15] [15] H[13] Reset Right INTR Flag X X X X X X L L 3FFF Set Left INTL Flag X X X X L[13] L L X 3FFE[15] X [14] X X X X X Reset Left INTL Flag X L L 3FFE [15] H Notes: 11. This column applies to x16 devices only. 12. See Interrupts Functional Description for specific highest memory locations by device. 13. If BUSYR = L, then no change. 14. If BUSYL = L, then no change. 15. See Functional Description for specific addresses by device. Document #: 001-01638 Rev. *E Page 7 of 26 [+] Feedback CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 Table 3. Input Read Register Operation[16, 19] SFEN H L CE L L R/W OE H UB L H LB L L ADDR I/O0–I/O1 I/O2–I/O15 [17] L x0000-Max VALID X L x0000 UB LB ADDR [18] VALID [17] VALID X Mode Standard Memory Access IRR Read Table 4. Output Drive Register [20] SFEN CE R/W H L H L L L L L OE X H [21] [17] L X X L X I/O0–I/O4 I/O5–I/O15 Mode [17] [17] x0000-Max VALID VALID Standard Memory Access [17] L L L x0001 VALID[18] X ODR Write[20, 22] x0001 [18] X ODR Read[20] VALID Table 5. Semaphore Operation Example Function No action I/O0–I/O15 Left I/O0–I/O15 Right 1 1 Status Semaphore-free Left port writes 0 to semaphore 0 1 Left Port has semaphore token Right port writes 0 to semaphore 0 1 No change. Right side has no write access to semaphore Left port writes 1 to semaphore 1 0 Right port obtains semaphore token Left port writes 0 to semaphore 1 0 No change. Left port has no write access to semaphore Right port writes 1 to semaphore 0 1 Left port obtains semaphore token Left port writes 1 to semaphore 1 1 Semaphore-free Right port writes 0 to semaphore 1 0 Right port has semaphore token Right port writes 1 to semaphore 1 1 Semaphore free Left port writes 0 to semaphore 0 1 Left port has semaphore token Left port writes 1 to semaphore 1 1 Semaphore-free Notes: 16. SFEN = VIL for IRR reads. 17. UB or LB = VIL. If LB = VIL, then DQ<7:0> are valid. If UB = VIL then DQ<15:8> are valid. 18. LB must be active (LB = VIL) for these bits to be valid. 19. SFEN active when either CEL = VIL or CER = VIL. It is inactive when CEL = CER = VIH. 20. SFEN = VIL for ODR reads and writes. 21. Output enable must be low (OE = VIL) during reads for valid data to be output. 22. During ODR writes data will also be written to the memory. Document #: 001-01638 Rev. *E Page 8 of 26 [+] Feedback CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 Maximum Ratings[23] Output Current into Outputs (LOW)............................. 90 mA (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Supply Voltage to Ground Potential ............... –0.5V to +3.3V DC Voltage Applied to Outputs in High-Z State..........................–0.5V to VCC + 0.5V DC Input Voltage[24] ...............................–0.5V to VCC + 0.5V Static Discharge Voltage.......................................... > 2000V Latch-up Current.................................................... > 200 mA Operating Range Range Ambient Temperature VCC 0°C to +70°C 1.8V ± 100 mV 2.5V ± 100 mV 3.0V ± 300 mV –40°C to +85°C 1.8V ± 100 mV 2.5V ± 100 mV 3.0V ± 300 mV Commercial Industrial Electrical Characteristics for VCC = 1.8V Over the Operating Range Parameter VOH VOL VOL ODR Description P1 I/O P2 I/O Voltage Voltage CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 -40 -55 Min. VIL IOZ ICEX ODR Max. Min. Typ. Max. Unit Output HIGH Voltage (IOH = –100 µA) 1.8V (any port) VDDIO – 0.2 VDDIO – 0.2 V Output HIGH Voltage (IOH = –2 mA) 2.5V (any port) 2.0 2.0 V Output HIGH Voltage (IOH = –2 mA) 3.0V (any port) 2.1 2.1 V Output LOW Voltage (IOL = 100 µA) 1.8V (any port) 0.2 0.2 V Output HIGH Voltage (IOL = 2 mA) 2.5V (any port) 0.4 0.4 V Output HIGH Voltage (IOL = 2 mA) 3.0V (any port) 0.4 0.4 V ODR Output LOW Voltage (IOL = 8 mA) 1.8V (any port) 0.2 0.2 V 2.5V (any port) 0.2 0.2 V 3.0V (any port) VIH Typ. Input HIGH Voltage Input LOW Voltage Output Leakage Current ODR Output Leakage Current. VOUT = VDDIO 0.2 V 1.8V (any port) 1.2 VDDIO + 0.2 0.2 1.2 VDDIO + 0.2 V 2.5V (any port) 1.7 VDDIO + 0.3 1.7 VDDIO + 0.3 V 3.0V (any port) 2.0 VDDIO + 0.2 2.0 VDDIO + 0.2 V 1.8V (any port) –0.2 0.4 –0.2 0.4 V 2.5V (any port) –0.3 0.6 –0.3 0.6 V 3.0V (any port) –0.2 0.7 –0.2 0.7 V 1.8V 1.8V –1 1 –1 1 µA 2.5V 2.5V –1 1 –1 1 µA 3.0V 3.0V –1 1 –1 1 µA 1.8V 1.8V –1 1 –1 1 µA 2.5V 2.5V –1 1 –1 1 µA 3.0V 3.0V –1 1 –1 1 µA Notes: 23. The voltage on any input or I/O pin can not exceed the power pin during power-up. 24. Pulse width < 20 ns. Document #: 001-01638 Rev. *E Page 9 of 26 [+] Feedback CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 Electrical Characteristics for VCC = 1.8V (continued) Over the Operating Range Parameter IIX P1 I/O P2 I/O Voltage Voltage Description Input Leakage Current CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 -40 -55 Min. Typ. Max. Min. Typ. Max. Unit 1.8V 1.8V –1 1 –1 1 µA 2.5V 2.5V –1 1 –1 1 µA 3.0V 3.0V –1 1 –1 1 µA ICC Operating Current (VCC = Max., IOUT = 0 mA) Outputs Disabled Ind. 1.8V 1.8V 25 40 15 25 mA ISB1 Standby Current (Both Ports TTL Ind. Level) CEL and CER ≥ VCC – 0.2, SEML = SEMR = VCC – 0.2, f = fMAX 1.8V 1.8V 2 6 2 6 µA ISB2 Standby Current (One Port TTL Level) CEL | CER ≥ VIH, f = fMAX Ind. 1.8V 1.8V 8.5 18 8.5 14 mA ISB3 Standby Current (Both Ports CMOS Level) CEL & CER ≥ VCC − 0.2V, SEML and SEMR > VCC – 0.2V, f = 0 Ind. 1.8V 1.8V 2 6 2 6 µA ISB4 Standby Current (One Port CMOS Ind. Level) CEL | CER ≥ VIH, f = fMAX[25] 1.8V 1.8V 8.5 18 8.5 14 mA Notes: 25. fMAX = 1/tRC = All inputs cycling at f = 1/tRC (except output enable). f = 0 means no address or control lines change. This applies only to inputs at CMOS level standby ISB3. Document #: 001-01638 Rev. *E Page 10 of 26 [+] Feedback CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 Electrical Characteristics for VCC = 2.5V Over the Operating Range Parameter Description CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 -40 -55 P1 I/O P2 I/O Voltage Voltage Min. 2.5V (any port) 2.0 2.1 Typ. Max. Min. Typ. Max. Unit VOH Output HIGH Voltage (IOH = –2 mA) 2.0 V Output HIGH Voltage (IOH = –2 mA) 3.0V (any port) VOL Output LOW Voltage (IOL = 2 mA) 2.5V (any port) 0.4 0.4 V 2.1 V Output LOW Voltage (IOL = 2 mA) 3.0V (any port) 0.4 0.4 V VOL ODR ODR Output LOW Voltage (IOL = 8 mA) 2.5V (any port) 0.2 0.2 V VIH Input HIGH Voltage 3.0V (any port) 0.2 V 2.5V (any port) 1.7 VDDIO + 0.3 0.2 1.7 VDDIO + 0.3 V 3.0V (any port) 2.0 VDDIO + 0.2 2.0 VDDIO + 0.2 V 2.5V (any port) –0.3 0.6 –0.3 0.6 V 3.0V (any port) VIL Input LOW Voltage IOZ Output Leakage Current ICEX ODR ODR Output Leakage Current. VOUT = VCC 3.0V IIX Input Leakage Current 2.5V 3.0V 3.0V –1 1 µA ICC Operating Current (VCC = Max., IOUT = 0 mA) Outputs Disabled Ind. 2.5V 2.5V 39 55 28 40 mA ISB1 Standby Current (Both Ports TTL Ind. Level) CEL and CER ≥ VCC – 0.2, SEM L= SEMR = VCC – 0.2, f=fMAX 2.5V 2.5V 6 8 6 8 µA ISB2 Standby Current (One Port TTL Level) CEL | CER ≥ VIH, f = fMAX Ind. 2.5V 2.5V 21 30 18 25 mA ISB3 Standby Current (Both Ports CMOS Level) CEL & CER ≥ VCC − 0.2V, SEML and SEMR > VCC – 0.2V, f = 0 Ind. 2.5V 2.5V 4 6 4 6 µA ISB4 Standby Current (One Port CMOS Ind. Level) CEL | CER ≥ VIH, f = fMAX[25] 2.5V 2.5V 21 30 18 25 mA Document #: 001-01638 Rev. *E –0.2 0.7 –0.2 0.7 V 2.5V 2.5V –1 1 –1 1 µA 3.0V 3.0V –1 1 –1 1 µA 2.5V 2.5V –1 1 –1 1 µA 3.0V –1 1 –1 1 µA 2.5V –1 1 –1 1 µA 1 –1 Page 11 of 26 [+] Feedback CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 Electrical Characteristics for 3.0V Over the Operating Range Parameter Description CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 -40 -55 P1 I/O P2 I/O Voltage Voltage Min. 3.0V (any port) 2.1 Typ. Max. Min. Typ. Max. Unit VOH Output HIGH Voltage (IOH = –2 mA) 2.1 V VOL Output LOW Voltage (IOL = 2 mA) 3.0V (any port) 0.4 0.4 V VOL ODR ODR Output LOW Voltage (IOL = 8 mA) 3.0V (any port) 0.2 0.2 V VIH Input HIGH Voltage 3.0V (any port) 2.0 VDDIO + 0.2 2.0 VDDIO + 0.2 V VIL Input LOW Voltage 3.0V (any port) –0.2 0.7 –0.2 0.7 V IOZ Output Leakage Current 3.0V 3.0V –1 1 –1 1 µA ICEX ODR ODR Output Leakage Current. VOUT = VCC 3.0V 3.0V –1 1 –1 1 µA IIX Input Leakage Current 3.0V 3.0V –1 1 –1 1 µA ICC Operating Current (VCC = Max., IOUT = 0 mA) Outputs Disabled Ind. 3.0V 3.0V 49 70 42 60 mA ISB1 Standby Current (Both Ports TTL Ind. Level) CEL and CER ≥ VCC – 0.2, SEML = SEMR = VCC – 0.2, f = fMAX 3.0V 3.0V 7 10 7 10 µA ISB2 Standby Current (One Port TTL Level) CEL | CER ≥ VIH, f = fMAX Ind. 3.0V 3.0V 28 40 25 35 mA ISB3 Standby Current (Both Ports CMOS Level) CEL & CER ≥ VCC − 0.2V, SEML and SEMR > VCC – 0.2V, f = 0 Ind. 3.0V 3.0V 6 8 6 8 µA ISB4 Standby Current (One Port CMOS Ind. Level) CEL | CER ≥ VIH, f = fMAX[25] 3.0V 3.0V 28 40 25 35 mA Capacitance[26] Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 3.0V Max. Unit 9 pF 10 pF Note: 26. Tested initially and after any design or process changes that may affect these parameters. Document #: 001-01638 Rev. *E Page 12 of 26 [+] Feedback CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 AC Test Loads and Waveforms 7 3.0V/2.5V/1.8V 3.0V/2.5V/1.8V R1 RTH = 6 kΩ OUTPUT OUTPUT R1 OUTPUT C = 30 pF C = 30 pF R2 VTH = 0.8V (a) Normal Load (Load 1) (b) Thévenin Equivalent (Load 1) 1.8V R1 1022Ω 13500Ω 1.8V R2 792Ω 10800Ω GND 10% R2 (c) Three-State Delay (Load 2) (Used for tLZ, tHZ, tHZWE, and tLZWE including scope and jig) ALL INPUT PULSES 3.0V/2.5V C = 5 pF 90% 10% 90% ≤ 3 ns ≤ 3 ns Switching Characteristics for VCC = 1.8V Over the Operating Range[27] CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 -40 Parameter Description Min. -55 Max. Min. Max. Unit Read Cycle tRC Read Cycle Time tAA Address to Data Valid tOHA Output Hold From Address Change tACE[28] CE LOW to Data Valid 40 55 ns tDOE OE LOW to Data Valid 25 30 ns tLZOE [29, 30, 31] OE Low to Low Z tHZOE[29, 30, 31] OE HIGH to High Z tLZCE[29, 30, 31] tHZCE[29, 30, 31] tPU[31] tPD[31] tABE[28] CE LOW to Low Z 40 40 5 ns 55 5 5 5 ns 25 5 15 0 ns ns 5 15 CE HIGH to High Z CE LOW to Power-Up 55 ns ns 25 0 ns ns CE HIGH to Power-Down 40 55 ns Byte Enable Access Time 40 55 ns Write Cycle tWC Write Cycle Time 40 55 ns tSCE[28] CE LOW to Write End 30 45 ns tAW Address Valid to Write End 30 45 ns Notes: 27. Test conditions assume signal transition time of 3 ns or less, timing reference levels of VCC/2, input pulse levels of 0 to VCC, and output loading of the specified IOI/IOH and 30-pF load capacitance. 28. To access RAM, CE = L, UB = L, SEM = H. To access semaphore, CE = H and SEM = L. Either condition must be valid for the entire tSCE time. 29. At any given temperature and voltage condition for any given device, tHZCE is less than tLZCE and tHZOE is less than tLZOE. 30. Test conditions used are Load 3. 31. This parameter is guaranteed but not tested. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy waveform Document #: 001-01638 Rev. *E Page 13 of 26 [+] Feedback CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 Switching Characteristics for VCC = 1.8V Over the Operating Range[27] (continued) Parameter Description CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 -40 -55 Min. Max. Min. Max. Unit tHA Address Hold From Write End 0 0 ns tSA[28] Address Set-up to Write Start 0 0 ns tPWE Write Pulse Width 25 40 ns tSD Data Set-up to Write End 20 30 ns tHD Data Hold From Write End 0 0 ns tHZWE[30, 31] tLZWE[30, 31] tWDD[32] tDDD[32] R/W LOW to High Z R/W HIGH to Low Z 15 0 25 0 ns ns Write Pulse to Data Delay 55 80 ns Write Data Valid to Read Data Valid 55 80 ns tBLA BUSY LOW from Address Match 30 45 ns tBHA BUSY HIGH from Address Mismatch 30 45 ns tBLC BUSY LOW from CE LOW 30 45 ns tBHC BUSY HIGH from CE HIGH 30 45 ns tPS[34] Port Set-up for Priority tWB R/W HIGH after BUSY (Slave) tWH R/W HIGH after BUSY HIGH (Slave) Busy Timing [33] tBDD[35] 5 5 ns 0 0 ns 20 35 ns BUSY HIGH to Data Valid 30 40 ns [33] Interrupt Timing tINS INT Set Time 35 45 ns tINR INT Reset Time 35 45 ns Semaphore Timing tSOP SEM Flag Update Pulse (OE or SEM) 10 15 ns tSWRD SEM Flag Write to Read Time 10 10 ns tSPS SEM Flag Contention Window 10 10 ns tSAA SEM Address Access Time 40 55 ns Notes: 32. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy waveform. 33. Test conditions used are Load 2. 34. Add 2ns to this value when the I/O ports are operating at different voltages. 35. tBDD is a calculated parameter and is the greater of tWDD–tPWE (actual) or tDDD–tSD (actual). Document #: 001-01638 Rev. *E Page 14 of 26 [+] Feedback CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 Switching Characteristics for VCC = 2.5V Over the Operating Range Parameter Description CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 -40 -55 Min. Max. Min. Max. Unit Read Cycle tRC Read Cycle Time tAA Address to Data Valid tOHA Output Hold From Address Change tACE[28] CE LOW to Data Valid 40 55 ns tDOE OE LOW to Data Valid 25 30 ns tLZOE [29, 30, 31] OE Low to Low Z tHZOE[29, 30, 31] tLZCE[29, 30, 31] tHZCE[29, 30, 31] tPU[31] tPD[31] tABE[28] 40 40 5 CE LOW to Power-Up 55 15 ns 15 2 15 0 ns ns 2 2 CE HIGH to High Z ns 5 2 OE HIGH to High Z CE LOW to Low Z 55 ns ns 15 0 ns ns CE HIGH to Power-Down 40 55 ns Byte Enable Access Time 40 55 ns Write Cycle tWC Write Cycle Time tSCE[28] CE LOW to Write End 30 45 ns tAW Address Valid to Write End 30 45 ns tHA Address Hold From Write End 0 0 ns tSA[28] Address Set-up to Write Start 0 0 ns tPWE Write Pulse Width 25 40 ns tSD Data Set-up to Write End 20 30 ns tHD Data Hold From Write End 0 0 ns tHZWE[30, 31] tLZWE[30, 31] tWDD[32] tDDD[32] R/W LOW to High Z Busy Timing R/W HIGH to Low Z 40 55 15 0 ns 25 ns 0 ns Write Pulse to Data Delay 55 80 ns Write Data Valid to Read Data Valid 55 80 ns [33] tBLA BUSY LOW from Address Match 30 45 ns tBHA BUSY HIGH from Address Mismatch 30 45 ns tBLC BUSY LOW from CE LOW 30 45 ns tBHC BUSY HIGH from CE HIGH 30 45 ns tPS[34] Port Set-up for Priority 5 5 ns tWB R/W HIGH after BUSY (Slave) 0 0 ns tWH R/W HIGH after BUSY HIGH (Slave) 20 35 ns tBDD[35] BUSY HIGH to Data Valid Document #: 001-01638 Rev. *E 30 40 ns Page 15 of 26 [+] Feedback CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 Switching Characteristics for VCC = 2.5V Over the Operating Range (continued) Parameter Description CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 -40 -55 Min. Max. Min. Max. Unit Interrupt Timing[33] tINS INT Set Time 35 45 ns tINR INT Reset Time 35 45 ns Semaphore Timing tSOP SEM Flag Update Pulse (OE or SEM) 10 15 ns tSWRD SEM Flag Write to Read Time 10 10 ns tSPS SEM Flag Contention Window 10 10 ns tSAA SEM Address Access Time 40 55 ns Switching Characteristics for VCC = 3.0V Over the Operating Range Parameter Description CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 -40 -55 Min. Max. Min. Unit Max. Read Cycle tRC Read Cycle Time tAA Address to Data Valid tOHA Output Hold From Address Change tACE[28] CE LOW to Data Valid 40 55 ns tDOE OE LOW to Data Valid 25 30 ns tLZOE [29, 30, 31] tHZOE[29, 30, 31] tLZCE[29, 30, 31] tHZCE[29, 30, 31] tPU[31] tPD[31] tABE[28] OE Low to Low Z 40 40 5 CE LOW to Power-Up 55 15 ns 15 1 15 0 ns ns 1 1 CE HIGH to High Z ns 5 1 OE HIGH to High Z CE LOW to Low Z 55 ns ns 15 0 ns ns CE HIGH to Power-Down 40 55 ns Byte Enable Access Time 40 55 ns Write Cycle tWC Write Cycle Time tSCE[28] CE LOW to Write End 30 45 ns tAW Address Valid to Write End 30 45 ns tHA Address Hold From Write End 0 0 ns tSA[28] Address Set-up to Write Start 0 0 ns tPWE Write Pulse Width 25 40 ns tSD Data Set-up to Write End 20 30 ns tHD Data Hold From Write End 0 0 ns Document #: 001-01638 Rev. *E 40 55 ns Page 16 of 26 [+] Feedback CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 Switching Characteristics for VCC = 3.0V Over the Operating Range (continued) Parameter Description tHZWE[30, 31] R/W LOW to High Z [30, 31] R/W HIGH to Low Z tLZWE tWDD[32] tDDD[32] CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 -40 -55 Min. Max. Min. 15 0 Unit Max. 25 0 ns ns Write Pulse to Data Delay 55 80 ns Write Data Valid to Read Data Valid 55 80 ns tBLA BUSY LOW from Address Match 30 45 ns tBHA BUSY HIGH from Address Mismatch 30 45 ns tBLC BUSY LOW from CE LOW 30 45 ns tBHC BUSY HIGH from CE HIGH 30 45 ns tPS[34] Port Set-up for Priority 5 5 ns tWB R/W HIGH after BUSY (Slave) 0 0 ns tWH R/W HIGH after BUSY HIGH (Slave) 20 tBDD[35] BUSY HIGH to Data Valid Busy Timing[33] 35 ns 30 40 ns Interrupt Timing[33] tINS INT Set Time 35 45 ns tINR INT Reset Time 35 45 ns Semaphore Timing tSOP SEM Flag Update Pulse (OE or SEM) 10 15 ns tSWRD SEM Flag Write to Read Time 10 10 ns tSPS SEM Flag Contention Window 10 tSAA SEM Address Access Time Document #: 001-01638 Rev. *E 10 40 ns 55 ns Page 17 of 26 [+] Feedback CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 Switching Waveforms Read Cycle No.1 (Either Port Address Access)[36, 37, 38] tRC ADDRESS tOHA DATA OUT tAA tOHA PREVIOUS DATA VALID DATA VALID Read Cycle No.2 (Either Port CE/OE Access)[36, 39, 40] tACE CE and LB or UB tHZCE tDOE OE tHZOE tLZOE DATA VALID DATA OUT tLZCE tPU CURRENT tPD ICC ISB Read Cycle No. 3 (Either Port)[36, 38, 41, 42] tRC ADDRESS tOHA tAA UB or LB tHZCE tLZCE tABE CE tHZCE tACE tLZCE DATA OUT Notes: 36. R/W is HIGH for read cycles. 37. Device is continuously selected CE = VIL and UB or LB = VIL. This waveform cannot be used for semaphore reads. 38. OE = VIL. 39. Address valid prior to or coincident with CE transition LOW. 40. To access RAM, CE = VIL, UB or LB = VIL, SEM = VIH. To access semaphore, CE = VIH, SEM = VIL. 41. R/W must be HIGH during all address transitions. 42. A write occurs during the overlap (tSCE or tPWE) of a LOW CE or SEM and a LOW UB or LB. Document #: 001-01638 Rev. *E Page 18 of 26 [+] Feedback CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 Switching Waveforms (continued) Write Cycle No.1: R/W Controlled Timing[41, 42, 43, 44, 45, 46] tWC ADDRESS tHZOE [47] OE tAW CE [45, 46] tPWE[44] tSA tHA R/W tHZWE[47] DATA OUT tLZWE NOTE 48 NOTE 48 tSD tHD DATA IN Write Cycle No. 2: CE Controlled Timing[41, 42, 43, 48] tWC ADDRESS tAW CE [45, 46] tSA tSCE tHA R/W tSD tHD DATA IN Notes: 43. tHA is measured from the earlier of CE or R/W or (SEM or R/W) going HIGH at the end of write cycle. 44. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tPWE or (tHZWE + tSD) to allow the I/O drivers to turn off and data to be placed on the bus for the required tSD. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tPWE. 45. To access RAM, CE = VIL, SEM = VIH. 46. To access upper byte, CE = VIL, UB = VIL, SEM = VIH. To access lower byte, CE = VIL, LB = VIL, SEM = VIH. 47. Transition is measured ±0 mV from steady state with a 5-pF load (including scope and jig). This parameter is sampled and not 100% tested. 48. During this period, the I/O pins are in the output state, and input signals must not be applied. Document #: 001-01638 Rev. *E Page 19 of 26 [+] Feedback CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 Switching Waveforms (continued) Semaphore Read After Write Timing, Either Side[49, 50] tSAA A0–A2 VALID ADRESS VALID ADRESS tAW tACE tHA SEM tOHA tSCE tSOP tSD I/O0 DATAIN VALID tSA tPWE DATAOUT VALID tHD R/W tSWRD tDOE tSOP OE WRITE CYCLE READ CYCLE Timing Diagram of Semaphore Contention[51, 52] A0L–A2L MATCH R/WL SEML tSPS A0R–A2R MATCH R/WR SEMR Notes: 49. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance state. 50. CE = HIGH for the duration of the above timing (both write and read cycle). 51. I/O0R = I/O0L = LOW (request semaphore); CER = CEL = HIGH. 52. If tSPS is violated, the semaphore will definitely be obtained by one side or the other, but which side will get the semaphore is unpredictable. Document #: 001-01638 Rev. *E Page 20 of 26 [+] Feedback CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 Switching Waveforms (continued) Timing Diagram of Read with BUSY (M/S=HIGH)[53] tWC ADDRESSR MATCH tPWE R/WR tHD tSD DATA INR VALID tPS ADDRESSL MATCH tBLA tBHA BUSYL tBDD tDDD DATAOUTL VALID tWDD Write Timing with Busy Input (M/S = LOW) tPWE R/W BUSY tWB tWH Note: 53. CEL = CER = LOW. Document #: 001-01638 Rev. *E Page 21 of 26 [+] Feedback CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 Switching Waveforms (continued) Busy Timing Diagram No.1 (CE Arbitration) CEL Valid First[54] ADDRESSL,R ADDRESS MATCH CEL tPS CER tBLC tBHC BUSYR CER Valid First ADDRESS L,R ADDRESS MATCH CER tPS CEL tBLC tBHC BUSYL Busy Timing Diagram No.2 (Address Arbitration)[54] Left Address Valid First tRC or tWC ADDRESSL ADDRESS MATCH ADDRESS MISMATCH tPS ADDRESSR tBLA tBHA BUSYR Right Address Valid First tRC or tWC ADDRESSR ADDRESS MATCH ADDRESS MISMATCH tPS ADDRESSL tBLA tBHA BUSYL Note: 54. If tPS is violated, the busy signal will be asserted on one side or the other, but there is no guarantee to which side BUSY will be asserted. Document #: 001-01638 Rev. *E Page 22 of 26 [+] Feedback CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 Switching Waveforms (continued) Interrupt Timing Diagrams Left Side Sets INTR: ADDRESSL tWC WRITE 1FFF (OR 1/3FFF) tHA[55] CEL R/WL INTR tINS [56] Right Side Clears INTR: tRC READ 1FFF (OR 1/3FFF) ADDRESSR CER tINR [56] R/WR OER INTR Right Side Sets INTL: ADDRESSR tWC WRITE 1FFE (OR 1/3FFE) tHA[55] CER R/WR INTL [56] tINS Left Side Clears INTL: tRC READ 1FFE OR 1/3FFE) ADDRESSR CEL tINR[56] R/WL OEL INTL Notes: 55. tHA depends on which enable pin (CEL or R/WL) is deasserted first. 56. tINS or tINR depends on which enable pin (CEL or R/WL) is asserted last. Document #: 001-01638 Rev. *E Page 23 of 26 [+] Feedback CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 Ordering Information 16k x16 1.8V Asynchronous Dual-Port SRAM Speed (ns) Ordering Code Package Name Package Type Operating Range 40 CYDC256B16-40AXC AZ0AB 100-pin Lead-free TQFP Commercial 55 CYDC256B16-55AXC AZ0AB 100-pin Lead-free TQFP Commercial 55 CYDC256B16-55AXI AZ0AB 100-pin Lead-free TQFP Industrial 8k x16 1.8V Asynchronous Dual-Port SRAM Speed (ns) Ordering Code Package Name Package Type Operating Range 40 CYDC128B16-40AXC AZ0AB 100-pin Lead-free TQFP Commercial 55 CYDC128B16-55AXC AZ0AB 100-pin Lead-free TQFP Commercial 55 CYDC128B16-55AXI AZ0AB 100-pin Lead-free TQFP Industrial 4k x16 1.8V Asynchronous Dual-Port SRAM Speed (ns) Ordering Code Package Name Package Type Operating Range 40 CYDC064B16-40AXC AZ0AB 100-pin Lead-free TQFP Commercial 55 CYDC064B16-55AXC AZ0AB 100-pin Lead-free TQFP Commercial 55 CYDC064B16-55AXI AZ0AB 100-pin Lead-free TQFP Industrial 16k x8 1.8V Asynchronous Dual-Port SRAM Speed (ns) Ordering Code Package Name Package Type Operating Range 40 CYDC128B08-40AXC AZ0AB 100-pin Lead-free TQFP Commercial 55 CYDC128B08-55AXC AZ0AB 100-pin Lead-free TQFP Commercial 55 CYDC128B08-55AXI AZ0AB 100-pin Lead-free TQFP Industrial 8k x8 1.8V Asynchronous Dual-Port SRAM Speed (ns) Ordering Code Package Name Package Type Operating Range 40 CYDC064B08-40AXC AZ0AB 100-pin Lead-free TQFP Commercial 55 CYDC064B08-55AXC AZ0AB 100-pin Lead-free TQFP Commercial 55 CYDC064B08-55AXI AZ0AB 100-pin Lead-free TQFP Industrial Document #: 001-01638 Rev. *E Page 24 of 26 [+] Feedback CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 Package Diagram 100-Pin Thin Plastic Quad Flat Pack (TQFP) A100 51-85048-*C All products and company names mentioned in this document may be the trademarks of their respective holders. Document #: 001-01638 Rev. *E Page 25 of 26 © Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. [+] Feedback CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 Document History Page Document Title: CYDC256B16/CYDC128B16/CYDC064B16/CYDC128B08/CYDC064B08 1.8V 4k/8k/16k x 16 and 8k/16k x 8 ConsuMoBL Dual-Port Static RAM Document Number: 001-01638 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 385185 SEE ECN YDT New data sheet *A 396697 SEE ECN KGH Updated ISB2 and ISB4 typo to mA. Updated tINS and tINR for -55 to 31ns. *B 404777 SEE ECN KGH Updated IOH and IOL values for the 1.8V, 2.5V and 3.0V parameters VOH and VOL Replaced -35 speed bin with -40 Updated Switching Characteristics for VCC = 2.5V and VCC = 3.0V Included note 34 *C 463014 SEE ECN HKH Changed spec title to from “Consumer Dual-Port” to “ConsuMoBL Dual-Port” Cypress Internet Release *D 505803 SEE ECN HKH Corrected typo in Features and Ordering Info sections. Cypress external web release. *E 735537 SEE ECN HKH Corrected typo in Pg5 power supply section Updated tDDD timing value to be consistent with tWDD Document #: 001-01638 Rev. *E Page 26 of 26 [+] Feedback