DAC161S055
Precision 16-Bit, Buffered Voltage-Output DAC
General Description
Key Specifications
The DAC161S055 is a precision 16-bit, buffered voltage output Digital-to-Analog Converter (DAC) that operates from a
2.7V to 5.25V supply with a separate I/O supply pin that operates down to 1.7V. The on-chip precision output buffer
provides rail-to-rail output swing and has a typical settling time
of 5 µsec. The external voltage reference can be set between
2.5V and VA (the analog supply voltage), providing the widest
dynamic output range possible.
The 4-wire SPI compatible interface operates at clock rates
up to 20 MHz. The part is capable of Diasy Chain and Data
Read Back. An on board power-on-reset (POR) circuit ensures the output powers up to a known state.
The DAC161S055 features a power-up value pin (MZB), a
load DAC pin (LDACB) and a DAC clear (CLRB) pin. MZB
sets the startup output voltage to either GND or mid-scale.
LDACB updates the output, allowing multiple DACs to update
their outputs simultaneously. CLRB can be used to reset the
output signal to the value determined by MZB.
The DAC161S055 has a power-down option that reduces
power consumption when the part is not in use. It is available
in a 16-lead LLP package.
■
■
■
■
■
■
Resolution (guaranteed monotonic)
16 bits
INL
±3 LSB (max)
Very low output noise
120 nV/√Hz (typ)
Glitch impulse
7 nV-s (typ)
Output settling time
5 µs (typ)
Power consumption
5.5 mW @ 5.25V (max)
Features
■
■
■
■
■
■
■
16-bit DAC with a two-buffer SPI interface
Asynchronous load DAC and reset pins
Compatibility with 1.8V controllers
Buffered voltage output with rail-to-rail capability
Wide voltage reference range of +2.5V to VA
Wide temperature range of −40°C to +105°C
Packaged in a 16-pin LLP
Applications
■
■
■
■
■
■
■
Process control
Automatic test equipment
Programmable voltage sources
Communication systems
Data acquisition
Industrial PLCs
Portable battery powered instruments
Block Diagram
30128803
SPI™ is a trademark of Motorola, Inc.
© 2012 Texas Instruments Incorporated
301288 SNAS503B
www.ti.com
DAC161S055 Precision 16-Bit, Buffered Voltage-Output DAC
January 27, 2012
DAC161S055
Connection Diagram
30128802
Pin Descriptions
Pin Name
Pin #
LLP-16
ESD Structure
Type
Function and Connection
VDDIO
16
Power
SPI, CLRB, LDACB Supply Voltage.
VA
1
Power
Analog Supply Voltage.
VOUT
2
Analog Output
VREF
6
Analog Input
GND
7
Ground
SDI
11
Digital Input
SPI data input .
Digital Input
Chip select signal for SPI interface. On the falling
edge of CSB the chip begins to accept data and
output data with the SCLK signal. This pin is active
low.
CSB
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12
2
DAC output.
Voltage Reference Input.
Ground (Analog and Digital).
Pin #
LLP-16
ESD Structure
Type
DAC161S055
Pin Name
Function and Connection
SCLK
10
Digital Input
SDO
9
Digital Output
LDACB
13
Digital Input
Load DAC signal. This signal transfers DAC data
from the SPI input register to the DAC output
register. The signal is active low.
CLRB
14
Digital Input
Asynchronous Reset. If this pin is pulled low, the
output will be updated to its power up condition set
by the MZB pin. This pin is active low.
MZB
15
Digital Input
Power up at Zero/Mid-scale. Tie this pin to GND to
power up to Zero or to VA to power up to mid-scale.
NC
DAP
Serial data clock for SPI Interface.
Data Out for daisy chain or data read back
verification.
No connect pins. Connect to GND in board layout
will result in the lowest amount of coupled noise.
3,4,5,8
Attach die attach paddle to GND for best noise
performance.
DAP
Ordering Information
Order Number
NS Package Number
DAC161S055CISQ
DAC161S055CISQE
Transport Media
Tape and Reel: 1000pcs
SQA16A
DAC161S055CISQX
Tape and Reel: 250psc
Tape and Reel: 4500pcs
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DAC161S055
Storage Temperature Range
−65°C to +150°C
Junction Temperature
+150°C
For soldering specifications:
see product folder at www.national.com and
www.national.com/ms/MS/MS-SOLDERING.pdf
Absolute Maximum Ratings (Note 1, Note
2)
If Military/Aerospace specified devices are required,
please contact the Texas Instruments Sales Office/
Distributors for availability and specifications.
Recommended Operating
Conditions(Note 1, Note 2)
Supply Voltage, VA
−0.3V to 6.0V
Supply Voltage VDDIO
−0.3V to VA+0.3V
Any pin relative to GND
6V, −0.3V
Voltage on MZB or VREF Input Pin
−0.3V to VA+0.3V
(Note 3)
Voltage on any other Input Pin (Note
−0.3V to VDDIO+0.3V
3)
Voltage on VOUT (Note 3)
−0.3V to VA+0.3V
Voltage on SDO (Note 3)
−0.3V to VDDIO+0.3V
Input Current at Any Pin (Note 3)
5mA
Output Current Source or Sink by Vout
10mA
Output Current Source or Sink by
SDO
3mA
Total Package Input and Output
Current
20mA
ESD Susceptibility
Human Body Model
3000V
Machine Model
250V
Charged Device Model (CDM)
1250V
Operating Temperature Range
Supply Voltage, VA
Supply Voltage VDDIO
Reference Voltage VREF
Digital Input Voltage
Output Load
Package Thermal Resistance
θJA (Note 4)
θJC
−40°C to +105°C
+2.7V to 5.25V
+1.7 V to VA
+2.5V to VA
0 to VDDIO
0 to 200 pF
41°C/W
6.5°C/W
Electrical Characteristics
The following specifications apply for VA = 2.7V to 5.25V, VDDIO = VA, VREF = 2.5V to VA, RL = 10k to GND, CL = 200 pF to
GND, fSCLK = 20 MHz, input code range 512 to 65023. Boldface limits apply for TMIN ≤ TA ≤ TMAX: all other limits apply to TA =
25°C, unless otherwise specified.(Note 1, Note 2, Note 5)
Symbol
Parameter
Conditions
Min
Typ
Max
±1
±3
Units
STATIC PERFORMANCE
N
Resolution
16
INL
Integral Non-Linearity
No load. From code 512 to Full Scale
- 512. VA=5V, VREF=4.096V
DNL
Differential Non-Linearity
No load. From code 512 to Full Scale
- 512. VA=5V, VREF=4.096V
-1
ZE
Zero Code Error
FSE
Full Scale Error
-15
OE
Offset Error
4
-11
Offset Error Drift
GE
Bits
Gain Error
No load. From code 512 to Full Scale
- 512. VA=5V, VREF=4.096V
Gain Temperature
Coefficient
No load. From code 512 to Full Scale
- 512. VA=5V, VREF=4.096V
±1
LSB
1.1
LSB
15
mV
15
mV
11
mV
±4
µV/°C
±0.05
% of FS
-25
25
±2
mV
ppm FS/°
C
REFERENCE INPUT CHARACTERISTICS
VREF
Reference Input Voltage
Range
VA = 2.7V to 5.25V
2.5
Reference Input
Impedance
VA
12.5
V
kΩ
ANALOG OUTPUT CHARACTERISTICS
Output Voltage Range
No load.
0.015
DC Output Impedance
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VA-0.04
2
4
V
Ω
ZCO
FSO
CL
Parameter
Zero Code Output
Full Scale Output
Conditions
Min
Typ
VA=3V, IOUT=200 µA; VREF=2.5
3
VA=3V, IOUT=1mA; VREF=2.5
4
VA=5V, IOUT=200 µA; VREF=4.096
4
VA=5V, IOUT=1mA; VREF=4.096
4
VA=3V, IOUT=200 µA; VREF=2.5
2.495
VA=3V, IOUT=1mA; VREF=2.5
2.494
VA=5V, IOUT=200 µA; VREF=4.096
4.091
VA=5V, IOUT=1mA; VREF=4.096
4.089
Maximum Capacitive Load Parallel R = 10KΩ
Max
Units
mV
V
500
pF
Series R = 50Ω
15
µF
RL
Minimum Resistive Load
10
kΩ
ISC
Short Circuit Current
VA = +5V, VREF=4.096
353
mA
tPU
Power-up Time
From Power Down Mode
25
ms
ANALOG OUTPUT DYNAMIC CHARCTERISTICS
SR
ts
Voltage Output Slew Rate
Positive and negative
2
V/µs
Voltage Output Settling
Time
¼ scale to ¾ scale VREF= VA = +5V,
settle to ±1 LSB.
5
µs
Digital Feedthrough
Code 0, all digital inputs from GND to
VDDIO
1
nV-s
Major Code Transition
Analog Glitch Impulse
VA=5V, VREF=2.5V. Transition from
mid-scale − 1LSB to mid-scale.
7
nV-s
Output Noise
Spot noise at 20 kHz
120
nV/√Hz
Integrated Output Noise
1Hz to 10 kHz
18
µV
DIGITAL INPUT CHARACTERISTICS
IIN
Input Current
VIL
Input Low Voltage
VIH
VILMZB
Input High Voltage
MZB Input Low Voltage
±1
VDDIO=5V
0.8
VDDIO=3V
0.8
VDDIO=1.8V
0.4
VDDIO=5V
2.1
VDDIO=3V
2.1
VDDIO=1.8V
1.4
CIN
MZB Input High Voltage
V
V
VA=5V
VA=3V
VIHMZB
µA
0.8
V
0.8
V
VA=5V
2.1
V
VA=3V
2.1
V
Input Capacitance
4
pF
DIGITAL OUTPUT CHARACTERISTICS
VOL
VOH
Output Low Voltage
Output High Voltage
Isink=200 µA; VDDIO>3V
400
Isink=2mA;VDDIO>3V
400
Isink=200 µA; VDDIO=1.8V
400
Isink=2mA;VDDIO=1.8V
400
Isink=200 µA; VDDIO>3V
VDDIO 0.2
Isink=2mA;VDDIO>3V
VDDIO 0.2
Isink=200 µA; VDDIO=1.8V
VDDIO 0.2
Isink=2mA;VDDIO=1.8V
lOZH, lOZL
TRI-STATE Leakage
Current
V
1.15
<1n
5
mV
±1µ
A
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DAC161S055
Symbol
DAC161S055
Symbol
COUT
Parameter
Conditions
Min
TRI-STATE Output
Capacitance
Typ
Max
4
Units
pF
POWER REQUIREMENTS
VA
Analog Supply Voltage
Range
2.7
5.25
V
VDDIO
Digital Supply Voltage
Range
1.7
VA
V
IVA
VA Supply Current
No load. SCLK Idle. All digital inputs
at GND or VDDIO. VA=5V
0.75
No load. SCLK Idle. All digital inputs
at GND or VDDIO. VA=3.3V
0.62
0.5
IREF
Reference Current
IPDVA
VA Power Down Supply
Current
All digital inputs at GND or VDDIO
IPDVO
VDDIO Power Down
Supply Current
All digital inputs at GND or VDDIO
IPDVR
VREF Power Down Supply
Current
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1
1
mA
mA
350
3
1
1
6
µA
These specifications apply for VA = 2.7V to 5.25V, VDDIO = 1.7V to VA, CL = 200 pF. Boldface limits apply for TA = −40°C to
105°C. All other limits apply to TA = 25°C, unless otherwise specified.
Symbol
fSCLK
Parameter
SCLK Frequency
Max
Units
VDDIO=1.7V to 2.7V
Conditions
Min
0
Typ
10
MHz
VDDIO=2.7V to 5.25V
0
20
tH
SCLK High Time
15
25
tL
SCLK Low Time
20
25
tCSB
CSB High Pulse width
tCSS
CSB Set-up Time Prior to
SCLK Rising edge
tCSH
CSB Hold Time after the
24th Falling Edge of SCLK
tZSDO
CSB Falling Edge to SDO
Valid
tSDOZ
CSB Rising Edge to SDO
HiZ
VDDIO=1.7V to 2.7V
75
VDDIO=2.7V to 5.25V
40
10
0
VDDIO=1.8V
40
VDDIO=3V
10
VDDIO=5V
6
VDDIO=1.8V
75
VDDIO=3V
40
VDDIO=5V
27
tCLRS
CSB Rising Edge to CLRB CLRB must not transition anytime
Falling Edge
CSB is low.
5
tLDACS
CSB Rising Edge to LDACB LDACB must not transition anytime
Falling Edge
CSB is low.
5
tLDAC
LDACB Low Time
10
2.5
tCLR
CLRB Low Time
10
2.5
tDS
SDI Data Set-up Time prior
to SCLK Rising Edge
10
tDH
SDI Data Hold Time after
SCLK Rising Edge
0
tDO
SDO Output Data Valid
ns
VDDIO=1.7
62
VDDIO=3.3
25
VDDIO=5
15
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability
and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in
the Recommended Operating Conditions is not implied. The recommended Operating Conditions indicate conditions at which the device is functional and the
device should not be operated beyond such conditions.
Note 2: The Electrical characteristics tables list guaranteed specifications under the listed Recommended Conditions except as otherwise modified or specified
by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed.
Note 3: When the input voltage (VI) at any pin exceeds the power supplies (VI < GND or VI > VDD) the current at that pin must be limited to 5mA and VI has to
be within the Absolute Maximum Rating for that pin. The 20mA package input current rating limits the number of pins that can safely exceed the power supplies
with current flow to four.
Note 4: The maximum power dissipation is a function of TJ(MAX) and θJA. The maximum allowable power dissipation at any ambient temperature is PD=(TJ(MAX)TA)/θJA
Note 5: Typical values represent most likely parametric norms at specific conditions (Example VA; specific temperature) and at the recommended Operating
Conditions at the time of product characterizations and are not guaranteed.
Note 6: Specification is guaranteed by characterization and is not tested in production.
Note 7: Specification is guaranteed by design and is not tested in production.
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DAC161S055
Digital Interface Timing Characteristics
DAC161S055
Timing Diagrams
30128806
FIGURE 1. DAC161S055 Input/Output Waveforms
30128807
30128808
30128810
30128809
30128812
30128811
FIGURE 2. Timing Parameter Specifics
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DAC161S055
Transfer Characteristics
30128805
FIGURE 3. Input/Output Transfer Characteristic
Specification Definitions
DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1 LSB, which is
VREF / 65536.
DIGITAL FEEDTHROUGH is a measure of the energy injected into the analog output of the DAC from the digital inputs when the
DAC outputs are not updated. It is measured with a full-scale code change on the data bus.
FULL-SCALE ERROR is the difference between the actual output voltage with a full scale code (FFFh) loaded into the DAC and
the value of VREF x 65535 / 65536.
GAIN ERROR is the deviation from the ideal slope of the transfer function. It can be calculated from Zero and Full-Scale Errors as
GE = FSE - ZE, where GE is Gain error, FSE is Full-Scale Error and ZE is Zero Error.
GLITCH IMPULSE is the energy injected into the analog output when the input code to the DAC register changes. It is specified
as the area of the glitch in nanovolt-seconds.
INTEGRAL NON_LINEARITY (INL) is a measure of the deviation of each individual code from a straight line through the input to
output transfer function. The deviation of any given code from this straight line is measured from the center of that code value. The
end point method is used. INL for this product is specified over a limited range, per the Electrical Tables.
LEAST SIGNIFICANT BIT (MSB) is the bit that has the smallest value or weight of all bits in a word. This value is LSB = VREF /
2n where VREF is the reference voltage for this product, and "n" is the DAC resolution in bits, which is 16 for the DAC161S055.
MAXIMUM LOAD CAPACITANCE is the maximum capacitance that can be driven by the DAC with output stability maintained,
although some ringing may be present.
MONOTONICITY is the condition of being monotonic, where the DAC output never decreases when the input code increases.
MOST SIGNIFICANT BIT (MSB) is the bit that has the largest value or weight of all bits in a word. Its value is 1/2 of VREF.
OFFSET ERROR is the difference between zero voltage and a where a straight line fit to the actual transfer function intersects the
y axis.
SETTLING TIME is the time for the output to settle to within 1 LSB of the final value after the input code is updated.
WAKE-UP TIME is the time for the output to recover after the device is commanded to the active mode from any of the power
down modes.
ZERO CODE ERROR is the output error, or voltage, present at the DAC output after a code of 0000h has been entered.
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DNL at VA = 5.0V
1.00
1.00
0.75
0.75
0.50
0.50
DNL (LSBs)
DNL (LSBs)
DNL at VA = 3.0V
0.25
0.00
-0.25
0.25
0.00
-0.25
-0.50
-0.50
-0.75
-0.75
-1.00
0
16,384
32,768
49,152
-1.00
65,536
0
OUTPUT CODE
16,384
32,768
49,152
65,536
OUTPUT CODE
30128820
30128821
INL at VA = 5.0V
1.00
1.00
0.75
0.75
0.50
0.50
0.25
0.25
INL (LSBs)
INL (LSBs)
INL at VA = 3.0V
0.00
-0.25
0.00
-0.25
-0.50
-0.50
-0.75
-0.75
-1.00
0
16,384
32,768
49,152
-1.00
65,536
0
OUTPUT CODE
16,384
32,768
49,152
65,536
OUTPUT CODE
30128822
30128823
DNL vs. Supply
INL vs. Supply
0.8
1.0
0.7
0.2
0.5
-DNL
+DNL
INL (LSBs)
0.4
INL (LSBs)
DAC161S055
Typical Performance Characteristics
0.0
-0.2
-0.4
-INL
+INL
0.0
-0.5
-0.6
-0.8
2.65
3.30
3.95
4.60
-1.0
2.65
5.25
SUPPLY VOLTAGE (V)
3.95
4.60
5.25
SUPPLY VOLTAGE (V)
30128824
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3.30
30128825
10
DAC161S055
DNL vs. VREF, VA=5V
INL vs. VREF, VA=5V
0.8
1.100
0.7
0.2
0.576
-DNL
+DNL
-INL
+INL
INL (LSBs)
DNL (LSBs)
0.4
0.0
0.051
-0.2
-0.4
-0.475
-0.6
-0.8
2.00
2.65
3.30
3.95
4.60
-1.000
2.00
5.25
2.65
3.30
V REF (V)
3.95
4.60
5.25
V REF (V)
30128826
30128827
DNL vs. Temperature, VA=5V, VREF=4.096
0.8
1.00
0.7
0.75
0.2
0.50
-DNL
+DNL
INL (LSBs)
0.4
DNL (LSBs)
INL vs. Temperature, VA=5V, VREF=4.096
0.0
-0.2
0.25
-DNL
+DNL
0.00
-0.25
-0.4
-0.50
-0.6
-0.75
-0.8
-50 -30 -10 10 30 50 70 90 110
-1.00
-50 -30 -10 10 30 50 70 90 110
TEMPERATURE (°C)
TEMPERATURE (°C)
30128828
30128829
Zero Code Error vs. IOUT
-0.08
VA=3V
VA=5V
VA=3V
VA=5V
FULL SCALE ERROR (%FS)
ZERO CODE ERROR (mV)
4.4
Full Scale Error vs. IOUT
-0.10
3.3
-0.12
2.2
-0.14
1.1
-0.16
0.0
200
400
600
800
-0.18
200
1,000
LOAD CURRENT (μA)
400
600
800
1,000
LOAD CURRENT (μA)
30128837
30128836
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DAC161S055
IVA vs VA
IVA vs TEMPERATURE
890
840
690
VA CURRENT (μA)
SUPPLY CURRENT (μA)
920
460
230
NO CLOCK, 5V
CLOCKING, 5V
NO CLOCK, 3.3V
CLOCKING, 3.3V
790
740
690
0
3
4
5
640
-50
6
SUPPLY VOLTAGE (VA)
-10
30
70
110
TEMPERATURE °C
30128834
30128843
IREF vs VREF
IREF vs TEMPERATURE
380
VA CURRENT (μA)
SUPPLY CURRENT (μA)
360
240
120
0
1.8
2.4
3.0
3.6
335
NO CLOCK, 5V
CLOCKING, 5V
NO CLOCK, 3.3V
CLOCKING, 3.3V
290
245
200
-50
4.2
SUPPLY VOLTAGE (VREF)
-10
30
70
110
TEMPERATURE °C
30128835
30128842
Settling Time
POR
3.5
3.60
5
2.0
1.5
1.65
VOUT
CSB
101
102
103
CSB (V)
VOUT (V)
2.5
2.30
1.00
100
OUTPUT VOLTAGE (V)
3.0
2.95
1.0
0.5
0.0
104
2
1
0
10
20
30
40
TIME (ms)
30128841
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3
0
TIME (μS)
VA
VOUT
4
30128838
12
DAC161S055
5V Glitch Response
1.275
Mid Scale-1 to Mid Scale
OUTPUT VOLTAGE (V)
1.270
1.265
1.260
1.255
1.250
1.245
1.240
2,000
2,500
3,000
3,500
4,000
TIME (ns)
30128839
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DAC161S055
1.0 Functional Description
1.1 DAC ARCHITECTURE OVERVIEW
The DAC161S055 uses a resistor array to convert the input
code to an analog signal, which in turn is buffered by the railto-rail output amplifier. The resistor array is factory trimmed
to achieve 16-bit accuracy.
An SPI interface shifts the input codes into the device. The
acquired input code is stored in the PREREG register. After
the input code is transferred to the DACREG register it affects
the state of the resistor array and the output level of the DAC.
The transfer can be initiated by the type of write command
used, by a software LDAC command or by the state of the
LDACB pin.
The user can control the power up state of the output using
the MZB pin and the power down state of the output using the
CONFIG register. Additionally, there are external pins and
CONFIG register bits that also control clearing the DAC.
NOTE: Although the DAC161S055 is a single channel device, the instruction set is for multichannel DACs. The
user must address channel 0 (A2,A1,A0={000}).
30128813
The acquired data is shifted into an internal 24 bit shift register
(MSB first) which is configured as a 24 bit deep FIFO. As the
data is being shifted into the FIFO via the SDI pin, the prior
contents of the register are being shifted out through the SDO
output. While CSB is high, SDO is in a high-Z state. At the
falling edge of CSB, SDO presents the MSB of the data
present in the shift register. SDO is updated on every subsequent falling edge of SCLK (note — the first SDO transition
will happen on the first falling edge AFTER the first rising edge
of SCLK when CSB is low).
The 24 bits of data contained in the FIFO are interpreted as
an 8 bit COMMAND word followed by 16 bits of DATA. The
general format of the 24 bit data stream is shown below. The
full Instruction Set is tabulated in Section 1.12 INSTRUCTION
SET.
1.2 OUTPUT AMPLIFIER
The output buffer amplifier is a rail to rail type which buffers
the signal produced by the resistor array and drives the external load. All amplifiers, including rail to rail amplifiers, exhibit a loss of linearity as the output nears the power rails (in
this case GND and VA). Thus the linearity of the part is specified over less than the full output range. The user can program the CONFIG register to power down the amplifier and
either place it in the high impedance state (HiZ), or have the
output terminated by an internal 10 kΩ pull-down resistor.
1.3 REFERENCE
An external reference source is required to produce an output.
The reference input is not internally buffered and presents a
resistive load to the external source. Loading presented by
the VREF pin varies by about 12.5% depending on the input
code. Thus a low impedance reference should be used for
best results.
30128814
1.4.1 SPI Write
SPI write operation is the simplest transaction available to the
user. There is no handshaking between master and the slave
(DAC161S055), and the master is the source of all signals
required for communication: SCLK, CSB, SDI. The format of
the data transfer is described in the section 1.4. The user instruction set is shown in Section 1.12 INSTRUCTION SET.
1.4 SERIAL INTERFACE
The 4-wire interface is compatible with SPI, QSPI and MICROWIRE, as well as most DSPs. See the Timing Diagrams for timing information about the read and write
sequences. The serial interface is the four signals CSB,
SCLK, SDI and SDO.
A bus transaction is initiated by the falling edge of the CSB.
Once CSB is low, the input data is sampled at the SDI pin by
the rising edge of the SCLK. The output data is put out on the
SDO pin on the falling edge of SCLK. At least 24 SCLK cycles
are required for a valid transfer to occur. If CSB is raised before 24th rising edge of the SCLK, the transfer is aborted. If
the CSB is held low after the 24th falling edge of the SCLK,
the data will continue to flow through the FIFO and out the
SDO pin. Once CSB transitions high, the internal controller
will decode the most recent 24 bits that were received before
the rising edge of CSB. The DAC will then change state depending on the instruction sent and the state of the LDACB
pin.
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1.4.2 SPI Read
The read operation requires all 4 wires of the SPI interface:
SCLK, SCB, SDI, SDO. The simplest READ operation occurs
automatically during any valid transaction on the SPI bus
since SDO pin of DAC161S055 always shifts out the contents
of the internal FIFO. Therefore the user can verify the data
being shifted in to the FIFO by initiating another transaction
and acquiring data at SDO. This allows for verification of the
FIFO contents only.
The 3 internal registers (PREREG, DACREG, CONFIG) can
be accessed by the user through the Register Read commands: RDDO, RDIN, RDCO respectively (see Section 1.12
INSTRUCTION SET). These operations require 2 SPI transaction to recover the register data. The first transaction shifts
in the Register Read command; an 8 bit command byte followed by 16 bit “dummy” data. The Register Read command
will cause the transfer of contents of the internal register into
the FIFO. The second transaction will shift out the FIFO contents; an 8 bit command byte (which is a copy of previous
14
DAC161S055
transaction) followed by the register data. The Register Read
operation is shown in the figure below.
30128815
1.4.2 SPI Daisy Chain
It is possible to control multiple DACs or other SPI devices
with a single master equipped with one SPI interface. This is
accomplished by connecting the DACs in a Daisy Chain. The
scheme is depicted in the figure below. An arbitrary length of
the chain and an arbitrary number of control bits for other devices in the chain is possible since individual DAC devices do
not count the data bits shifted in. Instead, they wait to decode
the contents of their respective shift registers until CSB is
raised high.
A typical bus cycle for this scheme is initiated by the falling
CSB. After the 24 SCLK cycles new data starts to appear at
the SDO pin of the first device in the chain, and starts shifting
into the second device. After 72 SCLK cycles following the
falling CSB edge, all three devices in this example will contain
new data in their input shift registers. Raising CSB will begin
the process of decoding data in each DAC. When in the Daisy
Chain the full READ and WRITE capability of every device is
maintained.
A sample of SPI data transfer appropriate for a 3 DAC Daisy
Chain is shown in the figure below.
1.6.1 Write-Through and Write-Block Modes
Using the SWB bit of the CONFIG register, the user can set
the part in WRITE-BLOCK or WRITE-THROUGH mode.
If the DAC channel is configured in the WRITE-BLOCK mode
(SWB=0, default), the DAC input DATA is held in the PREREG until the controller forces the transfer of DATA from
PREREG to DACREG register. Only DATA in DACREG register is converted to the equivalent analog output. The transfer
from PREREG into DACREG can be forced by both software
and hardware LDAC commands. The Data Writing commands WRUP and WRAL update both PREREG and
DACREG at the same time regardless of the channel mode.
WRITE-BLOCK mode is used in multi device or multi channel
applications. A user can preload all DAC channels with desired data, in multiple SPI transactions, and then issue a
single software LDAC command (or toggle the LDACB pin) to
simultaneously update all analog outputs.
If the DAC channel is configured in WRITE-THROUGH mode
(SWB=1) the controller updates both PREREG and DACREG
registers simultaneously. Therefore in WRITE-THROUGH
mode the channel output is updated as soon as the SPI transfer is completed i.e. upon the rising edge of CSB.
30128816
30128817
1.5 POWER-UP DEFAULT OUTPUT
It is possible to power up the DAC with the output either at
GND or midscale. This functionality is achieved by connecting
the MZB pin either to GND or to VA (note, the MZB pin is
referenced to VA, not VDDIO). Usually this function is hardwired in the application, but can also be controlled by a GPIO
pin of the µC. To power up with output at zero, tie the MZB
pin low. To power up with output at midscale, tie MZB high.
The MZB pin is level sensitive.
1.6 CHANGING DAC OUTPUT
There are multiple different ways to affect the DAC output.
The CONFIG register can be changed so that a write to the
PREREG is seen instantly at the output. The LDAC function
or LDACB pin updates the output instantly. Finally, the type
of write command (WRUP, WRAL, WR) can affect if the output updates instantly or not.
1.6.2 LDAC Function
The LDACB (Load DAC) pin provides a easy way to synchronize several DACs and update the output without any SPI
latency. If the LDACB is asserted low, the content of the PRE15
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DAC161S055
Clear function can also be accessed via the software instruction CLR, see Section 1.12 INSTRUCTION SET below. The
effect of hardware CLRB or software CLR is the same.
REG register is instantaneously moved into the DACREG
register. The LDACB pin is level sensitive. If the LDACB pin
is held low continuously, the DAC output will update as soon
as the CSB pin goes high.
1.9 POWER ON RESET
An on-chip power on reset circuit (POR) ensures that the DAC
always powers on in the same state. The registers will be
loaded with the defaults shown in Section 1.12 INSTRUCTION SET. The output state will be controlled by the state of
the MZB pin.
1.10 POWER DOWN
Power down is achieved by writing the PD instruction and
setting the appropriate bit to a logic '1'. In the PD command,
it is possible to specify if the output is left in a high impedance
(HIZ) state or if it is pulled to GND through a 10K resistor.
During power down, the output amplifier is disabled and the
resistor ladder is disconnected from Vref. The SPI interface
remains active. To exit power down, write the PD command
again, setting the appropriate bit to a logic '0'. Note that the
SPI interface and the registers are all active during power
down.
30128818
The DAC Configuration command LDAC (see Section 1.12
INSTRUCTION SET below) will also update the DAC output
as soon as it is received. The effect of hardware LDACB or
software LDAC is the same i.e. data is transferred from the
PREREG to DACREG and output of the DAC is updated.
1.6.3 Write Commands
There are three write commands available in the DAC command set. Issuing a WR command causes the DAC to update
either the PREREG or the DACREG depending on the setting
of the SWB bit (see Section 1.6.1 Write-Through and WriteBlock Modes). Issuing a WRUP command causes the specified channels output (for multiple channel parts) to update
immediately, regardless of the SWB bit setting. Issuing a
WRAL command causes all channels (for multiple channel
parts) to update immediately with the same data, regardless
of the SWB bit setting.
1.8 CLEAR FUNCTION
The CLRB pin provides a easy way to reset the DAC161S055
output. If the CLRB pin goes low, VOUT instantaneously
slews to the value indicated by the MZB pin, either zero or
midscale. The CLRB pin is level sensitive.
30128819
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16
MSB
LSB
Bit15–0:
MSB
LSB
Bit15–0:
MSB
Bit7–3:
Bit2:
Bit1:
Bit0:
PREREG: DAC Preload Data Register(16Bits)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PRD15
PRD14
PRD13
PRD12
PRD11
PRD10
PRD9
PRD8
R/W
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
R/w
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PRD7
PRD6
PRD5
PRD4
PRD3
PRD2
PRD1
PRD0
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
16 bit data word to be converted. Bit 15 has a weight of 1/2*Vref. Bit 0 has a weight of Vref/2^16.
DACREG: DAC Output Data Register(16Bits)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
IND15
IND14
IND13
IND12
IND11
IND10
IND9
IND8
R/W
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
R/w
R/W
R/W
R/W
R/W
R/W
R/W
R/W
IND7
IND6
IND5
IND4
IND3
IND2
IND1
IND0
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
16 bit data word to be converter. Bit 15 has a weight of 1/2*Vref. Bit 0 has a weight of Vref/2^16.
R
R
—
—
CONFIG: DAC Configuration Reporting Register (8 Bits)
R
R
R
R
R
R
—
—
—
SWB
SEL_10K
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Reserved. Read value is undefined and should be discarded.
SWB: Set Write Block bit
0: Channel is in WRITE THROUGH mode.
1: Channel is in WRITE BLOCK mode.
0: Channel is either active or SEL_HIZ is set.
1: Channel is powered down and output is terminated by a 10K resistor to GND.
0: Channel is either active or SEL_10K is set.
1: Channel is powered down and output is in high impedance state.
SEL_HIZ
Bit0
1.12 INSTRUCTION SET
The instruction set for the DAC161S055 is common to the
family of single and multi channel devices (DAC16xS055).
The DAC161S055 has only a single channel — Channel 0.
NOTE: DATA WRITING and REGISTER READING instructions encode the channel address as a binary triplet
(A2,A1,A0) as the last three LSBs of the command byte.
DAC CONFIGURATION instructions encode the channel
selection by a bit set in the data bytes. For example, when
executing the LDAC instruction a payload of {0100 0001}
in the least significant byte of the instruction indicates
channels 6 and 0 are targeted.
17
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DAC161S055
readable from the command set. Bits in the CONFIG register
are set by the commands detailed in Section 1.12 INSTRUCTION SET.
1.11 INTERNAL REGISTERS
There are 3 registers that are accessible to the user. The data
registers (PREREG and DACREG) are both readable and
writable from the command set. The CONFIG register is only
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18
0
0
0
0
CLR
LDAC
SWB
PD
0
0
WRUP
WRAL
1
1
1
1
<Reserved>
RDDO
RDCO
RDIN
Register Reading
0
WR
Data Writing
0
NOP
DAC Configuration
MNEMONIC
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
1
0
0
0
1
1
0
0
0
1
0
1
0
1
0
0
1
0
1
0
0
0
1
0
1
1
0
0
0
0
0
0
0
0
0
0
1
0
x
0
x
0
A2 A1 A0
A2 A1 A0
A2 A1 A0
x
0
A2 A1 A0
A2 A1 A0
0
0
0
0
0
Command Byte[7:0]
DACDATA[15:8]
0000 0000
DACDATA[15:8]
DACDATA[15:8]
DACDATA[15:8]
DACDATA[15:8]
CHANNEL[7:0]
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
DATA[15:8]
DACDATA[7:0]
DEFAULT
Read PREREG register.
<Reserved>
Update all channel's DACREG and PREREG
regardless of WRITE BLOCK or WRITE
THROUGH setting.
Update specified channel's DACREG and
PREREG regardless of WRITE BLOCK or WRITE
THROUGH setting.
Write to specified channel. WRITE BLOCK or
WRITE TRHOUGH setting controls destination
register (PREREG or DACREG).
Read DACREG register.
0004h
Sets SEL_10K or SEL_HIZ. Upper 8 bits PD Hi-Z; 0000h
Lower 8-bits PD 10K; if both are 1's; PD -> 10K
1: Upper 8 bits: SEL_HIZ
1: Lower 8 bits: SEL_10K
1: Both upper and lower: SEL_10K
Set WRITE BLOCK or WRITE THROUGH for the 00FFh
selected channels.
0: WRITE THROUGH
1: WRITE BLOCK
Software LOAD DAC. A '1' causes data stored in
the specified channel's PREREG to be transferred
to DACREG and the output updated.
Clear internal registers, return to Power-Up
default state
No Operation
Description
0000
Read CONFIG register.
0,swb,sel_10k,sel_hi
z
DACDATA[7:0]
DACDATA[7:0]
DACDATA[7:0]
DACDATA[7:0]
CHANNEL[7:0]
CHANNEL[7:0]
CHANNEL[7:0]
xxxx xxxx
xxxx xxxx
DATA [7:0]
DAC161S055
DAC161S055
2.0 Applications Information
2.1 SAMPLE INSTRUCTION SEQUENCE
The following table shows an example instruction sequence
to illustrate the usage of different modes of operation of the
DAC. This sequence is for a one channel DAC.
Step
Instruction
8-bit Command
16 bit Payload
Comments
1
CLR
0000 0001
0000 0000 0000 0000 Clear device - return to Power-Up Default State
2
WR
0000 1000
Write ¼ FS into channel 0. Since device by
default is in WRITE-BLOCK mode the data will
0100 0000 0000 0000
be written into PREREG, and DAC output will
not update
3
LDAC
0001 1000
xxxx xxxx 0000 0001
Issue LDAC command to channel 0. Data is
transferred from PREREG into DACREG and
DAC output updates to ¼ FS
4
SWB
0010 1000
xxxx xxxx 1111 1110
Set channels 1 to 7 to WRITE-BLOCK mode,
and channel 0 to WRITE-THROUGH mode
5
WR
0000 1000
1111 1111 1111 1111
DAC output updates immediately to FS since
the channel is set to write through mode.
6
PD
0011 0000
0000 0001 0000 0000
Power down the device, and set the channel 0
DAC output to the HIZ state
and will provide a more stable voltage source. The LM4140
has an initial accuracy of 0.1%, is capable of driving 8mA and
comes in a 4.096V version. Bypassing both the input and the
output will improve noise performance.
2.2 USING REFERENCES AS POWER SUPPLIES
Although the DAC has a separate reference and analog power pin, it is still possible to use a reference to drive both. This
arrangement will avoid a separate voltage regulator for VA
30128832
FIGURE 4. Using the LM4120 as a power supply
15mA rating. Note the largest current through the LM4050 will
occur when the DAC is shutdown. The maximum resistor value must allow the LM4050 to draw more than its minimum
current for regulation plus the maximum VREF current.
2.3 A LOW NOISE EXAMPLE
A LM4050 powered off of a battery is a good choice for very
low noise prototype circuits. The minimum value for R must
be chosen so that the LM4050 does not draw more than its
19
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DAC161S055
30128833
FIGURE 5. Using the LM4050 in a low noise circuit
to the device with the 0.1µF closest to the supply pin. The
10µF capacitor should be a tantalum type and the 0.1µF capacitor should be a low ESL, low ESR type. Sometime, the
loading requirements of the regulator driving the DAC do not
allow such capacitance to be placed on the regulator output.
In those cases, bypass should be as large as allowed by the
regulator using a low ESL, low ESR capacitance. In the
LM4120 example above, the supply is bypassed with 0.022µF
ceramic capacitors. The DAC should be fed with power that
is only used for analog circuits.
Avoid crossing analog and digital signals and keep the clock
and data lines on the component side of the board. The clock
and data lines should have controlled impedances.
2.4 LAYOUT, GROUNDING AND BYPASSING
For best accuracy and minimum noise, the printed circuit
board containing the DAC should have separate analog and
digital areas. These areas are defined by the locations of the
analog and digital power planes. Both power planes should
be in the same board layer. There should be a single ground
plane. Frequently a single ground plane design will utilize a
fencing technique to prevent the mixing of analog and digital
ground currents. Separate ground planes should only be used
if the fencing technique proves inadequate. The separate
ground planes must be connected in a single place, preferably
near the DAC. Special care is required to guarantee that digital signals with fast edge rates do not pass over split ground
planes. The fast digital signals must always have a continuous return path below their traces.
When possible, the DAC power supply should be bypassed
with a 10µF and a 0.1µF capacitor placed as close as possible
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20
DAC161S055
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead LLP
NS Package Number SQA16A
21
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DAC161S055 Precision 16-Bit, Buffered Voltage-Output DAC
Notes
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