NSC ADC0816CCJ 8-bit î¼p compatible a/d converters with 16-channel multiplexer Datasheet

ADC0816/ADC0817
8-Bit μP Compatible A/D Converters
with 16-Channel Multiplexer
General Description
Features
The ADC0816, ADC0817 data acquisition component is a
monolithic CMOS device with an 8-bit analog-to-digital converter, 16-channel multiplexer and microprocessor compatible control logic. The 8-bit A/D converter uses successive
approximation as the conversion technique. The converter
features a high impedance chopper stabilized comparator, a
256R voltage divider with analog switch tree and a successive
approximation register. The 16-channel multiplexer can directly access any one of 16-single-ended analog signals, and
provides the logic for additional channel expansion. Signal
conditioning of any analog input signal is eased by direct access to the multiplexer output, and to the input of the 8-bit A/
D converter.
The device eliminates the need for external zero and full-scale
adjustments. Easy interfacing to microprocessors is provided
by the latched and decoded multiplexer address inputs and
latched TTL TRI-STATE® outputs.
The design of the ADC0816, ADC0817 has been optimized
by incorporating the most desirable aspects of several A/D
conversion techniques. The ADC0816, ADC0817 offers high
speed, high accuracy, minimal temperature dependence, excellent long-term accuracy and repeatability, and consumes
minimal power. These features make this device ideally suited to applications from process and machine control to consumer and automotive applications. For similar performance
in an 8-channel, 28-pin, 8-bit A/D converter, see the
ADC0808, ADC0809 data sheet. (See AN-258 for more information.)
■ Easy interface to all microprocessors
■ Operates ratiometrically or with 5 VDC or analog span
adjusted voltage reference
16-channel multiplexer with latched control logic
Outputs meet TTL voltage level specifications
0V to 5V analog input voltage range with single 5V supply
No zero or full-scale adjust required
Standard hermetic or molded 40-pin DIP package
Temperature range −40°C to +85°C or −55°C to +125°C
Latched TRI-STATE output
Direct access to “comparator in” and “multiplexer out” for
signal conditioning
■ ADC0816 equivalent to MM74C948
■ ADC0817 equivalent to MM74C948-1
■
■
■
■
■
■
■
■
Key Specifications
■
■
■
■
■
Resolution
Total Unadjusted Error
Single Supply
Low Power
Conversion Time
8 Bits
±½ LSB and ±1 LSB
5 VDC
15 mW
100 μs
Block Diagram
527701
TRI-STATE® is a trademark of National Semiconductor Corporation.
© 2007 National Semiconductor Corporation
5277
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ADC0816/ADC0817 8-Bit μP Compatible A/D Converters with 16-Channel Multiplexer
March 2007
ADC0816/ADC0817
Connection Diagram
Dual-In-Line Package
527706
Order Number ADC0816CCN or ADC0817CCN
See NS Package Number N40A
Ordering Information
TEMPERATURE RANGE
Error
−40°C to +85°C
±½ Bit Unadjusted
ADC0816CCN
±1 Bit Unadjusted
ADC0817CCN
Package Outline
N40A Molded DIP
* This product is obsolete in the Hermetic DIP.
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2
ADC0816CCJ *
J40A Hermetic DIP
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (VCC) (Note 3)
Voltage at Any Pin
6.5V
−0.3V to (VCC
+0.3V)
215°C
220°C
400V
Operating Conditions
Except Control Inputs
Voltage at Control Inputs
−0.3V to 15V
(START, OE, CLOCK, ALE, EXPANSION CONTROL,
ADD A, ADD B, ADD C, ADD D)
Storage Temperature Range
−65°C to + 150°C
Package Dissipation at TA = 25°C
875 mW
Lead Temp. (Soldering, 10 seconds)
Dual-In-Line Package (Plastic)
260°C
(Notes 1, 2)
TMIN≤TA≤TMAX
Temperature Range (Note 1)
ADC0816CCN, ADC0817CCN
−40°C≤TA≤+85°C
4.5 VDC to 6.0 VDC
0V to VCC
Range of VCC (Note 1)
Voltage at Any Pin
Except Control Inputs
Voltage at Control Inputs
0V to 15V
(START, OE, CLOCK, ALE, EXPANSION CONTROL,
ADD A, ADD B, ADD C, ADD D)
Electrical Characteristics
Converter Specifications: VCC=5 VDC= VREF(+), VREF(−)=GND, VIN=VCOMPARATOR IN,TMIN≤TMAX and fCLK = 640 kHz unless otherwise stated.
Symbol
Parameter
Conditions
ADC0816
Total Unadjusted Error
(Note 5)
ADC0817
Total Unadjusted Error
(Note 5)
VREF(+)
Max
Units
25°C
±½
LSB
TMIN to TMAX
±¾
LSB
0°C to 70°C
TMIN to TMAX
±1
±1¼
LSB
LSB
VCC + 0.1
VDC
VCC
VCC+0.1
V
VCC/2
VCC/2 + 0.1
Input Resistance
From Ref(+) to Ref(−)
1.0
Analog Input Voltage Range
(Note 4) V(+) or V(−)
GND − 0.1
Voltage, Top of Ladder
Measured at Ref(+)
VCC/2 − 0.1
Voltage, Center of Ladder
VREF(−)
Min
Typ
4.5
Voltage, Bottom of Ladder
Measured at Ref(−)
−0.1
0
Comparator Input Current
fc=640 kHz, (Note 6)
−2
±0.5
kΩ
V
V
2
μA
Electrical Characteristics
Digital Levels and DC Specifications: ADC0816CCN, ADC0817CCN—4.75V≤VCC≤5.25V, −40°C≤TA≤+85°C unless otherwise
noted.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
1.5
ANALOG MULTIPLEXER
RON
ΔRON
Analog Multiplexer ON Resistance
ΔON Resistance Between Any 2
Channels
(Any Selected Channel)
TA=25°C, RL=10k
3
kΩ
TA=85°C
6
kΩ
TA=125°C
9
kΩ
Ω
75
(Any Selected Channel)
RL=10k
VCC=5V, VIN=5V,
IOFF+
OFF Channel Leakage Current
TA=25°C
10
TMIN to TMAX
200
nA
1.0
μA
VCC=5V, VIN=0,
IOFF(−)
OFF Channel Leakage Current
TA=25°C
−200
nA
TMIN to TMax
−1.0
μA
3
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ADC0816/ADC0817
Molded Chip Carrier Package
Vapor Phase (60 seconds)
Infrared (15 seconds)
ESD Susceptibility (Note 9)
Absolute Maximum Ratings (Notes 1, 2)
ADC0816/ADC0817
Symbol
Parameter
Conditions
Min
Typ
Max
Units
CONTROL INPUTS
VIN(1)
VCC − 1.5
Logical “1” Input Voltage
VIN(0)
Logical “0” Input Voltage
IIN(1)
Logical “1” Input Current
(The Control Inputs)
V
VIN=15V
IIN(0)
Logical “0” Input Current
(The Control Inputs)
VIN=0
ICC
Supply Current
fCLK=640 kHz
1.5
V
1.0
μA
μA
−1.0
0.3
3.0
mA
DATA OUTPUTS AND EOC (INTERRUPT)
IO=−360 μA, TA=85°C
VOUT(1)
Logical “1” Output Voltage
VOUT(0)
Logical “0” Output Voltage
IO=1.6 mA
0.45
V
VOUT(0)
Logical “0” Output Voltage EOC
IO=1.2 mA
0.45
V
IOUT
TRI-STATE Output Current
3.0
μA
IO=−300 μA, TA=125°C
VCC − 0.4
V
VO=VCC
VO=0
μA
−3.0
Electrical Characteristics
Timing Specifications: VCC=VREF(+)=5V, VREF(−)=GND, tr=tf=20 ns and TA=25°C unless otherwise noted.
Typ
Max
Units
tWS
Symbol
Minimum Start Pulse Width
Parameter
(Figure 5) (Note 7)
Conditions
Min
100
200
ns
tWALE
Minimum ALE Pulse Width
(Figure 5)
100
200
ns
ts
Minimum Address Set-Up Time
(Figure 5)
25
50
ns
TH
Minimum Address Hold Time
(Figure 5)
25
50
ns
tD
Analog MUX Delay Time
from ALE
RS=OΩ (Figure 5)
1
2.5
μs
tH1, tH0
OE Control to Q Logic State
CL=50 pF, RL=10k (Figure 8)
125
250
ns
t1H, t0H
OE Control to Hi-Z
CL=10 pF, RL=10k (Figure 8)
tC
Conversion Time
fc=640 kHz, (Figure 5) (Note 8)
fc
Clock Frequency
125
250
ns
90
100
116
μs
10
640
1280
kHz
8 + 2μs
Clock
Periods
tEOC
EOC Delay Time
(Figure 5)
CIN
Input Capacitance
At Control Inputs
10
15
pF
COUT
TRI-STATE Output
Capacitance
At TRI-STATE Outputs (Note 8)
10
15
pF
0
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its specified operating conditions.
Note 2: All voltages are measured with respect to GND, unless otherwise specified.
Note 3: A Zener diode exists, internally, from VCC to GND and has a typical breakdown voltage of 7 VDC.
Note 4: Two on-chip diodes are tied to each analog input which will forward conduct for analog input voltages one diode drop below ground or one diode drop
greater than the VCC supply. The spec allows 100 mV forward bias of either diode. This means that as long as the analog VIN does not exceed the supply voltage
by more than 100 mV, the output code will be correct. To achieve an absolute 0 VDC to 5 VDC input voltage range will therefore require a minimum supply voltage
of 4.900 VDC over temperature variations, initial tolerance and loading.
Note 5: Total unadjusted error includes offset, full-scale, and linearity errors. See Figure 3. None of these A/Ds requires a zero or full-scale adjust. However, if
an all zero code is desired for an analog input other than 0.0V, or if a narrow full-scale span exists (for example: 0.5V to 4.5V full-scale) the reference voltages
can be adjusted to achieve this. See Figure 13.
Note 6: Comparator input current is a bias current into or out of the chopper stabilized comparator. The bias current varies directly with clock frequency and has
little temperature dependence (Figure 6). See paragraph 4.0.
Note 7: If start pulse is asynchronous with converter clock or if fc > 640 kHz, the minimum start pulse width is 8 clock periods plus 2 μs. For synchronous operation
at fc ≤ 640 kHz take start high within 100 ns of clock going low.
Note 8: The outputs of the data register are updated one clock cycle before the rising edge of EOC.
Note 9: Human body model, 100 pF discharged through a 1.5 kΩ resistor.
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4
Additional single-ended analog signals can be multiplexed to
the A/D converter by disabling all the multiplexer inputs using
the expansion control. The additional external signals are
connected to the comparator input and the device ground.
Additional signal conditioning (i.e., prescaling, sample and
hold, instrumentation amplification, etc.) may also be added
between the analog input signal and the comparator input.
Multiplexer: The device contains a 16-channel single-ended
analog signal multiplexer. A particular input channel is selected by using the address decoder. Table 1 shows the input
states for the address line and the expansion control line to
select any channel. The address is latched into the decoder
on the low-to-high transition of the address latch enable signal.
CONVERTER CHARACTERISTICS
TABLE 1.
Selected
Analog Channel
IN0
IN1
IN2
IN3
IN4
IN5
IN6
IN7
IN8
IN9
IN10
IN11
IN12
IN13
IN14
IN15
All Channels OFF
Address Line
The Converter
The heart of this single chip data acquisition system is its 8bit analog-to-digital converter. The converter is designed to
give fast, accurate, and repeatable conversions over a wide
range of temperatures. The converter is partitioned into 3 major sections: the 256R ladder network, the successive approximation register, and the comparator. The converter's
digital outputs are positive true.
The 256R ladder network approach Figure 1 was chosen over
the conventional R/2R ladder because of its inherent monotonicity, which guarantees no missing digital codes. Monotonicity is particularly important in closed loop feedback
control systems. A non-monotonic relationship can cause oscillations that will be catastrophic for the system. Additionally,
the 256R network does not cause load variations on the reference voltage.
The bottom resistor and the top resistor of the ladder network
in Figure 1 are not the same value as the remainder of the
network. The difference in these resistors causes the output
characteristic to be symmetrical with the zero and full-scale
points of the transfer curve. The first output transition occurs
when the analog signal has reached + ½ LSB and succeeding
output transitions occur every 1 LSB later up to full-scale.
Expansion
D
C
B
A
Control
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
X
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
X
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
X
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
X
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
527702
FIGURE 1. Resistor Ladder and Switch Tree
5
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ADC0816/ADC0817
X=don't care
Functional Description
ADC0816/ADC0817
527703
527704
FIGURE 2. 3-Bit A/D Transfer Curve
FIGURE 3. 3-Bit A/D Absolute Accuracy Curve
527705
FIGURE 4. Typical Error Curve
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ADC0816/ADC0817
Timing Diagram
527707
FIGURE 5.
The successive approximation register (SAR) performs 8 iterations to approximate the input voltage. For any SAR type
converter, n-iterations are required for an n-bit converter. Figure 2 shows a typical example of a 3-bit converter. In the
ADC0816, ADC0817, the approximation technique is extended to 8 bits using the 256R network.
The A/D converter's successive approximation register (SAR)
is reset on the positive edge of the start conversion (SC)
pulse. The conversion is begun on the falling edge of the start
conversion pulse. A conversion in process will be interrupted
by receipt of a new start conversion pulse. Continuous conversion may be accomplished by tying the end-of-conversion
(EOC) output to the SC input. If used in this mode, an external
start conversion pulse should be applied after power up. Endof-conversion will go low between 0 and 8 clock pulses after
the rising edge of start conversion.
The most important section of the A/D converter is the comparator. It is this section which is responsible for the ultimate
accuracy of the entire converter. It is also the comparator drift
which has the greatest influence on the repeatability of the
device. A chopper-stabilized comparator provides the most
effective method of satisfying all the converter requirements.
The chopper-stabilized comparator converts the DC input signal into an AC signal. This signal is then fed through a high
gain AC amplifier and has the DC level restored. This technique limits the drift component of the amplifier since the drift
is a DC component which is not passed by the AC amplifier.
This makes the entire A/D converter extremely insensitive to
temperature, long term drift and input offset errors.
Figure 4 shows a typical error curve for the ADC0816 as
measured using the procedures outlined in AN-179.
7
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ADC0816/ADC0817
Typical Performance Characteristics
527718
527719
FIGURE 6. Comparator IIN vs. VIN
(VCC=VREF=5V)
FIGURE 7. Multiplexer RON vs. VIN
(VCC=VREF=5V)
TRI-STATE Test Circuits and Timing Diagrams
527709
527710
FIGURE 8.
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OPERATION
1.0 Ratiometric Conversion
The ADC0816, ADC0817 is designed as a complete Data
Acquisition System (DAS) for ratiometric conversion systems.
In ratiometric systems, the physical variable being measured
is expressed as a percentage of full-scale which is not necessarily related to an absolute standard. The voltage input to
the ADC0816 is expressed by the equation
2.0 Resistor Ladder Limitations
The voltages from the resistor ladder are compared to the
selected input 8 times in a conversion. These voltages are
coupled to the comparator via an analog switch tree which is
referenced to the supply. The voltages at the top, center and
bottom of the ladder must be controlled to maintain proper
operation.
The top of the ladder, Ref(+), should not be more positive than
the supply, and the bottom of the ladder, Ref(−), should not
be more negative than ground. The center of the ladder voltage must also be near the center of the supply because the
analog switch tree changes from N-channel switches to Pchannel switches. These limitations are automatically satisfied in ratiometric systems and can be easily met in ground
referenced systems.
Figure 10 shows a ground referenced system with a separate
supply and reference. In this system, the supply must be
trimmed to match the reference voltage. For instance, if a
5.12V reference is used, the supply should be adjusted to the
same voltage within 0.1V.
(1)
VIN = Input voltage into the ADC0816
Vfs = Full-scale voltage
VZ = Zero voltage
DX = Data point being measured
DMAX = Maximum data limit
DMIN = Minimum data limit
A good example of a ratiometric transducer is a potentiometer
used as a position sensor. The position of the wiper is directly
proportional to the output voltage which is a ratio of the fullscale voltage across it. Since the data is represented as a
proportion of full-scale, reference requirements are greatly
reduced, eliminating a large source of error and cost for many
applications. A major advantage of the ADC0816, ADC0817
is that the input voltage range is equal to the supply range so
the transducers can be connected directly across the supply
527711
FIGURE 9. Ratiometric Conversion System
The ADC0816 needs less than a milliamp of supply current
so developing the supply from the reference is readily accomplished. In Figure 11 a ground references system is
shown which generates the supply from the reference. The
buffer shown can be an op amp of sufficient drive to supply
the milliamp of supply current and the desired bus drive, or if
a capacitive bus is driven by the outputs a large capacitor will
supply the transient supply current as seen in Figure 12. The
LM301 is overcompensated to insure stability when loaded by
the 10 μF output capacitor.
The top and bottom ladder voltages cannot exceed VCC and
ground, respectively, but they can be symmetrically less than
VCC and greater than ground. The center of the ladder voltage
should always be near the center of the supply. The sensitivity
of the converter can be increased, (i.e., size of the LSB steps
decreased) by using a symmetrical reference system. In Figure 13, a 2.5V reference is symmetrically centered about
VCC/2 since the same current flows in identical resistors. This
system with a 2.5V reference allows the LSB to be half the
size of the LSB in a 5V reference system.
9
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ADC0816/ADC0817
and their outputs connected directly into the multiplexer inputs, (Figure 9).
Ratiometric transducers such as potentiometers, strain
gauges, thermistor bridges, pressure transducers, etc., are
suitable for measuring proportional relationships; however,
many types of measurements must be referred to an absolute
standard such as voltage or current. This means a system
reference must be used which relates the full-scale voltage to
the standard volt. For example, if VCC = VREF = 5.12V, then
the full-scale range is divided into 256 standard steps. The
smallest standard step is 1 LSB which is then 20 mV.
Applications Information
ADC0816/ADC0817
527712
FIGURE 10. Ground Referenced
Conversion System Using Trimmed Supply
527713
FIGURE 11. Ground Referenced Conversion System with
Reference Generating VCC Supply
527714
FIGURE 12. Typical Reference and Supply Circuit
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10
ADC0816/ADC0817
527715
FIGURE 13. Symmetrically Centered Reference
VREF = Voltage at Ref(+)
VREF = Voltage at Ref(−)
VTUE = Total unadjusted error voltage (typically
VREF(+) ÷512)
3.0 Converter Equations
The transition between adjacent codes N and N + 1 is given
by:
4.0 Analog Comparator Inputs
The dynamic comparator input current is caused by the periodic switching of on-chip stray capacitances These are connected alternately to the output of the resistor ladder/switch
tree network and to the comparator input as part of the operation of the chopper stabilized comparator.
The average value of the comparator input current varies directly with clock frequency and with VIN as shown in Figure
6.
If no filter capacitors are used at the analog or comparator
inputs and the signal source impedances are low, the comparator input current should not introduce converter errors, as
the transient created by the capacitance discharge will die out
before the comparator output is strobed.
If input filter capacitors are desired for noise reduction and
signal conditioning they will tend to average out the dynamic
comparator input current. It will then take on the characteristics of a DC bias current whose effect can be predicted
conventionally. See AN-258 for further discussion.
(2)
The center of an output code N is given by:
(3)
The output code N for an arbitrary input are the integers within
the range:
(4)
where: VIN = Voltage at comparator input
11
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ADC0816/ADC0817
Typical Application
527716
*Address latches needed for 8085 and SC/MP interfacing the ADC0816, 17 to a microprocessor
Microprocessor Interface Table
PROCESSOR
8080
8085
Z-80
SC/MP
6800
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READ
MEMR
RD
RD
NRDS
VMA•φ 2•R/W
WRITE
MEMW
WR
WR
NWDS
VMA•Q2•R/W
12
INTERRUPT (COMMENT)
INTR (Thru RST Circuit)
INTR (Thru RST Circuit)
INT (Thru RST Circuit, Mode 0)
SA (Thru Sense A)
IRQA or IRQB (Thru PIA)
ADC0816/ADC0817
Physical Dimensions inches (millimeters) unless otherwise noted
Molded Dual-In-Line Package (N)
NS Package Number N40A
13
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ADC0816/ADC0817 8-Bit μP Compatible A/D Converters with 16-Channel Multiplexer
Notes
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