FEATURES FUNCTIONAL BLOCK DIAGRAM High accuracy over line and load: ±0.9% at 25°C, ±1.8% over temperature Ultralow dropout voltage: 200 mV (typical) at 500 mA Requires only CO = 1.0 µF for stability anyCAP® = stable with any type of capacitor (including MLCC) Current and thermal limiting Low noise Low shutdown current: < 10 nA (typical) 2.6 V to 12 V supply range –40°C to +85°C ambient temperature range Q1 IN OUT ADP3335 THERMAL PROTECTION R1 CC NR DRIVER gm R2 SD BANDGAP + REF – 00147-0-001 Data Sheet High Accuracy, Ultralow IQ, 500 mA, anyCAP Low Dropout Regulator ADP3335 GND Figure 1. APPLICATIONS PCMCIA cards Cellular phones Camcorders, cameras Networking systems, DSL/cable modems Cable set-top box MP3/CD players DSP supplies 5 NR ADP3335 OUT 3 CIN 1µF + IN 8 IN OUT 2 OUT 1 SD GND 6 4 + COUT 1µF ON OFF VOUT 00147-0-002 VIN 7 Figure 2. Typical Application Circuit GENERAL DESCRIPTION The ADP3335 is a member of the ADP333x family of precision, low dropout, anyCAP voltage regulators. It operates with an input voltage range of 2.6 V to 12 V, and delivers a continuous load current up to 500 mA. The ADP3335 stands out from conventional low dropout regulators (LDOs) by using an enhanced process enabling it to offer performance advantages beyond its competition. Its patented design requires only a 1.0 µF output capacitor for stability. This device is insensitive to output capacitor equivalent series resistance (ESR), and is stable with any good quality capacitor—including ceramic (MLCC) types for space-restricted applications. The ADP3335 achieves exceptional accuracy of ±0.9% at room temperature and ±1.8% over temperature, line, and load. Rev. D The dropout voltage of the ADP3335 is only 200 mV (typical) at 500 mA. This device also includes a safety current limit, thermal overload protection, and a shutdown feature. In shutdown mode, the ground current is reduced to less than 1 µA. The ADP3335 has a low quiescent current of 80 µA (typical) in light load situations. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2000–2013 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADP3335 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Applications Information .............................................................. 10 Applications ....................................................................................... 1 Output Capacitor Selection....................................................... 10 Functional Block Diagram .............................................................. 1 Input Bypass Capacitor .............................................................. 10 General Description ......................................................................... 1 Noise Reduction ......................................................................... 10 Revision History ............................................................................... 2 Thermal Overload Protection .................................................. 10 Specifications..................................................................................... 3 Calculating Junction Temperature ........................................... 10 Absolute Maximum Ratings............................................................ 4 Printed Circuit Board Layout Considerations ....................... 11 ESD Caution .................................................................................. 4 LFCSP Layout Considerations .................................................. 11 Pin Configuration and Function Descriptions ............................. 5 Shutdown Mode ......................................................................... 11 Typical Performance Characteristics ............................................. 6 Outline Dimensions ....................................................................... 12 Theory of Operation ........................................................................ 9 Ordering Guide .......................................................................... 13 REVISION HISTORY 10/13—Rev. C to Rev. D Updated Outline Dimensions ....................................................... 12 Changes to Ordering Guide .......................................................... 13 12/12—Rev. B to Rev. C Changes to Figure 14 and Figure 16 ............................................... 7 Updated Outline Dimensions ....................................................... 12 Changes to Ordering Guide .......................................................... 13 1/04—Rev. 0 to Rev. A Format Updated .................................................................. Universal Renumbered Figures .......................................................... Universal Removed Figure 22............................................................................6 Change to Printed Circuit Board Layout Considerations Section.............................................................................................. 11 Added LFCSP Layout Considerations Section ........................... 11 Added Package Drawing ................................................... Universal Changes to Ordering Guide .......................................................... 16 6/10—Rev. A to Rev. B Added Exposed Pad Notation to Figure 4 and Table 3 ................ 5 Added Exposed Pad Notation to Outline Dimensions ............. 12 Changes to Ordering Guide .......................................................... 13 Rev. D | Page 2 of 16 Data Sheet ADP3335 SPECIFICATIONS All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC) methods. Ambient temperature of 85°C corresponds to a junction temperature of 125°C under pulsed full-load test conditions. Application stable with no load. VIN = 6.0 V, CIN = COUT = 1.0 µF, TA = –40°C to +85°C, unless otherwise noted. Table 1. Parameter OUTPUT Voltage Accuracy 1 Symbol Conditions Min VOUT VIN = VOUT(NOM) + 0.4 V to 12 V IL = 0.1 mA to 500 mA TA = 25°C VIN = VOUT(NOM) + 0.4 V to 12 V IL = 0.1 mA to 500 mA TA = 85°C VIN = VOUT(NOM) + 0.4 V to 12 V IL = 0.1 mA to 500 mA TJ = 150°C VIN = VOUT(NOM) + 0.4 V to 12 V IL = 0.1 mA TA = 25°C IL = 0.1 mA to 500 mA TA = 25°C VOUT = 98% of VOUT(NOM) IL = 500 mA IL = 300 mA IL = 50 mA IL = 0.1 mA VIN = VOUT(NOM) + 1 V f = 10 Hz to 100 kHz, CL = 10 µF IL = 500 mA, CNR = 10 nF f = 10 Hz to 100 kHz, CL = 10 µF IL = 500 mA, CNR = 0 nF Line Regulation1 Load Regulation Dropout Voltage Peak Load Current Output Noise GROUND CURRENT In Regulation In Dropout In Shutdown SHUTDOWN Threshold Voltage 1 VDROP ILDPK VNOISE IGND IGND IGNDSD VTHSD Max Unit –0.9 +0.9 % –1.8 +1.8 % –2.3 +2.3 % SD Input Current ISD Output Current in Shutdown IOSD VIN = 12 V, VOUT = 0 V VIN = 2.6 V to 12 V for models with VOUT(NOM) ≤ 2.2 V. Rev. D | Page 3 of 16 0.04 mV/V 0.04 mV/mA 200 140 30 10 800 47 370 230 110 40 95 IL = 500 mA IL = 300 mA IL = 50 mA IL = 0.1 mA VIN = VOUT(NOM) – 100 mV IL = 0.1 mA SD = 0 V, VIN = 12 V ON OFF 0 ≤ SD ≤ 5 V Typ mV mV mV mV mA µV rms µV rms 4.5 2.6 0.5 80 120 10 6 2.5 110 400 mA mA mA µA µA 0.01 1 µA 1.2 0.4 3 V V µA 0.01 5 µA 2.0 ADP3335 Data Sheet ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Input Supply Voltage Shutdown Input Voltage Power Dissipation Operating Ambient Temperature Range Operating Junction Temperature Range θJA, 2-layer MSOP-8 θJA, 4-layer MSOP-8 θJA, 2-layer LFCSP-8 θJA, 4-layer LFCSP-8 Storage Temperature Range Lead Temperature Range (Soldering 10 sec) Vapor Phase (60 sec) Infrared (15 sec) Rating –0.3 V to +16 V –0.3 V to +16 V Internally Limited –40°C to +85°C –40°C to +150°C 220°C/W 158°C/W 62°C/W 48°C/W –65°C to +150°C 300°C 215°C 220°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION Rev. D | Page 4 of 16 Data Sheet ADP3335 8 IN OUT 2 ADP3335 7 IN OUT 3 TOP VIEW (Not to Scale) 6 SD 5 NR OUT 1 GND 4 00147-0-022 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 3. 8-Lead MSOP OUT 1 OUT 3 GND 4 8 IN ADP3335 7 IN TOP VIEW (Not to Scale) 6 SD 5 NR 00147-0-025 OUT 2 NOTES 1. THE EXPOSED PAD ON THE BOTTOM OF THE PACKAGE ENHANCES THE THERMAL PERFORMANCE AND IS ELECTRICALLY CONNECTED TO DIE SUBSTRATE. THERMAL VIAS MUST BE ISOLATED OR CONNECTED TO IN. DO NOT CONNECT THE THERMAL PAD TO GROUND. Figure 4. 8-Lead LFCSP Table 3. Pin Function Descriptions Pin No. 1, 2, 3 Mnemonic OUT 4 5 GND NR 6 SD 7, 8 EP IN Exposed Pad Function Output of the Regulator. Bypass to ground with a 1.0 µF or larger capacitor. All pins must be connected together for proper operation. Ground Pin. Noise Reduction Pin. Used for further reduction of output noise (see the Noise Reduction section for further details). Active Low Shutdown Pin. Connect to ground to disable the regulator output. When shutdown is not used, this pin should be connected to the input pin. Regulator Input. All pins must be connected together for proper operation. The exposed pad on the bottom of the LFCSP package enhances thermal performance and is electrically connected to the die substrate, which is electrically common with the input pins, IN (Pin 7 and Pin 8), inside the package. Rev. D | Page 5 of 16 ADP3335 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted. 2.202 5.0 VOUT = 2.2V 2.201 GROUND CURRENT (µA) IL = 0 OUTPUT VOLTAGE (V) 2.200 2.199 150mA 2.198 2.197 4.0 3.0 2.0 2.196 300mA 500mA 2.194 2 4 6 8 INPUT VOLTAGE (V) 10 0 12 00147-0-006 00147-0-003 1.0 2.195 0 100 Figure 5. Line Regulation Output Voltage vs. Supply Voltage 2.201 400 500 Figure 8. Ground Current vs. Load Current 1.0 VOUT = 2.2V VIN = 6V 0.9 2.200 0 0.8 0.7 2.199 2.198 2.197 2.196 2.195 300mA 0.6 OUTPUT CHANGE (%) OUTPUT VOLTAGE (V) 200 300 LOAD CURRENT (mA) 0.5 0.4 0.3 0.2 0.1 500mA 0 2.193 0 100 200 300 LOAD CURRENT (mA) 400 –0.3 –0.4 –40 500 Figure 6. Output Voltage vs. Load Current 140 IL = 100µA –15 5 25 45 65 85 JUNCTION TEMPERATURE (°C) 105 125 Figure 9. Output Voltage Variation vs. Junction Temperature 8 VOUT = 2.2V IL = 500mA 7 GROUND CURRENT (mA) 120 100 80 IL = 0 60 6 5 300mA 4 3 20 0 0 2 4 6 8 INPUT VOLTAGE (V) 10 2 100mA 1 50mA 0 0 –40 12 Figure 7. Ground Current vs. Supply Voltage –15 00147-0-008 40 00147-0-005 GROUND CURRENT (µA) 500mA –0.2 00147-0-007 00147-0-004 –0.1 2.194 45 65 85 5 25 JUNCTION TEMPERATURE (°C) 105 Figure 10. Ground Current vs. Junction Temperature Rev. D | Page 6 of 16 125 Data Sheet ADP3335 250 2.210 VOUT (V) DROPOUT VOLTAGE (mV) 200 150 2.200 2.190 100 0 100 200 300 OUTPUT (mA) 400 3.500 3.000 500 40 Figure 11. Dropout Voltage vs. Output Current 80 140 TIME (µs) 180 Figure 14. Line Transient Response VOUT = 2.2V SD = VIN RL = 4.4Ω 3.0 00147-0-012 00147-0-009 0 VIN (V) 2.170 50 2.210 VOUT (V) 2.5 2.0 2.200 2.190 VOUT = 2.2V 1.5 2.189 1.0 2.179 0.5 3.500 RL = 4.4Ω 00147-0-010 0 1 2 3 00147-0-013 CL = 10µF VIN (V) INPUT/OUTPUT VOLTAGE (V) VOUT = 2.2V RL = 4.4Ω CL = 1µF 2.180 3.000 40 4 80 TIME (sec) Figure 12. Power-Up/Power-Down 2.3 VOUT (V) COUT = 1µF 2 1 2.2 2.1 COUT = 10µF VIN = 4V RL = 2.2Ω CL = 1µF 0 VOUT = 2.2V SD = VIN RL = 4.4Ω 0 200 400 600 TIME (µs) 00147-0-011 2 400 200 00147-0-014 ILOAD (mA) 4 VIN (V) 180 Figure 15. Line Transient Response 3 VOUT (V) 140 TIME (µs) 0 200 800 Figure 13. Power-Up Response 400 600 TIME (µs) Figure 16. Load Transient Response Rev. D | Page 7 of 16 800 ADP3335 Data Sheet –20 VOUT = 2.2V VIN = 4V RL = 4.4Ω CL = 10µF 400 00147-0-015 200 0 –40 400 600 TIME (µs) CL = 1µF IL = 50µA –50 –60 –70 CL = 10µF IL = 50µA –80 –90 200 CL = 1µF IL = 500mA 800 10 1k 100 2.2 140 0 120 FULL SHORT 2 400 600 TIME (µs) IL = 500mA WITHOUT NOISE REDUCTION IL = 500mA WITH NOISE REDUCTION 80 60 IL = 0mA WITHOUT NOISE REDUCTION 20 IL = 0mA WITH NOISE REDUCTION 0 800 0 10µF 1µF 2 00147-0-017 VSD (V) 0 1 200 400 600 TIME (µs) 40 50 VOUT = 2.2V IL = 1mA VOLTAGE NOISE SPECTRAL DENSITY (µV/ Hz) VOUT (V) 10µF 30 100 2 1 20 Figure 21. RMS Noise versus CL (10 Hz to 100 kHz) VIN = 4V VOUT = 2.2V RL = 4.4Ω 1µF 10 CL (µF) Figure 18. Short-Circuit Current 3 00147-0-019 40 00147-0-016 0 CNR = 10nF 100 VIN = 4V 1 200 10M 10 Figure 19. Turn On/Turn Off Response CL = 10µF CNR = 0nF CL = 1µF CNR = 0nF 1 0.1 CL = 1µF CNR = 10nF 0.01 0.001 800 CL = 10µF CNR = 10nF 00147-0-020 ILOAD (A) RMS NOISE (µV) VOUT (V) 160 3 1M 10k 100k FREQUENCY (Hz) Figure 20. Power Supply Ripple Rejection Figure 17. Load Transient Response 800mΩ SHORT 00147-0-018 2.2 2.1 ILOAD (mA) CL = 10µF IL = 500mA –30 RIPPLE REJECTION (dB) VOUT (V) 2.3 10 100 1k 10k FREQUENCY (Hz) Figure 22. Output Noise Density Rev. D | Page 8 of 16 100k 1M Data Sheet ADP3335 THEORY OF OPERATION The ADP3335 uses a single control loop for regulation and reference functions. The output voltage is sensed by a resistive voltage divider, R1 and R2, which is varied to provide the available output voltage option. Feedback is taken from this network by way of a series diode, D1, and a second resistor divider, R3 and R4, to the input of an amplifier. OUTPUT Q1 NONINVERTING WIDEBAND DRIVER COMPENSATION ATTENUATION R1 CAPACITOR (VBANDGAP/VOUT) D1 R3 PTAT (a) gm VOS PTAT R4 CURRENT R2 ADP3335 GND CLOAD RLOAD 00147-0-023 INPUT Figure 23. Functional Block Diagram A very high gain error amplifier is used to control this loop. The amplifier is constructed in such a way that equilibrium produces a large, temperature proportional input offset voltage that is repeatable and very well controlled. The temperature proportional offset voltage combines with the complementary diode voltage to form a virtual band gap voltage implicit in the network, although it never appears explicitly in the circuit. This patented design makes it possible to control the loop with only one amplifier. This technique also improves the noise characteristics of the amplifier by providing more flexibility in the trade-off of noise sources that leads to a low noise design. The R1 and R2 divider is chosen in the same ratio as the band gap voltage to the output voltage. Although the R1 and R2 resistor divider is loaded by the D1 diode and a second divider—R3 and R4, the values can be chosen to produce a temperature stable output. This unique arrangement specifically corrects for the loading of the divider, thus avoiding the error resulting from base current loading in conventional circuits. The patented amplifier controls a new and unique noninverting driver that drives the pass transistor, Q1. This special noninverting driver enables the frequency compensation to include the load capacitor in a pole-splitting arrangement to achieve reduced sensitivity to the value, type, and ESR of the load capacitance. Most LDOs place very strict requirements on the range of ESR values for the output capacitor, because they are difficult to stabilize due to the uncertainty of load capacitance and resistance. The ESR value required to keep conventional LDOs stable, moreover, changes depending on load and temperature. These ESR limitations make designing with LDOs more difficult because of their unclear specifications and extreme variations over temperature. With the ADP3335, ESR limitations are no longer a source of design constraints. The ADP3335 can be used with virtually any good quality capacitor and with no constraint on the minimum ESR. This innovative design allows the circuit to be stable with just a small 1 µF capacitor on the output. Additional advantages of the pole-splitting scheme include superior line noise rejecttion and very high regulator gain, which lead to excellent line and load regulation. Impressive ±1.8% accuracy is guaranteed over line, load, and temperature. Additional features of the circuit include current limit, thermal shutdown, and noise reduction. Rev. D | Page 9 of 16 ADP3335 Data Sheet APPLICATIONS INFORMATION OUTPUT CAPACITOR SELECTION THERMAL OVERLOAD PROTECTION As with any micropower device, output transient response is a function of the output capacitance. The ADP3335 is stable over a wide range of capacitor values, types, and ESR (anyCAP). A capacitor as low as 1 µF is all that is needed for stability; larger capacitors can be used if high output current surges are anticipated. The ADP3335 is stable with extremely low ESR capacitors (ESR ≈ 0), such as multilayer ceramic capacitors (MLCC) or organic semiconductor electrolytic capacitors (OSCON). Note that the effective capacitance of some capacitor types may fall below the minimum at extreme temperatures. Ensure that the capacitor provides more than 1 µF over the entire temperature range. The ADP3335 is protected against damage from excessive power dissipation by its thermal overload protection circuit, which limits the die temperature to a maximum of 165°C. Under extreme conditions (i.e., high ambient temperature and power dissipation) where die temperature starts to rise above 165°C, the output current is reduced until the die temperature has dropped to a safe level. The output current is restored when the die temperature is reduced. INPUT BYPASS CAPACITOR An input bypass capacitor is not strictly required, but is advisable in any application involving long input wires or high source impedance. Connecting a 1 µF capacitor from IN to ground reduces the circuit’s sensitivity to PC board layout. If a larger value output capacitor is used, then a larger value input capacitor is also recommended. NOISE REDUCTION A noise reduction capacitor (CNR) can be used, as shown in Figure 24, to further reduce the noise by 6 dB to 10 dB (Figure 22). Low leakage capacitors in the 100 pF to 1 nF range provide the best performance. Since the noise reduction pin, NR, is internally connected to a high impedance node, any connection to this node should be made carefully to avoid noise pickup from external sources. The pad connected to this pin should be as small as possible, and long PC board traces are not recommended. When adding a noise reduction capacitor, maintain a minimum load current of 1 mA when not in shutdown. It is important to note that as CNR increases, the turn-on time will be delayed. With NR values greater than 1 nF, this delay may be on the order of several milliseconds. CNR Current and thermal limit protections are intended to protect the device against accidental overload conditions. For normal operation, device power dissipation should be externally limited so that junction temperatures will not exceed 150°C. CALCULATING JUNCTION TEMPERATURE Device power dissipation is calculated as follows: PD = (VIN − VOUT)ILOAD + (VIN)IGND Where ILOAD and IGND are load current and ground current, and VIN and VOUT are input and output voltages, respectively. Assuming ILOAD = 400 mA, IGND = 4 mA, VIN = 5.0 V, and VOUT = 3.3 V, device power dissipation is PD = (5 V – 3.3 V)400 mA + 5.0 V(4 mA) = 700 mW The junction temperature can be calculated from the power dissipation, ambient temperature, and package thermal resistance. The thermal resistance is a function not only of the package, but also of the circuit board layout. Standard test conditions are used to determine the values published in this data sheet, but actual performance will vary. For an LFCSP-8 package mounted on a standard 4-layer board, θJA is 48°C/W. In the above example, where the power dissipation is 700 mW, the temperature rise above ambient will be approximately equal to ∆TJA = 0.700 W × 48°C/W = 33.6°C To limit the maximum junction temperature to 150°C, the maximum allowable ambient temperature will be TAMAX = 150°C − 33.6°C = 116.4°C 5 In this case, the resulting ambient temperature limitation is above the maximum allowable ambient temperature of 85°C. NR OUT 3 ADP3335 CIN 1µF + IN 8 IN OUT 2 OUT 1 SD GND 6 4 + VOUT COUT 1µF ON OFF 00147-0-021 VIN 7 Figure 24. Typical Application Circuit Rev. D | Page 10 of 16 Data Sheet ADP3335 PRINTED CIRCUIT BOARD LAYOUT CONSIDERATIONS 2. All surface-mount packages rely on the traces of the PC board to conduct heat away from the package. Use the following general guidelines when designing printed circuit boards to improve both electrical and thermal performance. 1. Keep the output capacitor as close as possible to the output and ground pins. 2. Keep the input capacitor as close as possible to the input and ground pins. 3. PC board traces with larger cross sectional areas will remove more heat from the ADP3335. For optimum heat transfer, specify thick copper and use wide traces. 4. It is not recommended to use solder mask or silkscreen on the PCB traces adjacent to the ADP3335’s pins, since doing so will increase the junction-to-ambient thermal resistance of the package. 5. Also, note that the thermal pad is attached to the die substrate, so the thermal planes to which the thermal vias connect must be electrically isolated or tied to VIN. Do NOT connect the thermal pad to ground. 3. The solder mask opening should be about 120 µ (4.7 mils) larger than the pad size, resulting in a minimum 60 µm (2.4 mils) clearance between the pad and the solder mask. 4. The paste mask opening is typically designed to match the pad size used on the peripheral pads of the LFCSP package. This should provide a reliable solder joint as long as the stencil thickness is about 0.125 mm. The paste mask for the thermal pad needs to be designed for the maximum coverage to effectively remove the heat from the package. However, due to the presence of thermal vias and the size of the thermal pad, eliminating voids may not be possible. 5. The recommended paste mask stencil thickness is 0.125 mm. A laser cut stainless steel stencil with trapezoidal walls should be used. A “No Clean” Type 3 solder paste should be used for mounting the LFCSP package. Also, a nitrogen purge during the reflow process is recommended. 6. The package manufacturer recommends that the reflow temperature should not exceed 220°C and the time above liquidus is less than 75 seconds. The preheat ramp should be 3°C/second or lower. The actual temperature profile depends on the board density and must be determined by the assembly house as to what works best. Use additional copper layers or planes to reduce the thermal resistance. When connecting to other layers, use multiple vias, if possible. LFCSP LAYOUT CONSIDERATIONS The LFCSP package has an exposed die paddle on the bottom, which efficiently conducts heat to the PCB. In order to achieve the optimum performance from the LFCSP package, special consideration must be given to the layout of the PCB. Use the following layout guidelines for the LFCSP package. 2× VIAS, 0.250∅ 35µm PLATING 0.73 0.30 1.80 0.90 The thermal pad of the LFCSP package provides a low thermal impedance path (approximately 20°C/W) to the PCB. Therefore, the PCB must be properly designed to effectively conduct heat away from the package. This is achieved by adding thermal vias to the PCB, which provide a thermal path to the inner or bottom layers. See Figure 25 for the recommended via pattern. Note that the via diameter is small to prevent the solder from flowing through the via and leaving voids in the thermal pad solder joint. 2.36 0.50 SHUTDOWN MODE 1.40 3.36 Applying a TTL high signal to the shutdown (SD) pin or tying it to the input pin, turns the output ON. Pulling SD down to 0.4 V or below, or tying it to ground, turns the output OFF. In shutdown mode, quiescent current is reduced to a typical value of 10 nA. 00147-0-024 1.90 Figure 25. 3 mm × 3 mm LFCSP Pad Pattern (Dimensions shown in millimeters) 1. The pad pattern is given in Figure 25. The pad dimension should be followed closely for reliable solder joints, while maintaining reasonable clearances to prevent solder bridging. Rev. D | Page 11 of 16 ADP3335 Data Sheet OUTLINE DIMENSIONS 1.84 1.74 1.64 3.10 3.00 SQ 2.90 PIN 1 INDEX AREA 1.55 1.45 1.35 EXPOSED PAD 0.50 0.40 0.30 1 4 BOTTOM VIEW 0.80 0.75 0.70 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.203 REF 0.30 0.25 0.20 PIN 1 INDICATOR (R 0.15) FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 12-07-2010-A TOP VIEW COMPLIANT TO JEDEC STANDARDS MO-229-WEED Figure 26. 8-Lead Lead Frame Chip Scale Package [LFCSP_WD] 3 mm × 3 mm Body, Very Very Thin, Dual Lead (CP-8-13) Dimensions shown in millimeters 3.20 3.00 2.80 8 3.20 3.00 2.80 1 5.15 4.90 4.65 5 4 PIN 1 IDENTIFIER 0.65 BSC 0.95 0.85 0.75 15° MAX 1.10 MAX 0.15 0.05 COPLANARITY 0.10 0.40 0.25 6° 0° 0.23 0.09 0.80 0.55 0.40 COMPLIANT TO JEDEC STANDARDS MO-187-AA Figure 27. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters Rev. D | Page 12 of 16 100709-B SEATING PLANE 0.50 BSC 8 5 Data Sheet ADP3335 ORDERING GUIDE Model 1 ADP3335ACPZ-1.8-R7 ADP3335ACPZ-2.5-R7 ADP3335ACPZ-2.85R7 ADP3335ACPZ-3.3-R7 ADP3335ACPZ-3.3-RL ADP3335ACPZ-5-R7 ADP3335ARMZ-1.8-R7 ADP3335ARMZ-1.8-RL ADP3335ARMZ-2.5-RL ADP3335ARMZ-2.5RL7 ADP3335ARMZ-2.85R7 ADP3335ARMZ-2.85RL ADP3335ARMZ-3.3-RL ADP3335ARMZ-3.3RL7 ADP3335ARMZ-5-R7 ADP3335ARMZ-5-REEL Output Voltage (V) 2 1.8 2.5 2.85 3.3 3.3 5 1.8 1.8 2.5 2.5 2.85 2.85 3.3 3.3 5 5 Temperature Range –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C Z = RoHS Compliant Part. For additional voltage options, contact a local sales or distribution representative. 3 Z = RoHS Compliant Parts have a "#" marked on the device preceding the date code. 1 2 Rev. D | Page 13 of 16 Package Description 8-Lead LFCSP_WD 8-Lead LFCSP_WD 8-Lead LFCSP_WD 8-Lead LFCSP_WD 8-Lead LFCSP_WD 8-Lead LFCSP_WD 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP Package Option CP-8-13 CP-8-13 CP-8-13 CP-8-13 CP-8-13 CP-8-13 RM-8 RM-8 RM-8 RM-8 RM-8 RM-8 RM-8 RM-8 RM-8 RM-8 Branding 3 L1G L1H L1J L1K L1K L1L LFA LFA LFC LFC LFD LFD LFE LFE LFF LFF ADP3335 Data Sheet NOTES Rev. D | Page 14 of 16 Data Sheet ADP3335 NOTES Rev. D | Page 15 of 16 ADP3335 Data Sheet NOTES ©2000–2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D00147-0-10/13(D) Rev. D | Page 16 of 16