TI CD74AC74M Dual positive-edge-triggered d-type flip-flops with clear and preset Datasheet

CD54AC74, CD74AC74
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH CLEAR AND PRESET
SCHS231D – SEPTEMBER 1998 – REVISED DECEMBER 2002
D
D
D
D
D
D
CD54AC74 . . . F PACKAGE
CD74AC74 . . . E OR M PACKAGE
(TOP VIEW)
AC Types Feature 1.5-V to 5.5-V Operation
and Balanced Noise Immunity at 30% of the
Supply
Speed of Bipolar F, AS, and S, With
Significantly Reduced Power Consumption
Balanced Propagation Delays
±24-mA Output Drive Current
– Fanout to 15 F Devices
SCR-Latchup-Resistant CMOS Process and
Circuit Design
Exceeds 2-kV ESD Protection Per
MIL-STD-883, Method 3015
1CLR
1D
1CLK
1PRE
1Q
1Q
GND
1
14
2
13
3
12
4
11
5
10
6
9
7
8
VCC
2CLR
2D
2CLK
2PRE
2Q
2Q
description/ordering information
The ’AC74 dual positive-edge-triggered devices are D-type flip-flops.
A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the
other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time
requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs
at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval,
data at the D input can be changed without affecting the levels at the outputs.
ORDERING INFORMATION
PDIP – E
55°C to 125°C
–55°C
ORDERABLE
PART NUMBER
PACKAGE†
TA
SOIC – M
Tube
CD74AC74E
Tube
CD74AC74M
Tape and reel
CD74AC74M96
TOP-SIDE
MARKING
CD74AC74E
AC74M
CDIP – F
Tube
CD54AC74F3A
CD54AC74F3A
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
FUNCTION TABLE
(each flip-flop)
INPUTS
OUTPUTS
PRE
CLR
CLK
D
Q
Q
L
H
X
X
H
L
H
L
X
X
L
H
L
L
X
X
H‡
H‡
H
H
↑
H
H
L
H
H
↑
L
L
H
H
H
L
X
Q0
Q0
‡ This configuration is nonstable; that is, it does not
persist when PRE or CLR returns to its inactive
(high) level.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2002, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
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1
CD54AC74, CD74AC74
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH CLEAR AND PRESET
SCHS231D – SEPTEMBER 1998 – REVISED DECEMBER 2002
logic diagram, each flip-flop (positive logic)
PRE
CLK
C
C
C
Q
TG
C
C
C
C
D
TG
TG
TG
C
C
C
Q
CLR
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 6 V
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 2): E package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W
M package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
2
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CD54AC74, CD74AC74
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH CLEAR AND PRESET
SCHS231D – SEPTEMBER 1998 – REVISED DECEMBER 2002
recommended operating conditions (see Note 3)
–55°C to
125°C
TA = 25°C
VCC
Supply voltage
VIH
High-level input voltage
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
1.5
5.5
1.5
5.5
1.5
5.5
VCC = 1.5 V
VCC = 3 V
1.2
1.2
1.2
2.1
2.1
2.1
VCC = 5.5 V
VCC = 1.5 V
3.85
VIL
Low-level input voltage
VI
VO
Input voltage
0
Output voltage
0
IOH
IOL
High-level output current
∆t/∆v
Input transition rise or fall rate
3.85
VCC = 3 V
VCC = 5.5 V
Low-level output current
–40°C to
85°C
V
3.85
0.3
0.3
0.3
0.9
0.9
0.9
1.65
VCC
VCC
1.65
0
0
V
VCC
VCC
V
1.65
0
0
VCC
VCC
V
V
VCC = 4.5 V to 5.5 V
VCC = 4.5 V to 5.5 V
–24
–24
–24
mA
24
24
24
mA
VCC = 1.5 V to 3 V
VCC = 3.6 V to 5.5 V
50
50
50
20
20
20
ns/V
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
IOH = –50 µA
VOH
VI = VIH or VIL
IOH = –4 mA
IOH = –24 mA
IOH = –50 mA†
IOH = –75 mA†
IOL = 50 µA
VOL
II
ICC
VI = VIH or VIL
VI = VCC or GND
VI = VCC or GND,
–55°C to
125°C
TA = 25°C
MAX
MIN
–40°C to
85°C
MAX
MIN
1.5 V
1.4
1.4
1.4
3V
2.9
2.9
2.9
4.5 V
4.4
4.4
4.4
3V
2.58
2.4
2.48
4.5 V
3.94
3.7
3.8
5.5 V
UNIT
MAX
V
3.85
5.5 V
3.85
1.5 V
0.1
0.1
0.1
3V
0.1
0.1
0.1
4.5 V
0.1
0.1
0.1
IOL = 12 mA
IOL = 24 mA
IOL = 50 mA†
3V
0.36
0.5
0.44
4.5 V
0.36
0.5
0.44
IOL = 75 mA†
5.5 V
5.5 V
5.5 V
IO = 0
5.5 V
Ci
V
1.65
1.65
±0.1
±1
±1
µA
4
80
40
µA
10
10
10
pF
† Test one output at a time, not exceeding 1-second duration. Measurement is made by forcing indicated current and measuring voltage to minimize
power dissipation. Test verifies a minimum 50-Ω transmission-line drive capability at 85°C and 75-Ω transmission-line drive capability at 125°C.
POST OFFICE BOX 655303
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3
CD54AC74, CD74AC74
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH CLEAR AND PRESET
SCHS231D – SEPTEMBER 1998 – REVISED DECEMBER 2002
timing requirements over recommended operating free-air temperature range, VCC = 1.5 V (unless
otherwise noted)
–55°C to
125°C
MIN
fclock
Clock frequency
tw
Pulse duration
tsu
Setup time
th
trec
Hold time
Recovery time, before CLK↑
–40°C to
85°C
MAX
MIN
UNIT
MAX
9
10
MHz
PRE or CLR low
50
44
CLK
56
49
Data
44
39
Data after CLK↑
0
0
ns
CLR↑ or PRE↑
34
30
ns
ns
ns
PRE or CLR inactive
ns
timing requirements over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V
(unless otherwise noted) (see Figure 1)
–55°C to
125°C
MIN
fclock
–40°C to
85°C
MAX
Clock frequency
MIN
79
90
PRE or CLR low
5.6
4.9
CLK
6.3
5.5
Data
4.9
4.3
tw
Pulse duration
tsu
Setup time
th
trec
Hold time
Data after CLK↑
Recovery time, before CLK↑
CLR↑ or PRE↑
UNIT
MAX
MHz
ns
ns
PRE or CLR inactive
ns
0
0
ns
4.7
4.1
ns
timing requirements over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V
(unless otherwise noted) (see Figure 1)
–55°C to
125°C
MIN
4
fclock
Clock frequency
tw
Pulse duration
tsu
Setup time
th
trec
Hold time
Data after CLK↑
Recovery time, before CLK↑
CLR↑ or PRE↑
MAX
–40°C to
85°C
MIN
110
PRE or CLR low
125
MHz
4
3.5
CLK
4.5
3.9
Data
3.5
3.1
0
0
ns
2.7
2.4
ns
PRE or CLR inactive
POST OFFICE BOX 655303
UNIT
MAX
• DALLAS, TEXAS 75265
ns
ns
ns
CD54AC74, CD74AC74
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH CLEAR AND PRESET
SCHS231D – SEPTEMBER 1998 – REVISED DECEMBER 2002
switching characteristics over recommended operating free-air temperature range,
VCC = 1.5 V, CL = 50 pF (unless otherwise noted) (see Figure 1)
PARAMETER
fmax
tPLH
tPHL
tPLH
tPHL
FROM
(INPUT)
TO
(OUTPUT)
–55°C to
125°C
MIN
–40°C to
85°C
MAX
9
CLK
Q or Q
PRE or CLR
Q or Q
MIN
UNIT
MAX
10
MHz
125
114
125
114
132
120
144
131
ns
ns
switching characteristics over recommended operating free-air temperature range,
VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
PARAMETER
fmax
tPLH
tPHL
tPLH
tPHL
FROM
(INPUT)
TO
(OUTPUT)
–55°C to
125°C
MIN
–40°C to
85°C
MIN
3.5
14
3.6
12.7
3.5
14
3.6
12.7
3.7
14.7
3.8
13.4
4
16.1
4.1
14.6
79
CLK
Q or Q
PRE or CLR
Q or Q
UNIT
MAX
MAX
90
MHz
ns
ns
switching characteristics over recommended operating free-air temperature range,
VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
fmax
tPLH
tPHL
tPLH
tPHL
FROM
(INPUT)
TO
(OUTPUT)
–55°C to
125°C
MIN
–40°C to
85°C
MAX
110
CLK
Q or Q
PRE or CLR
Q or Q
MIN
UNIT
MAX
125
MHz
2.5
10
2.6
9.1
2.5
10
2.6
9.1
2.6
10.5
2.7
9.5
2.9
11.5
3
10.4
ns
ns
operating characteristics, TA = 25°C
PARAMETER
Cpd
TYP
Power dissipation capacitance
55
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UNIT
pF
5
CD54AC74, CD74AC74
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH CLEAR AND PRESET
SCHS231D – SEPTEMBER 1998 – REVISED DECEMBER 2002
PARAMETER MEASUREMENT INFORMATION
S1
R1 = 500 Ω†
From Output
Under Test
2 × VCC
Open
GND
CL = 50 pF
(see Note A)
R2 = 500 Ω†
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
tw
VCC
† When VCC = 1.5 V, R1 = R2 = 1 kΩ
Input
50% VCC
50% VCC
0V
LOAD CIRCUIT
VOLTAGE WAVEFORMS
PULSE DURATION
CLR
Input
VCC
Reference
Input
VCC
50% VCC
50% VCC
0V
0V
tsu
trec
Data
50%
Input 10%
VCC
50% VCC
CLK
90%
VOLTAGE WAVEFORMS
RECOVERY TIME
tf
VCC
50% VCC
50% VCC
tPLH
tPHL
50%
10%
90%
90%
tr
tPHL
Out-of-Phase
Output
VCC
50% VCC
10% 0 V
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
0V
In-Phase
Output
90%
tr
0V
Input
th
90%
VOH
50% VCC
10%
VOL
tf
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPLH
50% VCC
10%
tf
50%
10%
90%
tr
VOH
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
VCC
Output
Control
50% VCC
50% VCC
0V
tPLZ
tPZL
50% VCC
tPHZ
tPZH
Output
Waveform 2
S1 at GND
(see Note B)
≈VCC
20% VCC
VOL
50% VCC
VOH
80% VCC
≈0 V
VOLTAGE WAVEFORMS
OUTPUT ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and test-fixture capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns.
Phase relationships between waveforms are arbitrary.
D. For clock inputs, fmax is measured with the input duty cycle at 50%.
E. The outputs are measured one at a time with one input transition per measurement.
F. tPLH and tPHL are the same as tpd.
G. tPZL and tPZH are the same as ten.
H. tPLZ and tPHZ are the same as tdis.
Figure 1. Load Circuit and Voltage Waveforms
6
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