TI DRV602 Directpathâ ¢, 2vrms line driver with adjustable gain Datasheet

DRV602
www.ti.com ........................................................................................................................................................................................... SLOS572 – DECEMBER 2008
DIRECTPATH™, 2Vrms Line Driver with Adjustable gain
FEATURES
1
• DIRECTPATH™
– Eliminates Pop/Clicks
– Eliminates Output DC-Blocking Capacitors
– Provides Flat Frequency Response
20Hz–20kHz
• Low Noise and THD
– SNR > 102 dB
– Typical VN < 15 µVms
– THD+N < 0.05% 20 Hz–20 kHz
• 2Vrms Output Voltage into 2.5 kΩR Load With
3.3V Supply Voltage
• Differential Input
234
APPLICATIONS
•
•
•
•
Set-Top Boxes
PDP / LCD TV
Blu-ray Disc™, DVD-Players
Home Theater in a Box
Designed using TI's patented DIRECTPATH™
technology, the DRV602 is capable of driving 2Vrms
into a 2.5kΩ load with 3.3V supply voltage. The
device has differential inputs and uses external gain
setting resistors, that supports a gain range of ±1V/V
to ±10V/V. The use of external gain resistors also
allows the implementation of a 2nd order low pass
filter to compliment DAC's and SOC converters. The
line output of the DRV602 has ±8kV IEC ESD
protection. The DRV602 (referred to as the '602) has
build-in shutdown control for pop-free on/off control.
Using the DRV602 in audio products can reduce
component count compared to traditional methods of
generating a 2Vrms output. The DRV602 doesn't
require a power supply greater than 3.3V to generate
its 5.6VPP output, nor does it require a split rail power
supply. The DRV602 integrates its own charge pump
to generate a negative supply rail that provides a
clean, pop-less ground biased 2Vrms output.
The DRV602 is available in a 14 pin TSSOP
package.
DESCRIPTION
The DRV602PW is a 2Vrms Pop-less stereo line
driver designed to allow the removal of the output
dc-blocking capacitors for reduced component count
and cost. The device is ideal for single supply
electronics where size and cost are critical design
parameters.
If higher SNR, trimmed DC-offset and external
undervoltage-mute functions are beneficial in the
application, TI recommends the footprint compatible
DRV603 (SLOS617).
DAC
SOC
DRV602
+
DAC
RIGHT
+
LEFT
-
1
2
3
4
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
DIRECTPATH, TI FilterPro are trademarks of Texas Instruments.
Blu-ray Disc is a trademark of Blu-ray Disc Association.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008, Texas Instruments Incorporated
DRV602
SLOS572 – DECEMBER 2008 ........................................................................................................................................................................................... www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
PW (TSSOP) PACKAGE
(TOP VIEW)
+INR
1
14
+INL
-INR
2
13
-INL
OUTR
3
12
OUTL
SGND
4
11
NC
EN
5
10
PGND
VDD
6
9
PVDD
CN
7
8
CP
Charge Pump
PIN FUNCTIONS
PIN
NAME
TSSOP (PW)
+INR
1
-INR
OUTR
I/O (1)
DESCRIPTION
I
Right channel OPAMP positive input
2
I
Right channel OPAMP negative input
3
O
Right channel OPAMP output
SGND
4
I
Signal ground
EN
5
I
Enable input, active high
VDD
6
O
Supply voltage
CN
7
I/O
Charge pump flying capacitor negative terminal
CP
8
I/O
Charge pump flying capacitor positive terminal
PVDD
9
I
Positive supply
PGND
10
I
Power ground
NC
11
OUTL
12
O
Left channel OPAMP output
-INL
13
I
Left channel OPAMP negative input
+INL
14
I
Left channel OPAMP positive input
(1)
No internal connection
I = input, O = output, P = power
2
Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): DRV602
DRV602
www.ti.com ........................................................................................................................................................................................... SLOS572 – DECEMBER 2008
ABSOLUTE MAXIMUM RATINGS (1) (2)
over operating free-air temperature range
VALUE
UNIT
–0.3 V to 5.5
V
VSS – 0.3 to VDD + 0.3
V
> 600
Ω
Supply voltage, VDD to GND
VI
Input voltage
RL
Minimum load impedance
EN to GND
TJ
Maximum operating junction temperature range,
Tstg
Storage temperature range
ESD
IEC Contact ESD Protection per IEC6100-4-2, on output pins measured on DRV602EVM
(1)
(2)
–0.3 to VDD +0.3
V
0 to 70
°C
–40 to 150
°C
±8
kV
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
These voltages represents the DC voltage + peak AC waveform measured at the terminal of the device in all conditions.
ORDERING INFORMATION
(1)
TA
PACKAGE (1)
DESCRIPTION
0°C to 70°C
DRV602PW
14-Pin TSSOP
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
RECOMMENDED OPERATING CONDITIONS
MIN
TYP
MAX
3
3.3
4.5
VDD
Supply voltage,
DC Supply Voltage
VIH
High-level input voltage
EN
60
VIL
Low-level input voltage
EN
40
TA
Operating free-air temperature
UNIT
V
% of VDD
% of VDD
0
70
°C
ELECTRICAL CHARACTERISTICS
TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
|VOS|
Output offset voltage
VDD = 3 V to 4.5 V, Voltage follower - gain = 1
PSRR
Supply Rejection Ratio
VDD = 3.3 V to 4.5 V
VOH
High-level output voltage
VDD = 3.3 V, RL = 2.5 kΩ
VOL
Low-level output voltage
VDD = 3.3 V, RL = 2.5 kΩ
|IIH|
High-level input current (EN)
|IIL|
Low-level input current (EN)
Supply Current
TYP
MAX
5
88
UNIT
mV
dB
3.10
V
–3.05
V
VDD = 4.5 V, VI = VDD
1
µA
VDD = 4.5 V, VI = 0 V
1
µA
VDD = 3.3 V, No load, EN = VDD
IDD
MIN
VDD = 4.5 V, No load, EN = VDD
Shutdown mode, Vdd = 3 V to 4.5 V
8
11
12.5
20
2
mA
mA
3
Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): DRV602
DRV602
SLOS572 – DECEMBER 2008 ........................................................................................................................................................................................... www.ti.com
OPERATING CHARACTERISTICS
VDD = 3.3 V , TA = 25°C, RL = 2.5kΩ, C(PUMP) = C(PVSS) = 1 µF , CIN = 1 µF, RIN = 33 kΩ, Rfb = 68kΩ (unless otherwise noted)
PARAMETER
VO
THD+N
TEST CONDITIONS
Output Voltage (Outputs In Phase)
THD = 1%, VDD = 3.3 V, f = 1 kHz
Total harmonic distortion plus noise
VO = 2 Vrms, f = 1 kHz
VO = 2 Vrms, f = 6.8 kHz
Crosstalk
VO = 2 Vrms, f = 1 kHz
IO
Output current limit
VDD = 3.3 V
RIN
Input resistor range
Rfb
Feedback resistor range
VN
MIN
TYP
MAX
2.05
UNIT
Vrms
0.01%
0.05%
–80
dB
20
mA
1
10
47
4.7
20
100
kΩ
kΩ
Slew rate
4.5
V/µs
Maximum capacitive load
220
pF
15
µVrms
102
dB
Noise output voltage
A-weighted, BW 20Hz–22kHz
SNR
Signal to noise ratio
VO = 2 Vrms, THD+N = 0.1%, 22 kHz BW,
A-weighted
GBW
Unity Gain Bandwidth
AVO
Open-loop voltage gain
Fcp
Charge Pump frequency
8
MHz
150
225
450
dB
675
kHz
APPLICATION CIRCUIT
LEFT
OUTPUT
3.3V
supply
R2
+
C2
CP
C2
DRV602
Line
Driver
Click and Pop
Suppression
Line
Driver
CN
PVSS
SGND
-INR
OUTR
C2
+INR
R2
1m F
Bias
Circuitry
R2
PVDD
R3
PGND
+INL
-
1mF
EN
R1
R3
NC
C3
C1
Short Circuit
Protection
R1
OUTL
C3
-INL
LEFT
INPUT
+
RIGHT
INPUT
C3
R1
C3
R1
C1
R3
-
1mF
R3
C2
R2
RIGHT
OUTPUT
ENABLE
R1 = 33kΩ, R2 = 68kΩ, R3 = 100kΩ, C1 = 150pF, C2 = 15pF, C3 = 1 µF
Differential input, single ended output, 2nd order filter. 40kHz –3dB frequency, Gain 2.06.
4
Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): DRV602
DRV602
www.ti.com ........................................................................................................................................................................................... SLOS572 – DECEMBER 2008
TYPICAL CHARACTERISTICS
VDD = 3.3V , TA = 25°C, C(PUMP) = C(PVSS) = 1 µF , CIN = 1 µF, RIN = 33 kΩ, Rfb = 68 kΩ (unless otherwise noted)
TOTAL HARMONIC DISTORTION + NOISE
vs
FREQUENCY
10
5
THD+N - Total Harmonic Distortion+Noise - %
THD+N - Total Harmonic Distortion+Noise - %
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT VOLTAGE
1
0.1
20 Hz
6.7 kHz
0.01
1 kHz
0.001
0.0001
100m
200m
500m 800m
2
3
VO - Output Voltage - Vrms
4
5
10
5
1
0.1
200 mVrms
0.01
2 Vrms
0.001
0.0001
20
50
100 200 500 1k 2k
f - Frequency - Hz
5k
Figure 1.
Figure 2.
FFT
vs
FREQUENCY
QUIESCENT SUPPLY CURRENT
vs
SUPPLY VOLTAGE
20k
+0
14m
VO = 2mVrms
-20
No Load,
VI = 0 V
Quiescent Current - A
12m
FFT - dBr
-40
-60
-80
-100
10m
8m
6m
4m
-120
2m
-140
0
5k
10k
15k
f - Frequency - Hz
20k
0
-0
Figure 3.
+1
+4
+2
+3
VDD - Supply Voltage - V
+5
Figure 4.
5
Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): DRV602
DRV602
SLOS572 – DECEMBER 2008 ........................................................................................................................................................................................... www.ti.com
APPLICATION INFORMATION
Line Driver Amplifiers
Single-supply line driver amplifiers typically require dc-blocking capacitors. The top drawing in Figure 5 illustrates
the conventional line driver amplifier connection to the load and output signal.
DC blocking capacitors are often large in value, and a mute circuit is needed during power up to minimize click &
pop. The output capacitor and mute circuit consume PCB area and increase cost of assembly, and can reduce
the fidelity of the audio output signal.
9-12 V
Conventional Solution
VDD
+
Mute Circuit
Co
+
+
OPAMP
Output
VDD/2
GND
Enable
5V
DVR602 Solution
+
DRV602
DirectPath
VDD
Output
GND
VSS
Enable
Figure 5. Conventional and DirectPath Line Driver
The DirectPath™ amplifier architecture operates from a single supply, but makes use of an internal charge pump
to provide a negative voltage rail.
Combining the user provided positive rail and the negative rail generated by the IC, the device operates in what
is effectively a split supply mode.
The output voltages are now centered at zero volts with the capability to swing to the positive rail or negative rail.
The DirectPath amplifier requires no output dc blocking capacitors.
The bottom block diagram and waveform of Figure 5 illustrate the ground-referenced Line Driver architecture.
This is the architecture of the DRV602.
6
Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): DRV602
DRV602
www.ti.com ........................................................................................................................................................................................... SLOS572 – DECEMBER 2008
Charge Pump Flying Capacitor and PVSS Capacitor
The charge pump flying capacitor serves to transfer charge during the generation of the negative supply voltage.
The PVSS capacitor must be at least equal to the charge pump capacitor in order to allow maximum charge
transfer. Low ESR capacitors are an ideal selection, and a value of 1µF is typical. Capacitor values that are
smaller than 1µF can be used, but the maximum output voltage may be reduced and the device may not operate
to specifications.
Decoupling Capacitors
The DRV602 is a DirectPath Line Driver amplifier that require adequate power supply decoupling to ensure that
the noise and total harmonic distortion (THD) are low. A good low equivalent-series-resistance (ESR) ceramic
capacitor, typically 1µF, placed as close as possible to the device VDD lead works best. Placing this decoupling
capacitor close to the DRV602 is important for the performance of the amplifier. For filtering lower frequency
noise signals, a 10-µF or greater capacitor placed near the audio power amplifier would also help, but it is not
required in most applications because of the high PSRR of this device.
Gain setting resistors ranges
The gain setting resistors, RIN and Rfb, must be chosen so that noise, stability and input capacitor size of the
DRV602 is kept within acceptable limits. Voltage gain is defined as Rfb divided by RIN.
Selecting values that are too low demands a large input ac-coupling capacitor, CIN . Selecting values that are too
high increases the noise of the amplifier. Table 1 lists the recommended resistor values for different gain
settings.
Table 1. Recommended Resistor Values
INPUT RESISTOR
VALUE, RIN
FEEDBACK RESISTOR
VALUE, Rfb
DIFFERENTIAL INPUT
GAIN
INVERTING INPUT GAIN
NON INVERTING INPUT
GAIN
22 kΩ
22 kΩ
1.0 V/V
–1.0 V/V
2.0 V/V
15 kΩ
30 kΩ
1.5 V/V
–1.5 V/V
2.5 V/V
33 kΩ
68 kΩ
2.1 V/V
–2.1 V/V
3.1 V/V
10 kΩ
100 kΩ
10.0 V/V
–10.0 V/V
11.0 V/V
CIN
RIN
CIN
-In
RIN
-In
Rfb
Differential
Input
Rfb
-
Inverting
+
+
+In
CIN
RIN
Rfb
Figure 6. Differential Input
Figure 7. Inverting
Cx
RIN
Rfb
-
Non
Inverting
+
+In
CIN
Rx
Figure 8. Non-Inverting
7
Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): DRV602
DRV602
SLOS572 – DECEMBER 2008 ........................................................................................................................................................................................... www.ti.com
Input-Blocking Capacitors
DC input-blocking capacitors are required to be added in series with the audio signal into the input pins of the
DRV602. These capacitors block the DC portion of the audio source and allow the DRV602 inputs to be properly
biased to provide maximum performance. The input blocking capacitors also limit the DC gain to 1, limiting the
DC-offset voltage at the output.
These capacitors form a high-pass filter with the input resistor, RIN. The cutoff frequency is calculated using
Equation 1. For this calculation, the capacitance used is the input-blocking capacitor and the resistance is the
input resistor chosen from Table 1, then the frequency and/or capacitance can be determined when one of the
two values are given.
1
1
fc IN +
or C IN + 2p fc R
2p RIN C IN
IN IN
(1)
Using the DRV602 as 2nd Order Filter
Several audio DACs used today require an external low-pass filter to remove out of band noise. This is possible
with the DRV602 as it can be used like a standard OPAMP.
Several filter topologies can be implemented both single ended and differential. In Figure 9, a Multi FeedBack MFB, with differential input and single ended input is shown.
An ac-coupling capacitor to remove dc-content from the source is shown, it serves to block any dc content from
the source and lowers the dc-gain to 1 helping reducing the output dc-offset to minimum.
The component values can be calculated with the help of the TI FilterPro™ program available on the TI website
at: http://focus.ti.com/docs/toolsw/folders/print/filterpro.html
Inverting Input
Differential Input
R2
R2
C3
R1
C3
C1
R3
C1
R3
R1
- In
- In
-
C2
-
C2
DRV602
DRV602
+
+
+ In
C3
R1
R3
C1
R2
Figure 9. 2nd Order Active Low Pass Filter
The resistor values should have a low value for obtaining low noise, but should also have a high enough value to
get a small size ac-coupling cap. With the proposed values, 33k, 68k, 100k, a DNR of 102dB can be achieved
with a small 1µF input ac-coupling capacitor.
8
Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): DRV602
DRV602
www.ti.com ........................................................................................................................................................................................... SLOS572 – DECEMBER 2008
Pop-Free Power Up
Pop-free power up is ensured by keeping the SD (shutdown pin) low during power supply ramp up and down.
The EN pin should be kept low until the input ac-coupling capacitors are fully charged before asserting the EN
pin high, this way proper precharge of the ac-coupling is performed, and pop-less power-up is achieved.
Figure 10 illustrates the preferred sequence.
Supply
Supply ramp
SD
Time for ac-coupling
capacitors to charge
Figure 10. Power-Up Sequence
Capacitive Load
The DRV602 has the ability to drive a high capacitive load up to 220pF directly, higher capacitive loads can be
accepted by adding a series resistor of 10Ω or larger. The figure below shows a 10kHz signal into a 470pF
capacitor using the 10R series resistor.
Layout Recommendations
A proposed layout for the DRV602 can be seen in the DRV602EVM user's guide (SLOU248) and the Gerber files
can be downloaded on www.ti.com, open the DRV602 product folder and look in the Tools and Software folder.
The gain setting resistors, RIN and Rfb , must be placed close to the input pins to minimize the capacitive loading
on these input pins and to ensure maximum stability of the DRV602. For the recommenced PCB layout, see the
DRV602EVM user's guide.
9
Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): DRV602
PACKAGE OPTION ADDENDUM
www.ti.com
1-Jan-2009
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
DRV602PW
ACTIVE
TSSOP
PW
14
90
TBD
Call TI
Call TI
DRV602PWR
ACTIVE
TSSOP
PW
14
2000
TBD
Call TI
Call TI
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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