ADS8325 AD S8 32 5 AD S8 3 25 SBAS226C – MARCH 2002 – REVISED AUGUST 2007 16-Bit, High-Speed, 2.7V to 5.5V microPower Sampling ANALOG-TO-DIGITAL CONVERTER FEATURES DESCRIPTION 1 • • • • 23 • • • • 16-Bits No Missing Codes Very Low Noise: 3LSBPP Excellent Linearity: ±1.5LSB typ microPower: – 4.5mW at 100kHz – 1mW at 10kHz MSOP-8 and SON-8 Packages (SON Package Size Same as 3x3 QFN) 16-Bit Upgrade to the 12-Bit ADS7816 and ADS7822 Pin-Compatible With the ADS7816, ADS7822, ADS7826, ADS7827, ADS7829, and ADS8320 Serial (SPI™/SSI) Interfaces The ADS8325 is a 16-bit, sampling, Analog-to-Digital (A/D) converter specified for a supply voltage range from 2.7V to 5.5V. It requires very little power, even when operating at the full 100kHz data rate. At lower data rates, the high speed of the device enables it to spend most of its time in the power-down mode. For example, the average power dissipation is less than 1mW at a 10kHz data rate. The ADS8325 offers excellent linearity and very low noise and distortion. It also features a synchronous serial (SPI/SSI compatible) interface and a differential input. The reference voltage can be set to any level within the range of 2.5V to VDD. Low power and small size make the ADS8325 ideal for portable and battery-operated systems. It is also a perfect fit for remote data acquisition modules, simultaneous multichannel systems, and isolated data acquisition. The ADS8325 is available in MSOP-8 and SON-8 packages. The SON package size is the same as a 3x3 QFN package. APPLICATIONS • • • • • • • Battery-Operated Systems Remote Data Acquisition Isolated Data Acquisition Simultaneous Sampling, Multi-Channel Systems Industrial Controls Robotics Vibration Analysis SAR REF ADS8325 DOUT +IN Serial Interface CDAC -IN DCLOCK S/H Amp Comparator CS/SHDN 1 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. SPI is a trademark of Motorola, Inc. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2002–2007, Texas Instruments Incorporated ADS8325 www.ti.com SBAS226C – MARCH 2002 – REVISED AUGUST 2007 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE/ORDERING INFORMATION (1) PRODUCT MAXIMUM INTEGRAL LINEARITY ERROR (LSB) NO MISSING CODES ERROR (LSB) (2) PACKAGELEAD PACKAGE DESIGNATOR SPECIFIED TEMPERATURE RANGE PACKAGE MARKING ADS8325I ±6 15 MSOP-8 DGK –40°C to +85°C B25 ADS8325IB ±4 ADS8325I ±6 ADS8325IB (1) (2) 16 MSOP-8 15 ±4 SON-8 16 SON-8 DGK –40°C to +85°C DRB –40°C to +85°C DRB –40°C to +85°C ORDERING NUMBER TRANSPORT MEDIA, QUANTITY ADS8325IDGKT Tape and Reel, 250 ADS8325IDGKR Tape and Reel, 2500 ADS8325IBDGKT Tape and Reel, 250 ADS8325IBDGKR Tape and Reel, 2500 B25 ADS8325IDRBT Tape and Reel, 250 ADS8325IDRBR Tape and Reel, 2500 B25 ADS8325IBDRBT Tape and Reel, 250 ADS8325IBDRBR Tape and Reel, 2500 B25 For the most current specifications and package information, refer to our web site at www.ti.com. No Missing Codes Error specifies a 5V power supply and reference voltage. ABSOLUTE MAXIMUM RATINGS (1) Over operating free-air temperature range (unless otherwise noted) Supply voltage, DGND to VDD –0.3 to 6 V –0.3 to VDD + 0.3 V Reference input voltage (2) –0.3 to VDD + 0.3 V Digital input voltage (2) –0.3 to VDD + 0.3 V –20 to 20 mA Power dissipation See Dissipation Rating Table –40 to +150 °C Operating free-air temperature range –40 to +85 °C Storage temperature range –65 to +150 °C +260 °C TJ Operating virtual junction temperature range TA TSTG Lead temperature 1,6 mm (1/16 inch) from case for 10 sec (2) UNIT Analog input voltage (2) Input current to any pin except supply (1) ADS8325 Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions of extended periods may affect device reliability. All voltage values are with respect to ground terminal. PACKAGE DISSIPATION RATINGS 2 PACKAGE RθJC RθJA DERATING FACTOR ABOVE TA = +25°C TA ≤ +25°C POWER RATING TA = +70°C POWER RATING TA = +85°C POWER RATING DGK 39.1°C/W 206.3°C/W 4.847mW/°C 606mW 388mW 315mW DRB 5°C/W 45.8°C/W 3.7mW/C 370mW 204mW 148mW Submit Documentation Feedback Copyright © 2002–2007, Texas Instruments Incorporated Product Folder Link(s): ADS8325 ADS8325 www.ti.com SBAS226C – MARCH 2002 – REVISED AUGUST 2007 EQUIVALENT INPUT CIRCUIT VDD VDD C(SAMPLE) 40pF RON 50W ANALOG IN VDD Shut-Down Switch 20pF I/O REF 5kW GND GND GND Diode Turn-On Voltage: 0.35V Equivalent Reference Equivalent Analog Input Circuit Input Circuit Equivalent Digital Input/Output Circuit RECOMMENDED OPERATING CONDITIONS Over operating free-air temperature range (unless otherwise noted) MIN Supply voltage, GND to VDD Low-voltage levels 2.7 5V logic levels 4.5 Reference input voltage 5.0 2.5 –IN Analog input voltage TJ TYP –0.3 +IN – (–IN) Operating junction temperature range 0 MAX UNIT 3.6 V 5.5 V VDD V 0.5 V 0 VREF V –40 +125 °C ELECTRICAL CHARACTERISTICS: VDD = +5 V Over recommended operating free-air temperature at –40°C to +85°C, VREF = 5V, –IN = GND, fSAMPLE = 100kHz, and fCLK = 24 × fSAMPLE, unless otherwise noted. ADS8325I PARAMETER TEST CONDITIONS MIN TYP ADS8325IB MAX MIN TYP MAX UNIT V ANALOG INPUT Full-scale range FSR +IN – (–IN) Operating common-mode signal Input resistance –IN = GND Input capacitance –IN = GND, during sampling Input leakage current –IN = GND Differential input capacitance Full-power bandwidth 0 VREF 0 VREF –0.3 0.5 –0.3 0.5 5 +IN to –IN, during sampling FSBW FS sinewave, SINAD = –3dB 5 V GΩ 45 45 pF ±50 ±50 nA 20 20 pF 20 20 kHz DC ACCURACY Resolution No missing code Integral linearity error Offset error Offset error drift Gain error Gain error drift NMC 16 16 15 16 Bits INL ±3 ±6 ±1.5 ±4 VOS ±0.75 ±1.5 ±0.5 ±1 TCVOS ±0.2 GERR ±0.2 ±24 TCGERR Noise Power-supply rejection Bits 4.75V ≤ VDD ≤ 5.25V LSB mV ppm/°C ±12 LSB ±3 ±3 ppm/°C 20 20 μVRMS 3 3 LSB SAMPLING DYNAMICS Conversion time Acquisition time tCONV 24kHz < fCLK ≤ 2.4MHz tAQ fCLK = 2.4MHz 6.667 1.875 Throughput rate Clock frequency 666.7 6.667 2.4 0.024 μs μs 1.875 100 0.024 666.7 100 kSPS 2.4 MHz AC ACCURACY Submit Documentation Feedback Copyright © 2002–2007, Texas Instruments Incorporated Product Folder Link(s): ADS8325 3 ADS8325 www.ti.com SBAS226C – MARCH 2002 – REVISED AUGUST 2007 ELECTRICAL CHARACTERISTICS: VDD = +5 V (continued) Over recommended operating free-air temperature at –40°C to +85°C, VREF = 5V, –IN = GND, fSAMPLE = 100kHz, and fCLK = 24 × fSAMPLE, unless otherwise noted. ADS8325I PARAMETER Total harmonic distortion Spurious-free dynamic range Signal-to-noise ratio TEST CONDITIONS MIN ADS8325IB TYP MAX MIN TYP MAX UNIT THD 5VPP sinewave, at 1kHz –100 –106 dB SFDR 5VPP sinewave, at 1kHz –100 –108 dB dB –90 –91 Signal-to-noise + distortion SINAD 5VPP sinewave, at 1kHz SNR –90 –91 dB Effective number of bits ENOB 14.6 14.7 Bits VOLTAGE REFERENCE INPUT Reference voltage 2.5 Reference input resistance VDD + 0.3 V 5 kΩ CS = VDD 5 5 GΩ 20 20 pF 1 Reference input current 2.5 5 Reference input capacitance DIGITAL INPUTS VDD + 0.3 CS = GND, fSAMPLE = 0Hz CS = VDD 1.5 1 0.1 1.5 mA μA 0.1 (1) Logic family CMOS CMOS High-level input voltage VIH 0.7 × VDD VDD + 0.3 0.7 × VDD VDD + 0.3 Low-level input voltage VIL –0.3 0.3 × VDD –0.3 0.3 × VDD V Input current IIN VI = VDD or GND ±50 nA Input capacitance CI ±50 5 5 V pF DIGITAL OUTPUTS (1) Logic family CMOS High-level output voltage VOH VDD = 4.5V, IOH = –100μA Low-level output voltage VOL VDD = 4.5V, IOL = 100μA High-impedance-state output current IOZ CS = VDD, VI = VDD or GND Output capacitance CO Load capacitance CL Data format (1) 4 CMOS 4.44 4.44 V 0.5 0.5 V ±50 ±50 nA 5 5 30 Straight Binary pF 30 pF Straight Binary Applies for 5.0V nominal supply: VDD (min) = 4.5V and VDD (max) = 5.5V. Submit Documentation Feedback Copyright © 2002–2007, Texas Instruments Incorporated Product Folder Link(s): ADS8325 ADS8325 www.ti.com SBAS226C – MARCH 2002 – REVISED AUGUST 2007 ELECTRICAL CHARACTERISTICS: VDD = +2.7V Over recommended operating free-air temperature at –40°C to +85°C, VREF = +2.5V, –IN = GND, fSAMPLE = 100kHz, and fCLK = 24 × fSAMPLE, unless otherwise noted. ADS8325I PARAMETER TEST CONDITIONS MIN TYP ADS8325IB MAX MIN VREF 0 0.5 –0.3 TYP MAX UNIT VREF V ANALOG INPUT Full-scale range FSR +IN – (–IN) 0 Operating common-mode signal –0.3 Input resistance –IN = GND Input capacitance –IN = GND, during sampling Input leakage current –IN = GND Differential input capacitance 5 +IN to –IN, during sampling Full-power bandwidth FSBW FS sinewave, SINAD = –3 dB 0.5 5 V GΩ 45 45 pF ±50 ±50 nA 20 20 pF 4 4 kHz DC ACCURACY Resolution No missing code NMC Integral linearity error Offset error Offset error drift Gain error Gain error drift 16 16 14 15 Bits Bits INL ±3 ±6 ±1.5 ±4 VOS ±0.75 ±1.5 ±0.5 ±1 TCVOS ±3 ±3 LSB mV ppm/°C GERR ±33 ±16 LSB TCGERR ±0.3 ±0.3 ppm/°C 20 20 μVRMS 7 7 LSB Noise 2.7V ≤ VDD ≤ 3.6V Power-supply rejection SAMPLING DYNAMICS Conversion time Acquisition time tCONV 24kHz < fCLK ≤ 2.4MHz tAQ fCLK = 2.4MHz 6.667 666.7 1.875 6.667 666.7 Throughput rate 100 Clock frequency 0.024 2.4 μs μs 1.875 0.024 100 kSPS 2.4 MHz AC ACCURACY Total harmonic distortion Spurious-free dynamic range Signal-to-noise ratio THD 2.5VPP sinewave, at 1kHz –94 –94 dB SFDR 2.5VPP sinewave, at 1kHz –96 –96 dB –85 –86 dB SNR Signal-to-noise + distortion SINAD 2.5VPP sinewave, at 1kHz –85 –85.5 dB Effective number of bits ENOB 13.8 13.9 Bits VOLTAGE REFERENCE INPUT Reference voltage 2.5 VDD + 0.3 CS = GND, fSAMPLE = 0Hz Reference input resistance CS = VDD Reference input capacitance CS = VDD VDD + 0.3 V 5 kΩ 5 5 GΩ 20 20 0.5 Reference input current 2.5 5 0.75 0.5 0.1 pF 0.75 mA μA 0.1 DIGITAL INPUTS (1) Logic family LVCMOS LVCMOS High-level input voltage VIH VDD = 3.6V 2 VDD + 0.3 2 VDD + 0.3 Low-level input voltage VIL VDD = 2.7V –0.3 0.8 –0.3 0.8 V Input current IIN VI = VDD or GND ±50 nA Input capacitance CI (1) ±50 5 5 V pF Applies for 3.0V nominal supply: VDD (min) = 2.7V and VDD (max) = 3.6V. Submit Documentation Feedback Copyright © 2002–2007, Texas Instruments Incorporated Product Folder Link(s): ADS8325 5 ADS8325 www.ti.com SBAS226C – MARCH 2002 – REVISED AUGUST 2007 ELECTRICAL CHARACTERISTICS: VDD = +2.7V (continued) Over recommended operating free-air temperature at –40°C to +85°C, VREF = +2.5V, –IN = GND, fSAMPLE = 100kHz, and fCLK = 24 × fSAMPLE, unless otherwise noted. ADS8325I PARAMETER TEST CONDITIONS MIN High-level output voltage VOH VDD = 2.7V, IOH = –100μA VDD – 0.2 Low-level output voltage VOL VDD = 2.7V, IOL = 100μA ADS8325IB TYP MAX MIN TYP MAX UNIT DIGITAL OUTPUTS (2) Logic family LVCMOS High-impedance-state output current IOZ CS = VDD, VI = VDD or GND Output capacitance CO Load capacitance CL V 0.2 ±50 ±50 5 0.2 V ±50 nA 5 pF 30 Data format (2) LVCMOS VDD – 0.2 30 Straight Binary pF Straight Binary Applies for 3.0V nominal supply: VDD (min) = 2.7V and VDD (max) = 3.6V. ELECTRICAL CHARACTERISTICS Over recommended operating free-air temperature at –40°C to +85°C, VREF = VDD, –IN = GND, fSAMPLE = 100kHz, and fCLK = 24 × fSAMPLE, unless otherwise noted. ADS8325I PARAMETER TEST CONDITIONS MIN TYP ADS8325IB MAX MIN TYP MAX UNIT POWER-SUPPLY REQUIREMENTS Power supply Operating supply current Power-down supply current Power dissipation Power dissipation in power-down 6 VDD IDD (IDD Low-voltage levels 2.7 3.6 2.7 3.6 5V logic levels 4.5 5.5 4.5 5.5 V V VDD = 3V 0.75 1.5 0.75 1.5 mA VDD = 5V 0.9 1.5 0.9 1.5 mA VDD = 3V 0.1 0.1 VDD = 5V 0.2 0.2 VDD = 3V 2.25 4.5 2.25 4.5 mW VDD = 5V 4.5 7.5 4.5 7.5 mW VDD = 3V, CS = VDD 0.3 0.3 μW VDD = 5V, CS = VDD 0.6 0.6 μW Submit Documentation Feedback μA μA Copyright © 2002–2007, Texas Instruments Incorporated Product Folder Link(s): ADS8325 ADS8325 www.ti.com SBAS226C – MARCH 2002 – REVISED AUGUST 2007 PIN CONFIGURATIONS DGK PACKAGE MSOP (TOP VIEW) REF 1 +IN 2 8 +VDD 7 DCLOCK ADS8325 -IN 3 6 DOUT GND 4 5 CS/SHDN DRB PACKAGE(1) SON (TOP VIEW) REF 1 +IN 2 8 +VDD 7 DCLOCK 6 DOUT 5 CS/SHDN ADS8325 (1) -IN 3 GND 4 (Thermal Pad) The thermal pad is internally connected to the substrate. This pad can be connected to the analog ground or left floating. Keep the thermal pad separate from the digital ground, if possible. PIN ASSIGNMENTS PIN NO. I/O (1) DESCRIPTION REF 1 AI Reference Input +IN 2 AI Noninverting Input –IN 3 AI Inverting Analog Input GND 4 P Ground CS/SHDN 5 DI Chip select when low; Shutdown mode when high. DOUT 6 DO The serial output data word. DCLOCK 7 DI Data clock synchronizes the serial data transfer and determines conversion speed. +VDD 8 P Power supply NAME (1) AI is Analog Input, DI is Digital Input, DO is Digital Output, and P is Power-Supply Connection. Submit Documentation Feedback Copyright © 2002–2007, Texas Instruments Incorporated Product Folder Link(s): ADS8325 7 ADS8325 www.ti.com SBAS226C – MARCH 2002 – REVISED AUGUST 2007 TIMING INFORMATION tCYC CS/SHDN Sample Power Down Conversion tSUCS DCLOCK tCSD Use positive clock edge for data transfer Hi-Z DOUT 0 tSMPL B7 B15 B14 B13 B12 B11 B10 B9 B8 (MSB) tCONV B6 B5 B4 B3 B2 Hi-Z (1) B1 B0 (LSB) NOTE: (1) A minimum of 22 clock cycles are required for 16-bit conversion; 24 clock cycles are shown. If CS remains low at the end of conversion, a new data stream is shifted out with LSB-first data followed by zeroes indefinitely. tCYC CS/SHDN tSUCS Power Down DCLOCK tCSD Hi-Z DOUT 0 B15 B14 B6 (MSB) tSMPL B5 B4 B3 tCONV B2 B1 B0 B1 (LSB) B2 B3 B4 B5 B0 (2) Hi-Z B11 B12 B13 B14 B15 (MSB) NOTE: (2) After completing the data transfer, if further clocks are applied with CS low, the A/D converter will output zeroes indefinitely. 1.4V 3kW DOUT 90% DOUT 10% Test Point tr 100pF CLOAD tf Voltage Waveforms for DOUT Rise and Fall Times, tr, tf Load Circuit for tdDO, tr, and tf Test Point DCLOCK VDD DOUT tdDO tdis Waveform 2, ten 3kW tdis Waveform 1 100pF CLOAD DOUT thDO Load Circuit for tdis and ten Voltage Waveforms for DOUT Delay Times, tdDO 90% CS/SHDN DOUT Waveform 1(3) CS/SHDN 90% DCLOCK 1 4 5 tdis DOUT Waveform 2(4) 10% DOUT B15 ten Voltage Waveforms for tdis Voltage Waveforms for ten NOTES: (3) Waveform 1 is for an output with internal conditions such that the output is high unless disabled by the output control. (4) Waveform 2 is for an output with internal conditions such that the output is low unless disabled by the output control. Figure 1. Timing Diagrams and Test Circuits for the Paramters in Table 1 8 Submit Documentation Feedback Copyright © 2002–2007, Texas Instruments Incorporated Product Folder Link(s): ADS8325 ADS8325 www.ti.com SBAS226C – MARCH 2002 – REVISED AUGUST 2007 TIMING INFORMATION (continued) Table 1. Timing Characteristics SYMBOL DESCRIPTION MIN TYP 4.5 MAX 5.0 UNIT tSMPL Analog Input Sample Time tCONV Conversion Time tCYC Throughput Rate tCSD CS Falling to DCLOCK LOW tSUCS CS Falling to DCLOCK Rising tHDO DCLOCK Falling to Current DOUT Not Valid tDIS CS Rising to DOUT 3-State 70 100 ns tEN DCLOCK Falling to DOUT Enabled 20 50 ns tF DOUT Fall Time 5 25 ns tR DOUT Rise Time 7 25 ns 16 Clk Cycles Clk Cycles 100 0 20 5 Product Folder Link(s): ADS8325 ns ns 15 ns Submit Documentation Feedback Copyright © 2002–2007, Texas Instruments Incorporated kHz 9 ADS8325 www.ti.com SBAS226C – MARCH 2002 – REVISED AUGUST 2007 TYPICAL CHARACTERISTICS: VDD = +5V At TA = +25°C, VDD = +5V, VREF = +5V, fSAMPLE = 100kHz, fCLK = 24 × fSAMPLE, unless otherwise noted. 3 3 2 2 1 1 0 -1 -2 -2 4000H 8000H C000H -3 0000H FFFFH 4000H C000H FFFFH Output Code Figure 2. Figure 3. FREQUENCY SPECTRUM (8192 Point FFT, fIN = 1.0132kHz, –0.2 dB) FREQUENCY SPECTRUM (8192 Point FFT, fIN = 10.0022kHz, –0.2 dB) 0 -20 -20 -40 -40 Amplitude (dB) 0 -60 -80 -100 -60 -80 -100 -120 -120 -140 -140 -160 10 20 30 40 50 0 10 20 30 40 50 Frequency (kHz) Frequency (kHz) Figure 4. Figure 5. SIGNAL-TO-NOISE RATIO AND SIGNAL-TO-NOISE + DISTORTION vs INPUT FREQUENCY SPURIOUS-FREE DYNAMIC RANGE AND TOTAL HARMONIC DISTORTION vs INPUT FREQUENCY 105 110 100 -110 SFDR 105 SNR -105 100 -100 90 95 -95 90 -90 85 -85 SFDR (dB) 95 85 80 THD (dB) 0 SINAD 75 80 70 NOTE: (1) First nine harmonics of the input frequency. 75 65 THD -80 (1) -75 70 1 10 100 245 1 Frequency (kHz) 10 100 -70 245 Frequency (kHz) Figure 6. 10 8000H Output Code -160 SNR and SINAD (dB) 0 -1 -3 0000H Amplitude (dB) DIFFERENTIAL LINEARITY ERROR vs CODE DLE (LSBS) ILE (LSBS) INTEGRAL LINEARITY ERROR vs CODE Figure 7. Submit Documentation Feedback Copyright © 2002–2007, Texas Instruments Incorporated Product Folder Link(s): ADS8325 ADS8325 www.ti.com SBAS226C – MARCH 2002 – REVISED AUGUST 2007 TYPICAL CHARACTERISTICS: VDD = +5V (continued) At TA = +25°C, VDD = +5V, VREF = +5V, fSAMPLE = 100kHz, fCLK = 24 × fSAMPLE, unless otherwise noted. SIGNAL-TO-NOISE + DISTORTION vs INPUT LEVEL PEAK-TO-PEAK NOISE FOR A DC INPUT vs REFERENCE VOLTAGE 200 fIN = 1.0132kHz 90 100 Peak-to-Peak Noise (LSB) Signal-to-Noise + Distortion (dB) 100 80 70 60 50 40 30 10 20 10 1 -80 -70 -60 -50 -40 -30 -20 -10 0.1 0 Figure 8. Figure 9. EFFECTIVE NUMBER OF BITS vs INPUT FREQUENCY CHANGE IN SIGNAL-TO-NOISE + DISTORTION vs TEMPERATURE 0.4 15.0 fIN = 1.0132kHz, -0.2dB 0.2 14.0 Delta from +25°C (dB) Effective Number of Bits 14.5 13.5 13.0 12.5 12.0 0.0 -0.2 -0.4 -0.6 11.5 11.0 1 10 -0.8 -50 100 -25 0 Frequency (kHz) 25 50 75 100 75 100 Temperature (°C) Figure 10. Figure 11. CHANGE IN GAIN vs TEMPERATURE CHANGE IN UPO vs TEMPERATURE 2.0 3.0 1.5 2.5 Delta from 25°C (LSBS) Delta from 25°C (LSBS) 5 1 Reference Voltage (V) Input Level (dB) 1.0 0.5 0.0 -0.5 -1.0 2.0 1.5 1.0 0.5 0.0 -0.5 -1.5 -50 -25 0 25 50 75 100 -1.0 -50 -25 0 25 50 Temperature (°C) Temperature (°C) Figure 12. Figure 13. Submit Documentation Feedback Copyright © 2002–2007, Texas Instruments Incorporated Product Folder Link(s): ADS8325 11 ADS8325 www.ti.com SBAS226C – MARCH 2002 – REVISED AUGUST 2007 TYPICAL CHARACTERISTICS: VDD = +5V (continued) At TA = +25°C, VDD = +5V, VREF = +5V, fSAMPLE = 100kHz, fCLK = 24 × fSAMPLE, unless otherwise noted. SUPPLY CURRENT vs TEMPERATURE Supply Current (mA) 1.1 1.0 0.9 0.8 0.7 -50 -25 0 25 50 75 100 Temperature (°C) 12 Submit Documentation Feedback Copyright © 2002–2007, Texas Instruments Incorporated Product Folder Link(s): ADS8325 ADS8325 www.ti.com SBAS226C – MARCH 2002 – REVISED AUGUST 2007 TYPICAL CHARACTERISTICS: VDD = +2.7V At TA = +25°C, VDD = 2.7V, VREF = 2.5V, fSAMPLE = 100kHz, fCLK = 24 × fSAMPLE, unless otherwise noted. DIFFERENTIAL LINEARITY ERROR vs CODE 3 3 2 2 1 1 DLE (LSBS) 0 0 -1 -1 -2 -2 -3 0000H 4000H 8000H C000H -3 0000H FFFFH 4000H 8000H FFFFH Figure 15. Figure 16. FREQUENCY SPECTRUM (8192 Point FFT, fIN = 1.0132kHz, –0.2 dB) FREQUENCY SPECTRUM (8192 Point FFT, fIN = 10.0022kHz, –0.2 dB) 0 0 -20 -20 -40 -40 -60 -80 -100 -60 -80 -100 -120 -120 -140 -140 -160 -160 0 10 20 30 40 50 0 10 20 30 40 50 Frequency (kHz) Frequency (kHz) Figure 17. Figure 18. SIGNAL-TO-NOISE RATIO AND SIGNAL-TO-NOISE + DISTORTION vs INPUT FREQUENCY SPURIOUS-FREE DYNAMIC RANGE AND TOTAL HARMONIC DISTORTION vs INPUT FREQUENCY 95 SNR 85 SFDR (dB) SNR and SINAD (dB) C000H Output Code Amplitude (dB) Amplitude (dB) Output Code 75 65 100 -100 90 -90 SFDR 80 -80 70 -70 60 55 SINAD -60 NOTE: (1) First nine harmonics of the input frequency. 50 THD (1) -50 40 45 1 10 100 245 THD (dB) ILE (LSBS) INTEGRAL LINEARITY ERROR vs CODE -40 1 Frequency (kHz) 10 100 245 Frequency (kHz) Figure 19. Figure 20. Submit Documentation Feedback Copyright © 2002–2007, Texas Instruments Incorporated Product Folder Link(s): ADS8325 13 ADS8325 www.ti.com SBAS226C – MARCH 2002 – REVISED AUGUST 2007 TYPICAL CHARACTERISTICS: VDD = +2.7V (continued) At TA = +25°C, VDD = 2.7V, VREF = 2.5V, fSAMPLE = 100kHz, fCLK = 24 × fSAMPLE, unless otherwise noted. SIGNAL-TO-NOISE + DISTORTION vs INPUT LEVEL EFFECTIVE NUMBER OF BITS vs INPUT FREQUENCY fIN = 1.0132kHz 90 80 Effective Number of Bits Signal-to-Noise + Distortion (dB) 100 70 60 50 40 30 20 10 -80 -70 -60 -50 -40 -30 -20 1 0 -10 10 100 Input Level (dB) Frequency (kHz) Figure 21. Figure 22. CHANGE IN SIGNAL-TO-NOISE + DISTORTION vs TEMPERATURE CHANGE IN GAIN vs TEMPERATURE 0.4 2.0 fIN = 1.0132kHz, -0.2dB 1.5 Delta from 25°C (LSBS) 0.2 Delta from +25°C (dB) 14.5 14.0 13.5 13.0 12.5 12.0 11.5 11.0 10.5 10.0 9.5 9.0 8.5 8.0 7.5 7.0 0.0 -0.2 -0.4 1.0 0.5 0.0 -0.5 -1.0 -0.6 -1.5 -0.8 -2.0 -50 -25 0 25 50 75 100 -50 25 50 Figure 23. Figure 24. CHANGE IN UPO vs TEMPERATURE SUPPLY CURRENT vs TEMPERATURE 75 100 75 100 0.9 0.8 Supply Current (mA) Delta from 25°C (LSBS) 0 Temperature (°C) 1.2 0.4 0.0 0.8 0.7 -0.4 -0.8 -50 0.6 -25 0 25 50 75 100 -50 -25 0 25 50 Temperature (°C) Temperature (°C) 14 -25 Temperature (°C) Submit Documentation Feedback Copyright © 2002–2007, Texas Instruments Incorporated Product Folder Link(s): ADS8325 ADS8325 www.ti.com SBAS226C – MARCH 2002 – REVISED AUGUST 2007 THEORY OF OPERATION ANALOG INPUT The ADS8325 is a classic Successive Approximation Register (SAR) Analog-to-Digital (A/D) converter. The architecture is based on capacitive redistribution that inherently includes a sample-andhold function. The converter is fabricated on a 0.6μ CMOS process. The architecture and process allow the ADS8325 to acquire and convert an analog signal at up to 100,000 conversions per second while consuming less than 4.5mW from +VDD. The analog input of ADS8325 is differential. The +IN and –IN input pins allow for a differential input signal. The amplitude of the input is the difference between the +IN and –IN input, or (+IN) – (–IN). Unlike some converters of this type, the –IN input is not resampled later in the conversion cycle. When the converter goes into the hold mode or conversion, the voltage difference between +IN and –IN is captured on the internal capacitor array. The ADS8325 requires an external reference, an external clock, and a single power source (VDD). The external reference can be any voltage between 2.5V and 5.5V. The value of the reference voltage directly sets the range of the analog input. The reference input current depends on the conversion rate of the ADS8325. The range of the –IN input is limited to –0.3V to +0.5V. Due to this, the differential input could be used to reject signals that are common to both inputs in the specified range. Thus, the –IN input is best used to sense a remote signal ground that may move slightly with respect to the local ground potential. The general method for driving the analog input of the ADS8325 is shown in Figure 26 and Figure 27. The –IN input is held at the common-mode voltage. The +IN input swings from –IN (or common-mode voltage) to –IN + VREF (or commonmode voltage + VREF), and the peak-to-peak amplitude is +VREF. The value of VREF determines the range over which the common-mode voltage may vary (see Figure 28). Figure 29 and Figure 30 illustrate the typical change in gain and offset as a function of the common-mode voltage applied to the –IN pin. The external clock can vary between 24kHz (1kHz throughput) and 2.4MHz (100kHz throughput). The duty cycle of the clock is essentially unimportant as long as the minimum high and low times are at least 200ns (VDD = 4.75V or greater). The minimum clock frequency is set by the leakage on the internal capacitors to the ADS8325. The analog input is provided to two input pins: +IN and –IN. When a conversion is initiated, the differential input on these pins is sampled on the internal capacitor array. While a conversion is in progress, both inputs are disconnected from any internal function. 0V to +VREF Peak-to-Peak The digital result of the conversion is clocked out by the DCLOCK input and is provided serially, most significant bit first, on the DOUT pin. The digital data that is provided on the DOUT pin is for the conversion currently in progress—there is no pipeline delay. It is possible to continue to clock the ADS8325 after the conversion is complete and to obtain the serial data least significant bit first. See the Timing Information section for more information. ADS8325 Common-Mode Voltage Figure 26. Methods of Driving the ADS8325 +IN Common-Mode Voltage + VREF +VREF t Common-Mode Voltage -IN = Common-Mode Voltage NOTE: The maximum differential voltage between +IN and –IN of the ADS8325 is VREF. See Figure 28 for a further explanation of the common-mode voltage range for differential inputs. Figure 27. Differential Input Mode of the ADS8325 Submit Documentation Feedback Copyright © 2002–2007, Texas Instruments Incorporated Product Folder Link(s): ADS8325 15 ADS8325 www.ti.com Common-Mode Voltage Range (V) SBAS226C – MARCH 2002 – REVISED AUGUST 2007 1 VDD = 5V 0.5 0 -0.3 -1 2 2.5 3 4 6 4.8 5 VREF (V) Figure 28. +IN Analog Input: Common-Mode Voltage Range vs VREF Delta Relative to VCM = 0V (LSB) 60 50 VDD = 5V VREF = 4V Care must be taken regarding the absolute analog input voltage. To maintain the linearity of the converter, the –IN input should not drop below GND – 0.3V or exceed GND + 0.5V. The +IN input should always remain within the range of GND – 0.3V to VDD + 0.3V, or –IN to –IN + VREF, whichever limit is reached first. Outside of these ranges, the converter's linearity may not meet specifications. To minimize noise, low bandwidth input signals with lowpass filters should be used. In each case, care should be taken to ensure that the output impedance of the sources driving the +IN and –IN inputs are matched. Often, a small capacitor (20pF) between the positive and negative inputs helps to match their impedance. To obtain maximum performance from the ADS8325, the input circuit from Figure 31 is recommended. 40 30 20 10 0 -10 -0.4 -0.3 -0.2 -0.1 0.0 The input current required by the analog inputs depends on a number of factors: sample rate, input voltage, source impedance, and power-down mode. Essentially, the current into the ADS8325 charges the internal capacitor array during the sample period. After this capacitance has been fully charged, there is no further input current. The source of the analog input voltage must be able to charge the input capacitance (40pF) to a 16-bit settling level within 4.5 clock cycles (1.875μs). When the converter goes into the hold mode, or while it is in the power-down mode, the input impedance is greater than 1GΩ. 0.1 0.2 0.3 0.4 0.5 0.6 0.7 VCM (V) Figure 29. Change in Gain vs Common-Mode Voltage CHANGE IN UPO vs COMMON-MODE VOLTAGE Delta Relative to VCM = 0V (LSBS) 30 VDD = 5V VREF = 4V 20 10 0 -10 -20 -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 VCM (V) Figure 30. Change in Unipolar Offset vs Common-Mode Voltage 16 Submit Documentation Feedback Copyright © 2002–2007, Texas Instruments Incorporated Product Folder Link(s): ADS8325 ADS8325 www.ti.com SBAS226C – MARCH 2002 – REVISED AUGUST 2007 50W 50W 40pF +IN OPA365 50W 100pF 50W 40pF +IN OPA365 100pF ADS8325 -IN ADS8325 1nF 50W 40pF 50W -IN OPA365 50W 40pF 100pF Single-Ended Differential Figure 31. Single-Ended and Differential Methods of Interfacing the ADS8325 The external reference sets the analog input range. The ADS8325 will operate with a reference in the range of 2.5V to VDD. There are several important implications to this. As the reference voltage is reduced, the analog voltage weight of each digital output code is reduced. This is often referred to as the Least Significant Bit (LSB) size and is equal to the reference voltage divided by 65,536. This means that any offset or gain error inherent in the A/D converter will appear to increase, in terms of LSB size, as the reference voltage is reduced. For a reference voltage of 2.5V, the value of LSB is 38.15μV, and for reference voltage of 5V, the LSB is 76.3μV. The noise inherent in the converter will also appear to increase with lower LSB size. With a 5V reference, the internal noise of the converter typically contributes only 1.5LSBs peak-to-peak of potential error to the output code. When the external reference is 2.5V, the potential error contribution from the internal noise will be 2 times larger (3LSBs). The errors due to the internal noise are Gaussian in nature and can be reduced by averaging consecutive conversion results. For more information regarding noise, consult Figure 9, Peak-to-Peak Noise vs Reference Voltage. Note that Figure 10, Effective Number Of Bits vs Input Frequency, is calculated based on the converter’s signal-to-(noise + distortion) ratio with a 1kHz, 0dB input signal. SINAD is related to ENOB as follows: SINAD = 6.02 × ENOB + 1.76 As the difference between the power-supply voltage and reference voltage increases, the gain and offset performance of the converter will decrease. Figure 32 shows the typical change in gain and offset as a function of the difference between the power-supply voltage and reference voltage. For the combination of VDD = 2.7V and VREF = 2.5V, or VDD = 5V and VREF = 5V, offset and gain error will be minimal. The most dramatic difference in offset can be seen when VDD = 5V and VREF = 2.5V. CHANGE IN OFFSET AND GAIN vs SUPPLY/REFERENCE DIFFERENTIAL 3.0 2.5 2.0 Delta (mV) REFERENCE INPUT Offset 1.5 1.0 Gain 0.5 0 -0.5 0 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 2.75 VDD to VREF (V) Figure 32. Change in Offset and Gain vs the Difference Between Power-Supply and Reference Voltage Submit Documentation Feedback Copyright © 2002–2007, Texas Instruments Incorporated Product Folder Link(s): ADS8325 17 ADS8325 www.ti.com SBAS226C – MARCH 2002 – REVISED AUGUST 2007 With lower reference voltages, extra care should be taken to provide a clean layout including adequate bypassing, a clean power supply, a low-noise reference, and a low-noise input signal. Due to the lower LSB size, the converter will also be more sensitive to external sources of error, such as nearby digital signals and electromagnetic interference. The equivalent input circuit for the reference voltage is presented in Figure 33. The 5kΩ resistor presents a constant load during the conversion process. At the same time, an equivalent capacitor of 20pF is switched. To obtain optimum performance from the ADS8325, special care must be taken in designing the interface circuit to the reference input pin. To ensure a stable reference voltage, a 47μF tantalum capacitor with low ESR should be connected as close as possible to the input pin. If a high output impedance reference source is used, an additional operational amplifier with a current limiting resistor must be placed in front of the capacitors. dividing the number of codes measured by 6 and this will yield the ±3σ distribution, or 99.7%, of all codes. Statistically, up to three codes could fall outside the distribution when executing 1000 conversions. The ADS8325, with < 3 output codes for the ±3σ distribution, will yield a < ±0.5LSBs of transition noise. Remember, to achieve this low-noise performance, the peak-to-peak noise of the input signal and reference must be < 50μV. 4005 VDD = 5.0V VREF = 5.0V 519 ADS8325 7FFD 100W 476 0 0 7FFE 7FFF 8000 8001 20pF VREF Code OPA340 47mF 5kW Figure 33. Input Reference Circuit and its Interface Figure 34. 5000 Conversion Histogram of a DC Input VDD = 2.7V VREF = 2.5V 3499 When the ADS8325 is in power-down mode, the input resistance of the reference pin will have a value of 5GΩ. Since the input capacitors must be recharged before the next conversion starts, an operational amplifier with good dynamic characteristics must be used to buffer the reference input. The transition noise of the ADS8325 itself is extremely low (see Figure 34 and Figure 35); it is much lower than competing A/D converters. These histograms were generated by applying a low-noise DC input and initiating 5000 conversions. The digital output of the A/D converter will vary in output code due to the internal noise of the ADS8325. This is true for all 16-bit, SAR-type A/D converters. Using a histogram to plot the output codes, the distribution should appear bell-shaped with the peak of the bell curve representing the nominal code for the input value. The ±1σ, ±2σ, and ±3σ distributions will represent the 68.3%, 95.5%, and 99.7%, respectively, of all codes. The transition noise can be calculated by 18 683 649 NOISE 90 7FFD 79 7FFE 7FFF 8000 8001 Code Figure 35. 5000 Conversion Histogram of a DC Input Submit Documentation Feedback Copyright © 2002–2007, Texas Instruments Incorporated Product Folder Link(s): ADS8325 ADS8325 www.ti.com SBAS226C – MARCH 2002 – REVISED AUGUST 2007 AVERAGING SERIAL INTERFACE The noise of the A/D converter can be compensated by averaging the digital codes. By averaging conversion results, transition noise will be reduced by a factor of 1/√n, where n is the number of averages. For example, averaging four conversion results will reduce the transition noise from ±0.5LSB to ±0.25LSB. Averaging should only be used for input signals with frequencies near DC. The ADS8325 communicates with microprocessors and other digital systems via a synchronous 3-wire serial interface, as illustrated in the Timing Information section. The DCLOCK signal synchronizes the data transfer with each bit being transmitted on the falling edge of DCLOCK. Most receiving systems will capture the bitstream on the rising edge of DCLOCK. However, if the minimum hold time for DOUT is acceptable, the system can use the falling edge of DCLOCK to capture each bit. For AC signals, a digital filter can be used to low-pass filter and decimate the output codes. This works in a similar manner to averaging; for every decimation by 2, the signal-to-noise ratio will improve 3dB. DIGITAL INTERFACE SIGNAL LEVELS The ADS8325 has a wide range of power-supply voltage. The A/D converter, as well as the digital interface circuit, is designed to accept and operate from 2.7V up to 5.5V. This voltage range will accommodate different logic levels. When the ADS8325's power-supply voltage is in the range of 4.5V to 5.5V (5V logic level), the ADS8325 can be connected directly to another 5V CMOS integrated circuit. Another possibility is that the ADS8325's power-supply voltage is in the range of 2.7V to 3.6V. The ADS8325 can be connected directly to another 3.3V LVCMOS integrated circuit. A falling CS signal initiates the conversion and data transfer. The first 4.5 to 5.0 clock periods of the conversion cycle are used to sample the input signal. After the fifth falling DCLOCK edge, DOUT is enabled and will output a LOW value for one clock period. For the next 16 DCLOCK periods, DOUT will output the conversion result, most significant bit first. After the least significant bit (B0) has been output, subsequent clocks will repeat the output data, but in a least significant bit first format. After the most significant bit (B15) has been repeated, DOUT will tri-state. Subsequent clocks will have no effect on the converter. A new conversion is initiated only when CS has been taken HIGH and returned LOW. DATA FORMAT The output data from the ADS8325 is in Straight Binary format (see Figure 36. This figure represents the ideal output code for a given input voltage and does not include the effects of offset, gain error, or noise. Submit Documentation Feedback Copyright © 2002–2007, Texas Instruments Incorporated Product Folder Link(s): ADS8325 19 ADS8325 www.ti.com SBAS226C – MARCH 2002 – REVISED AUGUST 2007 1111 1111 1111 1111 65535 1111 1111 1111 1111 65534 1111 1111 1111 1111 65533 1000 0000 0000 0001 32769 1000 0000 0000 0000 32768 Step Digital Output Code Straight Binary 32767 0111 1111 1111 1111 0000 0000 0000 0010 2 0000 0000 0000 0001 1 0000 0000 0000 0000 0 2.499962V VZ = VCM = 0V 2.500038V VFS = VCM + VREF = 5V 38.15mV VFS - 1LSB = 4.999924V VMS = VCM + VREF/2 = 2.5V 76.29mV 4.999847V Unipolar Analog Input Voltage 1LSB = 76.29mV 152.58mV VCM = 0V VREF = 5V 16-BIT Zero Code Midscale Code Full-Scale Code Straight Binary Output VZ = 0000H VMS = 8000H VFS = FFFFH Unipolar Analog Input VCODE = VCM VCODE = VCM + VREF/2 VCODE = (VCM + VREF) - 1LSB Figure 36. Ideal Conversion Characteristics (Condition: VCM = 0V, VREF = 5V) 20 Submit Documentation Feedback Copyright © 2002–2007, Texas Instruments Incorporated Product Folder Link(s): ADS8325 ADS8325 www.ti.com SBAS226C – MARCH 2002 – REVISED AUGUST 2007 POWER DISSIPATION In addition, the ADS8325 is in power-down mode under two conditions: when the conversion is complete and whenever CS is HIGH (see the Timing Information section). Ideally, each conversion should occur as quickly as possible, preferably at a 2.4MHz clock rate. This way, the converter spends the longest possible time in the power-down mode. This is very important as the converter not only uses power on each DCLOCK transition (as is typical for digital CMOS components), but also uses some current for the analog circuitry, such as the comparator. The analog section dissipates power continuously until the power-down mode is entered. See Figure 37 and Figure 38 for the current consumption of the ADS8325 versus sample rate. For these graphs, the converter is clocked at 2.4MHz regardless of the sample rate. CS is held HIGH during the remaining sample period. There is an important distinction between the power-down mode that is entered after a conversion is complete and the full power-down mode that is enabled when CS is HIGH. CS LOW will shut down only the analog section. The digital section is completely shut down only when CS is HIGH. Thus, if CS is left LOW at the end of a conversion, and the converter is continually clocked, the power consumption will not be as low as when CS is HIGH. SHORT CYCLING Another way to save power is to utilize the CS signal to short cycle the conversion. Due to the ADS8325 placing the latest data bit on the DOUT line as it is generated, the converter can easily be short cycled. This term means that the conversion can be terminated at any time. For example, if only 14 bits of the conversion result are needed, then the conversion can be terminated (by pulling CS HIGH ) after the 14th bit has been clocked out. TA = 25°C VDD = 5.0V VREF = 5.0V FCLK = 2.4MHz Current (mA) The power dissipation of the ADS8325 scales directly with conversion rate. Therefore, the first step to achieving the lowest power dissipation is to find the lowest conversion rate that will satisfy the requirements of the system. 1000 IDD 100 IREF 10 1 10 100 Sample Rate (kHz) Figure 37. Power-Supply and Reference Current vs Sample Rate at VDD = 5V POWER SUPPLY AND REFERENCE CURRENT vs SAMPLE RATE 1000 TA = 25°C VDD = 2.7V VREF = 2.5V FCLK = 2.4MHz Current (mA) The architecture of the converter, the semiconductor fabrication process, and a careful design, allow the ADS8325 to convert at up to a 100kHz rate while requiring very little power. However, for the absolute lowest power dissipation, there are several things to keep in mind. POWER SUPPLY AND REFERENCE CURRENT vs SAMPLE RATE IDD 100 IREF 10 1 10 100 Sample Rate (kHz) Figure 38. Power-Supply and Reference Current vs Sample Rate at VDD = 2.7V This technique can be used to lower the power dissipation (or to increase the conversion rate) in those applications where an analog signal is being monitored until some condition becomes true. For example, if the signal is outside a predetermined range, the full 16-bit conversion result may not be needed. If so, the conversion can be terminated after the first n bits, where n might be as low as 3 or 4. This results in lower power dissipation in both the converter and the rest of the system as they spend more time in power-down mode. Submit Documentation Feedback Copyright © 2002–2007, Texas Instruments Incorporated Product Folder Link(s): ADS8325 21 ADS8325 www.ti.com SBAS226C – MARCH 2002 – REVISED AUGUST 2007 LAYOUT For optimum performance, care should be taken with the physical layout of the ADS8325 circuitry. This will be particularly true if the reference voltage is low and/or the conversion rate is high. At a 100kHz conversion rate, the ADS8325 makes a bit decision every 416ns. That is, for each subsequent bit decision, the digital output must be updated with the results of the last bit decision, the capacitor array appropriately switched and charged, and the input to the comparator settled to a 16-bit level all within one clock cycle.6 The basic SAR architecture is sensitive to spikes on the power supply, reference, and ground connections that occur just prior to latching the comparator output. Thus, during any single conversion for an n-bit SAR converter, there are n windows in which large external transient voltages can easily affect the conversion result. Such spikes might originate from switching power supplies, digital logic, and high-power devices, to name a few. This particular source of error can be very difficult to track down if the glitch is almost synchronous to the converter's DCLOCK signal as the phase difference between the two changes with time and temperature, causing sporadic misoperation. With this in mind, power to the ADS8325 should be clean and well-bypassed. A 0.1μF ceramic bypass capacitor should be placed as close as possible to the ADS8325 package. In addition, a 1μF to 10μF capacitor and a 5Ω or 10Ω series resistor may be used to low-pass filter a noisy supply. resistor can help in this case). Keep in mind that while the ADS8325 draws very little current from the reference on average, there are still instantaneous current demands placed on the external input and reference circuitry. Texas Instruments' OPA627 op amp provides optimum performance for buffering both the signal and reference inputs. For low-cost, low-voltage, single-supply applications, the OPA2350 or OPA2340 dual op amps are recommended. Also, keep in mind that the ADS8325 offers no inherent rejection of noise or voltage variation in regards to the reference input. This is of particular concern when the reference input is tied to the power supply. Any noise and ripple from the supply will appear directly in the digital results. While high-frequency noise can be filtered out as described in the previous paragraph, voltage variation due to the line frequency (50Hz or 60Hz) can be difficult to remove. The GND pin on the ADS8325 should be placed on a clean ground point. In many cases, this will be the analog ground. Avoid connecting the GND pin too close to the grounding point for a microprocessor, microcontroller, or digital signal processor. If needed, run a ground trace directly from the converter to the power-supply connection point. The ideal layout will include an analog ground plane for the converter and associated analog circuitry. The reference should be similarly bypassed with a 47μF capacitor. Again, a series resistor and large capacitor can be used to low-pass filter the reference voltage. If the reference voltage originates from an op amp, make sure that the op amp can drive the bypass capacitor without oscillation (the series 22 Submit Documentation Feedback Copyright © 2002–2007, Texas Instruments Incorporated Product Folder Link(s): ADS8325 ADS8325 www.ti.com SBAS226C – MARCH 2002 – REVISED AUGUST 2007 APPLICATION CIRCUITS high-frequency noise from the supply itself. The exact values should be picked such that the filter provides adequate rejection of noise. Operational amplifiers and voltage reference are connected to analog power supply, AVDD. Figure 39 shows a basic data acquisition system. The ADS8325 input range is connected to 2.5V or 4.096V. The 5Ω resistor and 1μF to 10μF capacitor filters the microcontroller noise on the supply, as well as any DVDD 2.7V to 3.6V 0.1mF AVDD 2.7V to 5V + 10mF 5W REF5025 IN REF OUT GND 0.47mF VDD 0.1mF 4.7mF + 10mF ADS8325 DSP 50W TMS320C6xx or TMS320C5xx or TMS320C2xx +IN OPA365 VCM + (0V to 2.5V) 100pF CS 1nF DOUT DCLOCK 50W GND -IN OPA365 VCM GND 100pF DVDD 4.5V to 5.5V 0.1mF AVDD 4.3V to 5.5V + 10mF 5W REF5040 IN 0.47mF REF OUT GND VDD 0.1mF 4.7mF + 10mF ADS8325 50W Microcontroller or DSP +IN OPA365 0V to 4.096V 100pF CS DOUT DCLOCK -IN GND GND Figure 39. Two Examples of a Basic Data Acquisition System Submit Documentation Feedback Copyright © 2002–2007, Texas Instruments Incorporated Product Folder Link(s): ADS8325 23 ADS8325 www.ti.com SBAS226C – MARCH 2002 – REVISED AUGUST 2007 Revision History Changes from Revision B (June 2007) to Revision C .................................................................................................... Page • • Changed note for DRB package............................................................................................................................................ 7 Changed second timing diagram from the top; moved Hi-Z to span the entire range of tSMPL ............................................. 8 Changes from Revision A (June 2003) to Revision B .................................................................................................... Page • • • • • • • • • • • • 24 Changed format of document to current standard look ......................................................................................................... 1 Changed RON and C(SAMPLE) values in Equivalent Input Circuit.............................................................................................. 3 Added missing value from Digital Inputs, Input Current, B Grade (typo)............................................................................... 3 Added missing values from Sampling Dynamics, B Grade (typo) ......................................................................................... 5 Changed DRB package pinout drawing to include thermal pad outline (not to scale) .......................................................... 7 Changed timing diagram (added new diagram to existing figures) ....................................................................................... 8 Added Peak-to-Peak Noise For a DC Input vs Reference Voltage plot ............................................................................. 11 Changed input capcitance from 20pF to 40pF (regarding the source of the analog input voltage) .................................... 16 Changed Figure 31 ............................................................................................................................................................. 17 Changed Figure 33 capacitor from 47F to 47μF (typo) ....................................................................................................... 18 Changed VFS from 7FFFH to FFFFH in Figure 36............................................................................................................... 20 Changed Figure 39 ............................................................................................................................................................. 23 Submit Documentation Feedback Copyright © 2002–2007, Texas Instruments Incorporated Product Folder Link(s): ADS8325 PACKAGE OPTION ADDENDUM www.ti.com 6-Aug-2007 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty ADS8325IBDGKR ACTIVE MSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS8325IBDGKRG4 ACTIVE MSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS8325IBDGKT ACTIVE MSOP DGK 8 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS8325IBDGKTG4 ACTIVE MSOP DGK 8 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS8325IBDRBR ACTIVE SON DRB 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS8325IBDRBRG4 ACTIVE SON DRB 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS8325IBDRBT ACTIVE SON DRB 8 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS8325IBDRBTG4 ACTIVE SON DRB 8 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS8325IDGKR ACTIVE MSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS8325IDGKT ACTIVE MSOP DGK 8 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS8325IDGKTG4 ACTIVE MSOP DGK 8 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS8325IDRBR ACTIVE SON DRB 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS8325IDRBRG4 ACTIVE SON DRB 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS8325IDRBT ACTIVE SON DRB 8 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS8325IDRBTG4 ACTIVE SON DRB 8 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 6-Aug-2007 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 6-Aug-2007 TAPE AND REEL INFORMATION Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com Device 6-Aug-2007 Package Pins Site Reel Diameter (mm) Reel Width (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant ADS8325IBDGKR DGK 8 MLA 330 12 5.2 3.3 1.6 12 12 NONE ADS8325IBDGKT DGK 8 MLA 330 12 5.2 3.3 1.6 12 12 NONE ADS8325IBDRBR DRB 8 TUA 330 12 3.3 3.3 1.1 8 12 Q2 ADS8325IBDRBT DRB 8 TUA 330 12 3.3 3.3 1.1 8 12 Q2 ADS8325IDGKR DGK 8 MLA 330 12 5.2 3.3 1.6 12 12 NONE ADS8325IDGKT DGK 8 MLA 330 12 5.2 3.3 1.6 12 12 NONE ADS8325IDRBR DRB 8 TUA 330 12 3.3 3.3 1.1 8 12 Q2 ADS8325IDRBT DRB 8 TUA 330 12 3.3 3.3 1.1 8 12 Q2 TAPE AND REEL BOX INFORMATION Device Package Pins Site Length (mm) Width (mm) Height (mm) ADS8325IBDGKR DGK 8 MLA 390.0 348.0 63.0 ADS8325IBDGKT DGK 8 MLA 390.0 348.0 63.0 ADS8325IBDRBR DRB 8 TUA 0.0 0.0 0.0 ADS8325IBDRBT DRB 8 TUA 0.0 0.0 0.0 ADS8325IDGKR DGK 8 MLA 390.0 348.0 63.0 ADS8325IDGKT DGK 8 MLA 390.0 348.0 63.0 ADS8325IDRBR DRB 8 TUA 0.0 0.0 0.0 ADS8325IDRBT DRB 8 TUA 0.0 0.0 0.0 Pack Materials-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 6-Aug-2007 Pack Materials-Page 3 This package incorporates an exposed thermal pad that is designed to be attached directly to an external heatsink. The thermal pad must be soldered directly to the printed circuit board (PCB). After soldering, the PCB can be used as a heatsink. In addition, through the use of thermal vias, the thermal pad can be attached directly to the appropriate copper plane shown in the electrical schematic for the device, or alternatively, can be attached to a special heatsink structure designed into the PCB. This design optimizes the heat transfer from the integrated circuit (IC). PACKAGE MATERIALS INFORMATION www.ti.com 16-Aug-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing ADS8325IBDGKR VSSOP DGK 8 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 ADS8325IBDGKT VSSOP DGK 8 250 180.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 ADS8325IBDRBR SON DRB 8 2500 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 ADS8325IBDRBT SON DRB 8 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 ADS8325IDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 ADS8325IDGKT VSSOP DGK 8 250 180.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 ADS8325IDRBR SON DRB 8 2500 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 ADS8325IDRBT SON DRB 8 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 16-Aug-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS8325IBDGKR VSSOP DGK 8 2500 367.0 367.0 35.0 ADS8325IBDGKT VSSOP DGK 8 250 210.0 185.0 35.0 ADS8325IBDRBR SON DRB 8 2500 367.0 367.0 35.0 ADS8325IBDRBT SON DRB 8 250 210.0 185.0 35.0 ADS8325IDGKR VSSOP DGK 8 2500 367.0 367.0 35.0 ADS8325IDGKT VSSOP DGK 8 250 210.0 185.0 35.0 ADS8325IDRBR SON DRB 8 2500 367.0 367.0 35.0 ADS8325IDRBT SON DRB 8 250 210.0 185.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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