PRELIMINARY DATA SHEET MOS INTEGRATED CIRCUIT EDD1204ALTA, EDD1208ALTA, EDD1216ALTA 128 M-bit Synchronous DRAM with Double Data Rate (4-bank, SSTL_2) Description The EDD1204ALTA, EDD1208ALTA, EDD1216ALTA are high-speed 134,217,728 bits synchronous dynamic random-access memories, organized as 8,388,608x4x4, 4,194,304x8x4, 2,097,152x16x4 (word x bit x bank), respectively. The synchronous DRAMs use Double Data Rate (DDR) where data bandwidth is twice of regular synchronous DRAM. The synchronous DRAM is compatible with SSTL_2 (Stub Series terminated Logic for 2.5 V). The synchronous DRAM is packaged in 66-pin Plastic TSOP (II). Features • Fully Synchronous Dynamic RAM with all input signals except DM, DQS and DQ referenced to a positive clock edge • Double Data Rate interface Differential CLK (/CLK) input Data inputs and DM are synchronized with both edges of DQS Data outputs and DQS are synchronized with a cross point of CLK and /CLK • Quad internal banks operation • Possible to assert random column address in every clock cycle • Programmable Mode register set /CAS latency (2, 2.5) Burst length (2, 4, 8) Wrap sequence (Sequential / Interleave) • Automatic precharge and controlled precharge • CBR (Auto) refresh and self refresh • x4, x8, x16 organization • Byte write control (x4, x8) by DM • Byte write control (x16) by LDM and UDM • 2.5 V ± 0.2 V Power supply for VDD • 2.5 V ± 0.2 V Power supply for VDDQ • Maximum clock frequency up to 133 MHz • SSTL_2 compatible with all signals • 4,096 refresh cycles/64 ms • 66-pin Plastic TSOP (II) (10.16 mm (400)) • Burst termination by Precharge command and Burst stop command The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local Elpida Memory, Inc. for availability and additional information. Document No. E0136E30 (Ver. 3.0) Date Published October 2001 (K) Printed in Japan Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd. EDD1204ALTA, EDD1208ALTA, EDD1216ALTA Ordering Information Part Number Organization Clock frequency (word x bit x bank) MHz (MAX.) 8M x 4 x 4 133 66-pin Plastic TSOP (II) EDD1204ALTA-75 133 (10.16 mm (400)) EDD1204ALTA-1A 100 EDD1204ALTA-7A EDD1208ALTA-7A 4M x 8 x 4 133 EDD1208ALTA-75 133 EDD1208ALTA-1A 100 EDD1216ALTA-7A 2M x 16 x 4 133 EDD1216ALTA-75 133 EDD1216ALTA-1A 100 2 Preliminary Data Sheet E0136E30 Package EDD1204ALTA, EDD1208ALTA, EDD1216ALTA Part Number E D D 12 04 A L TA - 7A ELPIDA Memory Material Type D: Mono Function D: DDR (I) Density & Bank 12: 128M/4 Bank Bit Organization 4: x4 8: x8 16: x16 Interface A: SSTL_2 Mask Revision Package TA: TSOP (II) Speed 7A: 7.5 ns (133 MHz) 75: 7.5 ns (133 MHz) 1A: 10 ns (100 MHz) Preliminary Data Sheet E0136E30 3 EDD1204ALTA, EDD1208ALTA, EDD1216ALTA Pin Configurations /xxx indicates active low signal. [EDD1204ALTA] 66-pin Plastic TSOP (II) (10.16 mm (400)) 8M word x 4 bit x 4 bank VDD NC VDDQ NC DQ0 VSSQ NC NC VDDQ NC DQ1 VSSQ NC NC VDDQ NC NC VDD NC NC /WE /CAS /RAS /CS NC BA0 BA1 A10/AP A0 A1 A2 A3 VDD A0 - A11 A0 - A11 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 : Address inputs /CAS : Column address strobe : Row address inputs /WE : Write enable DM : DQ write mask enable : Supply voltage A0 - A9, A11 : Column address inputs 4 VSS NC VSSQ NC DQ3 VDDQ NC NC VSSQ NC DQ2 VDDQ NC NC VSSQ DQS NC VREF VSS DM /CLK CLK CKE NC NC A11 A9 A8 A7 A6 A5 A4 VSS BA0, BA1 : Bank select VDD DQ0 - DQ3 : Data inputs/outputs VSS : Ground DQS : Data strobe VDDQ : Supply voltage for DQ and DQS CLK, /CLK : System clock input VSSQ : Ground for DQ and DQS CKE : Clock enable VREF : Input reference /CS : Chip select NC : No connection /RAS : Row address strobe Preliminary Data Sheet E0136E30 EDD1204ALTA, EDD1208ALTA, EDD1216ALTA [EDD1208ALTA] 66-pin Plastic TSOP (II) (10.16 mm (400)) 4M word x 8 bit x 4 bank VDD DQ0 VDDQ NC DQ1 VSSQ NC DQ2 VDDQ NC DQ3 VSSQ NC NC VDDQ NC NC VDD NC NC /WE /CAS /RAS /CS NC BA0 BA1 A10/AP A0 A1 A2 A3 VDD 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 VSS DQ7 VSSQ NC DQ6 VDDQ NC DQ5 VSSQ NC DQ4 VDDQ NC NC VSSQ DQS NC VREF VSS DM /CLK CLK CKE NC NC A11 A9 A8 A7 A6 A5 A4 VSS : Address inputs /CAS : Column address strobe A0 - A11 : Row address inputs /WE : Write enable A0 - A9 : Column address inputs DM : DQ write mask enable BA0, BA1 : Bank select VDD : Supply voltage DQ0 - DQ7 : Data inputs/outputs VSS : Ground DQS : Data strobe VDDQ : Supply voltage for DQ and DQS CLK, /CLK : System clock input VSSQ : Ground for DQ and DQS CKE : Clock enable VREF : Input reference /CS : Chip select NC : No connection /RAS : Row address strobe A0 - A11 Preliminary Data Sheet E0136E30 5 EDD1204ALTA, EDD1208ALTA, EDD1216ALTA [EDD1216ALTA] 66-pin Plastic TSOP (II) (10.16 mm (400)) 2M word x 16bit x 4 bank VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 NC VDDQ LDQS NC VDD NC LDM /WE /CAS /RAS /CS NC BA0 BA1 A10/AP A0 A1 A2 A3 VDD VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 NC VSSQ UDQS NC VREF VSS UDM /CLK CLK CKE NC NC A11 A9 A8 A7 A6 A5 A4 VSS : Address inputs /CAS : Row address inputs /WE : Write enable : Column address inputs LDM, UDM : DQ write mask enable : Bank select VDD : Supply voltage : Data inputs/outputs VSS : Ground LDQS, UDQS : Data strobe VDDQ : Supply voltage for DQ, LDQS and UDQS CLK, /CLK : System clock input VSSQ : Ground for DQ, LDQS and UDQS CKE : Clock enable VREF : Input reference /CS : Chip select NC : No connection /RAS : Row address strobe A0 - A11 A0 - A11 A0 - A8 BA0, BA1 DQ0 - DQ15 6 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 Preliminary Data Sheet E0136E30 : Column address strobe EDD1204ALTA, EDD1208ALTA, EDD1216ALTA Clock Generator Block Diagram Bank D Bank C Bank B A0 - A11, BA0, BA1 Mode Register Row Address Buffer and Refresh Counter Row Decoder CLK /CLK CKE Memory Cell Array Bank A Control Logic /CS /RAS /CAS /WE Command Decoder Sense Amp. Column Decoder Column Address Buffer and Burst Counter Data Control Circuit Latch Circuit CLK, /CLK DLL Input & Output Buffer DQS DM DQ Preliminary Data Sheet E0136E30 7 EDD1204ALTA, EDD1208ALTA, EDD1216ALTA CONTENTS 1. Input/Output Pin Function....................................................................................................................................10 2. Commands ............................................................................................................................................................11 3. Simplified State Diagram......................................................................................................................................15 4. Truth Table ............................................................................................................................................................16 4.1 Command Truth Table...............................................................................................................................16 4.2 DM Truth Table ..........................................................................................................................................16 4.3 CKE Truth Table ........................................................................................................................................16 4.4 Operative Command Table Note1 ................................................................................................................17 4.5 Command Truth Table for CKE .................................................................................................................20 5. Initialization ...........................................................................................................................................................21 6. Programming the Mode Register.........................................................................................................................22 7. Mode Register .......................................................................................................................................................23 7.1 Burst Length and Sequence ......................................................................................................................24 8. Address Bits of Bank-Select and Precharge ......................................................................................................25 9. Precharge ..............................................................................................................................................................26 9.1 Read to Precharge Command Interval ......................................................................................................26 9.2 Write to Precharge Command Interval ......................................................................................................27 10. Auto Precharge ...................................................................................................................................................28 10.1 Read with Auto Precharge.......................................................................................................................28 10.2 Write with Auto Precharge.......................................................................................................................29 11. Read/Write Command Interval ...........................................................................................................................30 11.1 Read to Read Command Interval ............................................................................................................30 11.2 Write to Write Command Interval ............................................................................................................31 11.3 Write to Read Command Interval ............................................................................................................32 11.4 Read to Write Command Interval ............................................................................................................33 8 Preliminary Data Sheet E0136E30 EDD1204ALTA, EDD1208ALTA, EDD1216ALTA 12. Burst Termination ...............................................................................................................................................34 12.1 Burst Stop Command in Read Cycle .......................................................................................................34 12.2 Terminating a Burst Read Cycle by Precharge Command ......................................................................35 12.3 Terminating a Burst Write Cycle by Precharge Command ......................................................................36 13. Electrical Specifications.....................................................................................................................................37 13.1 Absolute Maximum Ratings .....................................................................................................................37 13.2 Recommended Operating Conditions......................................................................................................37 13.3 Pin Capacitance (TA = 25 °C, f = 100 MHz) .............................................................................................37 13.4 DC Characteristics 1 (Recommended Operating Conditions unless otherwise noted) ...........................38 13.5 DC Characteristics 2 (Recommended Operating Conditions unless otherwise noted) ...........................39 13.6 AC Characteristics (Recommended Operating Conditions unless otherwise noted)...............................39 13.6.1 Test Conditions .........................................................................................................................39 13.6.2 Timing Diagram .........................................................................................................................40 13.6.3 Synchronous Characteristics.....................................................................................................41 13.6.4 Synchronous Characteristics Example......................................................................................42 13.6.5 Asynchronous Characteristics...................................................................................................42 14. Package Drawing ................................................................................................................................................74 15. Recommended Soldering Conditions ...............................................................................................................75 16. Revision History..................................................................................................................................................76 Preliminary Data Sheet E0136E30 9 EDD1204ALTA, EDD1208ALTA, EDD1216ALTA 1. Input/Output Pin Function Pin name CLK, /CLK Input/Output Input Function CLK and /CLK are the master clock inputs. The timing reference point for the differential clock is when CLK and /CLK cross. All control and address inputs except for DQ and DM are latched by a rising edge of CLK. By both of rising and falling edges of CLK, output DQ and DQS are validated. CKE Input CKE controls power down mode. When the EDD12xxALTA is not in burst mode and CKE is negated, the device enters power down mode and deactivates internal clock signals, input buffers and output drivers. During power down mode, CKE must remain low. /CS Input /CS low starts a command input cycle. When /CS is high, commands are ignored but the current operations will be continued. /RAS, /CAS, /WE Input As well as regular SDRAMs, each combination of /RAS, /CAS, and /WE input in conjunction with /CS input at a rising edge of CLK determines SDRAM operation. Refer to the command table. A0 – A11 Input Row address is determined by A0 - A11 at the rising edge of CLK in active command cycle. It does not depend on the bit organization. Column address is determined by A0 - A9, A11 at the rising edge of CLK in read or write command cycle. It depends on the bit organization: A0 - A9, A11 for x4 device, A0 - A9 for x8 device, A0 - A8 for x16 device. A10 defines precharge mode. When A10 is high in precharge command cycle, all banks are precharged; when A10 is low, only the bank selected by BA0 and BA1 is precharged. When A10 is high in read or write command cycle, precharge starts automatically after the burst access. BA0, BA1 Input BA0, BA1 are bank select signals. In command cycle, BA0 and BA1 low select Bank A, BA0 high and BA1 low select bank B, BA0 low and BA1 high select bank C and then BA0 and BA1 high select bank D. DQ0 – DQ15 Input/Output DQ pins have the same function as I/O pins on conventional DRAMs. DQS, LDQS, UDQS Input/Output Active on the both edges for data input and output. DM, LDM, UDM Input DM's are latched by both of rising and falling edges of the DQS. In write mode, DM's control byte mask. Unlike regular SDRAMs, DM's do not control read operation. VREF Input VREF is reference voltage for SSTL input buffers. VDD, VDDQ, VSS, VSSQ (Power Supply) VDD and VSS are power supply pins for internal circuits. VDDQ and VSSQ are power supply pins for the output buffers. 10 Preliminary Data Sheet E0136E30 EDD1204ALTA, EDD1208ALTA, EDD1216ALTA 2. Commands Extended mode register set command Fig.1 Extended mode register set command (/CS, /RAS, /CAS, /WE Low) CLK The EDD12xxALTA has an extended mode register that defines enabling or disabling DLL. In this command, A0 through A11, BA0 and BA1 are the data CKE H /CS input pins. After power on, the extended mode register set command must be executed for /RAS /CAS enabling or disabling DLL. The extended mode register can be set only when all banks are in idle state. /WE During tMRD, the EDD12xxALTA can not accept any other commands. BA0 BA1 A10 Add Mode register set command Fig.2 Mode register set command (/CS, /RAS, /CAS, /WE Low) CLK The EDD12xxALTA has a mode register that defines how the device operates. In this command, A0 through A11, BA0 and BA1 are the data input pins. CKE /CS After power on, the mode register set command must be executed to initialize the /RAS device. /CAS The mode register can be set only when all banks are in idle state. During tMRD, the EDD12xxALTA can not accept any other commands. H /WE BA0,BA1 A10 Add Bank activate command Fig.3 Bank activate command (/CS, /RAS = Low, /CAS, /WE = High) The EDD12xxALTA has four banks, each with 4,096 rows. This command activates the bank and the row address selected by BA0 and CLK CKE H /CS /RAS BA1, and by A0 through A11 respectively. This command corresponds to a conventional DRAM's /RAS falling. /CAS /WE BA0,BA1 Preliminary Data Sheet E0136E30 A10 Row Add Row 11 EDD1204ALTA, EDD1208ALTA, EDD1216ALTA Precharge command Fig.4 Precharge command (/CS, /RAS, /WE= Low, /CAS = High) CLK This command begins precharge operation of the bank selected by BA0, BA1 and A10. When A10 is High, all banks are precharged, regardless of BA0 and CKE H /CS /RAS BA1. When A10 is Low, only the bank selected by BA0 and BA1 is precharged. After this command, the EDD12xxALTA can't accept the activate command to the precharging bank during tRP (precharge to activate command period). This command can terminate the current burst operation. This command corresponds to a conventional DRAM's /RAS rising. /CAS /WE BA0, BA1 A10 (Precharge select) Add Read command Fig.5 Read command (/CS, /CAS = Low, /RAS, /WE = High) CLK This command begins the burst read operation. The bank and the burst start column address are selected by BA0 and BA1 and by A0 through A11 respectively. CKE H /CS /RAS Read data is available after /CAS latency requirements which have been met. /CAS And it is synchronized with DQS. /WE BA0, BA1 A10 (Auto precharge select) Add Write command Col. Fig.6 Write command (/CS, /CAS, /WE = Low, /RAS = High) CLK This command begins burst write operation. The bank and the burst start column address are selected by BA0 and BA1 and by A0 through A11 CKE H /CS /RAS respectively. Write data must be input by DQ0 through DQ15. Byte mask data must be input by DM, LDM, and UDM. Both data must be synchronized with DQS that is inputted after this command. /CAS /WE BA0, BA1 A10 (Auto precharge select) Add 12 Preliminary Data Sheet E0136E30 Col. EDD1204ALTA, EDD1208ALTA, EDD1216ALTA CBR (auto) refresh command Fig.7 CBR (auto) refresh command (/CS, /RAS, /CAS = Low, /WE, CKE = High) CLK This command is a request to begin the CBR (auto) refresh operation. The refresh address is generated internally. Before executing CBR (auto) refresh, all banks must be precharged. After this cycle, all banks will be in the idle (precharged) state and ready for a CKE H /CS /RAS /CAS bank activate command. During tRFC (refresh command to refresh or activate command period), the EDD12xxALTA cannot accept any other command. /WE BA0, BA1 A10 Add Self refresh entry command Fig.8 Self refresh entry command (/CS, /RAS, /CAS, CKE = Low, /WE = High) CLK After the command execution, self refresh operation continues while CKE CKE /CS remains low. When CKE goes high, the EDD12xxALTA will exit the self refresh mode. /RAS During self refresh mode, refresh interval and refresh operation are performed /CAS internally, so there is no need for external control. Before executing self refresh, all banks must be precharged. /WE BA0, BA1 A10 Add Burst stop command Fig.9 Burst stop command (/CS, /WE = Low, /RAS, /CAS = High) CLK This command can stop the current read burst operation. CKE H /CS /RAS /CAS /WE BA0, BA1 A10 Add Preliminary Data Sheet E0136E30 13 EDD1204ALTA, EDD1208ALTA, EDD1216ALTA No operation Fig.10 No operation (/CS = Low, /RAS, /CAS, /WE = High) CLK This command is not an execution command. This command doesn't begin or terminate any operation. CKE /CS /RAS /CAS /WE BA0, BA1 A10 Add 14 Preliminary Data Sheet E0136E30 H EDD1204ALTA, EDD1208ALTA, EDD1216ALTA 3. Simplified State Diagram SREX Self Refresh Recovery Self Refresh SELF MRS, EMRS Mode Register Set REF IDLE (tMRD) CBR (auto) Refresh (tRFC) PW ACT DN PDE X Bank Activating Power Down DN PW EX PD BANK ACTIVE BS T RE ITA WR (B A AD (tW RE PRE/PALL R) AD ur st en d) READ WRIT READ READ RE AD A READA E( PR n) ) AL tD tio R/ (tW ina erm et arg ch Pre WRITA PR E( Pre ch arg et erm ina tion (B ur ) st en d) WRIT Precharge READA PRE/PALL POWER ON (tRP) Automatic sequence Manual input Preliminary Data Sheet E0136E30 15 EDD1204ALTA, EDD1208ALTA, EDD1216ALTA 4. Truth Table 4.1 Command Truth Table Function Symbol CKE /CS n-1 n /RAS /CAS /WE Address BA0 BA1 A10 A0-9,A11 Device deselect DESL H x H x x x x x x No operation NOP H x L H H H x x x BST H x L H H L x x x READ H x L H L H V L V Burst stop Read Read with auto precharge READA Write WRIT Write with auto precharge H H x L H L L V L WRITA Bank active ACT H x L L H H Prechrage select bank PRE H x L L H L Precharge all banks PALL Mode register set MRS H x L L L L Extended mode register set V H V V L x EMRS x H x L L L V H L L V 4.2 DM Truth Table Function Symbol CKE DM n-1 n Data write enable ENB H x U L L Data mask MASK H x H Upper byte write enable ENBU H x Lower byte write enable ENBL H Upper byte write inhibit MASKU H Lower byte write inhibit MASKL H L x x x L x H x x x H 4.3 CKE Truth Table Current State Function Symbol CKE n-1 n Idle CBR (auto) refresh command REF H H Idle Self refresh entry SELF H L Self refresh Self refresh exit SREX L H Idle Power down entry Bank(s) active Power down entry Power down Power down exit PWDN PWDN PDEX H H L L L H /CS /RAS /CAS /WE Address L L L H x H x x x x L H H x x H x x x x L H H x x H x x x x L H H x x H x x x x L H H x x Remark H = High level, L = Low level, V = Valid, x = High or Low level (Don't care) 16 Preliminary Data Sheet E0136E30 EDD1204ALTA, EDD1208ALTA, EDD1216ALTA 4.4 Operative Command Table Note1 (1/3) Current state Idle Row active Read /CS /RAS /CAS /WE Address Command Action Notes H x x x x DESL Nop or Power down L H H H x NOP Nop or Power down L H H L x BST ILLEGAL 2 L H L H BA, CA, A10 READ/READA ILLEGAL 2 L H L L BA, CA, A10 WRIT/WRITA ILLEGAL 2 L L H H BA, RA ACT Bank activating L L H L BA, A10 PRE/PALL Nop L L L H x REF/SELF CBR (auto) refresh or Self refresh 4 L L L L Op-Code MRS Mode register set 4 L L L L Op-Code EMRS Extended mode register set 4 3 H x x x x DESL Nop L H H H x NOP Nop L H H L x BST ILLEGAL L H L H BA, CA, A10 READ/READA Begin read/read with AP L H L L BA, CA, A10 WRIT/WRITA Begin write/write with AP L L H H BA, RA ACT ILLEGAL 2 L L H L BA, A10 PRE/PALL Precharge/Precharge all banks 5 L L L H x REF/SELF ILLEGAL L L L L Op-Code MRS ILLEGAL L L L L Op-Code EMRS ILLEGAL H x x x x DESL Nop (Row active after burst end) L H H H x NOP Nop (Row active after burst end) L H H L x BST terminate burst, Row active L H L H BA, CA, A10 READ/READA terminate burst, Begin new read/ 2 6 6 read with AP L H L L BA, CA, A10 WRIT/WRITA ILLEGAL L L H H BA, RA ACT ILLEGAL 2 L L H L BA, A10 PRE/PALL terminate burst, 6 L L L H x REF/SELF ILLEGAL L L L L Op-Code MRS ILLEGAL Precharge/Precharge all banks Write L L L L Op-Code EMRS ILLEGAL H x x x x DESL Nop (Row active after tWR) L H H H x NOP Nop (Row active after tWR) L H H L x BST ILLEGAL L H L H BA, CA, A10 READ/READA terminate burst, Begin read/read with AP 6 L H L L BA, CA, A10 WRIT/WRITA terminate burst, Begin new write/ L L H H BA, RA ACT ILLEGAL L L H L BA, A10 PRE/PALL terminate burst, Precharge/Precharge all 6 banks L L L H x REF/SELF ILLEGAL L L L L Op-Code MRS ILLEGAL L L L L Op-Code EMRS ILLEGAL 6 write with AP Preliminary Data Sheet E0136E30 2 17 EDD1204ALTA, EDD1208ALTA, EDD1216ALTA (2/3) Current state /CS /RAS /CAS /WE Address Command Action Notes Read with auto H x x x x DESL Nop (Precharge after burst end) precharge L H H H x NOP Nop (Precharge after burst end) L H H L x BST ILLEGAL L H L H BA, CA, A10 READ/READA ILLEGAL L H L L BA, CA, A10 WRIT/WRITA ILLEGAL L L H H BA, RA ACT ILLEGAL 2 L L H L BA, A10 PRE/PALL ILLEGAL 2 L L L H x REF/SELF ILLEGAL L L L L Op-Code MRS ILLEGAL L L L L Op-Code EMRS ILLEGAL Write with H x x x x DESL Nop (Idle after tDAL) auto precharge L H H H x NOP Nop (Idle after tDAL) L H H L x BST ILLEGAL L H L H BA, CA, A10 READ/READA ILLEGAL L H L L BA, CA, A10 WRIT/WRITA ILLEGAL L L H H BA, RA ACT ILLEGAL 2 L L H L BA, A10 PRE/PALL ILLEGAL 2 L L L H x REF/SELF ILLEGAL L L L L Op-Code MRS ILLEGAL Precharge Row activating 18 L L L L Op-Code EMRS ILLEGAL H x x x x DESL Nop (Idle after tRP) L H H H x NOP Nop (Idle after tRP) L H H L x BST ILLEGAL 2 L H L H BA, CA, A10 READ/READA ILLEGAL 2 L H L L BA, CA, A10 WRIT/WRITA ILLEGAL 2 L L H H BA, RA ACT ILLEGAL 2 L L H L BA, A10 PRE/PALL Nop (Idle after tRP) 3 L L L H x REF/SELF ILLEGAL L L L L Op-Code MRS ILLEGAL L L L L Op-Code EMRS ILLEGAL H x x x x DESL Nop (Row active after tRCD) L H H H x NOP Nop (Row active after tRCD) L H H L x BST ILLEGAL 2 L H L H BA, CA, A10 READ/READA ILLEGAL 2 L H L L BA, CA, A10 WRIT/WRITA ILLEGAL 2 L L H H BA, RA ACT ILLEGAL 2 L L H L BA, A10 PRE/PALL ILLEGAL 2 L L L H x REF/SELF ILLEGAL L L L L Op-Code MRS ILLEGAL L L L L Op-Code EMRS ILLEGAL Preliminary Data Sheet E0136E30 EDD1204ALTA, EDD1208ALTA, EDD1216ALTA (3/3) Current state Write recovering /CS /RAS /CAS /WE Address Command Action Notes H x x x x DESL Nop (Row active after tWR) L H H H x NOP Nop (Row active after tWR) L H H L x BST Nop (Row active after tWR) L H L H BA, CA, A10 READ/READA Begin read/read with AP L H L L BA, CA, A10 WRIT/WRITA Begin new write/write with AP L L H H BA, RA ACT ILLEGAL 2 L L H L BA, A10 PRE/PALL ILLEGAL 2 L L L H x REF/SELF ILLEGAL L L L L Op-Code MRS ILLEGAL L L L L Op-Code EMRS ILLEGAL Write recovering H x x x x DESL Nop (Idle after tDAL) with auto precharge L H H H x NOP Nop (Idle after tDAL) L H H L x BST ILLEGAL L H L H BA, CA, A10 READ/READA ILLEGAL L H L L BA, CA, A10 WRIT/WRITA ILLEGAL L L H H BA, RA ACT ILLEGAL 2 L L H L BA, A10 PRE/PALL ILLEGAL 2 L L L H x REF/SELF ILLEGAL L L L L Op-Code MRS ILLEGAL L L L L Op-Code EMRS ILLEGAL H x x x x DESL Nop (Idle after tRFC) L H H H x NOP Nop (Idle after tRFC) L H H L x BST Nop (Idle after tRFC) 2 L H L x x READ/WRIT ILLEGAL 2 L L H x x ACT/PRE/PALL ILLEGAL 3 L L L x x REF/SELF/MRS/E ILLEGAL MRS Mode register H x x x x DESL Nop (Idle after tMRD) accessing L H H H x NOP Nop (Idle after tMRD) L H H L x BST ILLEGAL 2 L H x x x READ/WRIT ILLEGAL 2 L L x x x ACT/PRE/PALL/R ILLEGAL EF/SELF/MRS/EM RS 2 Refresh Remark H = High level, L = Low level, x = High or Low level (Don't care), BA = Bank address, RA = Row address, CA = Column address, A10 = Precharge control address, Op-Code = Operand code, Nop = No operation, AP = Auto precharge, ILLEGAL = Device operation and/or data-integrity are not guaranteed Notes 1. All entries assume that CKE is active (High level) during the preceding clock cycle and the current clock cycle. 2. ILLEGAL to bank in specified states; function may be legal in the bank indicated by BA0, BA1 depending on the state of that bank. 3. Nop to bank precharging or in idle state. May precharge bank indicated by BA0, BA1. 4. ILLEGAL if any bank is not idle. 5. ILLEGAL if tRAS is not satisfied. 6. Must satisfy command interval and/or burst terminate condition. Preliminary Data Sheet E0136E30 19 EDD1204ALTA, EDD1208ALTA, EDD1216ALTA 4.5 Command Truth Table for CKE Current State Self refresh Self refresh recovery Power down All banks idle CKE /CS /RAS /CAS /WE Add Command n-1 n H x x x x x x L H H x x x x L H H x x Action ILLEGAL(Impossible) SREX Exit S.R, self refresh recovery L L x x x x x H H H x x x x DESL Nop (Idle after tRC) H H L H H H x NOP Nop (Idle after tRC) H L x x x x x ILLEGAL L x x x x x x ILLEGAL (Impossible) H x x x x x x ILLEGAL (Impossible) L H H x x x x L H H x x x x x x x PDEX Exit power down, Idle L L Maintain power down H H V V V V x H L H x x x x PWDN Power down entry 1 H L L H H H x PWDN Power down entry 1 H L L x x L x ILLEGAL H L L H L x x ILLEGAL H L L L H x x ILLEGAL H L L L L H x Refer to operative command table SELF Self refresh entry L x x x x x x Power down x x x x x x Refer to operative command table L x x x x x x Power down Any state except H H V V V V V Refer to operative command table listed above H L x x x x x ILLEGAL L x x x x x x ILLEGAL (Impossible) Remark H = High level, L = Low level, x = High or Low level (Don't care), V = Valid, Add = Address (A0 - A11, BA0, BA1), ILLEGAL = Device operation and/or data-integrity are not guaranteed Notes 1. Self refresh can be entered only from all banks idle state. Power down can be entered only from all banks idle or row active state. 2. CKE low to high transition will re-enable CLK and other inputs asynchronously. A Minimum setup time must be satisfied before any command other than exit. 20 2 Maintain self refresh H Row active Notes Preliminary Data Sheet E0136E30 1 1 EDD1204ALTA, EDD1208ALTA, EDD1216ALTA 5. Initialization The EDD12xxALTA is initialized in the power-on sequence according to the following. (1) Power must first be applied to VDD, then VDDQ, and finally to VREF. VTT must be applied. (2) Maintaining an LVCMOS LOW level on CKE during power-up is required to guarantee that the DQ and DQS output will be in Hi-Z state. (3) To stabilize internal circuits, when power is applied a 100 µs or longer pause must precede any signal toggling. (4) After the pause, all banks must be precharged using precharge command. The precharge all banks command is convenient. (5) EMRS command must be performed to enable or disable DLL. Then MRS command must be applied to reset DLL. After this MRS command additional 200 cycles are required before read command. (6) All banks must be precharged using precharge command again. Then two or more CBR (auto) refresh command must be performed. (7) After the refresh the mode register can be programmed by MRS command. Case 1: MRS after the REF Min. 200 cycles before Read command tMRD tMRD tRP tRFC tMRD tRFC CLK CKE Command Remark PALL EMRS MRS DLL enable / disable DLL reset PALL REF REF MRS Any Command Minimum 2 REF cycles must be performed. Two refresh commands may be follow the first MRS command. Preliminary Data Sheet E0136E30 21 EDD1204ALTA, EDD1208ALTA, EDD1216ALTA 6. Programming the Mode Register The mode register is programmed by the Mode register set command using address bits BA0, BA1, A11 through A0 as data inputs. The register retains data until it is reprogrammed or the device loses power. The mode register has five fields; Option : A11 through A9, A7 DLL reset : A8 /CAS latency : A6 through A4 Wrap type : A3 Burst length : A2 through A0 Following mode register programming, no command can be issued during tMRD. /CAS Latency /CAS latency is the critical parameter. It tells how many clocks must elapse before the data is available. The value is determined by the frequency of the clock and the speed grade of the device. Burst Length Burst length is the number of words that will be output or input in read or write cycle. After read burst is completed, the output bus becomes Hi-Z. The burst length is programmable as 2, 4 and 8. Wrap Type (Burst Sequence) The wrap type specifies the order in which the burst data is addressed. This order is programmable as either “Sequential” or “Interleave”. The method chosen depends on the type of CPU in the system. Some microprocessor cache system are optimized for sequential addressing and others for interleaved addressing. 7.1 Burst Length and Sequence shows the addressing sequence for each burst length using them. Both sequences support bursts of 2, 4 and 8. The extended mode register has two fields; Option : A11 through A1 DLL enable : A0 22 Preliminary Data Sheet E0136E30 EDD1204ALTA, EDD1208ALTA, EDD1216ALTA 7. Mode Register BA1 BA0 A11 x x x BA1 BA0 A11 0 1 0 BA1 BA0 A11 0 0 0 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 x x 0 1 V V V V V V V A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 0 0 0 0 0 0 0 0 0 0 DLL A10 A9 A8 A7 0 0 DLL 0 Bit 8 DLL 0 Normal 1 Reset A6 A5 LTMODE A4 A3 WT A2 A1 A0 Vender specific Extended mode register set Bit 0 DLL 0 Enable 1 Disable Mode register set BL Bit 2 - Bit 0 WT = 0 WT = 1 000 R R 001 2 2 Burst 010 4 4 Length 011 8 8 100 R R 101 R R 110 R R 111 R R Remark V = Valid, x = Don't care CLK CKE /CS Wrap Bit 3 Mode Type 0 Sequential 1 Interleave Bit 6 - Bit 4 /CAS Latency 000 R 001 R Latency 010 2 Mode 011 R 100 R 101 R 110 2.5 111 R /RAS /CAS /WE A0 - A11, BA0, BA1 Mode register set timming Remark R: Reserved Preliminary Data Sheet E0136E30 23 EDD1204ALTA, EDD1208ALTA, EDD1216ALTA 7.1 Burst Length and Sequence [Burst Length = Two] Starting Address Sequential Addressing Sequence Interleave Addressing Sequence (column address A0, binary) (decimal) (decimal) 0 0, 1 0, 1 1 1, 0 1, 0 Starting Address Sequential Addressing Sequence Interleave Addressing Sequence (column address A1 - A0, binary) (decimal) (decimal) 00 0, 1, 2, 3 0, 1, 2, 3 01 1, 2, 3, 0 1, 0, 3, 2 10 2, 3, 0, 1 2, 3, 0, 1 11 3, 0, 1, 2 3, 2, 1, 0 [Burst Length = Four] [Burst Length = Eight] 24 Starting Address Sequential Addressing Sequence Interleave Addressing Sequence (column address A2 - A0, binary) (decimal) (decimal) 000 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 001 1, 2, 3, 4, 5, 6, 7, 0 1, 0, 3, 2, 5, 4, 7, 6 010 2, 3, 4, 5, 6, 7, 0, 1 2, 3, 0, 1, 6, 7, 4, 5 011 3, 4, 5, 6, 7, 0, 1, 2 3, 2, 1, 0, 7, 6, 5, 4 100 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 101 5, 6, 7, 0, 1, 2, 3, 4 5, 4, 7, 6, 1, 0, 3, 2 110 6, 7, 0, 1, 2, 3, 4, 5 6, 7, 4, 5, 2, 3, 0, 1 111 7, 0, 1, 2, 3, 4, 5, 6 7, 6, 5, 4, 3, 2, 1, 0 Preliminary Data Sheet E0136E30 EDD1204ALTA, EDD1208ALTA, EDD1216ALTA 8. Address Bits of Bank-Select and Precharge [Activate Command] A10 A9 A8 A6 A5 A4 A3 A2 A1 A0 Row Address A7 A6 A5 A4 A3 A2 A1 A0 Row Address A7 A6 A5 A4 A3 A2 A1 A0 Column Address BA1 BA0 A11 A7 BA1 BA0 Result 0 0 Select Bank A, ''Activate'' command 0 1 Select Bank B, ''Activate'' command 1 0 Select Bank C, ''Activate'' command 1 1 Select Bank D, ''Activate'' command [Precharge Command] BA1 BA0 A11 A10 A9 A8 BA1 BA0 A10 Result 0 0 0 Precharge Bank A 0 1 0 Precharge Bank B 1 0 0 Precharge Bank C 1 1 0 Precharge Bank D x x 1 Precharge All Banks Remark x = Don't care [Read/Write Command] BA1 BA0 A11 A10 A10 Result A9 A8 0 Disables Auto-Precharge 1 Enables Auto-Precharge BA1 BA0 Result 0 0 Enables Read/Write commands for Bank A 0 1 Enables Read/Write commands for Bank B 1 0 Enables Read/Write commands for Bank C 1 1 Enables Read/Write commands for Bank D Preliminary Data Sheet E0136E30 25 EDD1204ALTA, EDD1208ALTA, EDD1216ALTA 9. Precharge 9.1 Read to Precharge Command Interval The precharge command can be issued anytime after tRAS (MIN.) is satisfied. Soon after the precharge command is issued, precharge operation performed and the DDR SDRAM enters the idle state after tRP is satisfied. The parameter tRP is the time required to perform the precharge. The earliest timing in a read cycle that a precharge command can be issued without losing any data in the burst is as follows. /CAS latency = 2 : (burst length/2) clocks after the read command is issued. /CAS latency = 2.5 : (burst length/2) clocks after the read command is issued. Burst length = 4 T0 T1 T2 T3 T4 T5 CLK /CLK CKE /CAS latency = 2 Command READ PRE Hi-Z DQS Q1 DQ Q2 Q3 Hi-Z Q4 /CAS latency = 2.5 Command READ PRE Hi-Z DQS DQ Q1 Q2 Q3 Q4 Hi-Z (Must satisfy tRAS) 26 Preliminary Data Sheet E0136E30 EDD1204ALTA, EDD1208ALTA, EDD1216ALTA 9.2 Write to Precharge Command Interval In order to write all burst data to the memory cell correctly, the asynchronous parameter tWR must be satisfied. The tWR specification defines the earliest time that a precharge command can be issued. Burst length = 4 T0 T1 T2 T3 T4 T5 tWR CLK /CLK DM /CAS latency = 2, 2.5 Command WRITE PRE Preamble Postamble DQS Hi-Z DQ Q1 Q2 Q3 Q4 (Must satisfy tRAS) Preliminary Data Sheet E0136E30 27 EDD1204ALTA, EDD1208ALTA, EDD1216ALTA 10. Auto Precharge During a read or write command cycle, A10 controls auto precharge. A10 high in the read or write command (read with auto precharge command or write with auto precharge command), auto precharge is selected and begin automatically. The tRAS must be satisfied with a read with auto precharge or a write with auto precharge operation. In addition, the next activate command to the bank being precharged cannot be executed until the precharge cycle ends. In read cycle, once auto precharge starts, an activate command to the bank can be issued after tRP is satisfied. In write cycle, tDAL must be satisfied to issue the next activate command to the bank being precharged. 10.1 Read with Auto Precharge When a read with auto precharge command is issued, the auto precharge begins (Burst length / 2) clocks later from a read with auto precharge command. Burst length = 4 T0 T1 T2 T3 Burst length / 2 cycle T4 T5 tRP CLK /CLK CKE /CAS latency = 2 Command READA ACT Auto precharge starts Hi-Z Q1 DQ Q2 Q3 Q4 /CAS latency = 2.5 Command READA ACT Auto precharge starts Hi-Z DQ Q1 Q2 Q3 Q4 (When tRAS is satisfied) Remark READA means Read with Auto Precharge command 28 Preliminary Data Sheet E0136E30 EDD1204ALTA, EDD1208ALTA, EDD1216ALTA 10.2 Write with Auto Precharge When a write with auto precharge command is issued, the auto precharge begins after tWR is satisfied. Burst length = 2 T0 T1 T2 T3 T4 T5 T6 tRP tWR CLK /CLK CKE /CAS latency = 2, 2.5 Command Auto precharge starts ACT WRITEA DQS DQ D1 D2 (When tRAS is satisfied) Remark WRITEA means Write with Auto Precharge command Preliminary Data Sheet E0136E30 29 EDD1204ALTA, EDD1208ALTA, EDD1216ALTA 11. Read/Write Command Interval 11.1 Read to Read Command Interval During a read cycle, when new read command is issued, it will be effective after /CAS latency, even if the previous read operation is not completed. READ will be interrupted by another READ. The interval between commands is minimum 1 cycle. Each read command can be issued in every clock without any restriction. Burst length = 4 T0 T1 T2 T3 T4 T5 T6 1 cycle CLK /CLK CKE /CAS latency = 2 Command READ A READ B Hi-Z DQ QA1 QA2 QB1 QB2 QB3 QB4 QA1 QA2 QB1 QB2 QB3 /CAS latency = 2.5 Command DQ 30 READ A READ B Preliminary Data Sheet E0136E30 QB4 Hi-Z EDD1204ALTA, EDD1208ALTA, EDD1216ALTA 11.2 Write to Write Command Interval During a write cycle, when new write command is issued, the previous burst will terminate and the new burst will begin with new write command. WRITE will be interrupted by another WRITE. The interval between commands is minimum 1 cycle. Each write command can be issued in every clock without any restriction. Burst length = 4 T0 T1 T2 T3 T4 T5 1 cycle CLK /CLK CKE /CAS latency = 2, 2.5 Command WRITE A WRITE B DQS DQ DA1 DA2 DB1 DB2 Preliminary Data Sheet E0136E30 DB3 DB4 31 EDD1204ALTA, EDD1208ALTA, EDD1216ALTA 11.3 Write to Read Command Interval The burst write operation can be interrupted by read command of any bank. The data bus must be high impedance at least 1 cycle prior to the first output data. The minimum time interval between the rising clock edge after the last input data and the read command is tWTR. When the read command is issued, the invalid data from the burst write cycle must be masked by DM. T0 T1 T2 T3 T4 T6 T5 tWTR CLK /CLK CKE /CAS latency = 2 Command WRITE A READ B Hi-Z DQS DA1 DQ Hi-Z DA2 QB1 QB2 QB3 QB4 QB1 QB2 QB3 DM /CAS latency = 2.5 Command WRITE A READ B Hi-Z DQS DQ DA1 Hi-Z DA2 DM DQ and DQS : Input 32 DQ and DQS : Output Preliminary Data Sheet E0136E30 EDD1204ALTA, EDD1208ALTA, EDD1216ALTA 11.4 Read to Write Command Interval To interrupt the burst read operation using the write command, the burst stop command must be issued to avoid data conflict. The data bus must be high impedance when the write command is issued. When the write command is issued, any residual data from the burst read cycle must be terminated by the burst stop command. When /CAS latency is 2, 2.5, the burst stop command must be issued at least 2 cycles prior to the write command. T0 T1 T2 T0 T3 T4 T1 T5 T6 T7 T8 T2 T9 T10 T3 T11 T12 T4 T13 T14Burst length = 8 T6 T5 CLK /CLK CKE /CAS latency = 2 Command READ A BST WRITE B Hi-Z DQS QA1 DQ QA2 QA3 QA4 Hi-Z DB1 DB2 DB DB1 DB2 DB /CAS latency = 2.5 Command READ A BST WRITE B Hi-Z DQS DQ QA1 QA2 QA3 DQ and DQS : Output Preliminary Data Sheet E0136E30 QA4 Hi-Z DQ and DQS : Input 33 EDD1204ALTA, EDD1208ALTA, EDD1216ALTA 12. Burst Termination 12.1 Burst Stop Command in Read Cycle During a burst read cycle, when the burst stop command is issued at the rising edge of the clock (CLK), the burst read data are terminated and the data bus goes to high impedance after the /CAS latency from the burst stop command. T0 T1 T2 T3 T0 T4 T5 T1 T6 T7 T9 T8 T2 T10 T3 T11 T4 Burst length = 8 T5 CLK /CLK CKE /CAS latency = 2 Command READ BST Hi-Z Q1 DQ Q2 Q3 Q4 Q1 Q2 Q3 /CAS latency = 2.5 Command READ BST Hi-Z DQ Q4 (When tRAS is satisfied) Remark BST means Burst Stop command 34 Preliminary Data Sheet E0136E30 EDD1204ALTA, EDD1208ALTA, EDD1216ALTA 12.2 Terminating a Burst Read Cycle by Precharge Command During a burst read cycle without auto precharge, the burst read operation is terminated by a precharge command of the same banks. When the precharge command is issued at the rising edge of the clock (CLK), the burst read operation is terminated and the data bus goes to high impedance after the /CAS latency from the precharge command. The precharge command can be issued after tRAS (MIN.) is satisfied. Burst length = Full page T0 T1 T2 T3 T4 T5 CLK /CLK CKE /CAS latency = 2 Command READ PRE Hi-Z Q1 DQ Q2 Q3 Q4 Q1 Q2 Q3 /CAS latency = 2.5 Command READ PRE Hi-Z DQ Q4 (When tRAS is satisfied) Preliminary Data Sheet E0136E30 35 EDD1204ALTA, EDD1208ALTA, EDD1216ALTA 12.3 Terminating a Burst Write Cycle by Precharge Command During a burst write cycle without auto precharge, the burst write operation is terminated by a precharge command of the same banks. In order to write the last input data to the memory cell correctly, tWR (MIN.) must be satisfied. When the precharge command is issued at the rising edge of the clock (CLK), the invalid data from the burst write cycle must be masked by DM. Burst length = 8 T0 T1 T2 T3 T4 tWR CLK /CLK CKE /CAS latency = 2, 2.5 Command WRITE PRE DQS DQ D1 D2 DM 36 Preliminary Data Sheet E0136E30 T5 EDD1204ALTA, EDD1208ALTA, EDD1216ALTA 13. Electrical Specifications • All voltages are referenced to VSS (GND). • After power up, wait more than 100 µs and then, execute Power on sequence and CBR (auto) Refresh before proper device operation is achieved. 13.1 Absolute Maximum Ratings Parameter Symbol Condition Rating Unit VDD, VDDQ −0.5 to +3.6 V Voltage on any pin relative to VSS VT −0.5 to +3.6 V Short circuit output current IO 50 mA Voltage on power supply pin relative to VSS Power dissipation PD 1 W Storage temperature Tstg −55 to + 125 °C Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. 13.2 Recommended Operating Conditions Parameter Supply voltage Symbol Condition MIN. TYP. MAX. Unit VDD 2.3 2.5 2.7 V Supply voltage for DQ, DQS VDDQ 2.3 2.5 2.7 V Input reference voltage VREF 0.49 × VDDQ 0.51 × VDDQ V VTT VREF − 0.04 VREF + 0.04 V High level dc input voltage VIH (DC) VREF + 0.18 VDD + 0.3 V Low level dc input voltage VIL (DC) −0.3 VREF − 0.18 V Input differential voltage (CLK and /CLK) VID (DC) 0.36 VDDQ + 0.6 V Input crossing point voltage (CLK and /CLK) VIX 0.5 × VDDQ–0.2 0.5 × VDDQ+0.2 V Operating ambient temperature TA 0 70 °C Termination voltage VREF 13.3 Pin Capacitance (TA = 25 °C, f = 100 MHz) Parameter Input capacitance Data input/output capacitance Symbol Condition MIN. TYP. MAX. Unit CI1 A0 - A11, BA0, BA1 2.5 3.5 pF CI2 CLK, /CLK, CKE, /CS, /RAS, /CAS, /WE 2.5 3.5 pF CIO1 DQS, LDQS, UDQS 4 5 pF CIO2 DQ0 - DQ15, DM, LDM, UDM 4 5 pF Preliminary Data Sheet E0136E30 37 EDD1204ALTA, EDD1208ALTA, EDD1216ALTA 13.4 DC Characteristics 1 (Recommended Operating Conditions unless otherwise noted) Parameter Operating current (ACT-PRE) Operating current Symbol IDD0 IDD1 (ACT-READ-PRE) Test condition /CAS Grade latency tRC = tRC(MIN.), tCK = tCK (MIN.), One bank, Active-precharge, DQ, DM and DQS inputs changing twice per clock cycle, Address and control inputs changing once per clock cycle tRC = tRC(MIN.), tCK = tCK (MIN.), One CL = 2 bank, Active-read-precharge, IO = 0 mA, Burst length = 2, Address and control inputs changing once per clock cycle CL = 2.5 Maximum x4 x8 -7A 115 -75 115 -1A 100 Unit Notes mA 1 x16 -7A 140 150 170 -75 130 140 160 -1A 130 140 160 -7A 150 160 180 -75 150 160 180 -1A 140 150 170 mA Precharge power down standby current IDD2P CKE ≤ VIL(MAX.), tCK = tCK(MIN.), All banks idle, Power down mode 2 mA Idle standby current IDD2N CKE ≥ VIH(MIN.), tCK = tCK(MIN.), /CS ≥ VIH(MIN.), All banks idle, Address and other control inputs 45 mA Active power down standby current IDD3P CKE ≤ VIL(MAX.), tCK = tCK(MIN.), One bank active, Power down mode 25 mA Active standby current IDD3N /CS ≥ VIH(MIN.), CKE ≥ VIH(MIN.), tCK = tCK(MIN.), tRC = tRAS(MAX.), One bank, Active-precharge, DQ, DM and DQS inputs changing twice per clock cycle, Address and other control inputs changing once per clock cycle 65 mA Operating current IDD4R tCK = tCK(MIN.), Continuous burst read, Burst length = 2, IO = 0mA, One bank active, Address and control inputs changing once per clock cycle changing once per clock cycle (Burst read) Operating current IDD4W (Burst write) CBR (auto) refresh current Self refresh current IDD5 IDD6 tCK = tCK(MIN.), Continuous burst write, Burst length = 2, One bank active, Address and control inputs changing once per clock cycle tRFC = tRFC(MIN.) CL = 2 CL = 2.5 CL = 2 CL = 2.5 -7A 200 210 230 -75 170 180 200 -1A 170 180 200 -7A 210 220 240 -75 210 220 240 -1A 180 190 210 -7A 195 205 225 -75 160 170 190 -1A 160 170 190 -7A 195 205 225 -75 195 205 225 -1A 160 170 190 -7A 250 -75 250 -1A 220 CKE ≤ 0.2 V 2 mA 2 mA 2 mA mA Notes 1. IDD1 depends on output loading and cycle rates. Specified values are obtained with the output open. 2. IDD4R and IDD4W depend on output loading and cycle rates. Specified values are obtained with the output open. 38 Preliminary Data Sheet E0136E30 EDD1204ALTA, EDD1208ALTA, EDD1216ALTA 13.5 DC Characteristics 2 (Recommended Operating Conditions unless otherwise noted) Parameter Symbol Test condition MIN. MAX. Unit Notes Input leakage current II(L) Any input 0 V ≤ VIN ≤ VDD, all other pins not under test = 0 V −2 2 µA Output leakage current IO(L) DOUT is disabled, VO = 0 to VDDQ + 0.3 V −5 5 µA Output high current IOH VOUT = 1.95 V –15.2 mA Output low current IOL VOUT = 0.35 V 15.2 mA 13.6 AC Characteristics (Recommended Operating Conditions unless otherwise noted) 13.6.1 Test Conditions Parameter Symbol MIN. MAX. Unit Input Reference voltage (Input timing measurement reference level) VREF 0.49 x VDDQ 0.51 x VDDQ V VREF + 0.04 V VTT VREF − 0.04 High level ac input voltage VIH(ac) VREF + 0.31 Low level ac input voltage VIL(ac) Input differential voltage (CLK and /CLK) VID(ac) 0.7 Input signal slew rate SLEW 1 Termination voltage (Output timing measurement reference level) Notes 1 V VREF − 0.31 VDDQ + 0.6 V V V/ns 2 Notes 1. Output waveform timing is measured where the output signal crosses through the VTT level. 2. Slew rate is to be maintained in the VIL (ac) to VIH(ac) range of the input signal swing. SLEW = (VIH(ac)-VIL(ac))/ ∆t VTT RT = 50 Ω Output CLOAD = 30 pF Preliminary Data Sheet E0136E30 39 EDD1204ALTA, EDD1208ALTA, EDD1216ALTA 13.6.2 Timing Diagram tCK tCL tCH CLK VID(ac) /CLK tIS Command (Input) tIS tIH VREF + 0.31 V Valid Valid VREF - 0.31 V tIS Address (Input) tIH tIH tIS tIH VREF + 0.31 V Valid Valid VREF - 0.31 V tRPRE DQS (Output) (CL = 2) tRPST tDQSCK tDQSCK VTT tQH tDQSQ tAC tQH tDQSQ tAC DQ (Output) (CL = 2) VTT tRPRE tDQSCK DQS (Output) (CL = 2.5) tDQSS (MIN.) DQS (Input) tRPST tDQSCK VTT tQH tQH tDQSQ tDQSQ tAC tAC DQ (Output) (CL = 2.5) Valid Valid Valid VTT Valid tDQSH tDQSL tDSH tDQSS VREF + 0.31 V VREF VREF - 0.31 V tWPRES tWPST tWPRE VREF + 0.31 V DQ and DM (Input) VREF Valid Valid tDS tDH tDS tDH VREF - 0.31 V tDQSS (MAX.) DQS (Input) tDQSH tDQSL tDSS tDQSS VREF + 0.31 V VREF VREF - 0.31 V tWPRES tWPST tWPRE VREF + 0.31 V DQ and DM (Input) VREF Valid Valid tDS tDH tDS tDH VREF - 0.31 V 40 Preliminary Data Sheet E0136E30 EDD1204ALTA, EDD1208ALTA, EDD1216ALTA 13.6.3 Synchronous Characteristics Parameter Clock cycle time Symbol CL = 2.5 tCK CL = 2 -7A -75 1A Unit MIN. MAX. MIN. MAX. MIN. MAX. 7.5 12 7.5 12 10 12 7.5 12 10 12 10 12 ns CLK high-level width tCH 0.45 0.55 0.45 0.55 0.45 0.55 tCK CLK low-level width tCL 0.45 0.55 0.45 0.55 0.45 0.55 tCK DQ output access time from CLK, /CLK tAC –0.75 0.75 –0.75 0.75 –0.8 0.8 ns DQS output access time from CLK, /CLK tDQSCK –0.75 0.75 –0.75 0.75 –0.8 0.8 ns DQS-DQ skew (for DQS and associated DQ signals) tDQSQ 0.5 0.5 0.6 ns DQS-DQ skew (for DQS and all DQ signals) tDQSQA 0.5 0.5 0.6 ns Data out low-impedance time from CLK, /CLK tLZ –0.75 0.75 –0.75 0.75 –0.8 0.8 ns Data out high-impedance time from CLK, /CLK tHZ –0.75 0.75 –0.75 0.75 –0.8 0.8 ns Half clock period tHP MIN. (tCH, tCL) Read preamble tRPRE 0.9 1.1 0.9 1.1 0.9 1.1 tCK Read postamble tRPST 0.4 0.6 0.4 0.6 0.4 0.6 tCK DQ output hold time from DQS tQH tHP – 0.75 tHP – 0.75 tHP – 1 ns DQ and DM input setup time tDS 0.5 0.5 0.6 ns DQ and DM input hold time tDH 0.5 0.5 0.6 ns tDIPW 1.75 1.75 2 ns Write preamble setup time tWPRES 0 0 0 ns Write preamble tWPRE 0.25 0.25 0.25 tCK Write postamble tWPST 0.4 0.6 0.4 0.6 0.4 0.6 tCK Write command to first DQS latching transition tDQSS 0.75 1.25 0.75 1.25 0.75 1.25 tCK DQS input high pulse width tDQSH 0.35 0.35 0.35 tCK DQS input low pulse width tDQSL 0.35 0.35 0.35 tCK DQS falling edge to CLK setup time tDSS 0.2 0.2 0.2 tCK DQS falling edge hold time from CLK tDSH 0.2 0.2 0.2 tCK Address and control input setup time tIS 0.9 0.9 1.1 ns Address and control input hold time tIH 0.9 0.9 1.1 ns Address and control input pulse width tIPW 2.2 2.2 2.5 ns Internal write to read command delay tWTR 1 1 1 tCK DQ and DM input pulse width (for each input) MIN. (tCH, tCL) Preliminary Data Sheet E0136E30 MIN. (tCH, tCL) Note ns 41 EDD1204ALTA, EDD1208ALTA, EDD1216ALTA 13.6.4 Synchronous Characteristics Example Symbol tCK =7.5 ns tCK =10 ns Unit MIN. MAX. MIN. MAX. tCH 3.4 4.1 4.5 5.5 ns tCL 3.4 4.1 4.5 5.5 ns tRPRE 6.75 8.25 9 11 ns tRPST 3 4.5 4 6 ns tWPRE 1.88 tWPST 3 4.5 4 6 ns 9.4 7.5 12.5 ns 2.5 ns tDQSS 5.6 tDQSH 2.63 3.5 ns tDQSL 2.63 3.5 ns tDSS 1.5 2 ns tDSH 1.5 2 ns tWTR 7.5 10 ns 13.6.5 Asynchronous Characteristics Parameter Symbol -7A MIN. ACT to REF/ACT command period -75 MAX. MIN. -1A MAX. MIN. Unit MAX. tRC 65 65 70 ns REF to REF/ACT command period (refresh) tRFC 75 75 80 ns ACT to PRE command period tRAS 45 PRE to ACT command period tRP 20 20 20 ns ACT to READ/WRITE delay tRCD 20 20 20 ns ACT(one) to ACT(another) command period tRRD 15 15 15 ns Write recovery time tWR 2 2 2 CLK Auto precharge write recovery time + precharge tDAL 35 35 35 ns Mode register set command cycle time tMRD 15 15 15 ns Exit self refresh to command tXSNR 75 75 80 ns Average periodic Refresh interval tREF1 (operation) 120,000 45 120,000 50 120,000 ns time 42 15.6 Preliminary Data Sheet E0136E30 15.6 15.6 µs AC Parameters for Read Timing 1 (Manual Precharge, Burst Length = 4, /CAS Latency = 2.5) T0 tCK T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 CLK tCH tCL tCK /CLK tCL tCH ;;;;; ;;;; ;;; ;;; ; ;; ; ; ;; ; ; ;;; ; ;; ; ; ;; ; ; ;;; ; ;; ; ; ;; ; ; ; ; ;; ; ; ;;; ;; ; ; ;; ; ;; ; ; ; ; ;; ; ;; ; ; ; ; ; ;; ; ; ;; ; ;; ; ; ; ; ;; ; ;; ; ; ;; ; ; ; ; ;; ; ;; ; ; ;; ; ; ; ;; ; ;; ; ; ;; ; ; ;; ; ;; ; ; ;; ; ; ;; ; ;; ; ; ;; ; ; ;; ; ;; ; ; ;; ; ; ;; ; ;; ; ; ;; ; ; ;; ;; ; ; ; ;; ; ; ;; ;; ; ; ;; ; ; CKE tIH tIS tIS tIH /CS /RAS ;;;; ;;;; /WE BA0 BA1 A10 ADD tIS tIH DM L tDQSCK tDQSCK tDQSCK tDQSCK tRPRE DQS DQ VTT VTT tRPST Hi-Z tDQSQ tDQSQ tDQSQ tDQSQ tQH tQH tQH tQH tAC tAC tAC tAC Hi-Z tRCD tRAS tRP tRC 43 Activate Command for Bank A Read Command for Bank A Precharge Command for Bank A Activate Command for Bank A EDD1204ALTA, EDD1208ALTA, EDD1216ALTA Preliminary Data Sheet E0136E30 /CAS 44 AC Parameters for Read Timing 2 (Auto Precharge, Burst Length = 4, /CAS Latency = 2.5) T0 tCK T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 CLK ;;;;;; ;;;; ;;; ; ;; ;; ; ;; ; ; ;; ; ;; ;; ;; ; ;; ; ; ;; ; ;; ;; ; ;; ; ;; ; ; ;; ;; ;; ;; ; ;; ; ; ;; ;; ;; ;; ; ;; ; ; ;; ;; ;; ; ;; ;; ; ;; ; ; ;; ;; ;; ; ;; ;; ; ;; ; ; ; ;; ;; ; ;; ; ;; ; ; ; ;; ; ;; ; ;; ; ; ; ;; ;; ; ;; ; ; ; ;; ;; ; ;; ;; ; ;; ; ;; ;; ; ;; ;; ; ;; ; ;; ;; ; ;; ;; ; ;; ; ;; ;; ; ;; ;; ; ;; ; ;; ;;; ;; ;; ;; ; ;; ; ;; tCH tCL tCK /CLK tCL tCH CKE tIS tIS Auto Precharge Start for Bank C tIH tIH /CS /RAS BA0 BA1 A10 ADD tIS tIH DM ;;;; ;;;; /WE tDQSCK tDQSCK tDQSCK tDQSCK tRPRE DQS VTT tRPST Hi-Z tDQSQ DQ VTT tDQSQ tDQSQ tDQSQ Hi-Z tRCD tRAS tQH tQH tQH tQH tAC tAC tAC tAC tRRD tRC Activate Command for Bank C Bank C Read Command with Auto Precharge Activate Command for Bank D Activate Command for Bank C EDD1204ALTA, EDD1208ALTA, EDD1216ALTA Preliminary Data Sheet E0136E30 /CAS EDD1204ALTA, EDD1208ALTA, EDD1216ALTA Relationship between Frequency and Latency Speed version -7A -75 -1A Clock cycle time [ns] 7.5 7.5 7.5 10 10 10 Frequency [MHz] 133 133 133 100 100 100 /CAS latency 2.5 2 2.5 2 2.5 2 [tRCD] 3 3 3 2 2 2 5.5 5 5.5 4 4.5 4 [tRC] 9 9 9 7 7 7 [tRFC] 10 10 10 8 8 8 [tRAS] 6 6 6 5 5 5 [tRRD] 2 2 2 2 2 2 [tRP] 3 3 3 2 2 2 [tWR] 2 2 2 2 2 2 [tDAL] 5 5 5 4 4 4 /RAS latency (/CAS latency + [tRCD]) [tMRD] 2 2 2 2 2 2 [tXSNR] 10 10 10 8 8 8 Preliminary Data Sheet E0136E30 45 46 AC Parameters for Write Timing (Burst Length = 8, /CAS Latency = 2.5) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK /CLK CKE Auto Precharge Start for Bank C tIS tIS tIH tIH /CS /RAS /CAS BA0 BA1 A10 ADD tIS tIH DM tDQSS tWPRE tWPRES DQS VTT DQ VTT Hi-Z tDS tWPST tDH Hi-Z tRCD tDAL tRC tRRD tRCD tWR tRP tRAS tRC Bank C Activate Activate Write Command Command Command for Bank C with Auto Precharge for Bank B Bank B Write Command without Auto Precharge Activate Command for Bank C Precharge Command for Bank B Activate Command for Bank B EDD1204ALTA, EDD1208ALTA, EDD1216ALTA Preliminary Data Sheet E0136E30 /WE Mode Register Set (Burst Length = 4, /CAS Latency = 2) /WE BA0 BA1 A10 ADD ADDRESS KEY DM VTT Mode Register Set Command 47 tRP Activate Command is valid EDD1204ALTA, EDD1208ALTA, EDD1216ALTA ;;; ;; ;;; ;; ;; ; ;; ; ;; ;; ; ;; ; ; ;; ; ;; ;; ; ;; ; ; ;; ; ;; ;; ; ;; ; ; ;; ; ;; ;; ; ;; ; ; ;; ; ;; ;; ; ;; ; ; ;; ; ;; ;; ; ;; ; ; ;; ; ;; ;; ; ;; ; ; ;; ; ;; ;; ; ;; ; ; ;; ; ;; ;; ; ;; ; ; ;; ; ;; ;; ; ;; ; ; ;; ; ;; ;; ; ;; ; ; ;; ; ;; ;; ; ;; ; ;; ; ; ;; ; ;; ;; ; ; ;; ; ; ;; ;; ;; ; ; ;; ; ;; ;; ; ;; ; ;; ; ; ;; ;; ; ;; ; /CAS Preliminary Data Sheet E0136E30 DQ Hi-Z VTT Hi-Z DQS tMRD H CKE All Banks Precharge Command T21 T20 T19 T18 T17 T16 T15 T14 T13 T12 T11 T10 T9 T8 T7 T6 T5 T4 T3 T2 T1 T0 CLK /CLK /CS /RAS 48 Power On Sequence and CBR (auto) Refresh T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK /CLK CKE tMRD Low level is necessary 2 refresh cycles are necessary ;; ; ;; ;;; ;; ;; ; ;; ; ;; ; ;; ;; ; ; ;; ; ;; ; ;; ;; ; ; ;; ; ;; ; ; ;; ; ; ;; ; ;; ; ; ;; ; ; ;; ; ;; ; ; ;; ; ; ;; ; ;; ; ; ;; ; ; ;; ; ;; ; ; ; ;; ; ;; ; ;; ; ; ; ;; ; ;; ; ;; ; ; ; ;; ; ;; ; ;; ;; ; ; ; ; ; ;; ; ;; ;; ;; ; ; ; ; ;; ; ; ;; ;; ; ;; ; ; ;; ;; ; ;; ;; ;; ; ;; ; ; ; ;; ; ;; ;; ;; ;; ; ;; ; ; ; ; ;; ;; ; ;; ;; ;; ; ;; ; ;; ; ;; ;; ;; ; /CS /RAS /CAS BA0 BA1 A10 ADDRESS KEY ADDRESS KEY ADDRESS KEY ADD DM DQS VTT DQ VTT Hi-Z Hi-Z All Banks Precharge Command is necessary All Banks Extended Mode Mode Refresh Precharge Register Set Register Set Command Command Command Command is necessary is necessary (DLL enable / (DLL reset) disable) is necessary is necessary tMRD tMRD tRP Refresh Command is necessary tRFC Mode Register Set Command is necessary tRFC More than 200 cycles are necessary before Read command Activate Command EDD1204ALTA, EDD1208ALTA, EDD1216ALTA Preliminary Data Sheet E0136E30 /WE /CS Function (at 100 MHz, Burst Length = 4, /CAS Latency = 2.5) Only /CS signal needs to be issued at minimum rate T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK /CLK CKE H /CS /RAS /WE BA0 L BA1 L A10 RAa ADD RAa DM CAa L DQS VTT Hi-Z Hi-Z DQ CAb QAa1 QAa2 QAa3 QAa4 VTT 49 Activate Command for Bank A Read Command for Bank A DAb1 DAb2 DAb3 DAb4 Write Command for Bank A Precharge Command for Bank A EDD1204ALTA, EDD1208ALTA, EDD1216ALTA Preliminary Data Sheet E0136E30 /CAS 50 Power Down Mode (Burst Length = 4, /CAS Latency = 2) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK /CLK tIS CKE ;;;; ;;; ; ; ; ; ;; ; ; ; ; ; ;; ; ; ; ; ; ;; ; ; ; ; ; ;; ; ; ; ; ; ; ;; ; ;; ; ; ; ; ; ; ;; ; ; ; ; ; ; ;; ; ; ; ; ; ; ;; ; ; ; ; ; ; ;; ; ; ; ; ; ; ;; ; ; ; ; ; ; ;; ; ; ; ; ; ; ;; ; ; ; ; ; ; ;; ; ; ; ; ; ; ; ; ; ;; ; ; /CS /RAS /CAS BA0 BA1 A10 RAa ADD RAa CAa DM DQS VTT DQ VTT Hi-Z Hi-Z QAa1 QAa2 QAa3 QAa4 Precharge Command for Bank A Power Down Mode Entry PRECHARGE STANDBY Activate Command for Bank A Power Down Mode Exit Read Command for Bank A EDD1204ALTA, EDD1208ALTA, EDD1216ALTA Preliminary Data Sheet E0136E30 /WE CBR (auto) Refresh H CKE /WE BA0 BA1 A10 ADD DM CBR (auto) Refresh Precharge CBR (auto) Refresh Command is necessary tRFC tRFC 51 tRP Activate Command Read Command EDD1204ALTA, EDD1208ALTA, EDD1216ALTA ; ;; ;; ;; ;; ;; ; ; ; ;; ;; ; ;; ;; ; ; ;; ;; ;; ;; ; ; ; ; ;; ;; ;; ; ;; ; ; ;; ; ;; ;; ; ;; ; ; ;; ; ;; ;; ; ; ;; ; ;; ; ;; ;; ; ; ;; ; ;; ; ;; ;; ; ; ;; ; ;; ; ;; ;; ; ; ;; ; ;; ; ;; ;; ; ; ;; ; ;; ; ;; ;; ; ; ;; ; ;; ; ;; ;; ; ; ;; ; ;; ; ;; ;; ; ; ;; ; ;; ; ;; ;; ; ; ; ;; ;; ; ; ;; ;; ; ;; ; ;; ;; ;; ; ; ;; ; ; ;; ; ;; ; ;; ; ;; ; /CAS Preliminary Data Sheet E0136E30 VTT Q1 Q2 DQ Hi-Z VTT Hi-Z DQS T21 T20 T19 T18 T17 T16 T15 T14 T13 T12 T11 T10 T9 T8 T7 T6 T5 T4 T3 T2 T1 T0 CLK /CLK /CS /RAS 52 Self Refresh (Entry and Exit) ;;;;;;;;;; ;;; ; ; ; ; ;;;;;;;;;; ;;;;;;;;;; ;;;;;;;;;; ;;;;;;;;;; ;;;;;;;;;;;;;; ;;;;;;;;;; ;;;;;;;;;; T0 T1 T2 T3 T4 Tn Tn+1 Tn+2 Tm Tm+1 Tm+2 Tk Tj Tj+1 Tj+2 CLK /CLK CKE /CS /RAS /WE BA0 BA1 A10 ADD DM Hi-Z DQS VTT Hi-Z DQ VTT Precharge Command is necessary Self Refresh Entry tRP Self Refresh Self Refresh Entry Exit (or Activate Command) Self Refresh Exit tXSNR Next Clock Enable Activate Command tXSNR Next Clock Enable EDD1204ALTA, EDD1208ALTA, EDD1216ALTA Preliminary Data Sheet E0136E30 /CAS Random Column Read (Page with Same Bank) (1/2) (Burst Length = 4, /CAS Latency = 2) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 ;;;; ;;;; ;;; ; ; ;; ; ; ;; ;;;; ; ;; ;; ; ;; ; ; ;; ; ;; ; ;; ; ; ;; ;;;; ; ;; ;; ; ;; ; ; ;; ; ;; ; ;; ; ; ;; ;;;; ; ;; ;; ; ;; ; ; ;; ; ;; ;; ; ; ;; ; ;;;;; ; ;; ; ; ;; ;; ; ; ;; ; ;; ; ;; ; ; ;; ;;;; ; ;; ;; ;; ; ;; ; ; ; ;; ; ; ;; ; ;; ;;;; ; ;; ;; ; ;; ; ; ; ; ;; ;;; ;; ; ; ;; ; ;;;; ; ;; ;; ;; ; ;; ; ; ; ;; ; ;; ; ;; ; ;;;; ; ;; ; ;; ;; ; ; ;; ; ;; ;;;; ; ;; ; ; ;; ; ;; CLK /CLK H CKE /CS /RAS /WE BA0 BA1 A10 RAa ADD RAa RAd CAa CAb CAc RAd CAd DM DQS VTT DQ VTT Hi-Z Hi-Z 53 Activate Command for Bank A QAa1 QAa2 QAa3 QAa4 QAb1 QAb2 QAc1 QAc2 QAc3 QAc4 Read Command for Bank A Read Read Command Command for Bank A for Bank A Precharge Command for Bank A Activate Command for Bank A QAd1 QAd2 QAd3 QAd4 Read Command for Bank A EDD1204ALTA, EDD1208ALTA, EDD1216ALTA Preliminary Data Sheet E0136E30 /CAS 54 Random Column Read (Page with Same Bank) (2/2) (Burst Length = 4, /CAS Latency = 2.5) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK ;; ;;;; ;;; ;;; ; ;; ; ; ; ;; ; ; ;; ;; ; ; ; ;; ; ; ;; ;; ; ; ; ;; ; ; ;; ;; ; ; ; ;; ; ; ;; ; ; ;; ;; ; ; ; ; ;; ; ;; ;; ; ; ; ; ;; ; ;; ;; ; ; ; ; ;; ; ;; ;; ; ; ; ; ;; ;; ; ;; ; ; ; ; ;; ;; ; ;; ; ; ; ; ; ;; ; ;; ; ;; ; ; ; ; ;; ;; ; ;; ; ; ; ; ;; ;; ; ; ;; ; ; ; ;; ;; ; ; ;; ; ; ; ;; ; ;; ; ; ; ;; ; ;; ; ;; ; ; ; ;; ; ;; /CLK H CKE /CS /RAS /WE BA0 BA1 A10 RAa RAa ADD RAa CAa CAb CAc RAa CAa DM DQS VTT DQ VTT Hi-Z Hi-Z Activate Command for Bank A QAa1 QAa2 QAa3 QAa4 QAb1 QAb2 QAc1 QAc2 QAc3 QAc4 Read Command for Bank A Read Read Command Command for Bank A for Bank A Precharge Command for Bank A Activate Command for Bank A QAd1 QAd2 QAd3 QAd4 Read Command for Bank A EDD1204ALTA, EDD1208ALTA, EDD1216ALTA Preliminary Data Sheet E0136E30 /CAS Random Column Write (Page with Same Bank) (1/2) (Burst Length = 4, /CAS Latency = 2) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK /CLK H CKE /CS /RAS /WE BA0 BA1 A10 RDa ADD RDa RDd CDa CDb CDc RDd CDd DM DQS VTT DQ VTT Hi-Z Hi-Z Activate Command for Bank D DDa1 DDa2 DDa3 DDa4 DDb1 DDb2 DDc1 DDc2 DDc3 DDc4 Write Command for Bank D Write Command for Bank D 55 Write Command for Bank D DDd1 DDd2 DDd3 DDd4 Precharge Command for Bank D Activate Command for Bank D Write Command for Bank D EDD1204ALTA, EDD1208ALTA, EDD1216ALTA Preliminary Data Sheet E0136E30 /CAS 56 Random Column Write (Page with Same Bank) (2/2) (Burst Length = 4, /CAS Latency = 2.5) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK /CLK CKE H /CS /RAS /WE BA0 BA1 A10 RDa ADD RDa RDd CDa CDb CDc RDd CDd L DM DQS VTT DQ VTT Hi-Z Hi-Z Activate Command for Bank D DDa1 DDa2 DDa3 DDa4 DDb1 DDb2 DDc1 DDc2 DDc3 DDc4 Write Command for Bank D Write Command for Bank D Write Command for Bank D DDd1 DDd2 DDd3 DDd4 Precharge Command for Bank D Activate Command for Bank D Write Command for Bank D EDD1204ALTA, EDD1208ALTA, EDD1216ALTA Preliminary Data Sheet E0136E30 /CAS Random Row Read (Ping-Pong Banks) (1/2) (Burst Length = 8, /CAS Latency = 2) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK ;;;;;;;;;;; ; ; ;; ; ;;;;; ;; ; ;; ; ; ; ;; ; ;; ; ; ; ;; ; ;;;;; ;; ; ;; ; ; ;; ; ; ;; ; ; ; ;; ; ;;;;; ;; ; ;; ; ; ; ;; ; ;; ; ; ; ;; ; ;;;;; ;; ; ;; ; ;; ; ;; ;;;;;; ;;;; ; ;;;; ;; ; ;; ; ; ;; ; ;; ; ;;; ; ; ;; ; ;;;; ;; ; ; ; ; ;; ; ;; ; ;;; ; ; ;; ; ;;;; ;; ; ;; ; ; ; ; ;; ;; ; ; ; ;; ; ;;;;; ;; ; ; ; ; ;; ;; ; ; ;;;; ;;; ; ; ;; ;; ; ; /CLK H CKE /CS /RAS /WE BA0 BA1 A10 RDa ADD RDa RDb RBa CDa RBa CBa RDb CDb DM DQS VTT DQ VTT Hi-Z Hi-Z QDa1 QDa2 QDa3 QDa4 QDa5 QDa6 QDa7 QDa8 QBa1 QBa2 QBa3 QBa4 QBa5 QBa6 QBa7 QBa8 Activate Command for Bank D Read Command for Bank D Activate Command for Bank B Read Command for Bank B 57 Precharge Command for Bank D Activate Command for Bank D QDb1 QDb2 QDb3 QDb4 QDb5 QDb6 QDb7 QDb8 Read Command for Bank D EDD1204ALTA, EDD1208ALTA, EDD1216ALTA Preliminary Data Sheet E0136E30 /CAS 58 Random Row Read (Ping-Pong Banks) (2/2) (Burst Length = 8, /CAS Latency = 2.5) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK ; ;; ;;; ;;; ;;; ;;;; ;; ; ; ; ;; ; ;; ;; ; ;; ; ; ;; ; ;; ;;;; ;; ; ; ; ; ;; ;; ; ;; ; ; ;; ; ;; ; ;;;;;; ;; ; ;; ; ; ; ;; ; ;; ; ;; ; ; ; ;;;;; ;; ; ; ; ;; ; ;; ; ; ;; ;; ; ; ; ; ;;;;; ;; ; ; ;; ; ; ; ;; ; ; ; ;;;; ;; ; ;;;;;; ;;; ; ; ;; ; ; ; ; ;; ;; ; ;;;;; ;; ; ;; ; ; ; ;; ; ;; ; ;; ; ; ; ;;;;; ;; ; ;; ; ; ; ; ;; ; ; ;; ; ; ;;;; ;;; ;; ; ; ;; ; ; /CLK H CKE /CS /RAS /WE BA0 BA1 A10 RBa ADD RBa RAa CBa RAa RBb CAa RBb CBb DM DQS VTT DQ VTT Hi-Z Hi-Z QBb1 QBb2 QBb3 QBb4 QBb5 QBb6 QBb7 QBa1 QBa2 QBa3 QBa4 QBa5 QBa6 QBa7 QBa8 QAa1 QAa2 QAa3 QAa4 QAa5 QAa6 QAa7 QAa8 Activate Command for Bank B Read Command for Bank B Activate Command for Bank A Read Command for Bank A Precharge Command for Bank B Activate Command for Bank B Read Command for Bank B Precharge Command for Bank A EDD1204ALTA, EDD1208ALTA, EDD1216ALTA Preliminary Data Sheet E0136E30 /CAS Random Row Write (Ping-Pong Banks) (1/2) (Burst Length = 8, /CAS Latency = 2) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK /CLK ;;;;;; ;;;;;;;;;;;; ;;;;;;;;;;; ;;;;;;;;;;; ;;;;;;;;;;; ;;;;;;;;;; ;;;;;;;;;;; ;;;;;;;;;;;; ;;;;;;;;;;;; H CKE /CS /RAS /WE BA0 BA1 A10 RAa ADD RAa RDa CAa RDa RAb RAb CDa CAb L DM Hi-Z DQS VTT DQ VTT Hi-Z Activate Command for Bank A DAa1 DAa2 DAa3 DAa4 DAa5 DAa6 DAa7 DAa8 DDa1 DDa2 DDa3 DDa4 DDa5 DDa6 DDa7 DDa8 Write Command for Bank A Activate Command for Bank D Write Command for Bank D Precharge Command for Bank A Activate Command for Bank A DAb1 DAb2 DAb3 DAb4 DAb5 DAb6 DAb7 DAb8 Write Command for Bank A 59 Precharge Command for Bank D EDD1204ALTA, EDD1208ALTA, EDD1216ALTA Preliminary Data Sheet E0136E30 /CAS 60 Random Row Write (Ping-Pong Banks) (2/2) (Burst Length = 8, /CAS Latency = 2.5) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK /CLK CKE H /CS /RAS /WE BA0 BA1 A10 RAa ADD RAa RAb RDa RDa CAa RAb CDa CAb L DM DQS VTT DQ VTT Hi-Z Hi-Z DAa1 DAa2 DAa3 DAa4 DAa5 DAa6 DAa7 DAa8 DDa1 DDa2 DDa3 DDa4 DDa5 DDa6 DDa7 DDa8 DAb1 DAb2 DAb3 DAb4 DAb5 DAb6 DAb7 DAb8 Hi-Z Activate Command for Bank A Write Command for Bank A Activate Command for Bank D Write Command for Bank D Precharge Command for Bank A Activate Command for Bank A Precharge Command for Bank D Write Command for Bank A EDD1204ALTA, EDD1208ALTA, EDD1216ALTA Preliminary Data Sheet E0136E30 /CAS Read and Write (1/2) (Burst Length = 8, /CAS Latency = 2) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK /CLK CKE H ;;;;; ;;;;; ;; ; ;;; ; ;; ;; ; ;; ; ;;; ; ;; ;; ; ;; ; ;;; ; ;; ;; ; ;; ; ;;; ; ;; ;; ; ;; ;;; ; ;; ;; ; ;; ; ;;; ; ;; ;; ; ;; ;;; ; ;; ;; ; ;; ; ; ; ; ;; ;; ; ;;;;;; ;;; ;; ; ; ;; ; ;;; ; ;; ;; ; ; ;; ; ;;; ; ;; ;; ; ; ;; ; ;;; ; ;; ;; ; ; ;; ; ;;; ;; ; ;; ;; ; ; ;; ; ;;; ;; ; ;; ;; ; ;; ; ;;; ;; ; ;; ; ;;; ; ;; ;; ; ;; ; /CS /RAS /WE BA0 BA1 A10 RAa ADD RAa CAb CAa CAc DM Word Masking DQS VTT DQ VTT Hi-Z Hi-Z Activate Command for Bank A QAa1 QAa2 QAa3 QAa4 QAa5 QAa6 QAa7 QAa8 Read Command for Bank A Hi-Z at the end of wrap function DAb1 QAc1 QAc2 QAc3 QAc4 QAc5 QAc6 QAc7 QAc8 DAb3 DAb4 DAb5 DAb6 DAb7 DAb8 Write Command for Bank A 61 0-Clock Latency Read Command for Bank A EDD1204ALTA, EDD1208ALTA, EDD1216ALTA Preliminary Data Sheet E0136E30 /CAS 62 Read and Write (2/2) (Burst Length = 8, /CAS Latency = 2.5) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK ;;;;; ;; ;;;;;; ;; ; ; ;; ;; ; ;; ; ; ;; ;; ; ;; ; ;;;;; ; ;; ; ; ;; ;; ; ;; ; ; ;; ;; ; ;; ;;;;; ;; ; ; ;; ;; ; ;; ; ;; ;; ; ;; ;;;;; ; ;; ; ; ; ;; ; ; ; ;;;;;; ;;; ;; ;; ;;;; ; ; ; ;; ;; ; ;; ; ;;; ; ;; ;; ; ;; ;;;; ; ; ; ;; ;; ; ;; ; ;;; ; ;; ;; ; ;; ; ;;;; ; ; ; ;; ; ;; ; ;; ;; ; ; ;; ;; ;; ; ;;;;; ; ; ;; ; ; ;; ; ;;;; ;;;;;; ;;; ;; ; ;; ; /CLK H CKE /CS /RAS /WE BA0 BA1 A10 RAa ADD RAa CAb CAa CAc DM Word Masking DQS VTT DQ VTT Hi-Z Hi-Z Activate Command for Bank A QAa1 QAa2 QAa3 QAa4 QAa5 QAa6 QAa7 QAa8 Read Command for Bank A DAb1 QAc1 QAc2 QAc3 DAb3 DAb4 DAb5 DAb6 DAb7 DAb8 Write Command for Bank A Read Command for Bank A 0-Clock Latency EDD1204ALTA, EDD1208ALTA, EDD1216ALTA Preliminary Data Sheet E0136E30 /CAS Interleaved Column Read Cycle (1/2) (Burst Length = 8, /CAS Latency = 2) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK /CLK H CKE /CS ;;;;; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ;;;; ; ; ; ; ; ; ; ; ; ; ; ; ; ;; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; /RAS /WE BA0 BA1 A10 RAa ADD RAa RDa CAa RDa CDa CDb CDc CAb CDd DQM Hi-Z DQS VTT DQ VTT Hi-Z Activate Command for Bank A Aa1 Aa2 Aa3 Aa4 Aa5 Aa6 Aa7 Aa8 Da1 Da2 Da3 Da4 Db1 Db2 Db3 Db4 Dc1 Dc2 Dc3 Dc4 Ab1 Ab2 Ab3 Ab4 Dd1 Dd2 Dd3 Dd4 Dd5 Dd6 Dd7 Dd8 Read Command for Bank A 63 Activate Command for bank D Read Command for Bank D Read Command for Bank D Read Command for Bank D Read Command for Bank A Read Command for Bank D Precharge Command for Bank A Precharge Command for Bank D EDD1204ALTA, EDD1208ALTA, EDD1216ALTA Preliminary Data Sheet E0136E30 /CAS 64 Interleaved Column Read Cycle (2/2) (Burst Length = 8, /CAS Latency = 2.5) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK /CLK ;;;;;; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ;; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; H CKE /CS /RAS /WE BA0 BA1 A10 RAa ADD RAa RDa CAa RDa CDa CDb CDc CAb L DQM DQS VTT DQ VTT Hi-Z Hi-Z Activate Command for Bank A Aa1 Aa2 Aa3 Aa4 Aa5 Aa6 Aa7 Aa8 Da1 Da2 Da3 Da4 Db1 Db2 Db3 Db4 Dc1 Dc2 Dc3 Dc4 Ab1 Ab2 Ab3 Ab4 Ab5 Ab6 Ab7 Ab8 Read Command for Bank A Activate Command for Bank D Read Command for Bank D Read Command for Bank D Read Command for Bank D Read Command for Bank A Precharge Command for Bank D Precharge Command for Bank A EDD1204ALTA, EDD1208ALTA, EDD1216ALTA Preliminary Data Sheet E0136E30 /CAS Interleaved Column Write Cycle (1/2) (Burst Length = 8, /CAS Latency = 2) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK /CLK CKE H /CS /RAS /WE BA0 BA1 A10 RAa ADD RAa RBa CAa RBa CBa CBb CBc CAb CBd DM DQS VTT DQ VTT Hi-Z Hi-Z Aa1 Aa2 Aa3 Aa4 Aa5 Aa6 Aa7 Aa8 Ba1 Ba2 Ba3 Ba4 Bb1 Bb2 Bb3 Bb4 Bc1 Bc2 Bc3 Bc4 Ab1 Ab2 Ab3 Ab4 Bd1 Bd2 Bd3 Bd4 Bd5 Bd6 Bd7 Bd8 Activate Command for Bank A Write Command for Bank A Write Command for Bank B 65 Activate Command for Bank B Write Command for Bank B Write Command for Bank B Write Command for Bank A Write Command for Bank B Precharge Command for Bank A Precharge Command for Bank B EDD1204ALTA, EDD1208ALTA, EDD1216ALTA Preliminary Data Sheet E0136E30 /CAS 66 Interleaved Column Write Cycle (2/2) (Burst Length = 8, /CAS Latency = 2.5) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23 CLK /CLK H CKE /CS /RAS /WE BA0 BA1 A10 RAa ADD RAa RBa CAa RBa CBa CBb CBc CAb CBd DQM Hi-Z DQS VTT DQ VTT Hi-Z Activate Command for Bank A Aa1 Aa2 Aa3 Aa4 Aa5 Aa6 Aa7 Aa8 Ba1 Ba2 Ba3 Ba4 Bb1 Bb2 Bb3 Bb4 Bc1 Bc2 Bc3 Bc4 Ab1 Ab2 Ab3 Ab4 Bd1 Bd2 Bd3 Bd4 Bd5 Bd6 Bd7 Bd8 Write Command for Bank A Activate Command for Bank B Write Command for Bank B Write Command for Bank B Write Command for Bank B Write Command for Bank A Write Command for Bank B Precharge Command for Bank A Precharge Command for Bank B EDD1204ALTA, EDD1208ALTA, EDD1216ALTA Preliminary Data Sheet E0136E30 /CAS Auto Precharge after Read Burst (1/2) (Burst Length = 8, /CAS Latency = 2) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 ;;;; ;; ;;; ;; ; ;; ; ; ; ; ;; ; ;; ; ; ; ; ;; ; ;; ; ; ; ; ;; ; ; ;; ; ; ; ;; ;; ; ; ; ; ; ;; ;; ; ; ; ; ; ;; ;; ; ; ; ; ; ;; ;; ; ; ; ; ; ;; ;; ; ; ; ; ; ;; ;; ; ; ; ; ; ;; ;; ; ; ; ; ; ;; ;; ; ; ; ; ; ;; ;; ; ; ; ; ; ;; ;; ; ; ; ; ; ;; ;; ; ; ; ; ; ; ;; ;; ; ; ; ; CLK /CLK CKE H /CS /RAS /CAS BA0 BA1 A10 RAa ADD RAa RDa CAa RDb RDa CDa CAb RDb RAc CDb RAc CAc DM Hi-Z DQS VTT DQ VTT Hi-Z Activate Command for Bank A Activate Command for Bank D Bank A Read Command without Auto Precharge Bank D Read Command with Auto Precharge Bank A Read Command with Auto Precharge 67 Auto Precharge Start for Bank D Activate Command for Bank D Auto Precharge Start for Bank A Activate Command for Bank A Auto Precharge Start for Bank D Bank D Read Command with Auto Precharge Bank A Read Command with Auto Precharge EDD1204ALTA, EDD1208ALTA, EDD1216ALTA Preliminary Data Sheet E0136E30 /WE 68 Auto Precharge after Read Burst (2/2) (Burst Length = 8, /CAS Latency = 2.5) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK ;;;;; ;;;; ; ;; ; ;; ; ; ;;;; ; ; ;; ; ; ; ;; ; ;; ; ; ;;;; ; ; ; ; ;; ; ;; ;; ; ; ; ;;;; ; ;; ; ; ; ; ; ; ;; ;; ; ;;;; ; ;; ; ; ; ; ;; ;; ; ; ; ;;;; ; ;; ; ; ; ; ;; ;; ; ; ; ;;;; ; ;; ; ; ; ; ;; ;; ; ; ; ;;;; ; ;; ; ; ; ; ;; ;; ; ; ; ;;;; ;; ; ; ; ; /CLK CKE H /CS /RAS /CAS BA0 BA1 A10 RAa ADD RAa RDa CAa RDa RDb CDa CAb RDb CDb DM DQS VTT DQ VTT Hi-Z Hi-Z Activate Command for Bank A Activate Command for Bank D Bank A Read Command without Auto Precharge Bank A Read Command with Auto Precharge Bank D Read Command with Auto Precharge Auto Precharge Start for Bank D Auto Precharge Start for Bank A Activate Command for Bank D Bank D Read Command with Auto Precharge EDD1204ALTA, EDD1208ALTA, EDD1216ALTA Preliminary Data Sheet E0136E30 /WE Auto Precharge after Write Burst (1/2) (Burst Length = 8, /CAS Latency = 2) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK /CLK CKE H /CS /RAS /CAS BA0 BA1 A10 RAa ADD RAa DM RDa CAa RDb RDa CDa CAb RDb RAc CDb RAc CAc L DQS VTT DQ VTT Hi-Z Hi-Z Activate Command for Bank A Activate Command for Bank D Bank A Write Command without Auto Precharge Bank D Write Command with Auto Precharge Activate Command for Bank A Activate Command for Bank D Bank A Write Command with Auto Precharge Bank D Write Command with Auto Precharge 69 Auto Precharge Start for Bank D Bank A Write Command with Auto Precharge Auto Precharge Start for Bank A EDD1204ALTA, EDD1208ALTA, EDD1216ALTA Preliminary Data Sheet E0136E30 /WE 70 Auto Precharge after Write Burst (2/2) (Burst Length = 8, /CAS Latency = 2.5) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK /CLK H CKE /CS /RAS /CAS BA0 BA1 A10 RAa ADD RAa RDa CAa RDa RDb CDa CAb RDb CDb DM DQS VTT DQ VTT Hi-Z Hi-Z Activate Command for Bank A Activate Command for Bank D Bank A Write Command without Auto Precharge Bank A Write Command with Auto Precharge Activate Command for Bank D Bank D Write Command with Auto Precharge Auto Precharge Start for Bank D Bank D Write Command with Auto Precharge Auto Precharge Start for Bank A EDD1204ALTA, EDD1208ALTA, EDD1216ALTA Preliminary Data Sheet E0136E30 /WE Byte Write Operation (Burst Length = 8, /CAS Latency = 2) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 ;;;;; ;;;;; ; ; ;; ; ;; ; ; ;;;; ; ; ; ;; ; ; ; ; ;; ; ;; ; ; ;;;; ; ; ; ;; ; ; ;; ; ; ; ; ;; ; ;;;; ; ;; ; ; ; ; ; ;; ; ;; ; ; ;;;; ; ; ;; ; ; ; ; ;; ; ;; ; ; ;;;; ; ; ; ;; ; ; ; ; ;; ; ;; ; ; ;;;; ; ; ; ;; ; ; ; ; ;; ; ;; ; ; ;;;; ; ; ; ;; ; ; ; ; ;; ; ;; ; ; ;;;; ; ; ; ; ; CLK /CLK H CKE /CS /RAS /CAS BA0 BA1 A10 ADD LDM UDM Hi-Z LDQS VTT UDQS VTT Lower DQ VTT Upper DQ VTT Hi-Z Hi-Z Hi-Z Activate Command Read Command Lower Byte Lower Byte not Write not Write Upper Byte not Write 71 Read Command EDD1204ALTA, EDD1208ALTA, EDD1216ALTA Preliminary Data Sheet E0136E30 /WE 72 PRE (Precharge) Termination of Burst (1/2) (Burst Length = 8, /CAS Latency = 2) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK /CLK ;;;;;; ;;;;;;;;;;;; ;;;;;;;;; ;;;;;;;;;;;; ;;;;;;;;;;;; ;;;;;;;;;;;; ;;;;;;;;;;;; ;;;;;;;;;;;; ;;;;;;;;;;;; H CKE /CS /RAS /CAS BA0 BA1 A10 RAa ADD RAa RAb CAa RAb RAc CAb RAc Write Mask DM DQS VTT DQ VTT Hi-Z Hi-Z QAb1 QAb2 QAb3 QAb4 QAb5 QAb6 DAa1 DAa2 DAa3 DAa4 Activate Command for Bank A Write Command for Bank A Read Command for Bank A Precharge PRE Command Command for Bank A Termination tRAS Precharge Command for Bank A Activate Command for Bank A Activate Command for Bank A tRP tRAS tRP PRE Command Termination EDD1204ALTA, EDD1208ALTA, EDD1216ALTA Preliminary Data Sheet E0136E30 /WE PRE (Precharge) Termination of Burst (2/2) (Burst Length = 8, /CAS Latency = 2.5) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK ;;;;;; ;;; ;; ; ;; ;;;;;;;;;; ;;; ;; ; ;; ;;;;;;;;;; ;;; ;; ; ;; ;;;;;;;;;; ;;; ;; ; ;; ;;;;;;;;;; ;;; ;; ; ;; ;;;;;;;;;; ;;; ;; ;; ; ;; ;;;;;;;;;; ; ;; ;; ; ;; ;;;;;;;;;;; ;; ; ;; ;;;;;;;;;; ;;; /CLK CKE H /CS /RAS /CAS BA0 BA1 A10 RAa ADD RAa RAb CAa RAb RAc CAb RAc Write Mask DM DQS VTT DQ VTT Hi-Z Hi-Z QAb1 QAb2 QAb3 QAb4 QAb5 QAb6 DAa1 DAa2 DAa3 DAa4 Activate Command for Bank A Write Command for Bank A PRE Command Termination 73 tRAS Read Command for Bank A Precharge Command for Bank A Activate Command for Bank A tRP tRAS Precharge Command for Bank A Activate Command PRE Command for Bank A Termination tRP EDD1204ALTA, EDD1208ALTA, EDD1216ALTA Preliminary Data Sheet E0136E30 /WE EDD1204ALTA, EDD1208ALTA, EDD1216ALTA 14. Package Drawing 66-PIN PLASTIC TSOP (II) (10.16 mm (400)) detail of lead end 66 34 F G R P L S 1 E 33 A H I J S C D M N L S K M B NOTES 1. Each lead centerline is located within 0.12 mm of its true position (T.P.) at maximum material condition. 2. Dimension "A" does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.15mm per side. ITEM A MILLIMETERS 22.22±0.05 B 0.865 MAX. C 0.65 (T.P.) D 0.24+0.08 −0.07 E 0.10±0.05 F 1.1±0.1 G 1.00 H 11.76±0.20 I 10.16±0.10 J 0.80±0.2 K 0.145+0.025 −0.015 L 0.50 M 0.12 N 0.10 P 3°+5° −3° R 0.25 S 0.60±0.15 S66G5-65-9LG-1 74 Preliminary Data Sheet E0136E30 EDD1204ALTA, EDD1208ALTA, EDD1216ALTA 15. Recommended Soldering Conditions Please contact our sales offices for soldering conditions of EDD12xxALTA. Type of Surface Mount Device EDD12xxALTA: 66-pin Plastic TSOP (II) (10.16 mm (400)) Preliminary Data Sheet E0136E30 75 EDD1204ALTA, EDD1208ALTA, EDD1216ALTA 16. Revision History Version / Date Ver. 1.0 / Page Description This edition Previous edition Type of revision Location — — — — April. 2001 — — — — Ver. 2.0 / 27 27 Modification Figure of Write to Precharge Command Interval May. 2001 29 29 Modification Figure of Write with Auto precharge 36 36 Modification Figure of Precharge Termination in Write Cycle 41 41 Modification tCK (CL = 2.5) (MIN.) : 8 ns to 10 ns 42 42 Modification tWR (MIN.) : 15/15/15 ns to 2/2/2 CLK 46 46 Modification AC Parameters for Write Timing 55 55 Modification Random Column Write (1/2) 56 56 Modification Random Column Write (2/2) 60 60 Modification Random Row Write (2/2) 65 65 Modification Interleaved Column Write Cycle (1/2) 66 66 Modification Interleaved Column Write Cycle (2/2) 69 69 Modification Auto Precharge after Write Burst (1/2) Auto Precharge after Write Burst (2/2) 70 70 Modification Ver. 3.0 38 38 Addition DC Characteristics specification October 2001 39 39 Modification VIH (ac) (MIN.): VREF + 0.35 to VREF + 0.31 41 41 Modification tHP (MIN.): tCH, tCL to MIN. (tCH, tCL) 42 42 Modification tWPRE (MIN.) (tCK = 7.5ns): 0.25 ns to 1.88 ns 42 42 Modification tDAL (MIN.): TBD to 35 ns 45 45 Modification [tDAL]: to 5/5/5/4/4/4 VIL (ac) (MAX.): VREF + 0.35 to VREF - 0.31 76 Preliminary Data Sheet E0136E30 EDD1204ALTA, EDD1208ALTA, EDD1216ALTA NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR MOS DEVICES Exposing the MOS devices to a strong electric field can cause destruction of the gate oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it, when once it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. MOS devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. MOS devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor MOS devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES No connection for CMOS devices input pins can be a cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. The unused pins must be handled in accordance with the related specifications. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Power-on does not necessarily define initial status of MOS devices. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the MOS devices with reset function have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. MOS devices are not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for MOS devices having reset function. CME0107 Preliminary Data Sheet E0136E30 77 EDD1204ALTA, EDD1208ALTA, EDD1216ALTA The information in this document is subject to change without notice. Before using this document, confirm that this is the latest version. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Elpida Memory, Inc. Elpida Memory, Inc. does not assume any liability for infringement of any intellectual property rights (including but not limited to patents, copyrights, and circuit layout licenses) of Elpida Memory, Inc. or third parties by or arising from the use of the products or information listed in this document. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of Elpida Memory, Inc. or others. Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of the customer's equipment shall be done under the full responsibility of the customer. Elpida Memory, Inc. assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. [Product applications] Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability. However, users are instructed to contact Elpida Memory's sales office before using the product in aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment, medical equipment for life support, or other such application in which especially high quality and reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk of bodily injury. [Product usage] Design your application so that the product is used within the ranges and conditions guaranteed by Elpida Memory, Inc., including the maximum ratings, operating supply voltage range, heat radiation characteristics, installation conditions and other related characteristics. Elpida Memory, Inc. bears no responsibility for failure or damage when the product is used beyond the guaranteed ranges and conditions. Even within the guaranteed ranges and conditions, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Elpida Memory, Inc. products does not cause bodily injury, fire or other consequential damage due to the operation of the Elpida Memory, Inc. product. [Usage environment] This product is not designed to be resistant to electromagnetic waves or radiation. This product must be used in a non-condensing environment. If you export the products or technology described in this document that are controlled by the Foreign Exchange and Foreign Trade Law of Japan, you must follow the necessary procedures in accordance with the relevant laws and regulations of Japan. Also, if you export products/technology controlled by U.S. export control regulations, or another country's export control laws or regulations, you must follow the necessary procedures in accordance with such laws or regulations. If these products/technology are sold, leased, or transferred to a third party, or a third party is granted license to use these products, that third party must be made aware that they are responsible for compliance with the relevant laws and regulations. M01E0107