Sony CXA2149 Us audio multiplexing decoder Datasheet

CXA2149Q
I2C-Bus-Compatible Audio/Video Switch
For the availability of this product, please contact the sales office.
Description
The CXA2149Q is a video and audio switch IC
featuring I2C bus compatibility for TV’s. The IC has
input pins that are compatible with the SCART
protocols. It offers other features such as an
electronic mute function with switching noise
reduction (zero cross detection), electronic volume
control, automatic SYNC pulse detection, and group
delay control.
Features
• 3 CVBS inputs.
• 2 CVBS outputs.
• Group delay control on TV and CVIN1.
• SYNC ID on TV and CVIN1.
• 3 Y/C inputs.
• 2 Y/C outputs.
• 6 L/R/2 inputs.
• 3 L/R/2 outputs.
• Mode inputs compatible with the SCART protocol.
• 3 Y/C mixer circuits.
• Audio muting via software control.
• External muting input.
• Audio switching noise elimination circuit.
• Volume adjustment via software control on L/R
channel 3.
• Wide band video amplifiers (20 MHz, –3 dB).
• Wide audio dynamic range (3 Vrms typ)
• Serial control via I2C bus.
• Separate control of video and audio switches.
• High impedance maintained by I 2C lines (SDA,
SCL) even when power is off.
• Configurable dual slave address 90/92.
• I2C bus 5 and 3.3 V compatible.
64 pin QFP (Plastic)
Absolute Maximum Ratings
(Ta=25 °C unless stated)
• Supply voltage
VCC
12
V
• Storage temperature
Tstg –65 to +150 °C
• Allowable power dissipation
PD
900
mW
Operating Conditions
• Supply voltage
• Typical supply current
• Operating temperature
VCC
Topr
9+/–0.5
75
–20 to +75
V
mA
°C
Applications
TV’s
Structure
Bipolar silicon monolithic IC
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
—1—
E99946A9Y-TE
CXA2149Q
Block Diagram
SYNC
DETECT
64
CVIN1
62
CVIN2
60
REXT
1
RGD1
7
RGD2
6
RGD3
4
RGD4
3
Y1
58
Y2
56
Y3
54
TRAP3
53
C1
52
C2
51
C3
49
DVCC
44
MODE1
18
MODE2
19
MODE3
20
MUTE
17
SDA
15
SCL
14
ADR
16
DGND
42
LO0
5
LO1
8
LTV
LV1
LV2
29
LV3
28
LV4
27
LV5
26
RTV
32
RV1
37
RV2
36
RV3
35
RV4
34
RV5
33
TC1
61
TC2
2
TVOUT
9
CVOUT1
11
YOUT1
10
TRAP1
13
COUT1
43
CVOUT2
45
YOUT2
46
TRAP2
47
COUT2
59,
12
VVCC1, 2
55
VBIAS
6dB
I 2C
TV
63
GROUP
DELAYS
I 2C
6dB
0dB
0dB
6dB
0dB
I 2C
LOGIC
0dB
BIAS
57,
48
VGND1, 2
21
AVCC
25
22
ABIAS
30
31
AGND
39
LOUT1
38
ROUT1
41
LOUT2
40
ROUT2
23
LOUT3
24
ROUT3
BIAS
6dB
–6dB
6dB
–6dB
6dB
6dB
6dB
0 to –63dB
6dB
0 to –63dB
—2—
CXA2149Q
C2
NC
C3
VGND2
COUT2
TRAP2
YOUT2
DVCC
CVOUT2
DGND
LOUT2
ROUT2
LOUT1
ROUT1
RV1
RV2
RV3
RV4
RV5
Pin Configuration
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
C1
52
32 RTV
TRAP3
53
31 AGND
Y3
54
30 LV1
VBIAS
55
29 LV2
Y2
56
28 LV3
VGND1
57
27 LV4
Y1
58
VVCC1
59
25 LTV
CVIN2
60
24 ROUT3
TC2
61
23 LOUT3
CVIN1
62
22 ABIAS
TC1
63
21 AVCC
TV
64
20 MODE3
RGD4
RGD3
LO0
RGD2
RGD1
LO1
CVOUT1
11
12
13
14
15
16
17
18
19
MODE2
TVOUT
10
MODE1
9
MUTE
8
ADR
7
SDA
6
SCL
5
COUT1
4
VVCC2
3
YOUT1
2
26 LV5
TRAP1
1
REXT
CXA2149Q
—3—
CXA2149Q
Pin Description
Pin
No
64
62
60
Symbol
Pin
voltage (V)
Equivalent circuit
TV
CVIN1
CVIN2
VCC
Video signal inputs.
64 58
3.9
58
56
54
Description
147
62 56
60 54
Y1
Y2
Y3
0.5µ
Luminance signal inputs.
VCC
5.2V
52
51
49
C1
C2
C3
20k
52
4.5
Chrominance signal inputs.
51
147
49
100µ
25
30
29
28
27
26
32
37
36
35
34
33
9
43
11
45
13
47
LTV
LV1
LV2
LV3
LV4
LV5
RTV
RV1
RV2
RV3
RV4
RV5
CVOUT1
CVOUT2
YOUT1
YOUT2
COUT1
COUT2
2
TVOUT
VCC
4.5V
25 32
30 37
4.5
33k
Audio signal inputs.
29 36
28 35
33k
27 34
26 33
VCC
3.8
3.5
Composite video signal outputs.
9
43
4.5
11
45
Luminance signal outputs.
13
47
Chrominance signal outputs.
2
1.8m
3.8
TV signal group delayed output.
—4—
CXA2149Q
Pin
No
Symbol
Pin
voltage (V)
Equivalent circuit
Description
VCC
7
3
RGD1
RGD4
4.5
7
Group delay output to external
filter.
3
0.5m
VCC
6
4
RGD2
RGD3
4.5
1.7k
6
Group delay inputs from external
filter.
4
VCC
3.8V
1
REXT
44
59
12
21
42
57
48
31
DVCC
VVCC1
VVCC2
AVCC
DGND
VGND1
VGND2
AGND
1.7
1
Pin connection for 39 kΩ group delay
setting resistor. Pin voltage is group
delay control dependent.
Digital supply.
Video supply.
Video supply.
Audio supply.
Digital ground.
Video ground.
Video ground.
Audio ground.
9
0
—5—
CXA2149Q
Pin
No
Symbol
Pin
voltage (V)
Equivalent circuit
Description
VCC
39
41
23
38
40
24
LOUT1
LOUT2
LOUT3
ROUT1
ROUT2
ROUT3
39
56
4.5
41
20k
23
Audio signal outputs.
38
40
24
VCC
20k
22
ABIAS
4.5
22
4.5V
Internal reference bias for audio
circuits. A capacitor is connected
from this pin to GND.
20k
VCC
55
14
VBIAS
4.5
55
4.5V
4k
SCL
Internal reference bias for video
circuits. A capacitor is connected
from this pin to GND.
I2C bus clock line.
14
15
15
SDA
16
ADR
I2C bus data line.
VCC
Slave address control.
16
17
72k
28k
17
Audio signal output mute.
MUTE
—6—
CXA2149Q
Pin
No
Symbol
Pin
voltage (V)
Equivalent circuit
Description
VCC
5
8
LO0
LO1
5
I 2C
control
Open collector logic outputs.
8
18
18
19
20
MODE1
MODE2
MODE3
19
25k
20
25k
Function SCART inputs from SCART
connectors.
VCC
63
61
TC1
TC2
5
63
147
61
Video detect time constant capacitor
connection pins.
VCC
10
46
53
TRAP1
TRAP2
TRAP3
10
3.5
200
46
53
Connects trap circuit for subcarrier.
200
Note. Pin voltages indicated the approximate DC voltage levels with no signals inputs.
—7—
CXA2149Q
Electrical Characteristics
Item
Supply voltage
Supply current
(Ta=25 °C, VCC=9 V unless stated.)
Symbol
VCC
ICC
Conditions
Min.
8.5
40
Typ.
9.0
75
Max.
9.5
100
Unit
V
mA
I2C (Operation of the I2C using either a 3.3 or 5 V supply on the external controller is possible)
Item
High level input voltage
Low level input voltage
Low level output voltage
Max. clock frequency
Min. waiting time for data change
Min. waiting time for data transfer start
Low level clock pulse width
High level clock pulse width
Min. waiting time for start preparation
Min. data hold time
Min data preparation time
Rise time
Fall time
Min. waiting time for stop preparation
Symbol
VIH
VIL
VOL
fSCL
tBUF
tHDSTA
tL
tH
tSUSTA
tHDDAT
tSUDAT
tR
tF
tSUSTO
—8—
Conditions
SDA 3 mA sink
Min.
2.3
0
0
0
4.5
4
4.7
4
4.7
Typ.
—
—
—
—
—
—
—
—
—
Max.
5
1.5
0.4
100
—
—
—
—
—
Unit
V
V
V
kHz
µs
µs
µs
µs
µs
5
250
—
—
4.7
—
—
—
—
50
—
—
1
300
—
s
ns
µs
ns
µs
CXA2149Q
Audio System
Item
Symbol
Gain
Channel 1/Channel 2
Channel 3 (max.)
Channel 3 (min.)
FGVA1
VGVAF
VGVA0
–3 dB bandwidth
FBWA
Total harmonic distortion
THD
Input dynamic range
VDRA
Crosstalk
VCtA
Ripple rejection ratio
RRA
Output DC offset
Voff
Input impedance
Output impedance
Zin
Zout
Phase difference
VPDA
S/N ratio
S/NA
Mute
Volume control
Fine
Coarse
Amute
Conditions
f=1 kHz, 1 Vp-p I/P.
1 Vp-p I/P, 1 kHz serving as 0 dB ref.
f=1 kHz, 0.5 Vp-p I/P with a 400 Hz to
80 kHz passband.
f=100 kHz, distortion at O/P less than
0.3 %
f=1 kHz, 1 Vp-p I/P, measure other
outputs.
f=100 Hz, 0.3 Vp-p signal applied to
AVCC
Offset voltage between I/P and O/P.
f=1 kHz, 1 Vrms input.
Compare left and right channels.
f=1 kHz, 1 Vp-p input with a 20 Hz to
20 kHz passband. See note 1.
f=1 kHz, 1 Vp-p input.
f=1 kHz, 0.5 Vp-p input.
FEVC
CEVC
Audio System Notes
1. Channel 3 should be set at maximum volume.
—9—
Min.
Typ.
Max.
Unit
–0.5
–0.5
–68
0
0
–63
0.5
0.5
–58
dB
dB
dB
—
1
—
MHz
—
0.01
0.05
%
2.8
3.0
—
Vrms
—
–90
–76
dB
—
–55
—
dB
–30
0
30
mV
—
—
66
20
—
—
kΩ
Ω
—
0.1
—
Deg
85
90
—
dB
—
–90
–70
dB
0.6
7.6
1
8
1.4
8.4
dB
dB
CXA2149Q
Video System
Item
CVOUT1/2 gain
Y/COUT1/2 gain
–3 dB bandwidth
–3 dB bandwidth
Y/C mixer
Symbol
GVCV
GVYC
FBWV1
Conditions
f=200 kHz, 0.3 Vp-p I/P.
f=200 kHz, 0.3 Vp-p I/P.
0.3 Vp-p I/P. See note 1.
Min.
5.5
–0.5
15
Typ.
6
0
20
Max.
6.5
0.5
—
Unit
dB
dB
MHz
FBWV2
0.3 Vp-p I/P. See note 1.
10
15
—
MHz
1.4
—
—
Vp-p
1.7
—
—
Vp-p
—
–55
—
dB
—
72
—
dB
–1.5
0
1.5
%
–1.5
0
1.5
Deg
200
250
350
ns
64 µs period.
100
91
—
—
—
—
mV
%
64 µs period.
—
—
—
—
30
84
mV
%
Input level, TV and CVIN1
VRIV
Input dynamic range,
CVIN2 and Y inputs.
VDRV
Crosstalk
VCtV
S/N ratio
S/NV
Differential gain
DG
Differential phase
DP
Group delay
GD
SYNC identification
detected when
SYNC amplitude
SYNC duty cycle
not detected when
SYNC amplitude
SYNC duty cycle
SYNC1
f=200 kHz, distortion at O/P less
than 1 %, GD=OFF
f=200 kHz, distortion at O/P less
than 1.0 %.
f=4.43 MHz, 0.7 Vp-p I/P,
measure other outputs.
Ratio of 0.7 Vp-p white level to
‘black line’ noise. 5 kHz to 5 MHz
passband. See note 2.
1.4 Vp-p 5 step staircase,
modulated with 150 mVp-p 4.43 MHz.
As above.
f=200 kHz, 0.7 Vp-p.
See figure 1 and note 3.
See note 4.
–7
×10
4.5
Figure 1 Group delay characteristic
Group delay (seconds)
4
3.5
3
2.5
2
1.5
1
0
1
2
3
Frequency (Hz)
—10—
4
5
6
6
×10
CXA2149Q
Video System Notes
1. 200 kHz is taken to be 0 dB for the purpose of this measurement. Where applicable, the group delay
function will be turned off to make this measurement.
2. Weighted using CCIR567.
3. This group delay characteristic, figure 1, is for the B, G specifications. It does not take into account the
input and output delays inherent within the AV switch.
4. The sync detection circuits operate on the video sources that have been switched into the TV and CVIN1
channels, respectively.
The internal SYNC discriminator circuit functions in the following way. The SYNC tip of the incoming video
input is clamped to a fixed level and the signal is then compared in magnitude with an internal threshold
voltage. If the signal is smaller than the threshold level the IC determines that the SYNC does not exist.
Conversely, if the signal is found to be greater than the threshold then the duty cycle of signal is passed to
the duty discrimination circuit. The discriminator circuit will identify whether the duty cycle of the signal is
above 91 % at which point SYNC is detected, or below 84 % when SYNC is not detected.
To prevent occasional video disturbances such as IF noise from the tuner causing malfunctioning of the
SYNC detector, a time constant of approximately 14 line periods is applied during which the status of the
SYNC detection is maintained.
—11—
100nF
75
—12—
39k
4
3.3k
3
5
7
3.3k
6
8
9
10
11
12
13
14
15
I 2C
17
16
18
MODE3 20
AVCC 21
ABIAS 22
LOUT3 23
ROUT3 24
19
10µF
+9V
100nF
+12V
+12V
+12V
+12V
Video Test Configuration
Video System Test Configuration (gain, dynamic range, bandwidth, signal to noise, crosstalk, differential gain, differential phase, sync ID, group delay)
Signals applied to inputs on Pins 64, 62, 60, 58, 56, 54, 52, 51, 49
Output signal measured form Pins 9, 11, 13, 43, 45, 47
Notes:
1) All +9 V supplies de-coupled close to supply Pins 21, 44, 59 with 10 nF ceramic capacitor.
2) Refer to application schematic for external pin configuration of sync detect circuits.
3) Input signal assumes 75 ohm video driver. All video outputs are loaded with an emitter follower during tests.
Input Signal
2
1
LV5 26
LTV 25
1k
64 TV
63 TC1
62 CVIN1
61 TC2
60 CVIN2
59 VVCC1
V
BC547B
1µF
1µF
CXA2149Q
LV4 27
58 Y1
LV3 28
57 VGND1
LV2 29
LV1 30
AGND 31
RTV 32
33
34
35
+12V
36
BC547B
56 Y2
55 VBIAS
54 Y3
37
38
1k
1k
75
75
+9V
100nF
75
100nF
75
100nF
10µF 100nF
53 TRAP3
52 C1
39
40
41
42
43
44
45
46
CVOUT1
75
47
48
TRAP1
100nF
C2
+9V
YOUT1
Measurement Point
BC547B
REXT
1k
TVOUT
BC547B
ADR
1k
MUTE
BC547B
MODE2
75
49
C3
NC
RGD4
50
RGD3
COUT2
VGND2
LO0
51
RGD2
100nF
TRAP2
RGD1
100nF
YOUT2
LO1
75
DVCC
VVCC2
75
CVOUT2
+12V
DGND
BC547B
LOUT2
1k
LOUT1
ROUT2
COUT1
RV2
+12V
SDA
RV3
BC547B
SCL
RV1
200
ROUT1
200
RV4
MODE1
RV5
1k
CXA2149Q
2
1
3
4
5
6
7
8
9
10
11
12
13
14
I 2C
15
19
SW1
HW mute
+5V
18
17
16
MODE3 20
AVCC 21
ABIAS 22
LOUT3 23
ROUT3 24
LTV 25
10µF
10µF
1µF
1µF
1µF
1µF
1µF
1µF
1µF
+9V
10µF
100nF
1k
1k
1k
1k
1k
1k
1k
Input Signal
Audio System Test Configuration (gain, dynamic range, signal to noise, crosstalk, distortion, volume control, ZCD and mute)
Signals applied to inputs on Pins 25, 26, 27, 28, 29, 30, 32, 33, 34, 35, 36, 37
Output signal measured form Pins 23, 24, 39, 40, 41
Notes:
1) All +9 V supplies de-coupled close to supply Pins 21, 44, 59 with 10 nF ceramic capacitor.
2) When muting audio using hardware mute, SW1 is closed.
64 TV
63 TC1
62 CVIN1
61 TC2
60 CVIN2
59 VVCC1
LV5 26
58 Y1
CXA2149Q
LV4 27
57 VGND1
LV1 30
AGND 31
RTV 32
LV3 28
CVOUT1
56 Y2
TRAP1
LV2 29
YOUT1
55 VBIAS
REXT
+9V
C2
TVOUT
100nF
54 Y3
ADR
10µF
C3
53 TRAP3
52 C1
33
34
35
36
RGD2
1k
1µF 1µF 1µF 1µF 1µF
37
38
39
40
41
42
43
44
45
46
RGD1
47
TRAP2
LO1
48
YOUT2
VVCC2
49
DVCC
COUT1
50
CVOUT2
SCL
51
DGND
10µF
LOUT2
10µF
ROUT2
+9V
LOUT1
10µF
ROUT1
10µF
RV1
200
NC
RGD4
1k
RV2
MUTE
10k
Measurement
Point
RGD3
1k
RV3
SDA
COUT2
1k
RV4
200
VGND2
LO0
1k
RV5
MODE1
—13—
MODE2
V
CXA2149Q
Audio Test Configuration
Video Input
Signal
Measurement
64 TV
63 TC1
2
1
62 CVIN1
61 TC2
60 CVIN2
4
5
6
7
8
9
10
11
12
13
14
I2 C
15
17
16
18
MODE3 20
AVCC 21
ABIAS 22
LOUT3 23
ROUT3 24
19
Notes:
1) All +9 V supplies de-coupled close to supply Pins 21, 44, 59 with 10 nF ceramic capacitor.
2) All video outputs are loaded with an emitter follower during test.
3
LV5 26
LTV 25
58 Y1
CXA2149Q
LV4 27
59 VVCC1
LV3 28
LV1 30
AGND 31
57 VGND1
CVOUT1
56 Y2
TRAP1
LV2 29
DC Tests (Audio and Video System)
V
+9V
43
RTV 32
33
34
35
36
37
38
39
40
41
42
DGND
CVOUT2
YOUT1
55 VBIAS
54 Y3
REXT
100nF
C2
TVOUT
10µF
C3
RGD4
NC
53 TRAP3
52 C1
RGD3
VGND2
LO0
TRAP2
COUT2
RGD2
44
RGD1
DVCC
YOUT2
LO1
45
LOUT2
VVCC2
46
ROUT2
COUT1
47
LOUT1
SCL
48
ROUT1
SDA
49
RV1
200
50
RV2
200
51
RV3
MODE1
+9V
RV4
ADR
V
RV5
MUTE
—14—
MODE2
Video Output
Signal
Measurement
10µF
+9V
Audio Input
Signal
V
Measurement
100nF
Audio Output
Signal
V
Measurement
CXA2149Q
DC Test Configuration
CXA2149Q
I2C Bus Register Assignment
Status Register
Slave
Address
1
0
Data1
SYNC1
Status
SYNC2
status
0
1
0
0
ADR
Mode
Status
R/W
POR
Control Registers
Slave
Address
1
0
Data1
Data2
Data3
Data4
Data5
Data6
0
1
0
0
CVOUT1
LO0
Control
ZCD
Switch
LO1
Control
AOUT3
Mute
Group
Delay
AOUT3 Volume Control
Coarse
GD1
GD2
SYNC1
Switch
Switch
Switch
ADR
R/W
CVOUT2
YCOUT1
YCOUT2
AOUT1
AOUT2
AOUT3
AOUT3 Volume Control
Fine
SYNC2
∗
∗
Switch
AOUT3L/R
Switch
∗
∗
Note.
1. The names CVOUT1, YCOUT1, AOUT1 etc., refer to the particular output or outputs that the register
controls.
2. ∗ Register undefined.
Status Register Descriptions
SYNC Detection Circuits Data1 Bit 6 (SYNC1) and Bit 7 (SYNC2)
Indicates whether a video signal is present or not. SYNC1 takes its input from TV and YOUT1. SYNC2 takes
its input from CVIN1 and YOUT2.
SYNC1 or SYNC2 bit
0
1
Meaning
no SYNC
SYNC present
—15—
CXA2149Q
Mode Status Data1 Bits 1 to 5
The mode inputs from the SCART ports are driven at three different voltage levels to indicate the mode format
of the port. These inputs are detected and then encoded to the status register in the following manner.
Input pin voltage
0 to 2 V
4.5 to 7 V
9.5 to 12 V
Mode status bits
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011 to 11111
Meaning
Internal TV
External 16:9
External 4:3
Meaning
for MODE1
Internal TV
External 16:9
External 4:3
Internal TV
External 16:9
External 4:3
Internal TV
External 16:9
External 4:3
Internal TV
External 16:9
External 4:3
Internal TV
External 16:9
External 4:3
Internal TV
External 16:9
External 4:3
Internal TV
External 16:9
External 4:3
Internal TV
External 16:9
External 4:3
Internal TV
External 16:9
External 4:3
Not used
Meaning
for MODE2
Internal TV
Internal TV
Internal TV
External 16:9
External 16:9
External 16:9
External 4:3
External 4:3
External 4:3
Internal TV
Internal TV
Internal TV
External 16:9
External 16:9
External 16:9
External 4:3
External 4:3
External 4:3
Internal TV
Internal TV
Internal TV
External 16:9
External 16:9
External 16:9
External 4:3
External 4:3
External 4:3
Not used
—16—
Meaning
for MODE3
Internal TV
Internal TV
Internal TV
Internal TV
Internal TV
Internal TV
Internal TV
Internal TV
Internal TV
External 16:9
External 16:9
External 16:9
External 16:9
External 16:9
External 16:9
External 16:9
External 16:9
External 16:9
External 4:3
External 4:3
External 4:3
External 4:3
External 4:3
External 4:3
External 4:3
External 4:3
External 4:3
Not used
CXA2149Q
Power on Reset Data1 Bit 0
After power on this bit will be set to 1 when DVCC, Pin 44, passes through a defined threshold level. The
control registers are then defined as below. After the first write command the bit will be reset to 0.
CVOUT1=CVOUT2=1001, LO0 switch=LO1 switch=1, YCOUT1=YCOUT2=111,
ZCD switch=AOUT3 mute=1, AOUT1=AOUT2=111, Group delay=10000,
AOUT3=111, AOUT3 volume control coarse=AOUT3 volume control fine=111,
AOUT3L/R switch=00, GD1 switch=GD2 switch=1, SYNC1 switch=SYNC2 switch=1.
Control Register Descriptions
Video Inputs
CVOUT1 Data1 Bits 4 to 7
These bits select the input signal that will be output on the CVOUT1 pin.
CVOUT1
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010 to 1111
Input or function selected
TV
CVin1
CVin2
Y1
Y2
Y3
Y1+C1
Y2+C2
Y3+C3
Mute
Not used
CVOUT2 Data1 Bits 0 to 3
These bits select the input signal that will be output on the CVOUT2 pin.
CVOUT2
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010 to 111
Input or function selected
TV
CVin1
CVin2
Y1
Y2
Y3
Y1+C1
Y2+C2
Y3+C3
Mute
Not used
—17—
CXA2149Q
YCOUT1 Data2 Bits 3 to 5
These bits select the input signals that will be output on the YOUT1/COUT1 pins.
YCOUT1/2
000
001
010
011
100
101
110
111
Input or function selected
TV and Mute
CVin1 and Mute
CVin2 and Mute
Mute and Mute
Y1 and C1
Y2 and C2
Y3 and C3
Mute and Mute
YCOUT2 Data2 Bits 0 to 2
These bits select the input signals that will be output on the YOUT2/COUT2 pins.
YCOUT2
000
001
010
011
100
101
110
111
Input or function selected
TV and Mute
CVin1 and Mute
CVin2 and Mute
Mute and Mute
Y1 and C1
Y2 and C2
Y3 and C3
Mute and Mute
—18—
CXA2149Q
Audio Inputs
AOUT1 Data3 Bits 3 to 5
These bits select the input signal that will be output on the ROUT1 and LOUT1.
AOUT1 bits
000
001
010
011
100
101
110
111
Input or function selected
Mute
LTV and RTV
LV1 and RV1
LV2 and RV2
LV3 and RV3
LV4 and RV4
LV5 and RV5
Mute
AOUT2 Data3 Bits 0 to 2
These bits select the input signal that will be output on ROUT2 and LOUT2
AOUT2 bits
000
001
010
011
100
101
110
111
Input or function selected
Mute
LTV and RTV
LV1 and RV1
LV2 and RV2
LV3 and RV3
LV4 and RV4
LV5 and RV5
Mute
AOUT3 Data4 Bits 0 to 2
These bits select the input signal that will be output on ROUT3 and LOUT3
AOUT3 bits
000
001
010
011
100
101
110
111
Input or function selected
Mute
LTV and RTV
LV1 and RV1
LV2 and RV2
LV3 and RV3
LV4 and RV4
LV5 and RV5
Mute
—19—
CXA2149Q
Group Delay Switches Data1 Bit 7 (GD1 Switch) and Bit 6 (GD2 Switch)
Switch the respective group delay function on or off. GD2 switches on and off the group delay on the TV input
and GD1 switches on and off the group delay on the CVIN1 input.
GD1 or GD2 bit
0
1
Group delay function
off
on
Group Delay Control Data4 Bits 3 to 7
Used to control the variation in group delay. If no adjustment is required then set a value 10000.
Group Delay bits
00000
11111
Change in the Max. delay frequency
–800 kHz
+800 kHz
AOUT3 Volume Control Coarse Data5 Bits 5 to 7
Selects the gain for the internal audio amplifiers in 8 dB steps.
Coarse bits
000
111
Gain of AOUT3 channels
0 dB
–56 dB
AOUT3 Volume Control Fine Data5 Bits 2 to 4
Selects the gain for the internal audio amplifiers in 1 dB steps.
Fine bits
000
111
Gain of AOUT3 channels
0 dB
–7 dB
AOUT3L/R Switch Data5 Bits 0 and 1
Controls which of channel 3’s left or right channels is output to LOUT3 and ROUT3, respectively.
AOUT3L/R bits
00
01
10
11
Output to LOUT3 and ROUT3
Normal
Left channel
Right channel
Inverted
—20—
CXA2149Q
AOUT3 Mute Switch Data3 Bit 6
Mutes the LOUT3 and ROUT3 channels at the electronic volume control output so that a click free audio
channel change can take place.
AOUT3 mute bit
0
1
Meaning
Mute off
Mute on
The normal sequence for a click free channel change is as follows:1. Mute the channel 3 outputs (AOUT3 mute=1) with zero cross detection on (ZCD switch=1).
2. Change the channel 3 audio source, AOUT3L/R control.
3. Un-mute the channel 3 outputs still with zero cross detection on.
LO0 or LO1 Control Data2 Bit 7 (LO0 control) and Bit 6 (LO1 control)
Used to control the switching of the open collector outputs. The output transistor emitters are connected to
digital ground. Each output is capable of sinking 1 mA.
LO0 or LO1 bit
0
1
Collector output
Low impedance
High impedance
Zero Cross Detection Switch Data3 Bit 7
Switches the ZCD function on or off. When the ZCD is on, a volume control change or mute instruction sent
via the I2C bus will only be implemented when a minimal, ie., zero cross, signal amplitude is detected.
ZCD bit
0
1
Meaning
ZCD off
ZCD on
SYNC ID Switches Data6 Bit 5 (SYNC1 Switch) and Bit 4 (SYNC2 Switch)
Switches the respective SYNC ID circuit to an input our output. SYNC1 switches between the TV input and
YOUT1 output. SYNC2 switches between the CVIN1 input and YOUT2 output.
SYNC1 or SYNC2 bit
0
1
Input to SYNC ID
YOUT1 and YOUT2
YV and CVIN1
External Logic Inputs and Output
Hardware Mute
The hardware mute (Pin 17) provided will mute all audio outputs when the pin voltage exceeds 2.5 V.
In this case the muting will be instantaneous.
SCART Modes
Three Mode inputs (Pins 18, 19 and 20) are used to allow the format identification of up to three SCART ports.
See the description for mode status.
LO0 and LO1 Logic Outputs
LO0 and LO1 are open collector output I2C controllable logic switch for any external switching functions an
application may require. See the description for LO0 and LO1 control.
—21—
—22—
Y1 DRIVE
9V
9V
0.1µ
0.1µ
0.1µ
0.1µ
0.1µ
0.1µ
0.1µ
0.1µ
0.1µ
0.1µ
180µ
64 TV
63 TC1
62 CVIN1
61 TC2
60 CVIN2
59 VVCC1
58 Y1
57 VGND1
56 Y2
55 VBIAS
54 Y3
53 TRAP3
52 C1
C2
9V
NC
560
10p
3
C3
2
0.1µ
1
5
6
100p 100p
4
10p
560
7
8
43
42
LOUT2
9
10
12
11
CXA2149Q
40
ROUT2
41
39
13
38
14
16
15
17
18
MODE3 20
AVCC 21
ABIAS 22
LOUT3 23
ROUT3 24
LTV 25
LV5 26
LV4 27
LV3 28
LV2 29
LV1 30
AGND 31
RTV 32
33
34
35
36
37
19
0.1µ 0.1µ
220
220
0.1µ
9V
10µ
0.1µ
180µ
10p
10µ
10µ
39k
(1%)
0.1µ
600
600
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
68k
68k
Y2 DRIVE 10µ
10p
0.1µ
44
45
VGND2
RGD3
COUT2
LO0
TRAP2
RGD2
YOUT2
RGD1
DVCC
LO1
46
CVOUT2
CVOUT1
47
0.1µ
48
0.1µ
49
10µ
50
DGND
51
10µ 10µ
REXT
1µ
TVOUT
1µ
RGD4
10µ
TRAP1
1µ
YOUT1
1µ
VVCC2
LOUT1
COUT1
0.1µ
ROUT1
10µ
SCL
600 10µ
1µ
SDA
600 10µ
MUTE
600 10µ
RV1
1µ
MODE1
600
RV2
1µ
RV3
1µ
RV4
1µ
RV5
1µ
1µ
ADR
1µ
MODE2
9V
CXA2149Q
Application Diagram
9V
10µ
CXA2149Q
Applications Notes (see circuits diagram on next page).
1. Care should be taken with polarity sensitive capacitors. The respective bias voltages for audio and video
inputs and outputs are as follows.
C1, C2, C3, COUT1 and COUT2 are biased at approximately 4.5 V.
TV, CVIN1, CVIN2, Y1, Y2 and Y3 are SYNC tip clamped at approximately 3.9 V.
CVOUT1, CVOUT2, TVOUT have their SYNC tip output at approximately 3.5 V.
YOUT1, YOUT2 have their SYNC tip output at approximately 3.3 V.
ABIAS and VBIAS are equal to approximately 4.5 V.
2. Connect ADR to VCC when wishing to set the slave address to 92H.
3. Setting the MUTE pin to 2.5 V or more can mute the audio outputs.
4. TRAP1, TRAP2 and TRAP3 are set for a 3.58 MHz subcarrier. For a 4.43 MHz subcarrier typical values for
the two traps would be 47 µ and 27 p, respectively. Values may require adjustment dependent upon the
application. Each trap gives 6 dB’s of attenuation at the desired frequency.
5. LO0 and LO1 connected to ground when not required.
6. Connect all NC to ground in application.
—23—
CXA2149Q
Example of Representative Characteristics
Typical audio system frequency response LTV-LOUT1
Audio system input/output gain [dB]
4
2
0
–2
–4
–6
–8
–10
1000
10000
100000
Frequency [Hz]
1000000
Video system typical frequency response
Video system input/output gain [dB]
8
6
4
2
0
–2
–4
–6
–8
–10
1
10
Frequency [MHz]
100
TV-CVOUT1
Typical audio system distortion vs. Input amplitude
Y1-CVOUT2 (Mx)
0
Total harmonic distortion [dB]
–10
–20
f=1kHz
400Hz HPE, 80kHz LPF
–30
–40
–50
–60
–70
–80
–90
–100
–110
0.5
1
1.5
2
Input amplitude [Vrms]
2.5
3
—24—
CXA2149Q
Package Outline
Unit : mm
64PIN QFP(PLASTIC)
23.9 ± 0.4
+ 0.4
20.0 – 0.1
+ 0.1
0.15 – 0.05
0.15
64
20
1
16.3
32
+ 0.4
14.0 – 0.1
52
17.9 ± 0.4
33
+ 0.2
0.1 – 0.05
19
+ 0.35
2.75 – 0.15
+ 0.15
0.4 – 0.1
1.0
0.2
M
0° to10°
0.8 ± 0.2
51
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
SONY CODE
QFP-64P-L01
LEAD TREATMENT
SOLDER/PALLADIUM
PLATING
EIAJ CODE
QFP064-P-1420
LEAD MATERIAL
42/COPPER ALLOY
PACKAGE MASS
1.5g
JEDEC CODE
—25—
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