CY2CC910 1:10 Clock Fanout Buffer Features ■ Low voltage operation ■ Full range support: ❐ 3.3V ❐ 2.5V ❐ 1.8V Description The Cypress series of network circuits are produced using advanced 0.35 micron CMOS technology, achieving the industry’s fastest logic and buffers. ■ Over voltage tolerant input hot swappable ■ 1:10 Fanout ■ Drives either a 50-Ohm or 75-Ohm load ■ Low input capacitance ■ Low output skew ■ Low propagation delay ■ Typical (tpd less than 4 ns) ■ High speed operation: ❐ 200 MHz at1.8V ❐ 650 MHz at 2.5V and 3.3V ■ Industrial versions available ■ Available packages include: SOIC, SSOP The Cypress CY2CC910 fanout buffer features one input and 10 outputs. It is ideal for conversion from and to 3.3V, 2.5V, and 1.8V Designed for Data Communications clock management applications, the large fanout from a single input reduces loading on the input clock. Cypress employs the unique AVCMOS type outputs VOI (Variable Output Impedance) that dynamically adjust for variable impedance matching, eliminate the need for series damping resistors, and reduce overall noise. Logic Block Diagram 3 5 7 VDD 9 4 ,8 1 5 ,2 0 11 IN 1 12 INPUT (AVCMOS) 2 ,6 ,1 0 1 3 ,1 7 14 16 GND 18 19 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q 10 OUTPUT (AVCMOS) Cypress Semiconductor Corporation Document #: 38-07348 Rev. *C • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised October 22, 2008 [+] Feedback CY2CC910 Pin Configuration IN GND Q1 VDD Q2 GND Q3 VDD Q4 GND 1 2 3 4 5 6 7 8 9 10 CY2CC910 Figure 1. 20-Pin SOIP-SSOP 20 19 18 17 16 15 14 13 12 11 VDD Q10 Q9 GND Q8 VDD Q7 GND Q6 Q5 20 pin SOIC/SSOP Pin Description Pin Number Pin Name Description 1 IN Input 2,6,10,13,17 Ground 4,8,15,20 GND VDD 3,5,7,9,11,12,14,16,18,19 Q1,Q2,Q3,Q4,Q5,Q6,Q7,Q8,Q9,Q10 Output Power Supply Maximum Ratings[1] Storage Temperature: ................................. –65°C to +150°C Supply Voltage to Ground Potential Ambient Temperature: .................................. –40°C to +85°C (Outputs only) ........................................... –0.5V to VDD + 1V Supply Voltage to Ground Potential DC Output Voltage.................................... –0.5V to VDD + 1V VCC ...................................................................–0.5V to 4.6V Power Dissipation........................................................ 0.75W Input..................................................................–0.5V to 5.8V Note 1. Stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. This is intended to be a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Document #: 38-07348 Rev. *C Page 2 of 11 [+] Feedback CY2CC910 Variable Output Impedance Control (VOI) Figure 2. Output Voltage versus Output Current (TA = 25°C) Pull Up Pull Down 3.5 3.5 3 3 2.5 2.5 2 2 1.5 1.5 1 1 0.5 0.5 0 0 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1 -0.18 -0.16 -0.14 -0.12 Vdd = 2.5 V -0.08 -0.06 -0.04 -0.02 0 Ioh (A) Iol (A) Vdd = 3.3 V -0.1 Vdd = 3.3 V Vdd = 1.8 V Vdd = 2.5 V Vdd = 1.8 V DC Electrical Characteristics At 3.3V (See Figure 3) Parameter Description VOH Output High Voltage Conditions Min Typ VDD = Min., VIN = VIH or VIL IOH = –12 mA VDD = Min., VIN = VIH or VIL IOL = 12 mA 2.3 3.3 VOL Output Low Voltage VIH Input High Voltage Guaranteed Logic High Level VIL Input Low Voltage Guaranteed Logic Low Level 0.2 2 Max Unit V 0.5 V 5.8 V 0.8 V IIH Input High Current VDD = Max. VIN = 2.7V 1 μA IIL Input Low Current VDD = Max. VIN = 0.5V –1 μA II Input High Current VDD = Max., VIN = VDD(Max.) VIK Clamp Diode Voltage VDD = Min., IIN = –18 mA –0.7 20 μA –1.2 V IOK Continuous Clamp Current VDD = Max., VOUT = GND –50 mA OOFF Power-down Disable VDD = GND, VOUT = < 4.5V 100 μA VH Input Hysteresis Document #: 38-07348 Rev. *C 80 mV Page 3 of 11 [+] Feedback CY2CC910 At 2.5V (See Figure 3) Parameter VOH Description Output High Voltage Conditions VDD = Min., VIN = VIH or VIL Min Typ Max Unit IOH = –7 mA 1.8 V IOH = 12 mA 1.6 V VOL Output Low Voltage VDD = Min., VIN = VIH or VIL VIH Input High Voltage Guaranteed Logic High Level IOL = 12 mA 0.65 V 5.0 V VIL Input Low Voltage Guaranteed Logic Low Level 0.8 V IIH Input High Current VDD = Max. VIN = 2.4V 1 μA IIL Input Low Current VDD = Max. VIN = 0.5V –1 μA II Input High Current VDD = Max., VIN = VDD(Max.) 20 μA VIK Clamp Diode Voltage VDD = Min., IIN = –18 mA IOK Continuous Clamp Current VDD = Max., VOUT = GND OOFF Power Down Disable VDD = GND, VOUT = < 4.5V VH Input Hysteresis 1.6 –0.7 –1.2 V –50 mA 100 80 μA mV At 1.8V (See Figure 7) Parameter Description Test Condition[2] VDD Supply Voltage VIH Input High Voltage VIL Input Low Voltage VOH Output High Voltage IOH = –2 mA VOL Output Low Voltage IOH = 2 mA Min Max Unit 1.71 1.89 V 0.65VDD[1.1] 4.3 V –0.3 0.35 VDD[0.6] VDD – 0.45[1.2] V V 0.45 V Max Unit Capacitance Parameter Description Test Conditions Typ CIN Input Capacitance VIN = 0V 2.5 pF COUT Output Capacitance VOUT = 0V 6.5 pF Power Supply Characteristics (See Figure 3) Parameter Description Test Conditions ΔICC Delta ICC Quiescent Power Supply Current (IDD @ VDD = Max and VIN = VDD) – (IDD @ VDD = Max and VIN = VDD – 0.6V) ICCD Dynamic Power Supply Current VDD = Max Input toggling 50% Duty Cycle, Outputs Open IC Total Power Supply Current VDD = Max Input toggling 50% Duty Cycle, Outputs Open fL = 40 MHZ Min Typ Max Unit 50 μA 0.63 mA/ MHz 25 mA Note 2. Test load conditions: 500-Ohm to ground with approximately 6-pF total loading and 200-MHz maximum frequency. Document #: 38-07348 Rev. *C Page 4 of 11 [+] Feedback CY2CC910 High Frequency Parametrics Max Unit DJ Parameter Jitter, Deterministic Description 50% duty cycle tW(50–50) The “point to point load circuit” | Output Jitter – Input Jitter | Test Conditions See Figure 5 Min Typ 20 ps Fmax 3.3V Maximum frequency VDD = 3.3V 50% duty cycle tW(50–50) Standard Load Circuit. See Figure 3 160 MHz 50% duty cycle tW(50–50) The “point to point load circuit” See Figure 5 650 Fmax 2.5V Maximum frequency VDD = 2.5V The “point-to-point load circuit” VIN = 2.4V/0.0V VOUT = 1.7V/0.7V See Figure 5 200 MHz Fmax 1.8V Maximum frequency VDD = 1.8V The “6-pF load circuit” VIN = 1.7/0.0V VOUT = 1.2V/0.4V See Figure 7 200 MHz Fmax(20) Maximum frequency VDD = 3.3V 20% duty cycle tW(20-80) The “point to point load circuit” VIN = 3.0V/0.0V VOUT = 2.3V/0.4V See Figure 6 250 MHz tW 3.3V Minimum pulse VDD = 3.3V The “point-to-point load circuit” VIN = 3.0V/0.0V F = 100 MHz VOUT = 2.0V/0.8V See Figure 5 1 ns tW 2.5V Minimum pulse VDD = 2.5V The “point-to-point load circuit” VIN = 2.4V/0.0V F = 100 MHz VOUT = 1.7V/0.7V See Figure 5 1 ns tW 1.8V Minimum pulse VDD = 1.8V The “6-pF load circuit” VIN = 1.7V/0.0V VOUT = 1.2V/0.4V See Figure 7 1 ns AC Switching Characteristics At 3.3V (VDD = 3.3V ± 5%, Temperature = –40°C to +85°C) Parameter Description Min Typ Max Unit 1.5 2.7 3.5 ns 1.5 2.7 3.5 tPLH Propagation Delay – Low to High tPHL Propagation Delay – High to Low tR Output Rise Time tF Output Fall Time tSK(0) Output Skew: Skew between outputs of the same package (in phase). See Figure 11 0.2 ns tSK(p) Pulse Skew: Skew between opposite transitions of the same output (tPHL – tPLH). See Figure 10 0.2 ns tSK(t) Package Skew: Skew between outputs of different packages at See Figure 12 the same power supply voltage, temperature and package type. 0.4 ns See Figure 4 ns 0.8 V/ns 0.8 V/ns At 2.5V (VDD = 2.5V ± 5%, Temperature = –40°C to +85°C) Parameter Description Min Typ Max Unit 1.5 2.7 3.5 ns 1.5 2.7 3.5 ns tPLH Propagation Delay – Low to High tPHL Propagation Delay – High to Low tR Output Rise Time 0.8 V/ns tF Output Fall Time 0.8 V/ns tSK(0) Output Skew: Skew between outputs of the same package (in phase). See Figure 11 0.2 ns tSK(p) Pulse Skew: Skew between opposite transitions of the same output (tPHL See Figure 10 – tPLH). 0.2 ns tSK(t) Package Skew: Skew between outputs of different packages at the same See Figure 12 power supply voltage, temperature and package type. 0.4 ns Document #: 38-07348 Rev. *C See Figure 4 Page 5 of 11 [+] Feedback CY2CC910 AC Switching Characteristics At 1.8V(VDD = 1.8V ±5%, Temperature = –40°C to +85°C) Parameter tPLH tPHL tR tF tSK(0) Description Propagation Delay – Low to High Propagation Delay – High to Low Output Rise Time 20 – 80% Output Fall Time 20 – 80% Output Skew: Skew between outputs of the same package (in phase). Pulse Skew: Skew between opposite transitions of the same output (tPHL – tPLH). Package Skew: Skew between outputs of different packages at the same power supply voltage, temperature and package type. tSK(p) tSK(t) See Figure 8 Min 1.5 1.5 0.2 0.2 See Figure 11 See Figure 10 Typ Max Unit 2.7 3.5 ns 2.7 3.5 ns 1.5 ns 1.5 ns 0.2 ns See Figure 12 0.2 ns 0.4 ns Parameter Measurement Information: VDD at 3.3V to 2.5V Figure 3. Load Circuit [3,4,5] Figure 5. Point to Point Load Circuit[3,4,5] From Output Under Test From Output Under Test C L = 50 pF CL = 3 pF 500 ohm Figure 4. Voltage Waveforms Propagation Delay Times[6] VDD/2 Input tPLH Output Figure 6. Voltage Waveforms – Pulse Duration[4] tw(50-50) 0.8VDD VDD/2 0V Input Document #: 38-07348 Rev. *C VDD/2 0.8VDD VDD/2 VDD/2 0V tPHL VDD/2 500 ohm VOH VOL tw(20-80) Input 0.8VDD VDD/2 0V Page 6 of 11 [+] Feedback CY2CC910 Parameter Measurement Information: VDD at 8V Figure 7. Load Circuit [3,4,5] Figure 9. Voltage Waveforms – Pulse Duration[4] From Output Under Test tw(50-50) Input CL = 6 pF 1.8V 0.9V 0.9V 500 ohm 0V tw(20-80) Input 1.8V 0.9V 0V Figure 10. Pulse Skew - tsk(p) Figure 8. Voltage Waveforms Propagation 3V 1.8V 0.9V Input 0.9V tPLH Output 1.5V INPUT 0V tPHL 0.9V 0.9V tPHL tPLH 0V VOH 1.5V VOH OUTPUT VOL VOL tsk(P) = l tPHL - tPLH l Figure 11. Output Skew - tsk(0) 3V 1.5V INPUT 0V tPHL1 tPLH1 VOH 1.5V OUTPUT 1 tsk (O) tsk (O) VOL VOH 1.5V OUTPUT 2 tPLH 2 tsk (P) = tPLH 2 VOL l tPLH2 - tPLH1 l or tPHL2 - tPHL1 l Notes 3. CL includes probe and jig capacitance. 4. All input pulses are supplied by generators having the following characteristics: PRR < 100 MHz, Z0 = 50Ω, tR < 2.5 ns, tF < 2.5 ns. 5. The outputs are measured one at a time with one transition per measurement. 6. TPLH and TPHL are the same as tpd. Document #: 38-07348 Rev. *C Page 7 of 11 [+] Feedback CY2CC910 Figure 12. Package Skew - tsk(t) 3V 1.5V INPUT 0V tPHL1 tPLH1 VOH 1.5V PACKAGE 1 OUTPUT tsk(t) tsk(t) VOL VOH 1.5V PACKAGE 2 OUTPUT tPLH 2 tsk(t) = tPLH 2 VOL l tPLH2 - tPLH1 l or tPHL2 - tPHL1 l Ordering Information Part Number CY2CC910SI CY2CC910SIT CY2CC910SC CY2CC910SCT CY2CC910OI CY2CC910OIT CY2CC910OC CY2CC910OCT Pb-free CY2CC910OXI CY2CC910OXIT CY2CC910OXC CY2CC910OXCT Package Type 20-pin SOIC 20-pin SOIC–Tape and Reel 20-pin SOIC 20-pin SOIC–Tape and Reel 20-pin SSOP 20-pin SSOP–Tape and Reel 20-pin SSOP 20-pin SSOP–Tape and Reel Product Flow Industrial, –40° to 85°C Industrial, –40° to 85°C Commercial, 0°C to 70°C Commercial, 0°C to 70°C Industrial, –40° to 85°C Industrial, –40° to 85°C Commercial, 0°C to 70°C Commercial, 0°C to 70°C Status Obsolete Obsolete Obsolete Obsolete Obsolete Obsolete Obsolete Obsolete 20-pin SSOP 20-pin SSOP–Tape and Reel 20-pin SSOP 20-pin SSOP–Tape and Reel Industrial, –40° to 85°C Industrial, –40° to 85°C Commercial, 0°C to 70°C Commercial, 0°C to 70°C Active Active Active Active Document #: 38-07348 Rev. *C Page 8 of 11 [+] Feedback CY2CC910 Package Drawing and Dimensions Figure 13. 20-Pin (300-Mil) SOIC S5 (51-85024) 51-85024 *C Document #: 38-07348 Rev. *C Page 9 of 11 [+] Feedback CY2CC910 Figure 14. 20-Pin Shrunk Small Outline Package O20 51-85077-*C Document #: 38-07348 Rev. *C Page 10 of 11 [+] Feedback CY2CC910 Document History Page Document Title: CY2CC910 1:10 Clock Fanout Buffer Document No: 38-07348 Rev. ECN NO. Orig. of Change Submission Date ** 114318 TSM 05/10/02 New Data Sheet *A 119148 RGL 10/07/02 Added 5.8 as the Max. value for VIH in the DC Electrical Characteristics @3.3V table. Changed the Max. value of VIH from 5.8 to 5.0 in the DC Electrical Characteristics @2.5V table. Changed the value of VIH from VDD+0.3 [2.25] to 4.3 in the DC Electrical Characteristics @1.8V table. Description of Change *B 404287 RGL See ECN Added Lead-free devices for SSOP *C 2595534 CXQ/PYRS 10/23/08 Added “Status” column to Ordering Information table Updated Package Diagram 51-85024 Updated template Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. 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Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 38-07348 Rev. *C Revised October 22, 2008 Page 11 of 11 All products and company names mentioned in this document may be trademarks of their respective holders. [+] Feedback