AD AD8622ARMZ Low power, precision rail-to-rail output op amp Datasheet

Low Power, Precision
Rail-to-Rail Output Op Amp
AD8622/AD8624
PIN CONFIGURATIONS
Very low offset voltage
125 μV maximum
Supply current: 215 μA/amp typical
Input bias current: 200 pA maximum
Low input offset voltage drift: 1.2 μV/°C maximum
Very low voltage noise: 11 nV/√Hz
Operating temperature: −40°C to +125°C
Rail-to-rail output swing
Unity gain stable
±2.5 V to ±15 V operation
OUT A 1
–IN A 2
+IN A 3
TOP VIEW
V– 4 (Not to Scale)
8
V+
7
OUT B
6
–IN B
5
+IN B
Figure 1. 8-Lead Narrow-Body SOIC
8
V+
–IN A 2
AD8622
7
OUT B
+IN A 3
TOP VIEW
(Not to Scale)
6
–IN B
5
+IN B
V– 4
07527-002
OUT A 1
Figure 2. 8-Lead MSOP
14 OUT D
OUT A 1
Portable precision instrumentation
Laser diode control loops
Strain gage amplifiers
Medical instrumentation
Thermocouple amplifiers
–IN A
13 –IN D
2
+IN A
3
AD8624
V+
4
TOP VIEW
(Not to Scale)
+IN B 5
12 +IN D
11 V–
10 +IN C
6
9
–IN C
OUT B 7
8
OUT C
–IN B
GENERAL DESCRIPTION
07527-067
APPLICATIONS
13 NC
15 OUT A
16 NC
14 OUT D
Figure 3. 14-Lead TSSOP
–IN A 1
+IN A 2
V+ 3
12 –IN D
AD8624
11 +IN D
TOP VIEW
10 V–
(Not to Scale)
9
+IN C
OUT C 7
–IN C 8
–IN B 5
OUT B 6
+IN B 4
NOTES
1. NC = NO CONNECT.
2. IT IS RECOMMENDED THAT THE EXPOSED
PAD BE CONNECTED TO V–.
07527-068
The AD8622/AD8624 are dual and quad precision rail-to-rail
output operational amplifiers with low supply currents of only
350 µA/amplifier maximum over temperature and supply
voltages. The AD8622/AD8624 also has an input bias current
cancellation circuitry that provides a very low input bias current
over the full operating temperature.
With a typical offset voltage of only 10 µV, offset drift of 0.5 µV/°C,
and noise of only 0.2 μV p-p (0.1 Hz to 10 Hz), they are
perfectly suited for applications where large error sources
cannot be tolerated. Many systems can take advantage of the
low noise, dc precision, and rail-to-rail output swing provided
by the AD8622/AD8624 to maximize the signal-to-noise ratio
and dynamic range for low power operation. The AD8622/
AD8624 are specified for the extended industrial temperature
range of −40°C to +125°C. The AD8622 is available in lead-free
8-lead SOIC and MSOP packages, while the AD8624 is available
in lead-free 14-lead TSSOP and 16-lead LFCSP packages.
AD8622
07527-001
FEATURES
Figure 4. 16-Lead LFCSP
Table 1. Low Power Op Amps
Supply
40 V
36 V
12 V to 18 V
Single
OP97
AD8663
Dual
OP297
Quad
OP497
OP777
OP1177
OP727
OP2177
OP747
OP4177
6V
AD8667
ADA4692-2
AD8669
ADA4692-4
Rev. C
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rights of third parties that may result from its use. Specifications subject to change without notice. No
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Tel: 781.329.4700
Fax: 781.461.3113 ©2009–2011 Analog Devices, Inc. All rights reserved.
AD8622/AD8624
TABLE OF CONTENTS
Features .............................................................................................. 1
ESD Caution...................................................................................5
Applications ....................................................................................... 1
Typical Performance Characteristics ..............................................6
General Description ......................................................................... 1
Applications Information .............................................................. 15
Pin Configurations ........................................................................... 1
Input Protection ......................................................................... 15
Revision History ............................................................................... 2
Phase Reversal ............................................................................ 15
Specifications..................................................................................... 3
Micropower Instrumentation Amplifier ................................. 15
Electrical Characteristics—±2.5 V Operation .......................... 3
Hall Sensor Signal Conditioning .............................................. 16
Electrical Characteristics—±15 V Operation ........................... 4
Simplified Schematic ...................................................................... 17
Absolute Maximum Ratings ............................................................ 5
Outline Dimensions ....................................................................... 18
Thermal Resistance ...................................................................... 5
Ordering Guide .......................................................................... 19
REVISION HISTORY
6/11—Rev. B to Rev. C
Changes to Figure 13 ........................................................................ 7
2/10—Rev. A to Rev. B
Changed 16-Lead to 14-Lead in Figure 62 Caption................... 19
1/10—Rev. 0 to Rev. A
Added 14-Lead TSSOP ...................................................... Universal
Added 16-Lead LFCSP....................................................... Universal
Added Figure 3 and Figure 4; Renumbered Sequentially ........... 1
Changes to Table 5 ............................................................................ 5
Changes to Figure 10 to Figure 16 .................................................. 6
Changes to Figure 26 ........................................................................ 9
Changes to Figure 29 ...................................................................... 10
Updated Outline Dimensions ....................................................... 18
Changes to Ordering Guide .......................................................... 19
7/09—Revision 0: Initial Version
Rev. C | Page 2 of 20
AD8622/AD8624
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—±2.5 V OPERATION
VSY = ±2.5 V, VCM = 0 V, TA = 25°C, unless otherwise specified.
Table 2.
Parameter
INPUT CHARACTERISTICS
Offset Voltage
Symbol
Conditions
Min
VOS
Offset Voltage Drift
Input Bias Current
ΔVOS/ΔT
IB
Input Offset Current
IOS
−40°C ≤ TA ≤ +125°C
−40°C ≤ TA ≤ +125°C
Typ
Max
Unit
10
125
230
1.2
200
400
200
300
+1.3
μV
μV
µV/°C
pA
pA
pA
pA
V
dB
dB
dB
dB
GΩ
TΩ
pF
pF
0.5
30
−40°C ≤ TA ≤ +125°C
Input Voltage Range
Common-Mode Rejection Ratio
CMRR
Open-Loop Gain
AVO
Input Resistance, Differential Mode
Input Resistance, Common Mode
Input Capacitance, Differential Mode
Input Capacitance, Common Mode
OUTPUT CHARACTERISTICS
Output Voltage High
Output Voltage Low
Short-Circuit Current
Closed-Loop Output Impedance
POWER SUPPLY
Power Supply Rejection Ratio
Supply Current/Amplifier
DYNAMIC PERFORMANCE
Slew Rate
Gain Bandwidth Product
Phase Margin
NOISE PERFORMANCE
Voltage Noise
Voltage Noise Density
Uncorrelated Current Noise Density
Correlated Current Noise Density
25
−40°C ≤ TA ≤ +125°C
−40°C ≤ TA ≤ +125°C
VCM = −1.3 V to +1.3 V
−40°C ≤ TA ≤ +125°C
RL = 10 kΩ, VO = −2.0 V to +2.0 V
−40°C ≤ TA ≤ +125°C
−1.3
110
107
118
109
RINDM
RINCM
CINDM
CINCM
VOH
VOL
ISC
ZOUT
PSRR
ISY
120
135
1
1
5.5
3
RL = 100 kΩ to ground
−40°C ≤ TA ≤ +125°C
RL = 10 kΩ to ground
−40°C ≤ TA ≤ +125°C
RL = 100 kΩ to ground
−40°C ≤ TA ≤ +125°C
RL = 10 kΩ to ground
−40°C ≤ TA ≤ +125°C
2.45
2.41
2.40
2.36
2.45
−2.49
−2.45
−2.45
−2.41
−2.40
−2.36
±30
2
f = 1 kHz, AV = 1
VS = ±2.0 V to ±18.0 V
−40°C ≤ TA ≤ +125°C
IO = 0 mA
−40°C ≤ TA ≤ +125°C
2.49
125
120
145
175
225
310
V
V
V
V
V
V
V
V
mA
Ω
dB
dB
μA
μA
SR
GBP
ΦM
RL = 10 kΩ, CL = 100 pF AV = 1
RL = 10 kΩ, CL = 20 pF, AV = 1
RL = 10 kΩ, CL = 20 pF, AV = 1
0.28
540
74
V/μs
kHz
Degrees
en p-p
en
in_uncorr
in_corr
f = 0.1 Hz to 10 Hz
f = 1 kHz
f = 1 kHz
f = 1 kHz
0.2
12
0.15
0.07
μV p-p
nV/√Hz
pA/√Hz
pA/√Hz
Rev. C | Page 3 of 20
AD8622/AD8624
ELECTRICAL CHARACTERISTICS—±15 V OPERATION
VSY = ±15 V, VCM = 0 V, TA = 25°C, unless otherwise specified.
Table 3.
Parameter
INPUT CHARACTERISTICS
Offset Voltage
Symbol
Conditions
Min
VOS
Offset Voltage Drift
Input Bias Current
ΔVOS/ΔT
IB
Input Offset Current
IOS
−40°C ≤ TA ≤ +125°C
−40°C ≤ TA ≤ +125°C
Typ
Max
Unit
10
125
230
1.2
200
500
200
500
+13.8
μV
μV
μV/°C
pA
pA
pA
pA
V
dB
dB
dB
dB
GΩ
TΩ
pF
pF
0.5
45
−40°C ≤ TA ≤ +125°C
35
−40°C ≤ TA ≤ +125°C
Input Voltage Range
Common-Mode Rejection Ratio
CMRR
Open-Loop Gain
AVO
Input Resistance, Differential Mode
Input Resistance, Common Mode
Input Capacitance, Differential Mode
Input Capacitance, Common Mode
OUTPUT CHARACTERISTICS
Output Voltage High
Output Voltage Low
Short-Circuit Current
Closed-Loop Output Impedance
POWER SUPPLY
Power Supply Rejection Ratio
Supply Current/Amplifier
DYNAMIC PERFORMANCE
Slew Rate
Gain Bandwidth Product
Phase Margin
NOISE PERFORMANCE
Voltage Noise
Voltage Noise Density
Uncorrelated Current Noise Density
Correlated Current Noise Density
VCM = −13.8 V to +13.8 V
−40°C ≤ TA ≤ +125°C
RL = 10 kΩ, VO = −13.5 V to +13.5 V
−40°C ≤ TA ≤ +125°C
−13.8
125
112
125
120
RINDM
RINCM
CINDM
CINCM
VOH
VOL
ISC
ZOUT
PSRR
ISY
135
137
1
1
5.5
3
RL = 100 kΩ to ground
−40°C ≤ TA ≤ +125°C
RL = 10 kΩ to ground
−40°C ≤ TA ≤ +125°C
RL = 100 kΩ to ground
−40°C ≤ TA ≤ +125°C
RL = 10 kΩ to ground
−40°C ≤ TA ≤ +125°C
14.94
14.84
14.86
14.75
14.89
−14.97
−14.89
−14.94
−14.92
−14.90
−14.80
±40
1.5
f = 1 kHz, AV = 1
VS = ±2.0 V to ±18.0 V
−40°C ≤ TA ≤ +125°C
IO = 0 mA
−40°C ≤ TA ≤ +125°C
14.97
125
120
145
215
250
350
V
V
V
V
V
V
V
V
mA
Ω
dB
dB
μA
μA
SR
GBP
ΦM
RL = 10 kΩ, CL = 100 pF, AV = 1
RL = 10 kΩ, CL = 20 pF, AV = 1
RL = 10 kΩ, CL = 20 pF, AV = 1
0.48
560
75
V/μs
kHz
Degrees
en p-p
en
in_uncorr
in_corr
f = 0.1 Hz to 10 Hz
f = 1 kHz
f = 1 kHz
f = 1 kHz
0.2
11
0.15
0.06
μV p-p
nV/√Hz
pA/√Hz
pA/√Hz
Rev. C | Page 4 of 20
AD8622/AD8624
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
Supply Voltage
Input Voltage
Input Current1
Differential Input Voltage2
Output Short-Circuit Duration to GND
Storage Temperature Range
Operating Temperature Range
Junction Temperature Range
Lead Temperature (Soldering, 60 sec)
Rating
±18 V
±VSY
±10 mA
±10 V
Indefinite
−65°C to +150°C
−40°C to +125°C
−65°C to +150°C
300°C
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages. This
was measured using a standard 4-layer board.
Table 3. Thermal Resistance
Package Type
8-Lead SOIC_N (R-8)
8-Lead MSOP (RM-8)
14-Lead TSSOP (RU-14)
16-Lead LFCSP (CP-16-17)
1
The input pins have clamp diodes to the power supply pins. The input
current should be limited to 10 mA or less whenever input signals exceed
the power supply rail by 0.5 V.
2
Differential input voltage is limited to 10 V or the supply voltage, whichever is less.
ESD CAUTION
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. C | Page 5 of 20
θJA
120
142
112
55
θJC
45
45
35
14
Unit
°C/W
°C/W
°C/W
°C/W
AD8622/AD8624
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, unless otherwise noted.
60
60
VSY = ±15V
VCM = 0V
VSY = ±2.5V
VCM = 0V
50
NUMBER OF AMPLIFIERS
40
30
20
40
30
20
–60
–40
–20
0
20
VOS (µV)
40
60
80
100
0
–100 –80
07527-065
0
–100 –80
Figure 5. Input Offset Voltage Distribution
–60
–40
–20
0
20
VOS (µV)
60
80
100
Figure 8. Input Offset Voltage Distribution
60
60
VSY = ±15V
–40°C ≤ TA ≤ +125°C
VSY = ±2.5V
–40°C ≤ TA ≤ +125°C
50
NUMBER OF AMPLIFIERS
50
NUMBER OF AMPLIFIERS
40
07527-063
10
10
40
30
20
10
40
30
20
10
0
0.2
0.4
0.6
0.8
TCVOS (µV/°C)
1.0
1.2
0
07527-066
0
0
Figure 6. Input Offset Voltage Drift Distribution
0.2
0.4
0.6
0.8
TCVOS (µV/°C)
1.0
1.2
07527-064
NUMBER OF AMPLIFIERS
50
Figure 9. Input Offset Voltage Drift Distribution
50
50
VSY = ±15V
VSY = ±2.5V
40
40
–40°C
30
30
20
20
10
10
VOS (µV)
+25°C
–10
+85°C
–20
0
+85°C
–20
+125°C
+125°C
–30
–30
–40
–40
–50
–2.5
–1.5
–0.5
+25°C
–10
0.5
1.5
VCM (V)
2.5
–50
–15
–10
–5
0
VCM (V)
5
10
+15
Figure 10. Input Offset Voltage vs. Common-Mode Voltage
Figure 7. Input Offset Voltage vs. Common-Mode Voltage
Rev. C | Page 6 of 20
07527-004
0
07527-007
VOS (µV)
–40°C
AD8622/AD8624
0
10
VSY = ±15V
VSY = ±2.5V
IB+
–10
0
IB+
IB–
–20
–10
–20
–40
–30
–50
–40
–25
0
25
50
75
100
125
TEMPERATURE (°C)
–50
–50
07527-008
–60
–50
–25
0
25
50
75
100
125
TEMPERATURE (°C)
07527-011
IB (pA)
IB (pA)
IB–
–30
Figure 14. Input Bias Current vs. Temperature
Figure 11. Input Bias Current vs. Temperature
60
50
VSY = ±15V
VSY = ±2.5V
25
40
0
20
IB (pA)
IB (pA)
–25
–50
–75
0
–20
–100
–40
–0.5
0.5
1.5
2.5
VCM (V)
–60
–15
OUTPUT VOLTAGE TO SUPPLY RAIL (V)
1
VOL – VEE
0.01
0.001
0.01
0.1
1
LOAD CURRENT (mA)
10
100
5
10
15
VSY = ±15V
10
1
VCC – VOH
0.1
VOL – VEE
0.01
0.001
0.01
07527-013
OUTPUT VOLTAGE TO SUPPLY RAIL (V)
100
VCC – VOH
0
Figure 15. Input Bias Current vs. Common-Mode Voltage
VSY = ±2.5V
0.1
–5
VCM (V)
Figure 12. Input Bias Current vs. Common-Mode Voltage
10
–10
Figure 13. Output Voltage to Supply Rail vs. Load Current
0.1
1
LOAD CURRENT (mA)
10
100
Figure 16. Output Voltage to Supply Rail vs. Load Current
Rev. C | Page 7 of 20
07527-010
–1.5
07527-012
–150
–2.5
07527-009
–125
AD8622/AD8624
0.06
0.16
OUTPUT VOLTAGE TO SUPPLY RAIL (V)
0.05
VCC – VOH
0.04
0.03
0.02
VOL – VEE
0.01
–25
0
25
50
TEMPERATURE (°C)
75
100
125
0.12
VCC – VOH
0.10
0.08
0.06
VOL – VEE
0.04
0.02
0
–50
07527-017
0
–50
VSY = ±15V
RL = 10kΩ
0.14
Figure 17. Output Voltage to Supply Rail vs. Temperature
–25
0
25
50
TEMPERATURE (°C)
75
100
125
07527-014
OUTPUT VOLTAGE TO SUPPLY RAIL (V)
VSY = ±2.5V
RL = 10kΩ
Figure 20. Output Voltage to Supply Rail vs. Temperature
0.35
0.35
0.30
+125°C
0.30
+85°C
0.25
0.25
+25°C
ISY (mA)
ISY (mA)
0.20
0.15
–40°C
VSY = ±15V
0.20
VSY = ±2.5V
0.10
0.15
0.05
4
6
8
10
VSY (±V)
12
14
16
18
0.05
–50
100
100
VSY = ±2.5V
RL = 10kΩ
25
50
75
TEMPERATURE (°C)
100
125
100
100
VSY = ±15V
RL = 10kΩ
PHASE
80
60
60
60
60
40
40
40
40
20
0
0
–20
–40
1k
GAIN (dB)
GAIN
20
PHASE (Degrees)
80
PHASE
–20
10k
100k
FREQUENCY (Hz)
1M
–40
10M
GAIN
20
0
–20
Figure 19. Open-Loop Gain and Phase vs. Frequency
–40
1k
–20
10k
100k
FREQUENCY (Hz)
1M
–40
10M
Figure 22. Open-Loop Gain and Phase vs. Frequency
Rev. C | Page 8 of 20
80
20
0
07527-018
GAIN (dB)
0
Figure 21. Supply Current vs. Temperature
Figure 18. Supply Current vs. Supply Voltage
80
–25
PHASE (Degrees)
2
07527-015
0
07527-044
–0.05
07527-045
0.10
0
AD8622/AD8624
60
60
VSY = ±2.5V
RL = 10kΩ
50
AV = 100
40
GAIN (dB)
20
30
AV = 10
10
AV = 1
0
20
AV = 1
0
–10
–20
–20
–30
–30
–40
100
1k
10k
100k
FREQUENCY (Hz)
1M
10M
AV = 10
10
–10
–40
100
07527-019
GAIN (dB)
30
AV = 100
Figure 23. Closed-Loop Gain vs. Frequency
1k
10k
100k
FREQUENCY (Hz)
1M
10M
07527-016
40
VSY = ±15V
RL = 10kΩ
50
Figure 26. Closed-Loop Gain vs. Frequency
10k
10k
VSY = ±2.5V
VSY = ±15V
AV = 100
1k
1k
AV = 100
AV = 10
AV = 1
ZOUT (Ω)
10
1
100
10
10k
FREQUENCY (Hz)
100k
1M
0.1
100
07527-023
1k
Figure 24. Output Impedance vs. Frequency
100
100
CMRR (dB)
120
80
60
1M
60
40
20
20
1M
0
10
Figure 25. CMRR vs. Frequency
VSY = ±15V
80
40
07527-021
CMRR (dB)
120
100k
100k
140
VSY = ±2.5V
1k
10k
FREQUENCY (Hz)
10k
FREQUENCY (Hz)
Figure 27. Output Impedance vs. Frequency
140
100
1k
07527-020
1
0.1
100
0
10
AV = 1
100
1k
10k
FREQUENCY (Hz)
Figure 28. CMRR vs. Frequency
Rev. C | Page 9 of 20
100k
1M
07527-024
ZOUT (Ω)
AV = 10
100
AD8622/AD8624
120
120
VSY = ±2.5V
VSY = ±15V
100
100
PSRR+
PSRR+
80
PSRR (dB)
60
PSRR–
PSRR–
40
40
20
20
100
1k
10k
FREQUENCY (Hz)
100k
1M
0
10
07527-025
0
10
100
Figure 29. PSRR vs. Frequency
1M
50
VSY = ±2.5V
AV = 1
RL = 10kΩ
45
40
VSY = ±15V
AV = 1
RL = 10kΩ
40
35
OS–
30
OS+
25
20
30
15
10
10
5
5
1
CAPACITANCE (nF)
10
100
0
0.01
07527-029
0.1
OS+
20
15
0
0.01
OS–
25
Figure 30. Small-Signal Overshoot vs. Load Capacitance
0.1
1
CAPACITANCE (nF)
10
100
Figure 33. Small-Signal Overshoot vs. Load Capacitance
VSY = ±2.5V
AV = 1
RL = 10kΩ
CL = 100pF
TIME (40µs/DIV)
07527-030
VOLTAGE (5V/DIV)
VOLTAGE (500mV/DIV)
VSY = ±15V
AV = 1
RL = 10kΩ
CL = 100pF
TIME (40µs/DIV)
Figure 31. Large-Signal Transient Response
Figure 34. Large-Signal Transient Response
Rev. C | Page 10 of 20
07527-026
OVERSHOOT (%)
35
OVERSHOOT (%)
100k
Figure 32. PSRR vs. Frequency
50
45
1k
10k
FREQUENCY (Hz)
07527-022
60
07527-027
PSRR (dB)
80
AD8622/AD8624
VSY = ±2.5V
AV = 1
RL = 10kΩ
CL = 100pF
TIME (10µs/DIV)
07527-028
VOLTAGE (50mV/DIV)
07527-031
VOLTAGE (50mV/DIV)
VSY = ±15V
AV = 1
RL = 10kΩ
CL = 100pF
TIME (10µs/DIV)
Figure 35. Small-Signal Transient Response
Figure 38. Small-Signal Transient Response
0.4
0.4
INPUT
OUTPUT
0
0
INPUT VOLTAGE (V)
OUTPUT
0
–1
–10
–2
–20
–3
TIME (20µs/DIV)
07527-032
INPUT VOLTAGE (V)
0
OUTPUT VOLTAGE (V)
INPUT
VSY = ±15V
AV = –100
RL = 10kΩ
0.2
07527-035
0.2
OUTPUT VOLTAGE (V)
VSY = ±2.5V
AV = –100
RL = 10kΩ
TIME (20µs/DIV)
Figure 39. Negative Overload Recovery
Figure 36. Negative Overload Recovery
0.2
0.2
INPUT
0
INPUT
OUTPUT
VSY = ±15V
AV = –100
RL = 10kΩ
TIME (20µs/DIV)
07527-036
0
–1
10
OUTPUT
0
1
VSY = ±2.5V
AV = –100
RL = 10kΩ
20
Figure 37. Positive Overload Recovery
Rev. C | Page 11 of 20
–10
–20
TIME (20µs/DIV)
Figure 40. Positive Overload Recovery
07527-033
2
OUTPUT VOLTAGE (V)
INPUT VOLTAGE (V)
3
INPUT VOLTAGE (V)
–0.2
–0.2
OUTPUT VOLTAGE (V)
0
AD8622/AD8624
12
12
VSY = ±15V
AV = +1
10
10
8
8
0.1%
OUTPUT STEP (V)
0.01%
6
4
0.01%
6
4
2
0
5
10
15
20
25
SETTLING TIME (µs)
30
35
0
07527-034
0
0
5
Figure 41. Output Step vs. Settling Time
10
15
20
25
SETTLING TIME (µs)
100
VSY = ±15V
10
1
10
100
1k
FREQUENCY (Hz)
1
07527-042
1
10
1
CURRENT NOISE DENSITY (pA/ Hz)
RS2
UNCORRELATED
RS1 = 0Ω
CORRELATED
RS1 = RS2
10
100
FREQUENCY (Hz)
1k
VSY = ±15V
RS2
UNCORRELATED
RS1 = 0Ω
0.1
CORRELATED
RS1 = RS2
0.01
07527-057
0.01
1
RS1
VSY = ±2.5V
0.1
1k
Figure 45. Voltage Noise Density vs. Frequency
1
RS1
100
FREQUENCY (Hz)
Figure 42. Voltage Noise Density vs. Frequency
1
10
07527-039
VOLTAGE NOISE DENSITY (nV Hz)
VSY = ±2.5V
VOLTAGE NOISE DENSITY (nV/ Hz)
35
Figure 44. Output Step vs. Settling Time
100
CURRENT NOISE DENSITY (pA/ Hz)
30
07527-037
2
0.1%
1
10
100
FREQUENCY (Hz)
Figure 46. Current Noise Density vs. Frequency
Figure 43. Current Noise Density vs. Frequency
Rev. C | Page 12 of 20
1k
07527-056
OUTPUT STEP (V)
VSY = ±15V
AV = –1
AD8622/AD8624
TIME (1s/DIV)
07527-040
07527-043
INPUT NOISE VOLTAGE (50nV/DIV)
VSY = ±15V
INPUT NOISE VOLTAGE (50nV/DIV)
VSY = ±2.5V
TIME (1s/DIV)
Figure 47. 0.1 Hz to 10 Hz Noise
Figure 49. 0.1 Hz to 10 Hz Noise
1
1
VSY = ±2.5V
f = 1kHz
RL = 10kΩ
VSY = ±15V
f = 1kHz
RL = 10kΩ
0.1
THD + N (%)
0.01
0.0001
0.001
0.001
0.01
0.1
AMPLITUDE (V rms)
1
10
07527-049
0.001
0.01
Figure 48. THD + Noise vs. Amplitude
0.0001
0.001
0.01
0.1
AMPLITUDE (V rms)
1
Figure 50. THD + Noise vs. Amplitude
Rev. C | Page 13 of 20
10
07527-046
THD + N (%)
0.1
AD8622/AD8624
0.1
0.1
VSY = ±15V
RL = 10kΩ
VIN = 300mV rms
VSY = ±2.5V
RL = 10kΩ
VIN = 300mV rms
0.01
THD + N (%)
THD + N (%)
0.01
100
1k
FREQUENCY (Hz)
10k
100k
100kΩ
1kΩ
RL
–40
–60
–80
–100
–120
–140
10
VSY = ±2.5V TO ±15V
RL = 10kΩ
AV = –100
100
1k
FREQUENCY (Hz)
10k
100k
07527-048
CHANNEL SEPARATION (dB)
–20
100
1k
FREQUENCY (Hz)
10k
Figure 53. THD + Noise vs. Frequency
Figure 51. THD + Noise vs. Frequency
0
0.0001
10
Figure 52. Channel Separation vs. Frequency
Rev. C | Page 14 of 20
100k
07527-050
0.0001
10
0.001
07527-051
0.001
AD8622/AD8624
APPLICATIONS INFORMATION
INPUT PROTECTION
VIN
1
3 500Ω
07527-055
R2
07527-053
MICROPOWER INSTRUMENTATION AMPLIFIER
The AD8622 is a dual, high precision, rail-to-rail output op amp
operating at just 215 μA quiescent current per amplifier. Its
ultralow offset, offset drift, and voltage noise, combined with its
very low bias current and high common-mode rejection ratio
(CMRR), are ideally suited for high accuracy and micropower
instrumentation amplifier.
2 500Ω
AD862x
TIME (200µs/DIV)
Figure 55. No Phase Reversal
Figure 54. Input Protection
PHASE REVERSAL
An undesired phenomenon, phase reversal (also known as
phase inversion) occurs in many op amps when one or both of
the inputs are driven beyond the specified input voltage range
(IVR), in effect reversing the polarity of the output. In some
cases, phase reversal can induce lockups and even cause
equipment damage as well as self destruction.
The AD8622/AD8624 amplifiers have been carefully designed to
prevent output phase reversal when both inputs are maintained
within the specified input voltage range. In addition, even if one
or both inputs exceed the input voltage range but remain within
the supply rails, the output still does not phase reverse. Figure 55
shows the input/output waveforms of the AD8622/AD8624
configured as a unity-gain buffer with a supply voltage of ±15 V.
Figure 56 shows the classic 2-op-amp instrumentation amplifier
with four resistors using the AD8622. The key to high CMRR
for this instrumentation amplifier are resistors that are well
matched from both the resistive ratio and the relative drift. For
true difference amplification, matching of the resistor ratio is
very important, where R3/R4 = R1/R2. Assuming perfectly
matched resistors, the gain of the circuit is 1 + R2/R1, which is
approximately 100. Tighter matching of two op amps in one
package, like the AD8622, offers a significant boost in
performance over the classical 3-op-amp configuration. Overall,
the circuit only requires about 430 µA of supply current.
R3
10.1kΩ
R2
1MΩ
+15V
R4
1MΩ
–
1/2
AD8622
V1
R1
10.1kΩ
+15V
–
1/2
AD8622
+
–15V
V2
VO
+
NOTES
–15V
1. VO = 100(V2 – V1)
2. TYPICAL: 0.01mV < |V2 – V1| < 149.7mV
3. TYPICAL: –14.97V < VO < +14.97V
4. USE MATCHED RESISTORS.
07527-054
R1
VOUT
VOLTAGE (5V/DIV)
The maximum differential input voltage that can be applied to
the AD8622/AD8624 is determined by the internal diodes
connected across its inputs and series resistors at each input. These
internal diodes and series resistors limit the maximum
differential input voltage to ±10 V and are needed to prevent baseemitter junction breakdown from occurring in the input stage of
the AD8622/AD8624 when very large differential voltages are
applied. In addition, the internal resistors limit the currents that
flow through the diodes. However, in applications where large
differential voltages can be inadvertently applied to the device,
large currents may still flow through these diodes. In such a
case, external resistors must be placed at both inputs of the op
amp to limit the input currents to ±10 mA (see Figure 54).
VSY = ±15V
Figure 56. Micropower Instrumentation Amplifier
Rev. C | Page 15 of 20
AD8622/AD8624
HALL SENSOR SIGNAL CONDITIONING
netic field. Using the 4.12k:98.8k resistive divider, the bias
voltage of the Hall element is reduced to 100 mV, leading to only
250 µA of power consumption. The 3-op-amp in-amp
configuration of the AD8622/AD8624 then increases the
sensitivity to 55 mV/mT. The key to high CMRR for this in-amp
configuration are resistors that are well matched (where R1/R2
= R3/R4) from both the resistive ratio and relative drift. The
resistors are important in determining the performance over
manufacturing tolerances, time and temperature. At least 1% or
better resistors are recommended. Using the AD8622/AD8624 to
amplify the sensor signal can reduce power while also achieving
higher sensitivity. The total current consumed is just 1.2 mA,
resulting in 21× improvement in sensitivity/power.
The AD8622/AD8624 is also highly suitable for high accuracy,
low power signal conditioning circuits. One such use is in Hall
sensor signal conditioning (see Figure 57). The magnetic
sensitivity of a Hall element is proportional to the bias voltage
applied across it. With 1 V bias voltage, the Hall element
consumes about 2.5 mA of supply current and has a sensitivity
of 5.5 mV/mT typical. To reduce power consumption, bias
voltage must be reduced, but at the risk of lower sensitivity. The
only way to achieve higher sensitivity is by introducing a gain
using a precision micropower amplifier. The AD8622/AD8624,
with all its features, is well suited to amplify the sensitivity of the
Hall element.
The ADR121 is a precision micropower 2.5 V voltage reference.
A precision voltage reference is required to hold a constant current
so that the Hall voltage only depends on the intensity of the magVSY
VSY
+
HALL
ELEMENT
–
ADR121 – 2.5V
C2
0.1µF
C3
0.1µF
TO 10µF
R8
4.12kΩ
+
R9
98.8kΩ
VSY
+
400Ω
×4
R2
9.9kΩ
AD862x
R7
200Ω
AD862x
R5
9.9kΩ
R1
9.9kΩ
R6
9.9kΩ
R3
9.9kΩ
VSY
–
VSY
–
AD862x
+
VOUT = 2.5V +
55mV
× MAGNETIC FIELD (mT)
mT
–
AD862x
+
NOTES
1. USE MATCHED RESISTORS FOR IN-AMP.
2. FOR INFORMATION ON C1, C2, AND C3, REFER TO ADR121 DATA SHEET.
Figure 57. Hall Sensor Signal Conditioning
Rev. C | Page 16 of 20
R4
9.9kΩ
07527-052
C1
1µF TO 10µF
AD8622/AD8624
SIMPLIFIED SCHEMATIC
V+
R3
R2
R1
Q10
Q11
C1
Q3
Q4
–IN x
500Ω
500Ω
Q1
D1
INPUT BIAS
CANCELLATION
CIRCUITRY
Q6
Q5
Q8
OUT x
Q2
D2
Q7
D3
V–
Figure 58. Simplified Schematic
Rev. C | Page 17 of 20
Q9
D4
Q12
07527-062
+IN x
VB2
VB1
AD8622/AD8624
OUTLINE DIMENSIONS
3.20
3.00
2.80
8
3.20
3.00
2.80
5.15
4.90
4.65
5
1
4
PIN 1
IDENTIFIER
0.65 BSC
0.95
0.85
0.75
15° MAX
1.10 MAX
0.80
0.55
0.40
0.23
0.09
6°
0°
0.40
0.25
100709-B
0.15
0.05
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-AA
Figure 59. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
5.00 (0.1968)
4.80 (0.1890)
1
5
4
1.27 (0.0500)
BSC
0.25 (0.0098)
0.10 (0.0040)
COPLANARITY
0.10
SEATING
PLANE
6.20 (0.2441)
5.80 (0.2284)
1.75 (0.0688)
1.35 (0.0532)
0.51 (0.0201)
0.31 (0.0122)
0.50 (0.0196)
0.25 (0.0099)
45°
8°
0°
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
COMPLIANT TO JEDEC STANDARDS MS-012-A A
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 60. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
Rev. C | Page 18 of 20
012407-A
8
4.00 (0.1574)
3.80 (0.1497)
AD8622/AD8624
4.10
4.00 SQ
3.90
PIN 1
INDICATOR
0.35
0.30
0.25
0.65
BSC
16
13
PIN 1
INDICATOR
12
1
EXPOSED
PAD
2.70
2.60 SQ
2.50
4
9
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
0.25 MIN
BOTTOM VIEW
012909-B
0.80
0.75
0.70
5
8
0.45
0.40
0.35
TOP VIEW
COMPLIANT TO JEDEC STANDARDS MO-220-WGGC.
Figure 61. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
4 mm × 4mm Body, Very Very Thin Quad
(CP-16-17)
Dimensions shown in millimeters
5.10
5.00
4.90
14
8
4.50
4.40
4.30
6.40
BSC
1
7
PIN 1
0.65 BSC
1.20
MAX
0.15
0.05
COPLANARITY
0.10
0.30
0.19
0.20
0.09
SEATING
PLANE
0.75
0.60
0.45
8°
0°
COMPLIANT TO JEDEC STANDARDS MO-153-AB-1
061908-A
1.05
1.00
0.80
Figure 62. 14-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-14)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
AD8622ARMZ
AD8622ARMZ-REEL
AD8622ARMZ-R7
AD8622ARZ
AD8622ARZ-REEL
AD8622ARZ-REEL7
AD8624ACPZ-R2
AD8624ACPZ-R7
AD8624ACPZ-RL
AD8624ARUZ
AD8624ARUZ-RL
1
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
16-Lead LFCSP_WQ
16-Lead LFCSP_WQ
16-Lead LFCSP_WQ
14-Lead TSSOP
14-Lead TSSOP
Z = RoHS Compliant Part.
Rev. C | Page 19 of 20
Package Option
RM-8
RM-8
RM-8
R-8
R-8
R-8
CP-16-17
CP-16-17
CP-16-17
RU-14
RU-14
Branding
A1P
A1P
A1P
AD8622/AD8624
NOTES
©2009–2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07527-0-6/11(C)
Rev. C | Page 20 of 20