BLM7G24S-30BG
LDMOS 2-stage power MMIC
Rev. 2 — 1 July 2015
Product data sheet
1. Product profile
1.1 General description
The BLM7G24S-30BG is a 2-stage power MMIC using NXP’s state of the art Gen7
LDMOS technology. This device is perfectly suited as general purpose driver in the
frequency range from 2100 MHz to 2400 MHz. Available in gull wing.
Table 1.
Application performance
Typical RF performance at Tcase = 25 C; IDq1 = 75 mA; IDq2 = 233 mA.
Test signal: 3GPP test model 1; 64 DPCH; clipping at 46 %; PAR = 8.4 dB at 0.01% probability on
CCDF per carrier; carrier spacing = 5 MHz; unless otherwise specified in a class-AB application
circuit.
Test signal
f
VDS
PL(AV)
Gp
D
ACPR
(MHz)
(V)
(W)
(dB)
(%)
(dBc)
2-carrier W-CDMA
2140
28
1.6
31.5
11.3
43
2-carrier W-CDMA
2350
28
1.6
29.3
10.7
42
1.2 Features and benefits
Integrated temperature compensated bias
Biasing of individual stages is externally accessible
Integrated current sense
Integrated ESD protection
Excellent thermal stability
High power gain
On-chip matching for ease of use (input matched to 50 ; output partially matched)
Designed for broadband operation (frequency 2100 MHz to 2400 MHz)
Compliant to Directive 2002/95/EC, regarding Restriction of Hazardous Substances
(RoHS)
1.3 Applications
RF power MMIC for W-CDMA base stations in the 2100 MHz to 2400 MHz frequency
range.
BLM7G24S-30BG
NXP Semiconductors
LDMOS 2-stage power MMIC
2. Pinning information
2.1 Pinning
SLQLQGH[
9'6 $
9*66 $
9'66 $
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9'66 $
QF
QF
QF
QF
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QF
QF
5)B287B$9'6 $
QF
DDD
Transparent top view
The exposed backside of the package is the ground terminal of the device.
Fig 1.
Pin configuration
2.2 Pin description
Table 2.
BLM7G24S-30BG
Product data sheet
Pin description
Symbol
Pin
Description
VDS(A1)
1
drain-source voltage of stage A1
VGSS(A2)
2
gate sense FET and gate source voltage of stage A2
VDSS(A2)
3
drain sense FET source voltage of stage A2
RF_IN_A
4
RF input path A
VGSS(A1)
5
gate sense FET and gate source voltage of stage A1
VDSS(A1)
6
drain sense FET source voltage of stage A1
n.c.
7
not connected
n.c.
8
not connected
n.c.
9
not connected
n.c.
10
not connected
n.c.
11
not connected
n.c.
12
not connected
n.c.
13
not connected
n.c.
14
not connected
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 1 July 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
2 of 19
BLM7G24S-30BG
NXP Semiconductors
LDMOS 2-stage power MMIC
Table 2.
Pin description …continued
Symbol
Pin
Description
n.c.
15
not connected
RF_OUT_A/VDS(A2)
16
RF output path A / drain source voltage of stage A2
GND
flange RF ground
3. Ordering information
Table 3.
Ordering information
Type number
Package
BLM7G24S-30BG
Name
Description
Version
HSOP16
plastic, heatsink small outline package; 16 leads
SOT1212-2
4. Block diagram
9'6 $
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9*66 $
9'66 $
9*66 $
9'66 $
5)B287B$9'6 $
7(03(5$785(
&203(16$7('%,$6
QF
QF
QF
QF
QF
QF
QF
DDD
Fig 2.
Block diagram of BLM7G24S-30BG
5. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
VDS
Min
Max
Unit
drain-source voltage
-
65
V
VGS
gate-source voltage
0.5
+13
V
VGS(sense)
sense gate-source voltage
0.5
+9
V
Tstg
storage temperature
65
+150
C
-
225
C
-
150
C
Tj
junction temperature
Tcase
case temperature
[1]
BLM7G24S-30BG
Product data sheet
Conditions
[1]
Continuous use at maximum temperature will affect the MTTF.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 1 July 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
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BLM7G24S-30BG
NXP Semiconductors
LDMOS 2-stage power MMIC
6. Thermal characteristics
Table 5.
Thermal characteristics
Measured for total device.
Symbol Parameter
Rth(j-c)
[1]
Conditions
thermal resistance from
junction to case
Value Unit
final stage; Tcase = 90 C; PL = 1.6 W
[1]
2.2
K/W
driver stage; Tcase = 90 C; PL = 1.6 W
[1]
6.4
K/W
When operated with a CW signal.
7. Characteristics
Table 6.
DC characteristics
Tcase = 25 C unless otherwise specified.
Symbol Parameter
Conditions
Min Typ
Max Unit
65
-
-
V
Final stage
V(BR)DSS drain-source breakdown voltage VGS = 0 V; ID = 0.422 mA
VGS(th)
gate-source threshold voltage
VDS = 10 V; ID = 42 mA
1.5
1.9
2.3
V
VGSq
gate-source quiescent voltage
VDS = 28 V; ID = 253 mA
1.7
2.1
2.5
V
IDSS
drain leakage current
VGS = 0 V; VDS = 28 V
-
-
1.4
A
IDSX
drain cut-off current
VGS = VGS(th) + 3.75 V;
VDS = 10 V
-
7.8
-
A
IGSS
gate leakage current
VGS = 11 V; VDS = 0 V
-
-
140
nA
gfs
forward transconductance
VDS = 10 V; ID = 1478 mA
-
2.85 -
S
RDS(on)
drain-source on-state resistance VGS = VGS(th) + 3.75 V;
ID = 1.48 A
-
350
-
m
IDq
quiescent drain current
208 233
257
mA
main transistor: VDS = 28 V
sense transistor: ID = 7 mA;
VDS = 28 V
Driver stage
V(BR)DSS drain-source breakdown voltage VGS = 0 V; ID = 0.116 mA
65
-
-
V
VGS(th)
gate-source threshold voltage
VDS = 10 V; ID = 11.6 mA
1.5
1.9
2.3
V
VGSq
gate-source quiescent voltage
VDS = 28 V; ID = 69.6 mA
1.7
2.1
2.5
V
IDSS
drain leakage current
VGS = 0 V; VDS = 28 V
-
-
1.4
A
IDSX
drain cut-off current
VGS = VGS(th) + 3.75 V;
VDS = 10 V
-
2.2
-
A
IGSS
gate leakage current
VGS = 11 V; VDS = 0 V
-
-
140
nA
gfs
forward transconductance
VDS = 10 V; ID = 406 mA
-
0.8
-
S
RDS(on)
drain-source on-state resistance VGS = VGS(th) + 3.75 V;
ID = 0.4 A
-
2350 -
m
IDq
quiescent drain current
67
75
mA
main transistor: VDS = 28 V
83
sense transistor: ID = 7 mA;
VDS = 28 V
BLM7G24S-30BG
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 1 July 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
4 of 19
BLM7G24S-30BG
NXP Semiconductors
LDMOS 2-stage power MMIC
Table 7.
RF Characteristics
Typical RF performance at Tcase = 25 C; VDS = 28 V; IDq1 = 75 mA; IDq2 = 233 mA. Test signal:
2-carrier W-CDMA; 3GPP test model 1; 64 DPCH; clipping at 46 %; PAR = 8.4 dB at 0.01%
probability on CCDF per carrier; carrier spacing = 5 MHz; f1 = 2112.5 MHz; f2 = 2117.5 MHz;
f3 = 2162.5 MHz; f4 = 2167.5 MHz; unless otherwise specified measured in a class-AB production
circuit.
Symbol
Parameter
Conditions
Min
Typ
Gp
D
Max
Unit
power gain
PL(AV) = 1.6 W
29.5
drain efficiency
PL(AV) = 1.6 W
10
31.5
33.5
dB
11.3
-
%
RLin
input return loss
PL(AV) = 1.6 W
-
17
10
dB
ACPR
adjacent channel power ratio
PL(AV) = 1.6 W
-
43
40
dBc
8. Application information
8.1 Circuit information for application circuit (2.1 GHz to 2.2 GHz)
Table 8.
List of components
For test circuit see Figure 3.
BLM7G24S-30BG
Product data sheet
Component
Description
Value
C1, C4, C100, C200
capacitor
10 F
Remarks
C2, C5, C6,
capacitor
1 F
C3, C7, C10
capacitor
8.2 pF
[1]
C8
capacitor
1.6 pF
[1]
C9
capacitor
0.4 pF
[1]
C11
electrolytic capacitor 470 F
C101, C201
capacitor
100 nF
C102, C103, C105, C202, C203, C205
capacitor
12 pF
C104, C204
capacitor
4.7 F
[2]
C21, C22, C23, C24, C25, C26, C27, C28,
capacitor
C29, C30, C31, C300, C301, C302, C303,
C304, C305, C400, C401, C402, C403, C404,
C405
-
D100, D200
IC: LM4051
-
D300, D400
IC
-
not mounted
P100
potentiometer
-
do not populate
P400
potentiometer
-
not mounted
Q100, Q200
IC
-
LM7341
Q300, Q400
IC
-
not mounted
R1
ferrite bead
-
R100, R200
resistor
4.7
R101, R108, R110, R208
resistor
0
R102
resistor
360
1% tolerance
R103
resistor
330
1% tolerance
R104, R203
resistor
68 k
R105
resistor
10 k
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 1 July 2015
not mounted
© NXP Semiconductors N.V. 2015. All rights reserved.
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BLM7G24S-30BG
NXP Semiconductors
LDMOS 2-stage power MMIC
Table 8.
List of components …continued
For test circuit see Figure 3.
Component
Description
Value
R106, R205
resistor
820
R107, R206
resistor
47
R109, R209
resistor
300 k
R201
resistor
180
1% tolerance
R202
resistor
3.6 k
1% tolerance
R204
resistor
9.1 k
R207
resistor
R21, R300, R301, R302, R303, R304, R305, resistor
R306, R307, R308, R309, R400, R401, R402,
R403, R404, R405, R406, R407, R408, R409
BLM7G24S-30BG
Product data sheet
Remarks
[1]
American Technical Ceramics type 100B or capacitor of same quality.
[2]
American Technical Ceramics type 100A or capacitor of same quality.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 1 July 2015
1 k
-
not mounted
© NXP Semiconductors N.V. 2015. All rights reserved.
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NXP Semiconductors
BLM7G24S-30BG
Product data sheet
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*1'
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DDD
Printed-Circuit Board (PCB): Rogers 4350; thickness = 0.762 mm.
See Table 8 for a list of components.
Fig 3.
Component layout for class-AB application circuit with auto-bias (a halve section of the BLM7G22S-60PBG [section A] is used for
characterization)
LDMOS 2-stage power MMIC
&
*1'
BLM7G24S-30BG
&
BLM7G24S-30BG
NXP Semiconductors
LDMOS 2-stage power MMIC
8.2 Performance curves (2.1 GHz to 2.2 GHz)
Performance curves are measured in a class-AB dedicated application circuit with
auto-bias from 2.1 GHz to 2.2 GHz, see Table 8 and Figure 3.
8.2.1 W-CDMA
DDD
*S
G%
Ș'
*S
Ș'
I 0+]
Tcase = 25 C; VDS = 28 V; PL(AV) = 1.6 W; IDq1 = 75 mA;
IDq2 = 233 mA; carrier spacing = 5 MHz.
Fig 4.
Power gain and drain efficiency as function of
frequency; typical values
DDD
I 0+]
Fig 5.
Adjacent channel power ratio as a function of
frequency; typical values
DDD
Ș'
Tcase = 25 C; VDS = 28 V; PL(AV) = 1.6 W; IDq1 = 75 mA;
IDq2 = 233 mA; carrier spacing = 5 MHz.
*S
G%
DDD
$&35
G%F
$&35
G%F
*S
Ș'
3/ :
Tcase = 25 C; VDS = 28 V; f = 2140 MHz; IDq1 = 75 mA;
IDq2 = 233 mA; carrier spacing = 5 MHz.
Fig 6.
Power gain and drain efficiency as a function
of output power; typical values
BLM7G24S-30BG
Product data sheet
3/ :
Tcase = 25 C; VDS = 28 V; f = 2140 MHz; IDq1 = 75 mA;
IDq2 = 233 mA; carrier spacing = 5 MHz.
Fig 7.
Adjacent channel power ratio as a function of
output power; typical values
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 1 July 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
8 of 19
BLM7G24S-30BG
NXP Semiconductors
LDMOS 2-stage power MMIC
DDD
,'T
P$
DDD
*S
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,'T
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Ș'
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7FDVH &
3/ :
VDS = 28 V; f = 2140 MHz; IDq1 = 75 mA; IDq2 = 233 mA;
carrier spacing = 5 MHz.
(1) Tcase = 30 C
(2) Tcase = +25 C
(3) Tcase = +100 C
Fig 8.
Quiescent drain current as a function of case
temperature; typical values
Fig 9.
Power gain and drain efficiency as function of
output power; typical values
8.2.2 1-Tone pulsed CW
DDD
DDD
*S
G%
*S
G%
3/ :
Tcase = 25 C; VDS = 28 V; PL(AV) = 1.6 W; f = 2140 MHz;
IDq1 = 75 mA; IDq2 = 233 mA; = 10 %; tp = 100 s.
(1) VDD = 24 V
(1) Tcase = 30 C
(2) Tcase = +25 C
(3) VDD = 32 V
(3) Tcase = +100 C
BLM7G24S-30BG
Product data sheet
3/ :
VDS = 28 V; PL(AV) = 1.6 W; f = 2140 MHz; IDq1 = 75 mA;
IDq2 = 233 mA; = 10 %; tp = 100 s.
(2) VDD = 28 V
Fig 10. Power gain as a function of output power;
typical values
Fig 11. Power gain as a function of output power;
typical values
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 1 July 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
9 of 19
BLM7G24S-30BG
NXP Semiconductors
LDMOS 2-stage power MMIC
8.2.3 2-Tone CW
DDD
,0'
G%F
,0'
,0'
,0'
3/ 3(3 :
Tcase = 25 C; VDS = 28 V; fc = 2140 MHz; IDq1 = 75 mA; IDq2 = 233 mA; tone spacing = 100 kHz.
Fig 12. Intermodulation distortion as a function of peak envelope power load power;
typical values
BLM7G24S-30BG
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 1 July 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
10 of 19
BLM7G24S-30BG
NXP Semiconductors
LDMOS 2-stage power MMIC
8.3 Performance curves (2.3 GHz to 2.4 GHz)
Performance curves are measured in a class-AB dedicated application circuit with
auto-bias from 2.3 GHz to 2.4 GHz.
8.3.1 2-Carrier W-CDMA
DDD
*S
G%
DDD
$&35
G%F
3/ G%P
VDS = 28 V; IDq1 = 220 mA; IDq2 = 75 mA; carrier
spacing = 5MHz.
(1) f = 2300 MHz
(2) f = 2350 MHz
(2) f = 2350 MHz
(3) f = 2400 MHz
(3) f = 2400 MHz
BLM7G24S-30BG
Product data sheet
3/ G%P
VDS = 28 V; IDq1 = 220 mA; IDq2 = 75 mA; carrier
spacing = 5MHz.
(1) f = 2300 MHz
Fig 13. Power gain as a function of output power;
typical values
Fig 14. Adjacent channel power ratio as a function of
output power; typical values
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Rev. 2 — 1 July 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
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BLM7G24S-30BG
NXP Semiconductors
LDMOS 2-stage power MMIC
DDD
Ș'
3/ G%P
VDS = 28 V; IDq1 = 220 mA; IDq2 = 75 mA; carrier spacing = 5MHz.
(1) f = 2300 MHz
(2) f = 2350 MHz
(3) f = 2400 MHz
Fig 15. Drain efficiency as a function of output power; typical values
8.3.2 Pulsed CW
DDD
DDD
*S
G%
Ș'
3/ G%P
VDS = 28 V; IDq1 = 220 mA; IDq2 = 75 mA; = 10 %;
tp = 100 s.
(1) f = 2300 MHz
(2) f = 2350 MHz
(2) f = 2350 MHz
(3) f = 2400 MHz
(3) f = 2400 MHz
BLM7G24S-30BG
Product data sheet
3/ G%P
VDS = 28 V; IDq1 = 220 mA; IDq2 = 75 mA; = 10 %;
tp = 100 s.
(1) f = 2300 MHz
Fig 16. Power gain as a function of output power;
typical values
Fig 17. Efficiency as a function of output power;
typical values
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 1 July 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
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BLM7G24S-30BG
NXP Semiconductors
LDMOS 2-stage power MMIC
8.4 Application without auto-bias
9'6 $
9*66 $
9'66 $
5)B,1B$
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QF
QF
QF
QF
QF
QF
QF
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QF
DDD
Connect pins 2 and 3; connect pins 5 and 6 at board level. The exposed backside of the package
is the ground terminal of the device.
Fig 18. Non auto-bias application
9. Test information
9.1 Ruggedness
The BLM7G24S-30BG is capable of withstanding a load mismatch corresponding to
VSWR = 10 : 1 through all phases under the following conditions: VDS = 28 V;
IDq1 = 75 mA; IDq2 = 233 mA; PL = 27 W (W-CDMA); f = 2140 MHz.
9.2 Impedance information
Table 9.
Typical impedance
Measured load-pull data. Typical values per section unless otherwise specified.
BLM7G24S-30BG
Product data sheet
f
ZS [1]
ZL [1]
(MHz)
()
()
2080
55.62 + j18.89
15.89 j2.28
2110
55.61 + j19.04
14.74 j2.59
2140
55.60 + j19.12
13.56 j2.75
2170
55.57 + j19.25
12.38 j2.75
2200
55.53 + j19.39
11.20 j2.61
2230
55.48 + j19.55
10.05 j2.34
2300
34.51 + j41.45
7.06 j6.36
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 1 July 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
13 of 19
BLM7G24S-30BG
NXP Semiconductors
LDMOS 2-stage power MMIC
Table 9.
Typical impedance …continued
Measured load-pull data. Typical values per section unless otherwise specified.
f
ZS [1]
ZL [1]
(MHz)
()
()
2350
29.26 + j36.91
6.35 j6.24
2400
22.86 + j32.52
5.65 j6.15
[1]
ZS and ZL defined in Figure 19.
GUDLQ
=/
JDWH
=6
DDI
Fig 19. Definition of transistor impedance
9.3 Performance curves
DDD
Ș'
3/ G% G%P
Tcase = 25 C; VDS = 28 V; PL(AV) = 1.6 W; f = 2140 MHz; IDq1 = 75 mA; IDq2 = 233 mA; = 10 %;
tp = 100 s.
Fig 20. One-tone pulsed CW drain efficiency at 1 dB gain compression as function of
output power at 1 dB gain compression; typical values
BLM7G24S-30BG
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 1 July 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
14 of 19
BLM7G24S-30BG
NXP Semiconductors
LDMOS 2-stage power MMIC
10. Package outline
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Fig 21. Package outline SOT1212-2 (HSOP16)
BLM7G24S-30BG
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 1 July 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
15 of 19
BLM7G24S-30BG
NXP Semiconductors
LDMOS 2-stage power MMIC
11. Handling information
CAUTION
This device is sensitive to ElectroStatic Discharge (ESD). Observe precautions for handling
electrostatic sensitive devices.
Such precautions are described in the ANSI/ESD S20.20, IEC/ST 61340-5, JESD625-A or
equivalent standards.
12. Abbreviations
Table 10.
Abbreviations
Acronym
Description
3GPP
3rd Generation Partnership Project
CCDF
Complementary Cumulative Distribution Function
CW
Continuous Waveform
DPCH
Dedicated Physical CHannel
ESD
ElectroStatic Discharge
FET
Field-Effect Transistor
Gen7
Seventh-Generation
LDMOS
Laterally Diffused Metal Oxide Semiconductor
MMIC
Monolithic Microwave Integrated Circuit
MTTF
Mean Time To Failure
PAR
Peak-to-Average Ratio
VSWR
Voltage Standing Wave Ratio
W-CDMA
Wideband Code Division Multiple Access
13. Revision history
Table 11.
Revision history
Document ID
Release date Data sheet status
BLM7G24S-30BG v.2 20150701
Modifications:
Product data sheet
Supersedes
-
BLM7G24S-30BG v.1
•
Table 3 on page 3: the package version of the BLM7G24S-30BG has been changed to
SOT1212-2
•
Figure 21 on page 15: the figure now shows the SOT1212-2 package outline
BLM7G24S-30BG v.1 20131104
BLM7G24S-30BG
Product data sheet
Change notice
Product data sheet
-
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 1 July 2015
-
© NXP Semiconductors N.V. 2015. All rights reserved.
16 of 19
BLM7G24S-30BG
NXP Semiconductors
LDMOS 2-stage power MMIC
14. Legal information
14.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
14.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
14.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
BLM7G24S-30BG
Product data sheet
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 1 July 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
17 of 19
BLM7G24S-30BG
NXP Semiconductors
LDMOS 2-stage power MMIC
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
14.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
15. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
BLM7G24S-30BG
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 1 July 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
18 of 19
NXP Semiconductors
BLM7G24S-30BG
LDMOS 2-stage power MMIC
16. Contents
1
1.1
1.2
1.3
2
2.1
2.2
3
4
5
6
7
8
8.1
8.2
8.2.1
8.2.2
8.2.3
8.3
8.3.1
8.3.2
8.4
9
9.1
9.2
9.3
10
11
12
13
14
14.1
14.2
14.3
14.4
15
16
Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1
General description . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pinning information . . . . . . . . . . . . . . . . . . . . . . 2
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 2
Ordering information . . . . . . . . . . . . . . . . . . . . . 3
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3
Thermal characteristics . . . . . . . . . . . . . . . . . . 4
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Application information. . . . . . . . . . . . . . . . . . . 5
Circuit information for application circuit
(2.1 GHz to 2.2 GHz) . . . . . . . . . . . . . . . . . . . . 5
Performance curves (2.1 GHz to 2.2 GHz). . . . 8
W-CDMA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1-Tone pulsed CW . . . . . . . . . . . . . . . . . . . . . . 9
2-Tone CW . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Performance curves (2.3 GHz to 2.4 GHz). . . 11
2-Carrier W-CDMA . . . . . . . . . . . . . . . . . . . . . 11
Pulsed CW . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Application without auto-bias . . . . . . . . . . . . . 13
Test information . . . . . . . . . . . . . . . . . . . . . . . . 13
Ruggedness . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Impedance information . . . . . . . . . . . . . . . . . . 13
Performance curves . . . . . . . . . . . . . . . . . . . . 14
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 15
Handling information. . . . . . . . . . . . . . . . . . . . 16
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 16
Legal information. . . . . . . . . . . . . . . . . . . . . . . 17
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 17
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Contact information. . . . . . . . . . . . . . . . . . . . . 18
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP Semiconductors N.V. 2015.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 1 July 2015
Document identifier: BLM7G24S-30BG