Voltage Detector IC Series Counter Timer Built-in CMOS Voltage Detector IC No.09006ECT06 BD45□□□G, BD46□□□G series Description ROHM’s BD45□□□G and BD46□□□G series are highly accurate, low current consumption reset IC series. Because the counter timer delay circuit is built into those series, an external capacitor for the delay time setting is unnecessary. The lineup was established with tow output types (Nch open drain and CMOS output) and detection voltages range from 2.3V to 4.8V in increments of 0.1V, so that the series may be selected according the application at hand. Features 1) Detection voltage: 2.3V to 4.8V (Typ.), 0.1V steps 2) High accuracy detection voltage:±1.0% 3) Ultra-low current consumption: 0.85µA (Typ.) 4) Operating temperature range: -40°C to +105°C 6) SSOP5 compact surface mount packages 5) Three internal, fixed delay time: 50ms, 100ms and 200ms 7) Nch open drain output (BD45□□□G), CMOS output (BD46□□□G) Applications All electronic devices that use microcontrollers and logic circuits Selection Guide No. 1 Part Number : BD4 G 1 2 2 Specifications Output Circuit Format Detection Voltage 3 3 Fixed Delay Times Description 5:Open Drain Output, 6:CMOS Output Example: Displays VDET over a 2.3V to 4.8V range in 0.1V increments. (2.9V is marked as “29”) 5: 50ms(Typ.), 1: 100ms(Typ.) 2: 200ms(Typ.) Lineup Detection Voltage Marking Part Number Marking Part Number Marking Part Number Marking Part Number Marking Part Number Marking Part Number 4.8V 4.7V 4.6V 4.5V 4.4V 4.3V 4.2V 4.1V 4.0V 3.9V 3.8V 3.7V 3.6V 3.5V 3.4V 3.3V 3.2V 3.1V 3.0V 2.9V 2.8V 2.7V 2.6V 2.5V 2.4V 2.3V T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 TA TB TC TD TE TF TG TH TJ TK TL TM TN TP TQ TR BD45485 BD45475 BD45465 BD45455 BD45445 BD45435 BD45425 BD45415 BD45405 BD45395 BD45385 BD45375 BD45365 BD45355 BD45345 BD45335 BD45325 BD45315 BD45305 BD45295 BD45285 BD45275 BD45265 BD45255 BD45245 BD45235 TS TT TU TV TW TX TY TZ U0 U1 U2 U3 U4 U5 U6 U7 U8 U9 UA UB UC UD UE UF UG UH BD45481 BD45471 BD45461 BD45451 BD45441 BD45431 BD45421 BD45411 BD45401 BD45391 BD45381 BD45371 BD45361 BD45351 BD45341 BD45331 BD45321 BD45311 BD45301 BD45291 BD45281 BD45271 BD45261 BD45251 BD45241 BD45231 UJ UK UL UM UN UP UQ UR US UT UU UV UW UX UY UZ V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 BD45482 BD45472 BD45462 BD45452 BD45442 BD45432 BD45422 BD45412 BD45402 BD45392 BD45382 BD45372 BD45362 BD45352 BD45342 BD45332 BD45322 BD45312 BD45302 BD45292 BD45282 BD45272 BD45262 BD45252 BD45242 BD45232 VA VB VC VD VE VF VG VH VJ VK VL VM VN VP VQ VR VS VT VU VV VW VX VY VZ W0 W1 BD46485 BD46475 BD46465 BD46455 BD46445 BD46435 BD46425 BD46415 BD46405 BD46395 BD46385 BD46375 BD46365 BD46355 BD46345 BD46335 BD46325 BD46315 BD46305 BD46295 BD46285 BD46275 BD46265 BD46255 BD46245 BD46235 W2 W3 W4 W5 W6 W7 W8 W9 WA WB WC WD WE WF WG WH WJ WK WL WM WN WP WQ WR WS WT BD46481 BD46471 BD46461 BD46451 BD46441 BD46431 BD46421 BD46411 BD46401 BD46391 BD46381 BD46371 BD46361 BD46351 BD46341 BD46331 BD46321 BD46311 BD46301 BD46291 BD46281 BD46271 BD46261 BD46251 BD46241 BD46231 WU WV WW WX WY WZ X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 XA XB XC XD XE XF XG XH XJ XK BD46482 BD46472 BD46462 BD46452 BD46442 BD46432 BD46422 BD46412 BD46402 BD46392 BD46382 BD46372 BD46362 BD46352 BD46342 BD46332 BD46322 BD46312 BD46302 BD46292 BD46282 BD46272 BD46262 BD46252 BD46242 BD46232 www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 1/9 2009.05 - Rev.C Technical Note BD45□□□G, BD46□□□G series Absolute maximum ratings (Ta=25°C) Parameter Power Supply Voltage Nch Open Drain Output Output Voltage CMOS Output ER pin Voltage *1 *2 Power Dissipation Operating Temperature Ambient Storage Temperature Symbol VDD-GND Limits -0.3 ~ +10 GND-0.3 ~ +10 GND-0.3 ~ VDD+0.3 GND-0.3 ~ VDD+0.3 540 -40 ~ +105 -55 ~ +125 VOUT VCT Pd Topr Tstg Unit V V V mW °C °C *1 Use above Ta=25°C results in a 5.4mW loss per degree. *2 When mounted on a 70mm×70mm×1.6mm glass epoxy board. Electrical characteristics (Unless Otherwise Specified Ta=-40 to 105°C) Parameter Symbol *1 Detection Voltage VDET VDD=HL, RL=470kΩ Detection Voltage Temperature coefficient VDET/ ∆T -40°C~+105°C Hysteresis Voltage ∆VDET VDD＝LHL, RL=470kΩ ‘High’ Output Delay time - BD4XXX5G CL=100pF, tPLH Limit Min. Typ. Max. VDET(T) VDET(T) VDET(T) ×0.99 ×1.01 Condition RL=100kΩ BD4XXX1G *1, *2, *3 BD4XXX2G VDD=VDET-0.2V, VER=0V VDET=2.3V~3.1V *1 VDD=VDET-0.2V, VER=0V VDET=2.3V~3.1V Circuit Current when ON IDD1 VDD=VDET-0.2V, VER=0V VDET=3.2V~4.2V *1 VDD=VDET-0.2V, VER=0V VDET=3.2V~4.2V VDD=VDET-0.2V, VER=0V VDET=4.3V~4.8V *1 VDD=VDET-0.2V, VER=0V VDET=4.3V~4.8V VDD=VDET+0.2V, VER=0V VDET=2.3V~3.1V *1 VDD=VDET+0.2V, VER=0V VDET=2.3V~3.1V Circuit Current when OFF IDD2 VDD=VDET+0.2V, VER=0V VDET=3.2V~4.2V VDD=VDET+0.2V, VER=0V VDET=3.2V~4.2V VDD=VDET+0.2V, VER=0V VDET=4.3V~4.8V Operating Voltage Range ‘High’ Output Current ‘Low’Output Current (Nch) Leak Current when OFF ER Pin ‘H’ Voltage ER Pin ‘L’ Voltage ER Pin Input Current VOPL IOH IOL Ileak VEH VEL IEL *1 *1 VDD=VDET+0.2V, VER=0V VDET=4.3V~4.8V VOL≤0.4V, RL=470kΩ, Ta=25~105°C VOL≤0.4V, RL=470kΩ, Ta=-40~25°C VDS=0.5V,VDD=6.0V,VDET≥4.3V VDS=0.5V, VDD=1.2V VDS=0.5V, VDD=2.4V VDET=2.7V~4.8V *1 VDD=VDS=10V *1 *1 ±100 ±360 VDET(T) VDET(T) VDET(T) ×0.03 ×0.05 ×0.08 45 50 55 90 100 110 180 200 220 0.70 2.10 0.70 2.85 0.75 2.25 0.75 3.00 0.80 2.40 0.80 3.15 0.75 2.25 0.75 4.28 0.80 2.40 0.80 4.50 0.85 2.55 0.85 4.73 0.95 1.20 1.2 2.7 0.4 1.2 2.0 5.0 0.1 2.0 0.8 1 10 Unit V ppm/°C V ms µA µA V mA mA µA V V µA VDET(T):Standard Detection Voltage (2.3V to 4.8V, 0.1V step) RL :Pull-up resistor to be connected between VOUT and power supply. CL :Capacitor to be connected between VOUT and GND. *1 Guarantee is Ta=25°C. *2 tPLH:VDD=(VDET(T)-0.5V)(VDET(T)+0.5V) *3 tPLH:VDD=Please set up the rise up time between VDD=0VDET more than 100µs. Attention: Please connect the GND when you don’t use ‘ER’ www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 2/9 2009.05 - Rev.C Technical Note BD45□□□G, BD46□□□G series Block Diagrams BD45□□□G BD46□□□G VDD VDD Oscillation VOUT Oscillation Circuit Counter Circuit Counter Timer Timer Vref VOUT Vref GND ER GND Fig.1 Fig.2 TOP VIEW SSOP5 www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. ER PIN No. Symbol Function 1 ER 2 SUB Substrate * 3 GND GND 4 VOUT Reset Output 5 VDD Power Supply Voltage Manual Reset *Connect the substrate to GND. 3/9 2009.05 - Rev.C Technical Note BD45□□□G, BD46□□□G series Reference Data (Unless specified otherwise, Ta=25°C) 【BD45281G】 1.5 1.0 0.5 0.0 0 1 2 3 4 5 6 7 8 【BD45281G】 15 VDD =2.4V 10 5 VDD =1.2V 0 0.0 9 10 0.5 2.0 VDD =6.0V 10 VDD =4.8V 5 0 2.5 0 1 2 3 4 5 6 Fig.3 Circuit Current Fig.4 “Low” Output Current Fig.5 “High” Output Current 20 4 3 Ta=25℃ 2 1 Ta=25℃ 15 10 5 【BD45421G】 ER BIAS CURRENT ： IER[μA] 5 20 【BD46281G】 OUTPUT VOLTAGE： VOUT [V] 【BD45421G】 6 0 1 2 4.6 4.2 High to low(VDET) 3.4 0 40 5 6 7 8 80 Fig.9 Detection Voltage Release Voltage 1.5 PLH [msec] "HIGH" DELAY DELAY TIME TIME ：: ttPLH “HIGH” [ms] 【BD45421G】 1.0 0.5 20 40 60 80 1 2 【BD45421G】 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 -40 -20 0 20 40 60 100 3 4 5 6 7 8 9 10 ER VOLTAGE ： VER [V] Fig.8 ER Terminal Input Current 80 100 3.0 2.8 2.6 2.4 2.2 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 -40 -20 【BD45421G】 0 20 40 60 80 100 TEMPERATURE ： Ta[℃] TEMPERATURE ： Ta[℃] Fig.10 Circuit Current when ON (VDET-0.2V) Fig.11 Circuit Current when OFF 250 50 【BD4528□G】 200 BD45282G 150 BD45281G 100 50 BD45285G 【BD45281G tPHL 】 40 30 20 10 0 0 0 0 1.6 TEMPERATURE ： Ta[℃] -20 5 9 10 CIRCUIT CURRENT WHEN OFF ： I DD2 [μA] Low to high(VDET+ΔVDET) 3.0 ～ -40 4 ： t:PHL "LOW" [μsec] “LOW”DELAY DELAYTIME TIME tPLH [µs] CIRCUIT CURRENT WHEN ON 【BD45421G】 3.8 3 Fig.7 ER Terminal Threshold Voltage ： IDD1 [μA] 5.8 5.0 10 ER VOLTAGE ： VER[V] Fig.6 I/O Characteristics 5.4 15 0 0 VDD SUPPLY VOLTAGE ：VDD [V] 0.0 -40 15 DRAIN-SOURCE VOLTAGE ： VDS[V] 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 DETECTION VOLTAGE： VDET[V] 1.5 【BD46281G】 DRAIN-SOURCE VOLTAGE ： VDS[V] 0 MINIMUM OPERATION VOLTAGE ： V OPL[μA] 1.0 20 VDD SUPPLY VOLTAGE ：VDD [V] 7 OUTPUT VOLTAGE： VOUT [V] 20 "HIGH" OUTPUT CURRENT ： IOH [mA] "LOW" OUTPUT CURRENT ： IOL [mA] CIRCUIT CURRENT ： IDD [μA] 2.0 -60 -40 -20 0 20 40 60 80 100 120 -60 -40 -20 0 20 40 60 80 100 120 TEMPERATURE ： Ta[℃] TEMPERATURE ： Ta[℃] TEMPERATURE ： Ta[℃] Fig.12 Operating Limit Voltage Fig.13 Output Delay Time “Low””High” Fig.14 Output Delay Time “High””Low” www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 4/9 2009.05 - Rev.C Technical Note BD45□□□G, BD46□□□G series Reference Data Examples of Leading (TPLH) and Falling (TPHL) Output Part Number tPLH[ms] tPHL[µs] BD45275G 50 18 BD46275G 50 18 VDD=2.2V3.2V VDD=3.2V2.2V *This data is for reference only. The figures will vary with the application, so please confirm actual operating conditions before use. Explanation of Operation For both the open drain type (Fig.15) and the CMOS output type (Fig.16), the detection and release voltages are used as threshold voltages. When the voltage applied to the VDD pins reaches the applicable threshold voltage, the VOUT terminal voltage switches from either “High” to “Low” or from “Low” to “High”. Because the BD45□□□G series uses an open drain output type, it is possible to connect a pull-up resistor to VDD or another power supply [The output “High” voltage (VOUT) in this case becomes VDD or the voltage of the other power supply]. VDD VDD VDD R1 R1 Q2 Vref Vref Reset VOUT Oscillation Oscillation Circuit Counter R2 R2 Timer Reset Circuit Counter Timer Q1 VOUT Q1 R3 R3 GND GND ER ER Fig.15 (BD45□□□G Type Internal Block Diagram) Fig.16 (BD46□□□G Type Internal Block Diagram) Timing Waveform Example: the following shows the relationship between the input voltages VDD, the output voltage VOUT and ER terminal when the input power supply voltage VDD is made to sweep up and sweep down (the circuits are those in Fig. 12 and 13). 1 VDD VDD VDET+ΔVDET VDET 0V ⑦ VOPL VOH tPLH tPLH tPLH VOUT tPHL VOL tPHL VEH ER tPHL ① ② ③ ④⑤ Fig.17 www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. ⑥ When the power supply is turned on, the output is unsettled from after over the operating limit voltage (VOPL) until TPHL. There fore it is possible that the reset signal is not outputted when the rise time of VDD is faster than TPHL. 2 When VDD is greater than VOPL but less than the reset release voltage (VDET + ∆VDET), the output voltages will switch to Low. 3 If VDD exceeds the reset release voltage (VDET + ∆VDET), the counter timer start and VOUT switches from L to H. 4 When more than the high level voltage is supplied ER terminal, VOUT comes to “L” after tPLH delay time. Therefore, a time when ER terminal is “H” is necessary for 100µsec or more. 5 When the ER terminal switches to Low, the counter timer starts to operate, a delay of tPLH occurs, and VOUT switches from “L” to “H”. 6 If VDD drops below the detection voltage (VDET) when the power supply is powered down or when there is a power supply fluctuation, VOUT switches to L (with a delay of tPHL). 7 The potential difference between the detection voltage and the release voltage is known as the hysteresis width (∆VDET). The system is designed such that the output does not flip-flop with power supply fluctuations within this hysteresis width, preventing malfunctions due to noise. These time changes by the application and use it, please verify and confirm using practical applications. 5/9 2009.05 - Rev.C Technical Note BD45□□□G, BD46□□□G series Circuit Applications 1) Examples of a common power supply detection reset circuit. VDD1 VDD2 RL BD45□□□ Microcontroller CL （Noise-filtering Capacitor） GND Application examples of BD45□□□G series (Open Drain output type) and BD46□□□G series (CMOS output type) are shown below. CASE1: the power supply of the microcontroller (VDD2) differs from the power supply of the reset detection (VDD1). Use the open drain output type (BD45□□□G) attached a load resistance (RL) between the output and VDD2. (As shown Fig.18) Fig.18 Open Collector Output Type CASE2: the power supply of the microcontroller (VDD1) is same as the power supply of the reset detection (VDD1). Use CMOS output type (BD46□□□G) or open drain output type (BD45□□□G) attached a load resistance (RL) between the output and Vdd1. (As shown Fig.19) VDD1 BD46□□□ Microcontroller CL When a capacitance CL for noise filtering is connected to the VOUT pin (the reset signal input terminal of the microcontroller), please take into account the waveform of the rise and fall of the output voltage (VOUT). （Noise-filtering Capacitor） GND Fig.19 CMOS Output Type 2) The following is an example of a circuit application in which an OR connection between two types of detection voltages resets the microcontroller. VDD1 VDD3 VDD2 RL ER BD45□□□ No.1 VOUT ER BD45□□□ No.2 VOUT microcontroller RST GND Fig.20 When there are many power supplies of the system, power supplies VDD1 and VDD2 are being monitored separately, and it is necessary to reset the microcomputer, it is possible to use an OR connection on the open drain output type BD45□□□G series to pull-up to the desired voltage (VDD3) as shown in Fig. 20 and make the output “High” voltage matches the power supply voltage VDD3 of the microcontroller. www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 6/9 2009.05 - Rev.C Technical Note BD45□□□G, BD46□□□G series Examples of the power supply with resistor dividers In applications where the power supply input terminal (VDD) of an IC with resistor dividers, it is possible that a through current will momentarily flow into the circuit when the output logic switches, resulting in malfunctions (such as output oscillatory state). (Through-current is a current that momentarily flows from the power supply (VDD) to ground (GND) when the output level switches from “High” to “Low” or vice versa.) V1 R2 I1 R1 CIN VDD ER BD45□□□G BD46□□□G VOUT CL GND Fig.21 A voltage drop of [the through-current (I1)] × [input resistor (R2)] is caused by the through current, and the input voltage to descends, when the output switches from “Low” to “High”. When the input voltage decreases and falls below the detection voltage, the output voltage switches from “High” to “Low”. At this time, the through-current stops flowing through output “Low”, and the voltage drop is eliminated. As a result, the output switches from “Low” to “High”, which again causes the through current to flow and the voltage drop. This process is repeated, resulting in oscillation. IDD Through Current VDD VDET 0 Fig.22 Current Consumption vs. Power Supply Voltage www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 7/9 2009.05 - Rev.C Technical Note BD45□□□G, BD46□□□G series Operation Notes (1) Absolute maximum range Absolute Maximum Ratings are those values beyond which the life of a device may be destroyed. We cannot be defined the failure mode, such as short mode or open mode. Therefore a physical security countermeasure, like fuse, is to be given when a specific mode to be beyond absolute maximum ratings is considered. (2) GND potential GND terminal should be a lowest voltage potential every state. Please make sure all pins, which are over ground even if, include transient feature. (3) Electrical Characteristics Be sure to check the electrical characteristics that are one the tentative specification will be changed by temperature, supply voltage, and external circuit. (4) Bypass Capacitor for Noise Rejection Please put into the capacitor of 1µF or more between VDD pin and GND, and the capacitor of about 1000pF between VOUT pin and GND, to reject noise. If extremely big capacitor is used, transient response might be late. Please confirm sufficiently for the point. (5) Short Circuit between Terminal and Soldering Don’t short-circuit between Output pin and VDD pin, Output pin and GND pin, or VDD pin and GND pin. When soldering the IC on circuit board, please be unusually cautious about the orientation and the position of the IC. When the orientation is mistaken the IC may be destroyed. (6) Electromagnetic Field Mal-function may happen when the device is used in the strong electromagnetic field. (7) The VDD line inpedance might cause oscillation because of the detection current. (8) A VDD -GND capacitor (as close connection as possible) should be used in high VDD line impedance condition. (9) Lower than the mininum input voltage makes the VOUT high impedance, and it must be VDD in pull up (VDD) condition. (10) This IC has extremely high impedance terminals. Small leak current due to the uncleanness of PCB surface might cause unexpected operations. Application values in these conditions should be selected carefully. If the leakage of about 1MΩ is assumed between the ER terminal and the GND terminal, 100kΩ connection between the ER terminal and the VDD terminal would be recommended. If the leakage is assumed between the VOUT terminal and the GND terminal, the pull-up resistor should be less than 1/10 of the assumed leak resistance. (11) External parameters The recommended parameter range for RL is 50kΩ~1MΩ. There are many factors (board layout, etc) that can affect characteristics. Please verify and confirm using practical applications. (12) Power on reset operation Please note that the power on reset output varies with the VDD rise up time. Please verify the actual operation. (13) Precautions for board inspection Connecting low-impedance capacitors to run inspections with the board may produce stress on the IC. Therefore, be certain to use proper discharge procedure before each process of the test operation. To prevent electrostatic accumulation and discharge in the assembly process, thoroughly ground yourself and any equipment that could sustain ESD damage, and continue observing ESD-prevention procedures in all handing, transfer and storage operations. Before attempting to connect components to the test setup, make certain that the power supply is OFF. Likewise, be sure the power supply is OFF before removing any component connected to the test setup. (14) When the power supply, is turned on because of in certain cases, momentary Rash-current flow into the IC at the logic unsettled, the couple capacitance, GND pattern of width and leading line must be considered. www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 8/9 2009.05 - Rev.C Technical Note BD45□□□G, BD46□□□G series Part Number Selection B D BD45: 4 2 5 3 1 － G T R Open Drain Type Reset Voltage Value Counter Timer Package Taping Specifications CMOS Detector IC with 23: 2.3V Delay Time Settings G：SSOP5 Embossed Taping Built-In Counter Timer 48: 4.8V 5: 50ms 1: 100ms BD46: 2: 200ms CMOS Output Type CMOS Detector IC with Built-In Counter Timer SSOP5 <Dimension> (Unit：mm) 2.9±0.2 1 2 0.2Min. +0.2 4 1.6 −0.1 2.8±0.2 5 +6° 4° −4° 3 0.05±0.05 1.25Max. 1.1±0.05 0.13 <Tape and Reel information> SSOP5 Tape Embossed carrier tape Quantity 3000pcs Direction of feed TR (The direction is the 1pin of product is at the upper left when you hold reel on the left hand and you pull out the tape on the right hand) +0.05 −0.03 0.42 +0.05 −0.04 0.95 X X X X X X 0.1 X X X X X X X X X X X X 1Pin X X X X X X X X X X X X Direction of feed Reel * When you order, please order in times the amount of package quantity. www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 9/9 2009.05 - Rev.C Notice Notes No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM Co.,Ltd. The content specified herein is subject to change for improvement without notice. The content specified herein is for the purpose of introducing ROHM's products (hereinafter "Products"). If you wish to use any such Product, please be sure to refer to the specifications, which can be obtained from ROHM upon request. Examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the Products. The peripheral conditions must be taken into account when designing circuits for mass production. Great care was taken in ensuring the accuracy of the information specified in this document. However, should you incur any damage arising from any inaccuracy or misprint of such information, ROHM shall bear no responsibility for such damage. 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