Product Folder Order Now Technical Documents Support & Community Tools & Software DAC5652A SLAS535E – SEPTEMBER 2007 – REVISED MAY 2018 DAC5652A Dual, 10-Bit, 275-MSPS Digital-to-Analog Converter 1 Features 3 Description • • • • The DAC5652A is a monolithic, dual-channel, 10-bit, high-speed digital-to-analog converter (DAC) with onchip voltage reference. 1 • • • • • • • 10-Bit Dual Transmit DAC 275 MSPS Update Rate Single Supply: 3.0 V to 3.6 V High Spurious-Free Dynamic Range (SFDR): 80 dBc at 5 MHz High Third-Order Two-Tone Intermodulation (IMD3): 78 dBc at 15.1 MHz and 16.1 MHz Independent or Single Resistor Gain Control Dual or Interleaved Data On-Chip 1.2-V Reference Low Power: 290 mW Power-Down Mode: 9 mW Packages: – 48-Pin Thin-Quad Flat Pack (TQFP) – 48-Pin Very-Thin-Quad Flat Pack (VQFN) 2 Applications • • • • • Cellular Base Transceiver Station Transmit Channel – CDMA: W-CDMA, CDMA2000, IS-95 – TDMA: GSM, IS-136, EDGE/UWC-136 Medical/Test Instrumentation Arbitrary Waveform Generators (ARB) Direct Digital Synthesis (DDS) Cable Modem Termination System (CMTS) Functional Block Diagram WRTB WRTA CLKB CLKA DEMUX IOUTA1 Latch A Operating with update rates of up to 275 MSPS, the DAC5652A offers exceptional dynamic performance, tight-gain, and offset matching characteristics that make it suitable in either I/Q baseband or direct IF communication applications. Each DAC has a high-impedance, differential-current output, suitable for single-ended or differential analog-output configurations. External resistors allow scaling of the full-scale output current for each DAC separately or together, typically between 2 mA and 20 mA. An accurate on-chip voltage reference is temperature-compensated and delivers a stable 1.2-V reference voltage. Optionally, an external reference may be used. The DAC5652A has two, 10-bit, parallel input ports with separate clocks and data latches. For flexibility, the DAC5652A also supports multiplexed data for each DAC on one port when operating in the interleaved mode. The DAC5652A has been specifically designed for a differential transformer-coupled output with a 50-Ω doubly-terminated load. For a 20-mA full-scale output current, both a 4:1 impedance ratio (resulting in an output power of 4 dBm) and 1:1 impedance ratio transformer (–2-dBm output power) are supported. The DAC5652A is available in a 48-pin TQFP package. Pin compatibility between family members provides 10-bit (DAC5652A), 12-bit (DAC5662), and 14-bit (DAC5672) resolution. Furthermore, the DAC5652A is pin compatible to the DAC2900 and AD9763 dual DACs. The device is characterized for operation over the industrial temperature range of –40°C to +85°C. 10−b DAC IOUTA2 DA[9:0] BIASJ_A Device Information(1) PART NUMBER DAC5652A BODY SIZE (NOM) 7 mm × 7 mm VQFN (48) 6 mm × 6 mm IOUTB1 Latch B DB[9:0] PACKAGE TQFP (48) 10−b DAC IOUTB2 MODE (1) For all available packages, see the package option addendum at the end of the data sheet. BIASJ_B GSET 1.2 V Reference EXTIO SLEEP DVDD DGND AVDD AGND 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. DAC5652A SLAS535E – SEPTEMBER 2007 – REVISED MAY 2018 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 5 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 6.10 5 5 5 5 6 7 8 8 8 9 Absolute Maximum Ratings ...................................... ESD Ratings ............................................................ Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics: DC .................................. Electrical Characteristics: AC................................... Electrical Characteristics: Digital Input..................... Electrical Characteristics: Power Supply .................. Switching Characteristics......................................... Typical Characteristics ............................................ Detailed Description ............................................ 11 7.1 Overview ................................................................. 11 7.2 Functional Block Diagram ....................................... 11 7.3 Feature Description................................................. 12 7.4 Device Functional Modes........................................ 14 8 Application and Implementation ........................ 17 8.1 Application Information............................................ 17 8.2 Typical Application ................................................. 21 9 Power Supply Recommendations...................... 22 10 Layout................................................................... 22 10.1 Layout Guidelines ................................................. 22 10.2 Layout Examples................................................... 23 11 Device and Documentation Support ................. 26 11.1 11.2 11.3 11.4 11.5 11.6 Documentation Support ....................................... Receiving Notification of Documentation Updates Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 26 26 26 26 26 26 12 Mechanical, Packaging, and Orderable Information ........................................................... 26 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision D (August 2012) to Revision E Page • Added Device Information, ESD Ratings, Recommended Operating Conditions tables; and Detailed Description, Applications and Implementation, Power-Supply Recommendations, Layout, Device and Documentation Support, and Mechanical, Packaging, and Orderable Information sections; existing content moved to new sections ........................ 1 • Added new VQFN-48 package and associated content......................................................................................................... 1 Changes from Revision C (June 2011) to Revision D Page • Deleted the VIH MAX value of 3.3 V ....................................................................................................................................... 8 • Deleted the VIL MIN value of 0 V............................................................................................................................................ 8 Changes from Revision B (December 2010) to Revision C • Added Thermal Information table ........................................................................................................................................... 5 Changes from Revision A (May 2009) to Revision B • Page Page Changed the non-printing µ symbols in the Digital Input section of the Electrical Characteristics table (units column) to the correct µ symbols recognized by the PDF processor .................................................................................................. 8 Changes from Original (September 2007) to Revision A Page • Added internal pulldown to DA and DB pin descriptions........................................................................................................ 4 • Added GSET to Absolute Maximum Ratings table................................................................................................................. 5 • Added "The pullup and pulldown circuitry is approximately equivalent to 100 kΩ" to Digital Inputs section ....................... 12 • Added resistor values to Figure 13....................................................................................................................................... 12 • Added resistor values to Figure 14....................................................................................................................................... 12 2 Submit Documentation Feedback Copyright © 2007–2018, Texas Instruments Incorporated Product Folder Links: DAC5652A DAC5652A www.ti.com SLAS535E – SEPTEMBER 2007 – REVISED MAY 2018 5 Pin Configuration and Functions MODE AVDD IOUTA1 IOUTA2 BIASJ_A EXTIO GSET BIASJ_B IOUTB2 IOUTB1 AGND SLEEP 48 47 46 45 44 43 42 41 40 39 38 37 PFB Package 48-Pin TQFP Top View DB0 DA4 6 31 DB1 DA3 7 30 DB2 DA2 8 29 DB3 DA1 9 28 DB4 DA0 10 27 DB5 NC 11 26 DB6 NC 12 25 DB7 Not to scale DB8 DB9 DVDD DGND WRTB/SELECTIQ CLKB/RESETIQ CLKA/CLKIQ WRTA/WRTIQ DVDD DGND NC NC 24 NC 32 23 33 5 22 4 DA5 21 DA6 20 NC 19 34 18 3 17 NC DA7 16 NC 35 15 36 2 14 1 DA8 13 DA9 NC NC DA0 DA1 DA2 DA3 DA4 DA5 DA6 DA7 DA8 DA9 48 47 46 45 44 43 42 41 40 39 38 37 RSL Package 48-Pin VQFN Top View NC 1 36 MODE NC 2 35 AVDD DGND 3 34 IOUTA1 DVDD 4 33 IOUTA2 WRTA/WRTIQ 5 32 BIASJ_A CLKA/CLKIQ 6 31 EXTIO CLKB/RESETIQ 7 30 GSET WRTB/SELECTIQ 8 29 BIASJ_B DGND 9 28 IOUTB2 DVDD 10 27 IOUTB1 DB9 11 26 AGND DB8 12 25 SLEEP Thermal 13 14 15 16 17 18 19 20 21 22 23 24 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 NC NC NC NC Pad Not to scale Submit Documentation Feedback Copyright © 2007–2018, Texas Instruments Incorporated Product Folder Links: DAC5652A 3 DAC5652A SLAS535E – SEPTEMBER 2007 – REVISED MAY 2018 www.ti.com Pin Functions PIN I/O DESCRIPTION NAME TQFP VQFN AGND 38 26 I Analog ground AVDD 47 35 I Analog supply voltage BIASJ_A 44 32 O Full-scale output current bias for DACA BIASJ_B 41 29 O Full-scale output current bias for DACB CLKA/CLKIQ 18 6 I Clock input for DACA, CLKIQ in interleaved mode CLKB/RESETIQ 19 7 I Clock input for DACB, RESETIQ in interleaved mode DA0 10 46 I Data port A0 (LSB). Internal pulldown. DA1 9 45 I Data port A1. Internal pulldown. DA2 8 44 I Data port A2. Internal pulldown. DA3 7 43 I Data port A3. Internal pulldown. DA4 6 42 I Data port A4. Internal pulldown. DA5 5 41 I Data port A5. Internal pulldown. DA6 4 40 I Data port A6. Internal pulldown. DA7 3 39 I Data port A7. Internal pulldown. DA8 2 38 I Data port A8. Internal pulldown. DA9 1 37 i Data port A9 (MSB). Internal pulldown. DB0 32 20 I Data port B0 (LSB). Internal pulldown. DB1 31 19 I Data port B1. Internal pulldown. DB2 30 18 I Data port B2. Internal pulldown. DB3 29 17 I Data port B3. Internal pulldown. DB4 28 16 I Data port B4. Internal pulldown. DB5 27 15 I Data port B5. Internal pulldown. DB6 26 14 I Data port B6. Internal pulldown. DB7 25 13 I Data port B7. Internal pulldown. DB8 24 12 I Data port B8. Internal pulldown. DB9 23 11 I Data port B9 (MSB). Internal pulldown. DGND 15, 21 3, 9 I Digital ground DVDD 16, 22 4, 10 I Digital supply voltage EXTIO 43 31 I/O GSET 42 30 I Gain-setting mode: H – 1 resistor, L – 2 resistors. Internal pullup. IOUTA1 46 34 O DACA current output. Full-scale with all bits of DA high. IOUTA2 45 33 O DACA complementary current output. Full-scale with all bits of DA low. IOUTB1 39 27 O DACB current output. Full-scale with all bits of DB high. IOUTB2 40 28 O DACB complementary current output. Full-scale with all bits of DB low. MODE 48 36 I Mode Select: H – Dual Bus, L – Interleaved. Internal pullup. 11-14, 3336 1,2, 21-24, 47, 48 — Factory use only. Pins must be connected to DGND or left unconnected. SLEEP 37 25 I Sleep function control input: H – DAC in power-down mode, L – DAC in operating mode. Internal pulldown. WRTA/WRTIQ 17 5 I Input write signal for PORT A (WRTIQ in interleaving mode) WRTB/SELECTIQ 20 8 I Input write signal for PORT B (SELECTIQ in interleaving mode) NC 4 Internal reference output (bypass with 0.1 μF to AGND) or external reference input Submit Documentation Feedback Copyright © 2007–2018, Texas Instruments Incorporated Product Folder Links: DAC5652A DAC5652A www.ti.com SLAS535E – SEPTEMBER 2007 – REVISED MAY 2018 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) Voltage MIN MAX AVDD (measured with respect to AGND) –0.5 4 DVDD (measured with respect to DGND) –0.5 4 Between AGND and DGND –0.5 0.5 Between AVDD and DVDD –4 4 DA[9:0] and DB[9:0] –0.5 DVDD + 0.5 MODE, SLEEP, CLKA, CLKB, WRTA, WRTB –0.5 DVDD + 0.5 –1 AVDD + 0.5 –0.5 AVDD + 0.5 IOUTA1, IOUTA2, IOUTB1, IOUTB2 EXTIO, BIASJ_A, BIASJ_B, GSET Current Temperature (1) Peak input current (any input) 20 Peak total input current (all inputs) –30 UNIT V mA Operating free-air, TA –40 85 °C Storage, Tstg –65 150 °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 6.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) UNIT ±2000 Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) V ±1000 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions MIN NOM MAX UNIT AVDD Analog supply voltage 3 3.3 3.6 V DVDD Digital supply voltage 3 3.3 3.6 V 1.25 V 275 MHz 85 °C Output voltage compliance range (1) –1 Clock input frequency TA (1) Operating free-air temperature –40 The lower limit of the output compliance is determined by the CMOS process. Exceeding this limit may result in transistor breakdown, resulting in reduced reliability of the DAC5652A device. The upper limit of the output compliance is determined by the load resistors and full-scale output current. Exceeding the upper limit adversely affects distortion performance and integral nonlinearity. 6.4 Thermal Information DAC5652A THERMAL METRIC (1) PFB (TQFP) RSL (VQFN) 48 PINS 48 PINS UNIT RθJA Junction-to-ambient thermal resistance 65.3 27.0 °C/W RθJC(top) Junction-to-case (top) thermal resistance 16.4 17.3 °C/W RθJB Junction-to-board thermal resistance 28.6 9.6 °C/W ψJT Junction-to-top characterization parameter 0.4 0.2 °C/W ψJB Junction-to-board characterization parameter 28.4 9.6 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A 2.2 °C/W (1) For information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Submit Documentation Feedback Copyright © 2007–2018, Texas Instruments Incorporated Product Folder Links: DAC5652A 5 DAC5652A SLAS535E – SEPTEMBER 2007 – REVISED MAY 2018 6.5 www.ti.com Electrical Characteristics: DC dc specifications over TA, AVDD = DVDD = 3.3 V, I(OUTFS) = 20 mA, and independent gain set mode (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT RESOLUTION Resolution 10 Bits DC ACCURACY (1) INL Integral nonlinearity DNL Differential nonlinearity 1 LSB = I(OUTFS)/210, TMIN to TMAX –1 ±0.25 1 LSB –0.5 ±0.16 0.5 LSB ANALOG OUTPUT Offset error Midscale value (internal reference) ±0.05 %FSR Offset mismatch Midscale value (internal reference) ±0.03 %FSR Gain error With internal reference ±0.75 %FSR Minimum full-scale output current (2) Maximum full-scale output current 2 (2) Gain mismatch 20 With internal reference Output voltage compliance range (3) RO Output resistance CO Output capacitance mA –2 0.2 –1 mA 2 1.25 %FSR V 300 kΩ 5 pF REFERENCE OUTPUT Reference voltage Reference output current 1.14 (4) 1.2 1.26 100 V nA REFERENCE INPUT V(EXTIO) Input voltage RI Input resistance CI 0.1 1.25 V 1 MΩ Small signal bandwidth 300 kHz Input capacitance 100 pF TEMPERATURE COEFFICIENTS Offset drift Gain drift 2 With external reference ±20 With internal reference ±40 ppm of FSR/°C ±20 ppm/°C Reference voltage drift (1) (2) (3) (4) 6 ppm of FSR/°C Measured differentially through 50 Ω to AGND. Nominal full-scale current, I(OUTFS), equals 32x the I(BIAS) current. The lower limit of the output compliance is determined by the CMOS process. Exceeding this limit may result in transistor breakdown, resulting in reduced reliability of the DAC5652A device. The upper limit of the output compliance is determined by the load resistors and full-scale output current. Exceeding the upper limit adversely affects distortion performance and integral nonlinearity. Use an external buffer amplifier with high-impedance input to drive any external load. Submit Documentation Feedback Copyright © 2007–2018, Texas Instruments Incorporated Product Folder Links: DAC5652A DAC5652A www.ti.com 6.6 SLAS535E – SEPTEMBER 2007 – REVISED MAY 2018 Electrical Characteristics: AC ac specifications over TA, AVDD = DVDD = 3.3 V, I(OUTFS) = 20 mA, independent gain set mode, differential 1:1 impedance ratio transformer coupled output, and 50-Ω doubly terminated load (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ANALOG OUTPUT fclk Maximum output update rate (1) ts Output settling time to 0.1% (DAC) tr tf 275 20 ns Output rise time 10% to 90% (OUT) 1.4 ns Output fall time 90% to 10% (OUT) 1.5 ns Output noise Midscale transition MSPS I(OUTFS) = 20 mA 55 I(OUTFS) = 2 mA 30 1st Nyquist zone, TA = 25°C, fDATA = 50 MSPS, fOUT = 1 MHz, I(OUTFS) = 0 dB 79 1st Nyquist zone, TA = 25°C, fDATA = 50 MSPS, fOUT = 1 MHz, I(OUTFS) = –6 dB 78 1st Nyquist zone, TA = 25°C, fDATA = 50 MSPS, fOUT = 1 MHz, I(OUTFS) = –12 dB 73 1st Nyquist zone, TA = 25°C, fDATA = 100 MSPS, fOUT = 5 MHz, I(OUTFS) = 0 dB 80 1st Nyquist zone, TA = 25°C, fDATA = 100 MSPS, fOUT = 20 MHz, I(OUTFS) = 0 dB 76 pA/√Hz AC LINEARITY SFDR Spurious-free dynamic range 1st Nyquist zone, TMIN to TMAX, fDATA = 200 MSPS, fOUT = 20 MHz, I(OUTFS) = 0 dB SNR IMD3 IMD Signal-to-noise ratio Third-order two-tone intermodulation Four-tone intermodulation Channel isolation (1) dBc 61 70 1st Nyquist zone, TA = 25°C, fDATA = 200 MSPS, fOUT = 41 MHz, I(OUTFS) = 0 dB 67 1st Nyquist zone, TA = 25°C, fDATA = 275 MSPS, fOUT = 20 MHz 70 1st Nyquist zone, TA = 25°C, fDATA = 100 MSPS, fOUT = 5 MHz, I(OUTFS) = 0 dB 63 dB 1st Nyquist zone, TA = 25°C, fDATA = 160 MSPS, fOUT = 20 MHz, I(OUTFS) = 0 dB 62 dB Each tone at –6 dBFS, TA = 25°C, fDATA = 200 MSPS, fOUT = 45.4 MHz and 46.4 MHz 61 Each tone at –6 dBFS, TA = 25°C, fDATA = 100 MSPS, fOUT = 15.1 MHz and 16.1 MHz 78 Each tone at –12 dBFS, TA = 25°C fDATA = 100 MSPS, fOUT = 15.6, 15.8, 16.2, and 16.4 MHz 76 Each tone at –12 dBFS, TA = 25°C fDATA = 165 MSPS, fOUT = 19.0, 19.1, 19.3, and 19.4 MHz 55 Each tone at –12 dBFS, TA = 25°C fDATA = 165 MSPS, fOUT = 68.8, 69.6, 71.2, and 72.0 MHz 70 TA = 25°C, fDATA = 165 MSPS fOUT (CH1) = 20 MHz, fOUT (CH2) = 21 MHz 90 dBc dBc dBc Specified by design and bench characterization. Not production tested. Submit Documentation Feedback Copyright © 2007–2018, Texas Instruments Incorporated Product Folder Links: DAC5652A 7 DAC5652A SLAS535E – SEPTEMBER 2007 – REVISED MAY 2018 6.7 www.ti.com Electrical Characteristics: Digital Input digital specifications over TA, AVDD = DVDD = 3.3 V, and I(OUTFS) = 20 mA (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VIH High-level input voltage VIL Low-level input voltage 2 V IIH High-level input current ±50 µA IIL Low-level input current ±10 µA IIH(GSET) High-level input current, GSET pin 7 µA IIL(GSET) Low-level input current, GSET pin –80 µA IIH(MODE) High-level input current, MODE pin –30 µA IIL(MODE) Low-level input current, MODE pin –80 µA CI Input capacitance 5 pF 0.8 V 6.8 Electrical Characteristics: Power Supply power supply specifications over TA, AVDD = DVDD = 3.3 V, I(OUTFS) = 20 mA, fDATA = 200 MSPS, fOUT = 1 MHz, and independent gain set mode (unless otherwise noted) PARAMETER I(AVDD) Supply current, analog I(DVDD) Supply current, digital TEST CONDITIONS MIN TYP MAX Including output current through load resistor 75 90 Sleep mode with clock 2.5 Sleep mode without clock 2.5 Sleep mode with clock Sleep mode without clock mA 12 20 11.3 18 mA 0.6 290 Power dissipation UNIT Sleep mode with clock 360 45.5 Sleep mode without clock 9.2 fDATA = 275 MSPS, fOUT = 20 MHz 310 mW APSRR Analog power supply rejection ratio –0.2 –0.01 0.2 %FSR/V DPSRR Digital power supply rejection ratio –0.2 0 0.2 %FSR/V TYP MAX 6.9 Switching Characteristics digital specifications over TA, AVDD = DVDD = 3.3 V, and I(OUTFS) = 20 mA (unless otherwise noted) PARAMETER TEST CONDITIONS MIN UNIT TIMING - DUAL BUS MODE tsu Input setup time 1 th Input hold time 1 tLPH Input clock pulse high time tLAT Clock latency (WRTA/B to outputs) tPD Propagation delay time ns ns 1 4 ns 4 clk 1.5 ns TIMING - SINGLE BUS INTERLEAVED MODE tsu Input setup time 0.5 ns th Input hold time 0.5 ns tLAT Clock latency (WRTA/B to outputs) tPD Propagation delay time 8 4 4 1.5 Submit Documentation Feedback clk ns Copyright © 2007–2018, Texas Instruments Incorporated Product Folder Links: DAC5652A DAC5652A www.ti.com SLAS535E – SEPTEMBER 2007 – REVISED MAY 2018 0.5 0.4 0.3 0.2 0.1 0.0 −0.1 −0.2 −0.3 −0.4 −0.5 0 100 200 300 400 500 600 700 800 900 Input Code 1000 G001 DNL − Differential Nonlinearity Error − LSB INL − Integral Nonlinearity Error − LSB 6.10 Typical Characteristics 0.25 0.20 0.15 0.10 0.05 0.00 −0.05 −0.10 −0.15 −0.20 −0.25 0 100 200 300 400 500 600 700 800 900 Input Code Figure 1. Integral Nonlinearity vs Input Code 100 SFDR − Spurious-Free Dynamic Range − dBc SFDR − Spurious-Free Dynamic Range − dBc G002 Figure 2. Differential Nonlinearity vs Input Code 100 fdata = 52 MSPS Dual Bus Mode 95 90 85 −6 dBfS 0 dBfS 80 75 −12 dBfS 70 65 60 fdata = 78 MSPS Dual Bus Mode 95 90 85 −6 dBfS 80 75 −12 dBfS 70 0 dBfS 65 60 0 4 8 12 16 20 fout − Output Frequency − MHz 0 5 10 15 20 25 fout − Output Frequency − MHz G003 Figure 3. Spurious-Free Dynamic Range vs Output Frequency 30 G004 Figure 4. Spurious-Free Dynamic Range vs Output Frequency 100 SFDR − Spurious-Free Dynamic Range − dBc 100 SFDR − Spurious-Free Dynamic Range − dBc 1000 fdata = 100 MSPS Dual Bus Mode 95 90 85 −6 dBfS 80 0 dBfS 75 −12 dBfS 70 65 60 fdata = 165 MSPS Dual Bus Mode 95 90 85 80 0 dBfS −6 dBfS 75 70 −12 dBfS 65 60 0 5 10 15 20 25 fout − Output Frequency − MHz 30 35 0 Figure 5. Spurious-Free Dynamic Range vs Output Frequency 5 10 15 20 25 30 35 40 45 50 55 60 fout − Output Frequency − MHz G005 G006 Figure 6. Spurious-Free Dynamic Range vs Output Frequency Submit Documentation Feedback Copyright © 2007–2018, Texas Instruments Incorporated Product Folder Links: DAC5652A 9 DAC5652A SLAS535E – SEPTEMBER 2007 – REVISED MAY 2018 www.ti.com Typical Characteristics (continued) 0 0 fdata = 78 MSPS fOUT = 15 MHz Dual Bus Mode fdata = 165 MSPS fOUT = 30.1 MHz Dual Bus Mode −20 Power − dBm Power − dBm −20 −40 −60 −80 −40 −60 −80 −100 0.0 7.8 15.6 23.4 31.2 −100 0.0 39.0 16.5 f − Frequency − MHz 33.0 49.5 66.0 82.5 f − Frequency − MHz G007 G008 Figure 7. Single-Tone Spectrum Figure 8. Single-Tone Spectrum 95 100 95 90 Two-Tone IMD3 − dBc Two-Tone IMD3 − dBc 90 85 80 75 70 85 80 75 70 65 60 fdata = 78 MSPS Dual Bus Mode fout2 = fout1 + 1 MHz 65 60 50 0 5 10 15 20 25 30 35 fout1 − Output Frequency − MHz 0 G009 30 40 50 G010 fdata = 165 MSPS −10 fout1 = 30.1 MHz fout2 = 31.1 MHz Dual Bus Mode −30 Power − dBm −30 Power − dBm 20 Figure 10. Two-Tone IMD3 vs Output Frequency fdata = 78 MSPS fout1 = 20.1 MHz fout2 = 21.1 MHz Dual Bus Mode −50 −70 −90 −110 19.0 10 fout1 − Output Frequency − MHz Figure 9. Two-Tone IMD3 vs Output Frequency −10 fdata = 165 MSPS Dual Bus Mode fout2 = fout1 + 1 MHz 55 −50 −70 −90 19.5 20.0 20.5 21.0 21.5 −110 29.0 22.0 f − Frequency − MHz 29.5 30.0 30.5 31.0 31.5 32.0 f − Frequency − MHz G011 Figure 11. Two-Tone Spectrum 10 Submit Documentation Feedback G012 Figure 12. Two-Tone Spectrum Copyright © 2007–2018, Texas Instruments Incorporated Product Folder Links: DAC5652A DAC5652A www.ti.com SLAS535E – SEPTEMBER 2007 – REVISED MAY 2018 7 Detailed Description 7.1 Overview The architecture of the DAC5652A uses a current steering technique to enable fast switching and a high update rate. The core element within the monolithic DAC is an array of segmented current sources that are designed to deliver a full-scale output current of up to 20 mA. An internal decoder addresses the differential current switches each time the DAC is updated, and a corresponding output current is formed by steering all currents to either output summing node, IOUT1 or IOUT2. The complementary outputs deliver a differential output signal, which improves the dynamic performance through reduction of even-order harmonics, common-mode signals (noise), and doubles the peak-to-peak output signal swing by a factor of two, as compared to single-ended operation. The segmented architecture results in a significant reduction of the glitch energy and improves the dynamic performance (SFDR) and DNL. The current outputs maintain a very high output impedance of greater than 300 kΩ. When pin 42 (GSET) is high (simultaneous gain set mode), the full-scale output current for DACs is determined by the ratio of the internal reference voltage (1.2 V) and an external resistor (RSET) connected to BIASJ_A. When GSET is low (independent gain set mode), the full-scale output current for each DAC is determined by the ratio of the internal reference voltage (1.2 V) and separate external resistors (RSET) connected to BIASJ_A and BIASJ_B. The resulting IREF is internally multiplied by a factor of 32 to produce an effective DAC output current that can range from 2 mA to 20 mA, depending on the value of RSET. The DAC5652A is split into a digital and an analog portion, each of which is powered through its own supply pin. The digital section includes edge-triggered input latches and the decoder logic, while the analog section comprises both the current source array with its associated switches, and the reference circuitry. 7.2 Functional Block Diagram WRTB WRTA CLKB CLKA DEMUX IOUTA1 Latch A 10−b DAC IOUTA2 DA[9:0] BIASJ_A IOUTB1 Latch B DB[9:0] 10−b DAC IOUTB2 MODE BIASJ_B GSET 1.2 V Reference EXTIO SLEEP DVDD DGND AVDD AGND Submit Documentation Feedback Copyright © 2007–2018, Texas Instruments Incorporated Product Folder Links: DAC5652A 11 DAC5652A SLAS535E – SEPTEMBER 2007 – REVISED MAY 2018 www.ti.com 7.3 Feature Description 7.3.1 Digital Inputs The data input ports of the DAC5652A accept a standard positive coding with data bits DA9 and DB9 being the most significant bits (MSB). The converter outputs support a clock rate of up to 275 MSPS. The best performance is typically achieved with a symmetric duty cycle for write and clock; however, the duty cycle may vary as long as the timing specifications are met. Similarly, the setup and hold times may be chosen within their specified limits. All digital inputs of the DAC5652A are CMOS compatible. Figure 13 and Figure 14 show schematics of the equivalent CMOS digital inputs of the DAC5652A. The pullup and pulldown circuitry is approximately equivalent to 100 kΩ. The 10-bit digital data input follows the offset positive binary coding scheme. The DAC5652A is designed to operate with a digital supply (DVDD) of 3 V to 3.6 V. DVDD DA[9:0] DB[9:0] SLEEP CLKA/B WRTA/B 400W Internal Digital In 100kW DGND Figure 13. CMOS/TTL Digital Equivalent Input With Internal Pulldown Resistor DVDD 100kW GSET MODE 400W Internal Digital In DGND Figure 14. CMOS/TTL Digital Equivalent Input With Internal Pullup Resistor 12 Submit Documentation Feedback Copyright © 2007–2018, Texas Instruments Incorporated Product Folder Links: DAC5652A DAC5652A www.ti.com SLAS535E – SEPTEMBER 2007 – REVISED MAY 2018 Feature Description (continued) 7.3.2 References 7.3.2.1 Internal Reference The DAC5652A has an on-chip reference circuit which comprises a 1.2-V bandgap reference and two control amplifiers, one for each DAC. The full-scale output current, I(OUTFS), of the DAC5652A is determined by the reference voltage, VREF, and the value of resistor RSET. I(OUTFS) is calculated by: V REF I + 32 I + 32 OUTFS REF R SET (1) The reference control amplifier operates as a V-to-I converter producing a reference current, IREF, which is determined by the ratio of VREF and RSET (see Equation 9). The full-scale output current, I(OUTFS), results from multiplying IREF by a fixed factor of 32. Using the internal reference, a 2-kΩ resistor value results in a full-scale output of approximately 20 mA. Resistors with a tolerance of 1% or better should be considered. Selecting higher values, the output current can be adjusted from 20 mA down to 2 mA. Operating the DAC5652A at lower than 20-mA output currents may be desirable for reasons of reducing the total power consumption, improving the distortion performance, or observing the output compliance voltage limitations for a given load condition. It is recommended to bypass the EXTIO pin with a ceramic chip capacitor of 0.1 µF or more. The control amplifier is internally compensated and its small signal bandwidth is approximately 300 kHz. 7.3.2.2 External Reference The internal reference can be disabled by simply applying an external reference voltage into the EXTIO pin, which in this case functions as an input. The use of an external reference may be considered for applications that require higher accuracy and drift performance or to add the ability of dynamic gain control. While a 0.1-µF capacitor is recommended to be used with the internal reference, it is optional for the external reference operation. The reference input, EXTIO, has a high input impedance (1 MΩ) and can be driven by various sources. Note that the voltage range of the external reference must stay within the compliance range of the reference input. Submit Documentation Feedback Copyright © 2007–2018, Texas Instruments Incorporated Product Folder Links: DAC5652A 13 DAC5652A SLAS535E – SEPTEMBER 2007 – REVISED MAY 2018 www.ti.com 7.4 Device Functional Modes 7.4.1 Input Interfaces The DAC5652A features two operating modes selected by the MODE pin, as shown in Table 1. • For dual-bus input mode, the device essentially consists of two separate DACs. Each DAC has its own separate data input bus, clock input, and data write signal (data latch-in). • In single-bus interleaved mode, the data must be presented interleaved at the A-channel input bus. The Bchannel input bus is not used in this mode. The clock and write input are now shared by both DACs. Table 1. Operating Modes MODE PIN MODE PIN CONNECTED TO DGND MODE PIN CONNECTED TO DVDD Bus input Single-bus interleaved mode, clock and write input equal for both DACs Dual-bus mode, DACs operate independently 7.4.1.1 Dual-Bus Data Interface and Timing In dual-bus mode, the MODE pin is connected to DVDD. The two converter channels within the DAC5652A consist of two independent, 10-bit, parallel data ports. Each DAC channel is controlled by its own set of write (WRTA, WRTB) and clock (CLKA, CLKB) lines. The WRTA/B lines control the channel input latches and the CLKA/B lines control the DAC latches. The data is first loaded into the input latch by a rising edge of the WRTA/B line. The internal data transfer requires a correct sequence of write and clock inputs, since essentially two clock domains having equal periods (but possibly different phases) are input to the DAC5652A. This is defined by a minimum requirement of the time between the rising edge of the clock and the rising edge of the write inputs. This essentially implies that the rising edge of CLKA/B must occur at the same time or before the rising edge of the WRTA/B signal. A minimum delay of 2 ns must be maintained if the rising edge of the clock occurs after the rising edge of the write. Note that these conditions are satisfied when the clock and write inputs are connected externally. Note that all specifications were measured with the WRTA/B and CLKA/B lines connected together. DA[9:0]/DB[9:0] Valid Data tsu th tLPH WRTA/WRTB CLKA/CLKB ts tPD tLAT IOUT or IOUT Figure 15. Dual-Bus Mode Operation 14 Submit Documentation Feedback Copyright © 2007–2018, Texas Instruments Incorporated Product Folder Links: DAC5652A DAC5652A www.ti.com SLAS535E – SEPTEMBER 2007 – REVISED MAY 2018 7.4.1.2 Single-Bus Interleaved Data Interface and Timing In single-bus interleaved mode, the MODE pin is connected to DGND. Figure 16 shows the timing diagram. In interleaved mode, the A- and B-channels share the write input (WRTIQ) and update clock (CLKIQ and internal CLKDACIQ). Multiplexing logic directs the input word at the A-channel input bus to either the A-channel input latch (SELECTIQ is high) or to the B-channel input latch (SELECTIQ is low). When SELECTIQ is high, the data value in the B-channel latch is retained by presenting the latch output data to its input again. When SELECTIQ is low, the data value in the A-channel latch is retained by presenting the latch output data to its input. In interleaved mode, the A-channel input data rate is twice the update rate of the DAC core. As in dual-bus mode, it is important to maintain a correct sequence of write and clock inputs. The edge-triggered flip-flops latch the A- and B-channel input words on the rising edge of the write input (WRTIQ). This data is presented to the Aand B-DAC latches on the following falling edge of the write inputs. The DAC5652A clock input is divided by a factor of two before it is presented to the DAC latches. Correct pairing of the A- and B-channel data is done by RESETIQ. In interleaved mode, the clock input CLKIQ is divided by two, which would translate to a non-deterministic relation between the rising edges of the CLKIQ and CLKDACIQ. RESETIQ ensures, however, that the correct position of the rising edge of CLKDACIQ with respect to the data at the input of the DAC latch is determined. CLKDACIQ is disabled (low) when RESETIQ is high. DA[9:0] Valid Data tsu th SELECTIQ WRTIQ CLKIQ RESETIQ ts tPD tLAT IOUT or IOUT Figure 16. Single-Bus Interleaved Mode Operation Submit Documentation Feedback Copyright © 2007–2018, Texas Instruments Incorporated Product Folder Links: DAC5652A 15 DAC5652A SLAS535E – SEPTEMBER 2007 – REVISED MAY 2018 www.ti.com 7.4.2 Gain Setting Option The full-scale output current on the DAC5652A can be set two ways: either for each of the two DAC channels independently or for both channels simultaneously. For the independent gain set mode, the GSET pin (pin 42) must be low (that is, connected to AGND). In this mode, two external resistors are required — one RSET connected to the BIASJ_A pin (pin 44) and the other to the BIASJ_B pin (pin 41). In this configuration, the user has the flexibility to set and adjust the full-scale output current for each DAC independently, allowing for the compensation of possible gain mismatches elsewhere within the transmit signal path. Alternatively, bringing the GSET pin high (that is, connected to AVDD), the DAC5652A switches into the simultaneous gain set mode. Now the full-scale output current of both DAC channels is determined by only one external RSET resistor connected to the BIASJ_A pin. The resistor at the BIASJ_B pin may be removed; however, this is not required since this pin is not functional in this mode and the resistor has no effect on the gain equation. 7.4.3 Sleep Mode The DAC5652A features a power-down function that can reduce the total supply current to approximately 3.1 mA over the specified supply range if no clock is present. Applying a logic high to the SLEEP pin initiates powerdown mode, whereas a logic low enables normal operation. When left unconnected, an internal active pulldown circuit enables the normal operation of the converter. 16 Submit Documentation Feedback Copyright © 2007–2018, Texas Instruments Incorporated Product Folder Links: DAC5652A DAC5652A www.ti.com SLAS535E – SEPTEMBER 2007 – REVISED MAY 2018 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information The DAC5652A is a 10-bit dual DAC with max update rate of 275 MSPS. The DAC supports two different modes of operation: dual bus and single bus. In dual-bus mode, the DAC provides two independent transmit paths that can be programmed for two different update rates. In single-bus mode, the interleaved data for both channels are applied at the A-channel input bus. The B-channel input bus is not used in this mode. The clock and write input are now shared by both DACs. Thus, two different input signals can be transmitted from the two channels, but the update rate for both channels is the same. 8.1.1 DAC Transfer Function Each of the DACs in the DAC5652A has a set of complementary current outputs, IOUT1 and IOUT2. The fullscale output current, IOUTFS, is the summation of the two complementary output currents: I +I )I OUTFS OUT1 OUT2 (2) The individual output currents depend on the DAC code and can be expressed as: I I OUT1 +I OUTFS OUT2 +I OUTFS Ǔ ǒCode 1024 * CodeǓ ǒ10231024 (3) (4) where Code is the decimal representation of the DAC data input word. Additionally, IOUTFS is a function of the reference current IREF, which is determined by the reference voltage and the external setting resistor (RSET). V REF I + 32 I + 32 OUTFS REF R SET (5) In most cases, the complementary outputs drive resistive loads or a terminated transformer. A signal voltage develops at each output according to: V +I R OUT1 OUT1 LOAD (6) V +I R OUT2 OUT2 LOAD (7) The value of the load resistance is limited by the output compliance specification of the DAC5652A. To maintain specified linearity performance, the voltage for IOUT1 and IOUT2 must not exceed the maximum allowable compliance range. The total differential output voltage is: V +V *V OUTDIFF OUT1 OUT2 (2 Code * 1023) V + OUTDIFF 1024 (8) I OUTFS R LOAD (9) Submit Documentation Feedback Copyright © 2007–2018, Texas Instruments Incorporated Product Folder Links: DAC5652A 17 DAC5652A SLAS535E – SEPTEMBER 2007 – REVISED MAY 2018 www.ti.com Application Information (continued) 8.1.1.1 Analog Outputs The DAC5652A provides two complementary current outputs, IOUT1 and IOUT2. The simplified circuit of the analog output stage representing the differential topology is shown in Figure 17. The output impedance of IOUT1 and IOUT2 results from the parallel combination of the differential switches, along with the current sources and associated parasitic capacitances. AVDD S(1) IOUT1 RLOAD S(1)C IOUT2 S(2) S(2)C S(N) S(N)C Current Source Array RLOAD Figure 17. Analog Outputs The signal voltage swing that may develop at the two outputs, IOUT1 and IOUT2, is limited by a negative and positive compliance. The negative limit of –1 V is given by the breakdown voltage of the CMOS process and exceeding it compromises the reliability of the DAC5652A (or even causes permanent damage). With the fullscale output set to 20 mA, the positive compliance equals 1.2 V. Note that the compliance range decreases to about 1 V for a selected output current of I(OUTFS) = 2 mA. Care must be taken that the configuration of DAC5652A does not exceed the compliance range to avoid degradation of the distortion performance and integral linearity. Best distortion performance is typically achieved with the maximum full-scale output signal limited to approximately 0.5 VPP. This is the case for a 50-Ω doubly-terminated load and a 20-mA full-scale output current. A variety of loads can be adapted to the output of the DAC5652A by selecting a suitable transformer while maintaining optimum voltage levels at IOUT1 and IOUT2. Furthermore, using the differential output configuration in combination with a transformer is instrumental for achieving excellent distortion performance. Common-mode errors, such as even-order harmonics or noise, can be substantially reduced. This is particularly the case with high output frequencies. For those applications requiring the optimum distortion and noise performance, it is recommended to select a fullscale output of 20 mA. A lower full-scale range of 2 mA may be considered for applications that require low power consumption, but can tolerate a slight reduction in performance level. 8.1.2 Output Configurations The current outputs of the DAC5652A allow for a variety of configurations. As mentioned previously, utilizing the converter’s differential outputs yield the best dynamic performance. Such a differential output circuit may consist of an RF transformer or a differential amplifier configuration. The transformer configuration is ideal for most applications with ac coupling, while op amps are suitable for a dc-coupled configuration. The single-ended configuration may be considered for applications requiring a unipolar output voltage. Connecting a resistor from either one of the outputs to ground converts the output current into a groundreferenced voltage signal. To improve on the dc linearity by maintaining a virtual ground, an I-to-V or op-amp configuration may be considered. 18 Submit Documentation Feedback Copyright © 2007–2018, Texas Instruments Incorporated Product Folder Links: DAC5652A DAC5652A www.ti.com SLAS535E – SEPTEMBER 2007 – REVISED MAY 2018 Application Information (continued) 8.1.3 Differential With Transformer Using an RF transformer provides a convenient way of converting the differential output signal into a singleended signal while achieving excellent dynamic performance. The appropriate transformer must be carefully selected based on the output frequency spectrum and impedance requirements. The differential transformer configuration has the benefit of significantly reducing common-mode signals, thus improving the dynamic performance over a wide range of frequencies. Furthermore, by selecting a suitable impedance ratio (winding ratio) the transformer can provide optimum impedance matching while controlling the compliance voltage for the converter outputs. Figure 18 and Figure 19 show 50-Ω doubly-terminated transformer configurations with 1:1 and 4:1 impedance ratios, respectively. Note that the center tap of the primary input of the transformer has to be grounded to enable a dc-current flow. Applying a 20-mA full-scale output current would lead to a 0.5-VPP output for a 1:1 transformer and a 1-VPP output for a 4:1 transformer. In general, the 1:1 transformer configuration has a better output distortion, but the 4:1 transformer has 6 dB higher output power. 50 Ω 1:1 IOUT1 100 Ω RLOAD 50 Ω AGND IOUT2 50 Ω Figure 18. Driving a Doubly-Terminated 50-Ω Cable Using a 1:1 Impedance Ratio Transformer 100 Ω 4:1 IOUT1 AGND RLOAD 50 Ω IOUT2 100 Ω Figure 19. Driving a Doubly-Terminated 50-Ω Cable Using a 4:1 Impedance Ratio Transformer Submit Documentation Feedback Copyright © 2007–2018, Texas Instruments Incorporated Product Folder Links: DAC5652A 19 DAC5652A SLAS535E – SEPTEMBER 2007 – REVISED MAY 2018 www.ti.com Application Information (continued) 8.1.4 Single-Ended Configuration Figure 20 shows the single-ended output configuration, where the output current IOUT1 flows into an equivalent load resistance of 25 Ω. Node IOUT2 must be connected to AGND or terminated with a resistor of 25 Ω to AGND. The nominal resistor load of 25 Ω gives a differential output swing of 1 VPP when applying a 20-mA fullscale output current. IOUT1 RLOAD 50 Ω IOUT2 50 Ω 25 Ω AGND Figure 20. Driving a Doubly-Terminated 50-Ω Cable Using a Single-Ended Output 20 Submit Documentation Feedback Copyright © 2007–2018, Texas Instruments Incorporated Product Folder Links: DAC5652A DAC5652A www.ti.com SLAS535E – SEPTEMBER 2007 – REVISED MAY 2018 8.2 Typical Application A typical application for the DAC5652A is a dual- or single-carrier transmitter. The DAC is provided with some input digital baseband signal, and outputs an analog carrier. A design example for a single-carrier transmitter is described in this section. WRT B WRT A CLK B CLK A 50 DE-MUX 14-Bit ADC LATCH A Output 1:1 50 100 DA[13:0] 50 FPGA 50 DB[13:0] 14-Bit ADC LATCH A Output 1:1 50 100 50 EXTIO 1.2-V Reference 0.1 …F Figure 21. Single-Carrier Transmitter 8.2.1 Design Requirements The requirements for this design are to generate a single WCDMA signal at an intermediate frequency of 30.72 MHz. The ACLR needs to be better than 72 dBc. Table 2. Design Parameters FEATURE SPECIFICATION Number of carriers 1 AVDD and DVDD 3.3 V Clock rate 122.88 MSPS Input data WCDMA with IF at 30.72 MHz ACPR > 72 dB 8.2.2 Detailed Design Procedure The single WCDMA carrier signal with an intermediate frequency (IF) of 30.72 MHz must be created in the digital processor at a sample rate of 122.88 MSPS for the DAC. These 10-bit samples are placed on the 10-bit CMOS input port of the DAC. A CMOS DAC clock must be generated from a clock source at 122.88 MHz. This clock must be provided to the CLK pin of the DAC. The IOUTA and IOUTB differential connections must be connected to a transformer in order to provide a single-ended output. A typical 1:1 impedance transformer is used on the device EVM. The DAC5672A evaluation module (EVM) provides a good reference for this design example. Submit Documentation Feedback Copyright © 2007–2018, Texas Instruments Incorporated Product Folder Links: DAC5652A 21 DAC5652A SLAS535E – SEPTEMBER 2007 – REVISED MAY 2018 www.ti.com 8.2.3 Application Curve Figure 22 presents a spectrum analyzer plot shows the adjacent channel power ratio (ACPR) for the transformeroutput, single-carrier signal with an intermediate frequency of 30.72 MHz. The results meet the system requirements for a minimum of 72-dBc ACPR. Figure 22. ACPR Performance 9 Power Supply Recommendations Power the device with the nominal supply voltages as indicated in the Recommended Operating Conditions. In most instances, the best performance is achieved with LDO supplies. However, the supplies may be driven with direct outputs from a DC/DC switcher, as long as the noise performance of the switcher is acceptable. For best performance: • Use at least two power layers. • Avoid placing digital supplies and clean supplies on adjacent board layers. • Use a ground layer between noisy and clean supplies, if possible. • Decouple all supply pins as close to the pins as possible, using small-value capacitors, with larger, bulk capacitors placed further away. 10 Layout 10.1 Layout Guidelines Use the DAC5652AEVM layout as a reference to obtain the best performance. A sample layout is shown in Figure 23 through Figure 26. Some important layout recommendations are: 1. Use a single ground plane. Keep the digital and analog signals on distinct separate sections of the board. This may be virtually divided down the middle of the device package when doing placement and layout. 2. Keep the analog outputs as far away from the switching clocks and digital signals as possible. This keeps coupling from the digital circuits to the analog outputs to a minimum. 3. Keep decoupling capacitors close to the power pins of the device. 22 Submit Documentation Feedback Copyright © 2007–2018, Texas Instruments Incorporated Product Folder Links: DAC5652A DAC5652A www.ti.com SLAS535E – SEPTEMBER 2007 – REVISED MAY 2018 10.2 Layout Examples Figure 23 through Figure 26 show the layout examples. Digital Signal Analog Output Digital Signal Figure 23. Layout Example: Top Layer (Layer 1) Figure 24. Layout Example: Single Ground Plane (Layer 2) Submit Documentation Feedback Copyright © 2007–2018, Texas Instruments Incorporated Product Folder Links: DAC5652A 23 DAC5652A SLAS535E – SEPTEMBER 2007 – REVISED MAY 2018 www.ti.com Layout Examples (continued) Digital Power Plane Analog Power Plane Figure 25. Layout Example: Power Plane (Layer 3) 24 Submit Documentation Feedback Copyright © 2007–2018, Texas Instruments Incorporated Product Folder Links: DAC5652A DAC5652A www.ti.com SLAS535E – SEPTEMBER 2007 – REVISED MAY 2018 Layout Examples (continued) Decoupling Capacitors Figure 26. Layout Example: Bottom Layer (Layer 4) Submit Documentation Feedback Copyright © 2007–2018, Texas Instruments Incorporated Product Folder Links: DAC5652A 25 DAC5652A SLAS535E – SEPTEMBER 2007 – REVISED MAY 2018 www.ti.com 11 Device and Documentation Support 11.1 Documentation Support 11.1.1 Related Documentation For related documentation see the following: DAC5652AEVM User's Guide 11.2 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 11.3 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 11.4 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 11.5 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 11.6 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 26 Submit Documentation Feedback Copyright © 2007–2018, Texas Instruments Incorporated Product Folder Links: DAC5652A PACKAGE OPTION ADDENDUM www.ti.com 30-May-2018 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) DAC5652AIPFB ACTIVE TQFP PFB 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 DAC5652AI DAC5652AIPFBR ACTIVE TQFP PFB 48 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 DAC5652AI PDAC5652AIRSLT ACTIVE VQFN RSL 48 250 TBD Call TI Call TI -40 to 85 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 30-May-2018 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 20-Feb-2018 TAPE AND REEL INFORMATION *All dimensions are nominal Device DAC5652AIPFBR Package Package Pins Type Drawing TQFP PFB 48 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 1000 330.0 16.4 Pack Materials-Page 1 9.6 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 9.6 1.5 12.0 16.0 Q2 PACKAGE MATERIALS INFORMATION www.ti.com 20-Feb-2018 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DAC5652AIPFBR TQFP PFB 48 1000 367.0 367.0 38.0 Pack Materials-Page 2 MECHANICAL DATA MTQF019A – JANUARY 1995 – REVISED JANUARY 1998 PFB (S-PQFP-G48) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 36 0,08 M 25 37 24 48 13 0,13 NOM 1 12 5,50 TYP 7,20 SQ 6,80 9,20 SQ 8,80 Gage Plane 0,25 0,05 MIN 0°– 7° 1,05 0,95 Seating Plane 0,75 0,45 0,08 1,20 MAX 4073176 / B 10/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. 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Designers agree that it has the necessary expertise to select the product with the appropriate qualification designation for their applications and that proper product selection is at Designers’ own risk. Designers are solely responsible for compliance with all legal and regulatory requirements in connection with such selection. Designer will fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of Designer’s noncompliance with the terms and provisions of this Notice. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2018, Texas Instruments Incorporated