DSC2133 DSC2233 Low-Jitter I2C/SPI Programmable Dual LVDS Oscillator General Description Datasheet Features The DSC2133 and DSC2233 series of programmable, high-performance dual LVDS oscillators utilizes a proven silicon MEMS technology to provide excellent jitter and stability while incorporating high output frequency flexibility. DSC2133 and DSC2233 allow the user to independently modify the frequency of each output using I2C or SPI interface, respectively. User can also select from two pre-programmed default output frequencies using the control pin. DSC2133 and DSC2233 are packaged in 14pin 3.2x2.5 mm QFN package and available in temperature grades from Ext. Commercial to Industrial. Low RMS Phase Jitter: <1 ps (typ) High Stability: ±25, ±50 ppm Wide Temperature Range o Industrial: -40° to 85° C o Ext. commercial: -20° to 70° C High Supply Noise Rejection: -50 dBc Two Independent LVDS Outputs I2C/SPI Programmable Frequencies Short Lead Times: 2 Weeks Wide Frequency Range: o LVDS Output: 2.3 to 460 MHz Miniature Footprint of 3.2x2.5mm Excellent Shock & Vibration Immunity o Qualified to MIL-STD-883 Block Diagram High Reliability o 20x better MTF than quartz oscillators Supply Range of 2.25 to 3.6 V Lead Free & RoHS Compliant Applications Pin # 3 5 6 7 DSC2133 (I2C) NC SDA SCL CS_bar DSC2233 (SPI) SCLK MOSI MISO SS Storage Area Networks o SATA, SAS, Fibre Channel Passive Optical Networks o EPON, 10G-EPON, GPON, 10G-PON Ethernet o 1G, 10GBASE-T/KR/LR/SR, and FCoE HD/SD/SDI Video & Surveillance PCI Express _____________________________________________________________________________________________________________________________ _________________ DSC2133 DSC2233 Page 1 MK-Q-B-P-D-12050109 DSC2133 DSC2233 Low-Jitter I2C/SPI Programmable Dual LVDS Oscillator Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Pin Name Enable NC NC SCLK GND SDA MOSI SCL MISO CS_bar SS Output1+ Output1Output 2Output 2+ VDD2 VDD FS Pin Type I NA NA I Power I I O I I O O O O Power Power I Description Enables outputs when high and disables when low Leave unconnected or grounded DSC2133: Leave unconnected or grounded DSC2233: Serial clock from master Ground DSC2133: I2C Serial Data DSC2233: SPI Serial Data from Master to Slave DSC2133: I2C Serial Clock DSC2233: SPI Serial Data from Slave to Master DSC2133: I2C Chip Select (Active Low) DSC2233: SPI Slave Select (Active Low) Positive LVDS Output 1 Negative LVDS Output 1 Negative LVDS Output 2 Positive LVDS Output 2 Power Supply for LVDS Output 2 Power Supply Default output clock frequency bit Operational Description The DSC2133/2233 is a dual LVDS oscillator consisting of a MEMS resonator and a support PLL IC. The outputs are generated through independent 8-bit programmable dividers from the output of the internal PLL. DSC2133/2233 allows for easy programming of the output frequencies using I2C/SPI interface. Upon power-up, the initial output frequencies are controlled by an internal preprogrammed memory (OTP). This memory stores all coefficients required by the PLL for two different default frequency pairs. The control pin (FS) selects the initial pair. Once the device is powered up, a new output frequency pair can be programmed. Programming details are provided in the Programming Guide. Standard default frequency pairs are described in the following sections. Discera supports customer defined versions of the DSC2133/2233. When Enable (pin 1) is floated or connected to VDD, the DSC2133/2233 is in operational mode. Driving Enable to ground will tri-state both output drivers (hi-impedance mode). _____________________________________________________________________________________________________________________________ _________________ DSC2133 DSC2233 Page 2 MK-Q-B-P-D-12050109 DSC2133 DSC2233 Low-Jitter I2C/SPI Programmable Dual LVDS Oscillator Output Clock Frequencies Table 1 lists the standard default frequency configurations and the associated ordering information to be used in conjunction with the ordering code. Customer defined combinations are available. Table 1. Pre-programmed pin-selectable output frequency pairs Ordering Info G0001 G0002 GXXXX Freq (MHz) fOUT1 fOUT2 fOUT1 fOUT2 fOUT1 fOUT2 Select Bit [FS] – Default is [1] 0 1 148.5 156.25 74.25 125 100 125 100 125 Contact factory for additional configurations. Frequency select bit are weakly tied high so if left unconnected the default setting will be [1] and the device will output the associated frequency highlighted in Bold. _____________________________________________________________________________________________________________________________ _________________ DSC2133 DSC2233 Page 3 MK-Q-B-P-D-12050109 DSC2133 DSC2233 Low-Jitter I2C/SPI Programmable Dual LVDS Oscillator Absolute Maximum Ratings Ordering Code Item Min Max Unit Supply Voltage -0.3 +4.0 V Input Voltage Junction Temp Storage Temp Soldering Temp -0.3 -55 - VDD+0.3 +150 +150 +260 V °C °C °C ESD HBM MM CDM - Condition Prog Mode 1: I2C bus 2: SPI bus Temp Range E: -20 to 70 I: -40 to 85 DSC2 1 33 F I 2 40sec max. V Package F: 3.2x2.5mm 4000 400 1500 - xxxxx Stability 1: ±50ppm 2: ±25ppm Packing T: Tape & Reel : Tube T Freq (MHz) See Freq. table Note: 1000+ years of data retention on internal memory Specifications (Unless specified otherwise: T=25° C) Parameter Supply Voltage Condition 1 VDD Supply Current IDD Supply Current2 IDD Frequency Stability Δf Aging Startup Time3 Input Logic Levels Input logic high Input logic low Δf tSU VIH VIL Output Disable Time4 Output Enable Time Min. Typ. 2.25 EN pin low – outputs are disabled EN pin high – outputs are enabled RL=100Ω, FO1=FO2 =156.25 MHz Includes frequency variations due to initial tolerance, temp. and power supply voltage 1 year @25°C T=25°C 21 Max. Unit 3.6 V 23 mA 38 mA ±25 ±50 ppm ±5 5 ppm ms 0.25xVDD V tDA 5 ns tEN 20 ns 2 Pull-Up Resistor 0.75xVDD - Pull-up exists on all digital IO 40 kΩ LVDS Outputs Output Offset Voltage R=100Ω Differential 1.125 Delta Offset Voltage Pk to Pk Output Swing Output Transition time Rise Time Fall Time 4 Frequency tR tF 1.4 V 50 mV Single-Ended 350 mV 20% to 80% RL=50Ω, CL= 2pF 200 ps f0 Single Frequency 2.3 460 MHz SYM Differential 48 52 % Period Jitter JPER FO1=FO2=156.25 MHz 2.5 Integrated Phase Noise JCC 200kHz to 20MHz @148.5MHz 100kHz to 20MHz @148.5MHz 12kHz to 20MHz @148.5MHz 0.28 0.4 1.7 Output Duty Cycle 5 Notes: 1. 2. 3. 4. 5. psRMS 2 psRMS Pin 4 VDD should be filtered with 0.01uf capacitor. Output is enabled if Enable pad is floated or not connected. tsu is time to 100PPM stable output frequency after VDD is applied and outputs are enabled. Output Waveform and Test Circuit figures below define the parameters. Period Jitter includes crosstalk from adjacent output. _____________________________________________________________________________________________________________________________ _________________ DSC2133 DSC2233 Page 4 MK-Q-B-P-D-12050109 DSC2133 DSC2233 Low-Jitter I2C/SPI Programmable Dual LVDS Oscillator Nominal Performance Parameters (Unless specified otherwise: T=25° C, VDD=3.3 V) 2.5 Phase Jitter (ps RMS) 156MHz-LVDS 212MHz-LVDS 2.0 320MHz-LVDS 1.5 410MHz-LVDS 1.0 0.5 0.0 0 200 400 600 800 1000 Low-end of integration BW: x kHz to 20 MHz LVDS Phase jitter (integrated phase noise) Output Waveform: LVDS tR Output tF 80% 350 mV 830 mv 50% Output 20% tEN 1/f o tDA VIH Enable VIL _____________________________________________________________________________________________________________________________ _________________ DSC2133 DSC2233 Page 5 MK-Q-B-P-D-12050109 DSC2133 DSC2233 Low-Jitter I2C/SPI Programmable Dual LVDS Oscillator Solder Reflow Profile . ax Se cM ax cM Se 3C / Pre heat 8 min max Reflow a x. 25°C 60-180 Sec 60-150 Sec cM . 3C / 217°C 200°C 150°C 20-40 Sec Se 6C/ Temperature (°C) 260°C Cool Time MSL 1 @ 260°C refer to JSTD-020C Ramp-Up Rate (200°C to Peak Temp) 3°C/Sec Max. Preheat Time 150°C to 200°C 60-180 Sec Time maintained above 217°C 60-150 Sec 255-260°C Peak Temperature Time within 5°C of actual Peak 20-40 Sec 6°C/Sec Max. Ramp-Down Rate Time 25°C to Peak Temperature 8 min Max. Package Dimensions 3.2 x 2.5 mm 14 Lead Plastic Package Disclaimer: Discera makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. Discera reserves the right to make changes without further notice to materials described herein. Discera does not assume any liability arising from the application or use of any product or circuit described herein. Discera does not authorize its products for use a critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Discera’s product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Discera against all charges. DISCERA, Inc. ● Phone: +1 (408) 432-8600 1961 Concourse Drive, San Jose, California 95131 ● Fax: +1 (408) 432-8609 ● Email: [email protected] ● ● USA www.discera.com _____________________________________________________________________________________________________________________________ _________________ DSC2133 DSC2233 Page 6 MK-Q-B-P-D-12050109